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dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018

The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.

Add the related compatible for IPQ6018 to the ipq9574-cmn-pll
generic schema.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311183942.10134-2-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

John Crispin and committed by
Bjorn Andersson a5766600 16ba98da

+16
+1
Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
··· 26 26 enum: 27 27 - qcom,ipq5018-cmn-pll 28 28 - qcom,ipq5424-cmn-pll 29 + - qcom,ipq6018-cmn-pll 29 30 - qcom,ipq9574-cmn-pll 30 31 31 32 reg:
+15
include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H 7 + #define _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H 8 + 9 + /* CMN PLL core clock. */ 10 + #define IPQ6018_CMN_PLL_CLK 0 11 + 12 + /* The output clocks from CMN PLL of IPQ6018. */ 13 + #define IPQ6018_BIAS_PLL_CC_CLK 1 14 + #define IPQ6018_BIAS_PLL_NSS_NOC_CLK 2 15 + #endif