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Merge tag 'imx-dt64-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree update for 5.20:

- Add device tree support for i.MX93 SoC.
- New board device tree: TQMa8MPQL, DH electronics i.MX8M Plus DHCOM and
PDK2, i.MX93 11x11 EVK, phyBOARD-Polis-i.MX8MM.
- A series from Abel Vesa and Viorel Suman to fix i.MX8QXP device tree
to comply with DT schema.
- Disable job ring 0 device for i.MX8MM to avoid caam_jr probe error, due
to that JR0 reservation is done in both upstream (v2.7) and downstream
(NXP lf_v2.4) TF-A.
- A series from Krzysztof Kozlowski to align gpio-key and LED node names
with dtschema.
- Add SNVS LPGPR device for i.MX8MM so that some preserving registers
becomes available as NVMEM.
- Add NoC device support for i.MX8MP SoC.
- A couple of changes from Sean Anderson to add SFP node for TA devices
for LayerScape SoCs.
- A series from Shengjiu Wang to enable bt-sco sound card support for
NXP i.MX8M EVK boards.
- Other small and random board updates.

* tag 'imx-dt64-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (33 commits)
arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP
arm64: dts: freescale: imx8qxp: Fix the keys node name
arm64: dts: freescale: imx8: Fix the system-controller node name
arm64: dts: freescale: imx8qxp: Fix the ocotp node name
arm64: dts: freescale: imx8qxp: Add fallback compatible for clock controller
arm64: dts: freescale: imx8: Fix power controller name
arm64: dts: freescale: imx8qxp: Remove unnecessary clock related entries
arm64: dts: imx8mp: add NoC node
arm64: dts: Add SFP node for TA 3.0 devices
arm64: dts: layerscape: Add SFP node for TA 2.1 devices
arm64: dts: freescale: Add phyBOARD-Polis-i.MX8MM support
arm64: dts: imx8m{m,p}-verdin: use IT temperatures
arm64: dts: imx8mn-evk: add bt-sco sound card support
arm64: dts: imx8mq-evk: add bt-sco sound card support
arm64: dts: imx8mm-evk: add bt-sco sound card support
arm64: freescale/imx8mp-evk.dts: reorder nodes alphabetically
arm64: dts: imx8mq: Pass a label to the AIPS nodes
arm64: dts: imx8m: Pass a label to the soc node
arm64: dts: imx8mm-venice-gw7902: fix UART1 CTS
arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK2
...

Link: https://lore.kernel.org/r/20220709082951.15123-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann a5959198 dbd68eb5

+4550 -172
+4
arch/arm64/boot/dts/freescale/Makefile
··· 58 58 dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb 59 59 dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb 60 60 dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb 61 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb 61 62 dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb 62 63 dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb 63 64 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb ··· 80 79 dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb 81 80 dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb 82 81 dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb 82 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb 83 83 dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb 84 84 dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb 85 85 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb 86 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb 86 87 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb 87 88 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb 88 89 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb ··· 110 107 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb 111 108 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb 112 109 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb 110 + dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb 113 111 114 112 imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo 115 113 imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
··· 69 69 flash@0 { 70 70 #address-cells = <1>; 71 71 #size-cells = <1>; 72 - compatible = "n25q128a11", "jedec,spi-nor"; 72 + compatible = "micron,n25q128a11", "jedec,spi-nor"; 73 73 reg = <0>; 74 74 spi-max-frequency = <10000000>; 75 75 };
+13 -5
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
··· 204 204 compatible = "fsl,sec-v5.4-job-ring", 205 205 "fsl,sec-v5.0-job-ring", 206 206 "fsl,sec-v4.0-job-ring"; 207 - reg = <0x10000 0x10000>; 207 + reg = <0x10000 0x10000>; 208 208 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 209 209 }; 210 210 ··· 212 212 compatible = "fsl,sec-v5.4-job-ring", 213 213 "fsl,sec-v5.0-job-ring", 214 214 "fsl,sec-v4.0-job-ring"; 215 - reg = <0x20000 0x10000>; 215 + reg = <0x20000 0x10000>; 216 216 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 217 217 }; 218 218 ··· 220 220 compatible = "fsl,sec-v5.4-job-ring", 221 221 "fsl,sec-v5.0-job-ring", 222 222 "fsl,sec-v4.0-job-ring"; 223 - reg = <0x30000 0x10000>; 223 + reg = <0x30000 0x10000>; 224 224 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 225 225 }; 226 226 ··· 228 228 compatible = "fsl,sec-v5.4-job-ring", 229 229 "fsl,sec-v5.0-job-ring", 230 230 "fsl,sec-v4.0-job-ring"; 231 - reg = <0x40000 0x10000>; 231 + reg = <0x40000 0x10000>; 232 232 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 233 233 }; 234 234 ··· 269 269 reg = <0x60 0x20>, <0x400 0x100>; 270 270 }; 271 271 }; 272 + }; 273 + 274 + sfp: efuse@1e80000 { 275 + compatible = "fsl,ls1021a-sfp"; 276 + reg = <0x0 0x1e80000 0x0 0x10000>; 277 + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 278 + QORIQ_CLK_PLL_DIV(4)>; 279 + clock-names = "sfp"; 272 280 }; 273 281 274 282 sec_mon: sec_mon@1e90000 { ··· 473 465 status = "disabled"; 474 466 }; 475 467 476 - edma0: edma@2c00000 { 468 + edma0: dma-controller@2c00000 { 477 469 #dma-cells = <2>; 478 470 compatible = "fsl,vf610-edma"; 479 471 reg = <0x0 0x2c00000 0x0 0x10000>,
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
··· 93 93 compatible = "mdio-mux-multiplexer"; 94 94 mux-controls = <&mux 0>; 95 95 mdio-parent-bus = <&enetc_mdio_pf3>; 96 - #address-cells=<1>; 96 + #address-cells = <1>; 97 97 #size-cells = <0>; 98 98 99 99 /* on-board RGMII PHY */
+8 -8
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
··· 96 96 }; 97 97 98 98 reboot { 99 - compatible ="syscon-reboot"; 99 + compatible = "syscon-reboot"; 100 100 regmap = <&rst>; 101 101 offset = <0>; 102 102 mask = <0x02>; ··· 120 120 }; 121 121 122 122 gic: interrupt-controller@6000000 { 123 - compatible= "arm,gic-v3"; 123 + compatible = "arm,gic-v3"; 124 124 #address-cells = <2>; 125 125 #size-cells = <2>; 126 126 ranges; 127 - reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 127 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 128 128 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 129 - #interrupt-cells= <3>; 129 + #interrupt-cells = <3>; 130 130 interrupt-controller; 131 131 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 132 132 IRQ_TYPE_LEVEL_LOW)>; ··· 769 769 sec_jr0: jr@10000 { 770 770 compatible = "fsl,sec-v5.0-job-ring", 771 771 "fsl,sec-v4.0-job-ring"; 772 - reg = <0x10000 0x10000>; 772 + reg = <0x10000 0x10000>; 773 773 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 774 774 }; 775 775 776 776 sec_jr1: jr@20000 { 777 777 compatible = "fsl,sec-v5.0-job-ring", 778 778 "fsl,sec-v4.0-job-ring"; 779 - reg = <0x20000 0x10000>; 779 + reg = <0x20000 0x10000>; 780 780 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 781 781 }; 782 782 783 783 sec_jr2: jr@30000 { 784 784 compatible = "fsl,sec-v5.0-job-ring", 785 785 "fsl,sec-v4.0-job-ring"; 786 - reg = <0x30000 0x10000>; 786 + reg = <0x30000 0x10000>; 787 787 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 788 788 }; 789 789 790 790 sec_jr3: jr@40000 { 791 791 compatible = "fsl,sec-v5.0-job-ring", 792 792 "fsl,sec-v4.0-job-ring"; 793 - reg = <0x40000 0x10000>; 793 + reg = <0x40000 0x10000>; 794 794 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 795 795 }; 796 796 };
+14 -6
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
··· 144 144 }; 145 145 146 146 reboot { 147 - compatible ="syscon-reboot"; 147 + compatible = "syscon-reboot"; 148 148 regmap = <&dcfg>; 149 149 offset = <0xb0>; 150 150 mask = <0x02>; ··· 354 354 compatible = "fsl,sec-v5.4-job-ring", 355 355 "fsl,sec-v5.0-job-ring", 356 356 "fsl,sec-v4.0-job-ring"; 357 - reg = <0x10000 0x10000>; 357 + reg = <0x10000 0x10000>; 358 358 interrupts = <0 71 0x4>; 359 359 }; 360 360 ··· 362 362 compatible = "fsl,sec-v5.4-job-ring", 363 363 "fsl,sec-v5.0-job-ring", 364 364 "fsl,sec-v4.0-job-ring"; 365 - reg = <0x20000 0x10000>; 365 + reg = <0x20000 0x10000>; 366 366 interrupts = <0 72 0x4>; 367 367 }; 368 368 ··· 370 370 compatible = "fsl,sec-v5.4-job-ring", 371 371 "fsl,sec-v5.0-job-ring", 372 372 "fsl,sec-v4.0-job-ring"; 373 - reg = <0x30000 0x10000>; 373 + reg = <0x30000 0x10000>; 374 374 interrupts = <0 73 0x4>; 375 375 }; 376 376 ··· 378 378 compatible = "fsl,sec-v5.4-job-ring", 379 379 "fsl,sec-v5.0-job-ring", 380 380 "fsl,sec-v4.0-job-ring"; 381 - reg = <0x40000 0x10000>; 381 + reg = <0x40000 0x10000>; 382 382 interrupts = <0 74 0x4>; 383 383 }; 384 + }; 385 + 386 + sfp: efuse@1e80000 { 387 + compatible = "fsl,ls1021a-sfp"; 388 + reg = <0x0 0x1e80000 0x0 0x10000>; 389 + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 390 + QORIQ_CLK_PLL_DIV(4)>; 391 + clock-names = "sfp"; 384 392 }; 385 393 386 394 dcfg: dcfg@1ee0000 { ··· 792 784 big-endian; 793 785 }; 794 786 795 - edma0: edma@2c00000 { 787 + edma0: dma-controller@2c00000 { 796 788 #dma-cells = <2>; 797 789 compatible = "fsl,vf610-edma"; 798 790 reg = <0x0 0x2c00000 0x0 0x10000>,
+14 -6
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
··· 112 112 }; 113 113 114 114 reboot { 115 - compatible ="syscon-reboot"; 115 + compatible = "syscon-reboot"; 116 116 regmap = <&dcfg>; 117 117 offset = <0xb0>; 118 118 mask = <0x02>; ··· 360 360 compatible = "fsl,sec-v5.4-job-ring", 361 361 "fsl,sec-v5.0-job-ring", 362 362 "fsl,sec-v4.0-job-ring"; 363 - reg = <0x10000 0x10000>; 363 + reg = <0x10000 0x10000>; 364 364 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 365 365 }; 366 366 ··· 368 368 compatible = "fsl,sec-v5.4-job-ring", 369 369 "fsl,sec-v5.0-job-ring", 370 370 "fsl,sec-v4.0-job-ring"; 371 - reg = <0x20000 0x10000>; 371 + reg = <0x20000 0x10000>; 372 372 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 373 373 }; 374 374 ··· 376 376 compatible = "fsl,sec-v5.4-job-ring", 377 377 "fsl,sec-v5.0-job-ring", 378 378 "fsl,sec-v4.0-job-ring"; 379 - reg = <0x30000 0x10000>; 379 + reg = <0x30000 0x10000>; 380 380 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 381 381 }; 382 382 ··· 384 384 compatible = "fsl,sec-v5.4-job-ring", 385 385 "fsl,sec-v5.0-job-ring", 386 386 "fsl,sec-v4.0-job-ring"; 387 - reg = <0x40000 0x10000>; 387 + reg = <0x40000 0x10000>; 388 388 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 389 389 }; 390 390 }; ··· 411 411 412 412 bportals: bman-portals@508000000 { 413 413 ranges = <0x0 0x5 0x08000000 0x8000000>; 414 + }; 415 + 416 + sfp: efuse@1e80000 { 417 + compatible = "fsl,ls1021a-sfp"; 418 + reg = <0x0 0x1e80000 0x0 0x10000>; 419 + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 420 + QORIQ_CLK_PLL_DIV(4)>; 421 + clock-names = "sfp"; 414 422 }; 415 423 416 424 dcfg: dcfg@1ee0000 { ··· 691 683 big-endian; 692 684 }; 693 685 694 - edma0: edma@2c00000 { 686 + edma0: dma-controller@2c00000 { 695 687 #dma-cells = <2>; 696 688 compatible = "fsl,vf610-edma"; 697 689 reg = <0x0 0x2c00000 0x0 0x10000>,
+5 -5
arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
··· 35 35 * external power off (e.g ATX Power Button) 36 36 * asserted 37 37 */ 38 - powerdn { 38 + button-powerdn { 39 39 label = "External Power Down"; 40 40 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; 41 41 linux,code = <KEY_POWER>; 42 42 }; 43 43 44 44 /* Rear Panel 'ADMIN' button (GPIO_H) */ 45 - admin { 45 + button-admin { 46 46 label = "ADMIN button"; 47 47 gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; 48 48 linux,code = <KEY_WPS_BUTTON>; ··· 52 52 leds { 53 53 compatible = "gpio-leds"; 54 54 55 - sfp1down { 55 + led-0 { 56 56 label = "ten64:green:sfp1:down"; 57 57 gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; 58 58 }; 59 59 60 - sfp2up { 60 + led-1 { 61 61 label = "ten64:green:sfp2:up"; 62 62 gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; 63 63 }; 64 64 65 - admin { 65 + led-2 { 66 66 label = "ten64:admin"; 67 67 gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; 68 68 };
+12 -4
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
··· 269 269 }; 270 270 }; 271 271 272 + sfp: efuse@1e80000 { 273 + compatible = "fsl,ls1028a-sfp"; 274 + reg = <0x0 0x1e80000 0x0 0x10000>; 275 + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 276 + QORIQ_CLK_PLL_DIV(4)>; 277 + clock-names = "sfp"; 278 + }; 279 + 272 280 tmu: tmu@1f80000 { 273 281 compatible = "fsl,qoriq-tmu"; 274 282 reg = <0x0 0x1f80000 0x0 0x10000>; ··· 534 526 sec_jr0: jr@10000 { 535 527 compatible = "fsl,sec-v5.0-job-ring", 536 528 "fsl,sec-v4.0-job-ring"; 537 - reg = <0x10000 0x10000>; 529 + reg = <0x10000 0x10000>; 538 530 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 539 531 }; 540 532 541 533 sec_jr1: jr@20000 { 542 534 compatible = "fsl,sec-v5.0-job-ring", 543 535 "fsl,sec-v4.0-job-ring"; 544 - reg = <0x20000 0x10000>; 536 + reg = <0x20000 0x10000>; 545 537 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 546 538 }; 547 539 548 540 sec_jr2: jr@30000 { 549 541 compatible = "fsl,sec-v5.0-job-ring", 550 542 "fsl,sec-v4.0-job-ring"; 551 - reg = <0x30000 0x10000>; 543 + reg = <0x30000 0x10000>; 552 544 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 553 545 }; 554 546 555 547 sec_jr3: jr@40000 { 556 548 compatible = "fsl,sec-v5.0-job-ring", 557 549 "fsl,sec-v4.0-job-ring"; 558 - reg = <0x40000 0x10000>; 550 + reg = <0x40000 0x10000>; 559 551 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 560 552 }; 561 553 };
+13 -5
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
··· 73 73 }; 74 74 75 75 reboot { 76 - compatible ="syscon-reboot"; 76 + compatible = "syscon-reboot"; 77 77 regmap = <&rstcr>; 78 78 offset = <0x0>; 79 79 mask = <0x2>; ··· 278 278 little-endian; 279 279 }; 280 280 281 + sfp: efuse@1e80000 { 282 + compatible = "fsl,ls1028a-sfp"; 283 + reg = <0x0 0x1e80000 0x0 0x10000>; 284 + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 285 + QORIQ_CLK_PLL_DIV(4)>; 286 + clock-names = "sfp"; 287 + }; 288 + 281 289 isc: syscon@1f70000 { 282 290 compatible = "fsl,ls2080a-isc", "syscon"; 283 291 reg = <0x0 0x1f70000 0x0 0x10000>; ··· 487 479 sec_jr0: jr@10000 { 488 480 compatible = "fsl,sec-v5.0-job-ring", 489 481 "fsl,sec-v4.0-job-ring"; 490 - reg = <0x10000 0x10000>; 482 + reg = <0x10000 0x10000>; 491 483 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 492 484 }; 493 485 494 486 sec_jr1: jr@20000 { 495 487 compatible = "fsl,sec-v5.0-job-ring", 496 488 "fsl,sec-v4.0-job-ring"; 497 - reg = <0x20000 0x10000>; 489 + reg = <0x20000 0x10000>; 498 490 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 499 491 }; 500 492 501 493 sec_jr2: jr@30000 { 502 494 compatible = "fsl,sec-v5.0-job-ring", 503 495 "fsl,sec-v4.0-job-ring"; 504 - reg = <0x30000 0x10000>; 496 + reg = <0x30000 0x10000>; 505 497 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 506 498 }; 507 499 508 500 sec_jr3: jr@40000 { 509 501 compatible = "fsl,sec-v5.0-job-ring", 510 502 "fsl,sec-v4.0-job-ring"; 511 - reg = <0x40000 0x10000>; 503 + reg = <0x40000 0x10000>; 512 504 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 513 505 }; 514 506 };
+2 -2
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
··· 36 36 compatible = "mdio-mux-multiplexer"; 37 37 mux-controls = <&mux 0>; 38 38 mdio-parent-bus = <&emdio1>; 39 - #address-cells=<1>; 39 + #address-cells = <1>; 40 40 #size-cells = <0>; 41 41 42 42 mdio@0 { /* On-board PHY #1 RGMI1*/ ··· 104 104 compatible = "mdio-mux-multiplexer"; 105 105 mux-controls = <&mux 1>; 106 106 mdio-parent-bus = <&emdio2>; 107 - #address-cells=<1>; 107 + #address-cells = <1>; 108 108 #size-cells = <0>; 109 109 110 110 mdio@0 { /* Slot #1 (secondary EMI) */
+12 -4
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
··· 632 632 sec_jr0: jr@10000 { 633 633 compatible = "fsl,sec-v5.0-job-ring", 634 634 "fsl,sec-v4.0-job-ring"; 635 - reg = <0x10000 0x10000>; 635 + reg = <0x10000 0x10000>; 636 636 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 637 637 }; 638 638 639 639 sec_jr1: jr@20000 { 640 640 compatible = "fsl,sec-v5.0-job-ring", 641 641 "fsl,sec-v4.0-job-ring"; 642 - reg = <0x20000 0x10000>; 642 + reg = <0x20000 0x10000>; 643 643 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 644 644 }; 645 645 646 646 sec_jr2: jr@30000 { 647 647 compatible = "fsl,sec-v5.0-job-ring", 648 648 "fsl,sec-v4.0-job-ring"; 649 - reg = <0x30000 0x10000>; 649 + reg = <0x30000 0x10000>; 650 650 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 651 651 }; 652 652 653 653 sec_jr3: jr@40000 { 654 654 compatible = "fsl,sec-v5.0-job-ring", 655 655 "fsl,sec-v4.0-job-ring"; 656 - reg = <0x40000 0x10000>; 656 + reg = <0x40000 0x10000>; 657 657 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 658 658 }; 659 659 }; ··· 669 669 compatible = "fsl,lx2160a-dcfg", "syscon"; 670 670 reg = <0x0 0x1e00000 0x0 0x10000>; 671 671 little-endian; 672 + }; 673 + 674 + sfp: efuse@1e80000 { 675 + compatible = "fsl,ls1028a-sfp"; 676 + reg = <0x0 0x1e80000 0x0 0x10000>; 677 + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 678 + QORIQ_CLK_PLL_DIV(4)>; 679 + clock-names = "sfp"; 672 680 }; 673 681 674 682 isc: syscon@1f70000 {
+2 -2
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
··· 34 34 compatible = "mdio-mux-multiplexer"; 35 35 mux-controls = <&mux 0>; 36 36 mdio-parent-bus = <&emdio1>; 37 - #address-cells=<1>; 37 + #address-cells = <1>; 38 38 #size-cells = <0>; 39 39 40 40 mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */ ··· 114 114 compatible = "mdio-mux-multiplexer"; 115 115 mux-controls = <&mux 1>; 116 116 mdio-parent-bus = <&emdio2>; 117 - #address-cells=<1>; 117 + #address-cells = <1>; 118 118 #size-cells = <0>; 119 119 120 120 mdio@0 { /* Slot #1 (secondary EMI) */
+5 -5
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
··· 54 54 clock-names = "ipg", "per", "ahb"; 55 55 power-domains = <&pd IMX_SC_R_SDHC_1>; 56 56 fsl,tuning-start-tap = <20>; 57 - fsl,tuning-step= <2>; 57 + fsl,tuning-step = <2>; 58 58 status = "disabled"; 59 59 }; 60 60 ··· 83 83 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 84 84 <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; 85 85 assigned-clock-rates = <250000000>, <125000000>; 86 - fsl,num-tx-queues=<3>; 87 - fsl,num-rx-queues=<3>; 86 + fsl,num-tx-queues = <3>; 87 + fsl,num-rx-queues = <3>; 88 88 power-domains = <&pd IMX_SC_R_ENET_0>; 89 89 status = "disabled"; 90 90 }; ··· 103 103 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 104 104 <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; 105 105 assigned-clock-rates = <250000000>, <125000000>; 106 - fsl,num-tx-queues=<3>; 107 - fsl,num-rx-queues=<3>; 106 + fsl,num-tx-queues = <3>; 107 + fsl,num-rx-queues = <3>; 108 108 power-domains = <&pd IMX_SC_R_ENET_1>; 109 109 status = "disabled"; 110 110 };
+2 -2
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
··· 285 285 &usbotg1 { 286 286 vbus-supply = <&reg_usbotg1>; 287 287 disable-over-current; 288 - dr_mode="otg"; 288 + dr_mode = "otg"; 289 289 status = "okay"; 290 290 }; 291 291 292 292 &usbotg2 { 293 293 pinctrl-names = "default"; 294 294 disable-over-current; 295 - dr_mode="host"; 295 + dr_mode = "host"; 296 296 status = "okay"; 297 297 }; 298 298
+43
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
··· 75 75 linux,autosuspend-period = <125>; 76 76 }; 77 77 78 + audio_codec_bt_sco: audio-codec-bt-sco { 79 + compatible = "linux,bt-sco"; 80 + #sound-dai-cells = <1>; 81 + }; 82 + 78 83 wm8524: audio-codec { 79 84 #sound-dai-cells = <0>; 80 85 compatible = "wlf,wm8524"; 81 86 pinctrl-names = "default"; 82 87 pinctrl-0 = <&pinctrl_gpio_wlf>; 83 88 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 89 + }; 90 + 91 + sound-bt-sco { 92 + compatible = "simple-audio-card"; 93 + simple-audio-card,name = "bt-sco-audio"; 94 + simple-audio-card,format = "dsp_a"; 95 + simple-audio-card,bitclock-inversion; 96 + simple-audio-card,frame-master = <&btcpu>; 97 + simple-audio-card,bitclock-master = <&btcpu>; 98 + 99 + btcpu: simple-audio-card,cpu { 100 + sound-dai = <&sai2>; 101 + dai-tdm-slot-num = <2>; 102 + dai-tdm-slot-width = <16>; 103 + }; 104 + 105 + simple-audio-card,codec { 106 + sound-dai = <&audio_codec_bt_sco 1>; 107 + }; 84 108 }; 85 109 86 110 sound-wm8524 { ··· 370 346 status = "okay"; 371 347 }; 372 348 349 + &sai2 { 350 + #sound-dai-cells = <0>; 351 + pinctrl-names = "default"; 352 + pinctrl-0 = <&pinctrl_sai2>; 353 + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 354 + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 355 + assigned-clock-rates = <24576000>; 356 + status = "okay"; 357 + }; 358 + 373 359 &sai3 { 374 360 pinctrl-names = "default"; 375 361 pinctrl-0 = <&pinctrl_sai3>; ··· 525 491 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 526 492 fsl,pins = < 527 493 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 494 + >; 495 + }; 496 + 497 + pinctrl_sai2: sai2grp { 498 + fsl,pins = < 499 + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 500 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 501 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 502 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 528 503 >; 529 504 }; 530 505
+6 -6
arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
··· 84 84 }; 85 85 86 86 reg_buck1: buck1 { 87 - regulator-min-microvolt = <400000>; 87 + regulator-min-microvolt = <400000>; 88 88 regulator-max-microvolt = <1800000>; 89 89 regulator-always-on; 90 90 regulator-boot-on; 91 91 }; 92 92 93 93 reg_buck2: buck2 { 94 - regulator-min-microvolt = <400000>; 94 + regulator-min-microvolt = <400000>; 95 95 regulator-max-microvolt = <1800000>; 96 96 regulator-always-on; 97 97 regulator-boot-on; 98 98 }; 99 99 100 100 reg_buck3: buck3 { 101 - regulator-min-microvolt = <400000>; 101 + regulator-min-microvolt = <400000>; 102 102 regulator-max-microvolt = <1800000>; 103 103 regulator-always-on; 104 104 regulator-boot-on; 105 105 }; 106 106 107 107 reg_buck4: buck4 { 108 - regulator-min-microvolt = <400000>; 108 + regulator-min-microvolt = <400000>; 109 109 regulator-max-microvolt = <1800000>; 110 110 regulator-always-on; 111 111 regulator-boot-on; 112 112 }; 113 113 114 114 reg_buck5: buck5 { 115 - regulator-min-microvolt = <400000>; 115 + regulator-min-microvolt = <400000>; 116 116 regulator-max-microvolt = <1800000>; 117 117 regulator-always-on; 118 118 regulator-boot-on; 119 119 }; 120 120 121 121 reg_buck6: buck6 { 122 - regulator-min-microvolt = <400000>; 122 + regulator-min-microvolt = <400000>; 123 123 regulator-max-microvolt = <1800000>; 124 124 regulator-always-on; 125 125 regulator-boot-on;
+2 -2
arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
··· 20 20 pinctrl-names = "default"; 21 21 pinctrl-0 = <&pinctrl_led>; 22 22 23 - user1 { 23 + led-1 { 24 24 label = "TestLed601"; 25 25 gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; 26 26 linux,default-trigger = "mmc0"; 27 27 }; 28 28 29 - user2 { 29 + led-2 { 30 30 label = "TestLed602"; 31 31 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; 32 32 linux,default-trigger = "heartbeat";
+450
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (C) 2022 PHYTEC Messtechnik GmbH 4 + * Author: Teresa Remmet <t.remmet@phytec.de> 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include <dt-bindings/interrupt-controller/irq.h> 10 + #include <dt-bindings/leds/common.h> 11 + #include <dt-bindings/phy/phy-imx8-pcie.h> 12 + #include "imx8mm-phycore-som.dtsi" 13 + 14 + / { 15 + model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; 16 + compatible = "phytec,imx8mm-phyboard-polis-rdk", 17 + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 18 + 19 + chosen { 20 + stdout-path = &uart3; 21 + }; 22 + 23 + bt_osc_32k: bt-lp-clock { 24 + compatible = "fixed-clock"; 25 + clock-frequency = <32768>; 26 + clock-output-names = "bt_osc_32k"; 27 + #clock-cells = <0>; 28 + }; 29 + 30 + can_osc_40m: can-clock { 31 + compatible = "fixed-clock"; 32 + clock-frequency = <40000000>; 33 + clock-output-names = "can_osc_40m"; 34 + #clock-cells = <0>; 35 + }; 36 + 37 + fan { 38 + compatible = "gpio-fan"; 39 + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; 40 + gpio-fan,speed-map = <0 0 41 + 13000 1>; 42 + pinctrl-names = "default"; 43 + pinctrl-0 = <&pinctrl_fan>; 44 + #cooling-cells = <2>; 45 + }; 46 + 47 + leds { 48 + compatible = "gpio-leds"; 49 + pinctrl-names = "default"; 50 + pinctrl-0 = <&pinctrl_leds>; 51 + 52 + led-0 { 53 + color = <LED_COLOR_ID_RED>; 54 + function = LED_FUNCTION_DISK; 55 + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 56 + linux,default-trigger = "mmc2"; 57 + }; 58 + 59 + led-1 { 60 + color = <LED_COLOR_ID_BLUE>; 61 + function = LED_FUNCTION_DISK; 62 + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; 63 + linux,default-trigger = "mmc1"; 64 + }; 65 + 66 + led-2 { 67 + color = <LED_COLOR_ID_GREEN>; 68 + function = LED_FUNCTION_CPU; 69 + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 70 + linux,default-trigger = "heartbeat"; 71 + }; 72 + }; 73 + 74 + usdhc1_pwrseq: pwr-seq { 75 + compatible = "mmc-pwrseq-simple"; 76 + post-power-on-delay-ms = <100>; 77 + power-off-delay-us = <60>; 78 + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 79 + }; 80 + 81 + reg_can_en: regulator-can-en { 82 + compatible = "regulator-fixed"; 83 + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; 84 + pinctrl-names = "default"; 85 + pinctrl-0 = <&pinctrl_can_en>; 86 + regulator-max-microvolt = <3300000>; 87 + regulator-min-microvolt = <3300000>; 88 + regulator-name = "CAN_EN"; 89 + startup-delay-us = <20>; 90 + }; 91 + 92 + reg_usb_otg1_vbus: regulator-usb-otg1 { 93 + compatible = "regulator-fixed"; 94 + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 95 + enable-active-high; 96 + pinctrl-names = "default"; 97 + pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; 98 + regulator-name = "usb_otg1_vbus"; 99 + regulator-max-microvolt = <5000000>; 100 + regulator-min-microvolt = <5000000>; 101 + }; 102 + 103 + reg_usdhc2_vmmc: regulator-usdhc2 { 104 + compatible = "regulator-fixed"; 105 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 106 + enable-active-high; 107 + off-on-delay-us = <20000>; 108 + pinctrl-names = "default"; 109 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 110 + regulator-max-microvolt = <3300000>; 111 + regulator-min-microvolt = <3300000>; 112 + regulator-name = "VSD_3V3"; 113 + }; 114 + 115 + reg_vcc_3v3: regulator-vcc-3v3 { 116 + compatible = "regulator-fixed"; 117 + regulator-max-microvolt = <3300000>; 118 + regulator-min-microvolt = <3300000>; 119 + regulator-name = "VCC_3V3"; 120 + }; 121 + }; 122 + 123 + /* SPI - CAN MCP251XFD */ 124 + &ecspi1 { 125 + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 126 + pinctrl-names = "default"; 127 + pinctrl-0 = <&pinctrl_ecspi1>; 128 + status = "okay"; 129 + 130 + can0: can@0 { 131 + compatible = "microchip,mcp251xfd"; 132 + clocks = <&can_osc_40m>; 133 + interrupt-parent = <&gpio1>; 134 + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 135 + pinctrl-names = "default"; 136 + pinctrl-0 = <&pinctrl_can_int>; 137 + reg = <0>; 138 + spi-max-frequency = <20000000>; 139 + xceiver-supply = <&reg_can_en>; 140 + }; 141 + }; 142 + 143 + &gpio1 { 144 + gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", 145 + "", "", "", "RESET_ETHPHY", 146 + "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", 147 + "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; 148 + }; 149 + 150 + &gpio2 { 151 + gpio-line-names = "", "", "", "", 152 + "", "", "BT_REG_ON", "WL_REG_ON", 153 + "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", 154 + "X_SD2_CD_B", "", "", "", 155 + "", "", "", "SD2_RESET_B"; 156 + }; 157 + 158 + &gpio4 { 159 + gpio-line-names = "", "", "", "", 160 + "", "", "", "", 161 + "FAN", "miniPCIe_nPERST", "", "", 162 + "COEX1", "COEX2"; 163 + }; 164 + 165 + &gpio5 { 166 + gpio-line-names = "", "", "", "", 167 + "", "", "", "", 168 + "", "ECSPI1_SS0"; 169 + }; 170 + 171 + /* PCIe */ 172 + &pcie0 { 173 + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 174 + <&clk IMX8MM_CLK_PCIE1_CTRL>; 175 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 176 + <&clk IMX8MM_SYS_PLL2_250M>; 177 + assigned-clock-rates = <10000000>, <250000000>; 178 + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 179 + <&clk IMX8MM_CLK_PCIE1_PHY>; 180 + clock-names = "pcie", "pcie_aux", "pcie_bus"; 181 + pinctrl-names = "default"; 182 + pinctrl-0 = <&pinctrl_pcie>; 183 + reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; 184 + status = "okay"; 185 + }; 186 + 187 + &pcie_phy { 188 + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 189 + fsl,clkreq-unsupported; 190 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 191 + fsl,tx-deemph-gen1 = <0x2d>; 192 + fsl,tx-deemph-gen2 = <0xf>; 193 + status = "okay"; 194 + }; 195 + 196 + &rv3028 { 197 + trickle-resistor-ohms = <3000>; 198 + }; 199 + 200 + &snvs_pwrkey { 201 + status = "okay"; 202 + }; 203 + 204 + /* UART - RS232/RS485 */ 205 + &uart1 { 206 + assigned-clocks = <&clk IMX8MM_CLK_UART1>; 207 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 208 + pinctrl-names = "default"; 209 + pinctrl-0 = <&pinctrl_uart1>; 210 + uart-has-rtscts; 211 + status = "okay"; 212 + }; 213 + 214 + /* UART - Sterling-LWB Bluetooth */ 215 + &uart2 { 216 + assigned-clocks = <&clk IMX8MM_CLK_UART2>; 217 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 218 + fsl,dte-mode; 219 + pinctrl-names = "default"; 220 + pinctrl-0 = <&pinctrl_uart2_bt>; 221 + uart-has-rtscts; 222 + status = "okay"; 223 + 224 + bluetooth { 225 + compatible = "brcm,bcm43438-bt"; 226 + clocks = <&bt_osc_32k>; 227 + clock-names = "lpo"; 228 + device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 229 + interrupt-names = "host-wakeup"; 230 + interrupt-parent = <&gpio2>; 231 + interrupts = <9 IRQ_TYPE_EDGE_BOTH>; 232 + max-speed = <2000000>; 233 + pinctrl-names = "default"; 234 + pinctrl-0 = <&pinctrl_bt>; 235 + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 236 + vddio-supply = <&reg_vcc_3v3>; 237 + }; 238 + }; 239 + 240 + /* UART - console */ 241 + &uart3 { 242 + pinctrl-names = "default"; 243 + pinctrl-0 = <&pinctrl_uart3>; 244 + status = "okay"; 245 + }; 246 + 247 + /* USB */ 248 + &usbotg1 { 249 + adp-disable; 250 + dr_mode = "otg"; 251 + over-current-active-low; 252 + samsung,picophy-pre-emp-curr-control = <3>; 253 + samsung,picophy-dc-vol-level-adjust = <7>; 254 + srp-disable; 255 + vbus-supply = <&reg_usb_otg1_vbus>; 256 + status = "okay"; 257 + }; 258 + 259 + &usbotg2 { 260 + disable-over-current; 261 + dr_mode = "host"; 262 + samsung,picophy-pre-emp-curr-control = <3>; 263 + samsung,picophy-dc-vol-level-adjust = <7>; 264 + status = "okay"; 265 + }; 266 + 267 + /* SDIO - Sterling-LWB Wifi */ 268 + &usdhc1 { 269 + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; 270 + assigned-clock-rates = <200000000>; 271 + bus-width = <4>; 272 + mmc-pwrseq = <&usdhc1_pwrseq>; 273 + non-removable; 274 + no-1-8-v; 275 + pinctrl-names = "default"; 276 + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; 277 + #address-cells = <1>; 278 + #size-cells = <0>; 279 + status = "okay"; 280 + 281 + brcmf: wifi@1 { 282 + compatible = "brcm,bcm4329-fmac"; 283 + reg = <1>; 284 + }; 285 + }; 286 + 287 + /* SD-Card */ 288 + &usdhc2 { 289 + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 290 + assigned-clock-rates = <200000000>; 291 + bus-width = <4>; 292 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 293 + disable-wp; 294 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 295 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 296 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 297 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 298 + vmmc-supply = <&reg_usdhc2_vmmc>; 299 + vqmmc-supply = <&reg_nvcc_sd2>; 300 + status = "okay"; 301 + }; 302 + 303 + &iomuxc { 304 + pinctrl_bt: btgrp { 305 + fsl,pins = < 306 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 307 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 308 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 309 + >; 310 + }; 311 + 312 + pinctrl_can_en: can-engrp { 313 + fsl,pins = < 314 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 315 + >; 316 + }; 317 + 318 + pinctrl_can_int: can-intgrp { 319 + fsl,pins = < 320 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 321 + >; 322 + }; 323 + 324 + pinctrl_ecspi1: ecspi1grp { 325 + fsl,pins = < 326 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 327 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 328 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 329 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 330 + >; 331 + }; 332 + 333 + pinctrl_fan: fan0grp { 334 + fsl,pins = < 335 + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 336 + >; 337 + }; 338 + 339 + pinctrl_leds: leds1grp { 340 + fsl,pins = < 341 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 342 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 343 + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 344 + >; 345 + }; 346 + 347 + pinctrl_pcie: pciegrp { 348 + fsl,pins = < 349 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 350 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 351 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 352 + >; 353 + }; 354 + 355 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 356 + fsl,pins = < 357 + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 358 + >; 359 + }; 360 + 361 + pinctrl_uart1: uart1grp { 362 + fsl,pins = < 363 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 364 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 365 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 366 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 367 + >; 368 + }; 369 + 370 + pinctrl_uart2_bt: uart2btgrp { 371 + fsl,pins = < 372 + MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 373 + MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 374 + MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 375 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 376 + >; 377 + }; 378 + 379 + pinctrl_uart3: uart3grp { 380 + fsl,pins = < 381 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 382 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 383 + >; 384 + }; 385 + 386 + pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { 387 + fsl,pins = < 388 + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 389 + >; 390 + }; 391 + 392 + pinctrl_usdhc1: usdhc1grp { 393 + fsl,pins = < 394 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 395 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 396 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 397 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 398 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 399 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 400 + >; 401 + }; 402 + 403 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 404 + fsl,pins = < 405 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 406 + >; 407 + }; 408 + 409 + pinctrl_usdhc2: usdhc2grp { 410 + fsl,pins = < 411 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 412 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 413 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 414 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 415 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 416 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 417 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 418 + >; 419 + }; 420 + 421 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 422 + fsl,pins = < 423 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 424 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 425 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 426 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 427 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 428 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 429 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 430 + >; 431 + }; 432 + 433 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 434 + fsl,pins = < 435 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 436 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 437 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 438 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 439 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 440 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 441 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 442 + >; 443 + }; 444 + 445 + pinctrl_wlan: wlangrp { 446 + fsl,pins = < 447 + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 448 + >; 449 + }; 450 + };
+440
arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (C) 2022 PHYTEC Messtechnik GmbH 4 + * Author: Teresa Remmet <t.remmet@phytec.de> 5 + */ 6 + 7 + #include "imx8mm.dtsi" 8 + #include <dt-bindings/net/ti-dp83867.h> 9 + 10 + / { 11 + model = "PHYTEC phyCORE-i.MX8MM"; 12 + compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 13 + 14 + aliases { 15 + rtc0 = &rv3028; 16 + rtc1 = &snvs_rtc; 17 + }; 18 + 19 + memory@40000000 { 20 + device_type = "memory"; 21 + reg = <0x0 0x40000000 0 0x80000000>; 22 + }; 23 + 24 + reg_vdd_3v3_s: regulator-vdd-3v3-s { 25 + compatible = "regulator-fixed"; 26 + regulator-always-on; 27 + regulator-boot-on; 28 + regulator-max-microvolt = <3300000>; 29 + regulator-min-microvolt = <3300000>; 30 + regulator-name = "VDD_3V3_S"; 31 + }; 32 + }; 33 + 34 + &A53_0 { 35 + cpu-supply = <&reg_vdd_arm>; 36 + }; 37 + 38 + &A53_1 { 39 + cpu-supply = <&reg_vdd_arm>; 40 + }; 41 + 42 + &A53_2 { 43 + cpu-supply = <&reg_vdd_arm>; 44 + }; 45 + 46 + &A53_3 { 47 + cpu-supply = <&reg_vdd_arm>; 48 + }; 49 + 50 + &ddrc { 51 + operating-points-v2 = <&ddrc_opp_table>; 52 + 53 + ddrc_opp_table: opp-table { 54 + compatible = "operating-points-v2"; 55 + 56 + opp-25M { 57 + opp-hz = /bits/ 64 <25000000>; 58 + }; 59 + 60 + opp-100M { 61 + opp-hz = /bits/ 64 <100000000>; 62 + }; 63 + 64 + opp-750M { 65 + opp-hz = /bits/ 64 <750000000>; 66 + }; 67 + }; 68 + }; 69 + 70 + /* Ethernet */ 71 + &fec1 { 72 + fsl,magic-packet; 73 + phy-mode = "rgmii-id"; 74 + phy-handle = <&ethphy0>; 75 + pinctrl-names = "default"; 76 + pinctrl-0 = <&pinctrl_fec1>; 77 + status = "okay"; 78 + 79 + mdio { 80 + #address-cells = <1>; 81 + #size-cells = <0>; 82 + 83 + ethphy0: ethernet-phy@0 { 84 + compatible = "ethernet-phy-ieee802.3-c22"; 85 + enet-phy-lane-no-swap; 86 + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 87 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 88 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 89 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 90 + reg = <0>; 91 + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 92 + reset-assert-us = <1000>; 93 + reset-deassert-us = <1000>; 94 + }; 95 + }; 96 + }; 97 + 98 + /* SPI Flash */ 99 + &flexspi { 100 + pinctrl-names = "default"; 101 + pinctrl-0 = <&pinctrl_flexspi0>; 102 + status = "okay"; 103 + 104 + som_flash: flash@0 { 105 + compatible = "jedec,spi-nor"; 106 + reg = <0>; 107 + spi-max-frequency = <80000000>; 108 + spi-rx-bus-width = <4>; 109 + spi-tx-bus-width = <1>; 110 + }; 111 + }; 112 + 113 + &gpio1 { 114 + gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", 115 + "", "", "", "RESET_ETHPHY", 116 + "", "", "nENABLE_FLATLINK"; 117 + }; 118 + 119 + /* I2C1 */ 120 + &i2c1 { 121 + clock-frequency = <400000>; 122 + pinctrl-names = "default","gpio"; 123 + pinctrl-0 = <&pinctrl_i2c1>; 124 + pinctrl-1 = <&pinctrl_i2c1_gpio>; 125 + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 126 + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 127 + status = "okay"; 128 + 129 + pmic@8 { 130 + compatible = "nxp,pf8121a"; 131 + reg = <0x08>; 132 + 133 + regulators { 134 + reg_nvcc_sd1: ldo1 { 135 + regulator-always-on; 136 + regulator-boot-on; 137 + regulator-max-microvolt = <3300000>; 138 + regulator-min-microvolt = <3300000>; 139 + regulator-name = "NVCC_SD1 (LDO1)"; 140 + 141 + regulator-state-mem { 142 + regulator-off-in-suspend; 143 + }; 144 + }; 145 + 146 + reg_nvcc_sd2: ldo2 { 147 + regulator-always-on; 148 + regulator-boot-on; 149 + regulator-max-microvolt = <3300000>; 150 + regulator-min-microvolt = <1800000>; 151 + regulator-name = "NVCC_SD2 (LDO2)"; 152 + vselect-en; 153 + 154 + regulator-state-mem { 155 + regulator-off-in-suspend; 156 + }; 157 + }; 158 + 159 + reg_vcc_enet: ldo3 { 160 + regulator-always-on; 161 + regulator-boot-on; 162 + regulator-max-microvolt = <2500000>; 163 + regulator-min-microvolt = <1500000>; 164 + regulator-name = "VCC_ENET_2V5 (LDO3)"; 165 + 166 + regulator-state-mem { 167 + regulator-off-in-suspend; 168 + }; 169 + }; 170 + 171 + reg_vdda_1v8: ldo4 { 172 + regulator-always-on; 173 + regulator-boot-on; 174 + regulator-max-microvolt = <1800000>; 175 + regulator-min-microvolt = <1500000>; 176 + regulator-name = "VDDA_1V8 (LDO4)"; 177 + 178 + regulator-state-mem { 179 + regulator-on-in-suspend; 180 + regulator-suspend-min-microvolt = <1500000>; 181 + regulator-suspend-max-microvolt = <1500000>; 182 + }; 183 + }; 184 + 185 + reg_soc_vdda_phy: buck1 { 186 + regulator-always-on; 187 + regulator-boot-on; 188 + regulator-max-microvolt = <900000>; 189 + regulator-min-microvolt = <400000>; 190 + regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; 191 + 192 + regulator-state-mem { 193 + regulator-on-in-suspend; 194 + regulator-suspend-min-microvolt = <400000>; 195 + regulator-suspend-max-microvolt = <400000>; 196 + }; 197 + }; 198 + 199 + reg_vdd_gpu_dram: buck2 { 200 + regulator-always-on; 201 + regulator-boot-on; 202 + regulator-max-microvolt = <1000000>; 203 + regulator-min-microvolt = <1000000>; 204 + regulator-name = "VDD_GPU_DRAM (BUCK2)"; 205 + 206 + regulator-state-mem { 207 + regulator-on-in-suspend; 208 + regulator-suspend-max-microvolt = <1000000>; 209 + regulator-suspend-min-microvolt = <1000000>; 210 + }; 211 + }; 212 + 213 + reg_vdd_gpu: buck3 { 214 + regulator-always-on; 215 + regulator-boot-on; 216 + regulator-max-microvolt = <1000000>; 217 + regulator-min-microvolt = <400000>; 218 + regulator-name = "VDD_VPU (BUCK3)"; 219 + 220 + regulator-state-mem { 221 + regulator-off-in-suspend; 222 + }; 223 + }; 224 + 225 + reg_vdd_mipi: buck4 { 226 + regulator-always-on; 227 + regulator-boot-on; 228 + regulator-max-microvolt = <1050000>; 229 + regulator-min-microvolt = <900000>; 230 + regulator-name = "VDD_MIPI_0P9 (BUCK4)"; 231 + 232 + regulator-state-mem { 233 + regulator-off-in-suspend; 234 + }; 235 + }; 236 + 237 + reg_vdd_arm: buck5 { 238 + regulator-always-on; 239 + regulator-boot-on; 240 + regulator-max-microvolt = <1050000>; 241 + regulator-min-microvolt = <400000>; 242 + regulator-name = "VDD_ARM (BUCK5)"; 243 + 244 + regulator-state-mem { 245 + regulator-off-in-suspend; 246 + }; 247 + }; 248 + 249 + reg_vdd_1v8: buck6 { 250 + regulator-always-on; 251 + regulator-boot-on; 252 + regulator-max-microvolt = <1800000>; 253 + regulator-min-microvolt = <1800000>; 254 + regulator-name = "VDD_1V8 (BUCK6)"; 255 + 256 + regulator-state-mem { 257 + regulator-on-in-suspend; 258 + regulator-suspend-max-microvolt = <1800000>; 259 + regulator-suspend-min-microvolt = <1800000>; 260 + }; 261 + }; 262 + 263 + reg_nvcc_dram: buck7 { 264 + regulator-always-on; 265 + regulator-boot-on; 266 + regulator-max-microvolt = <1100000>; 267 + regulator-min-microvolt = <1100000>; 268 + regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; 269 + }; 270 + 271 + reg_vsnvs: vsnvs { 272 + regulator-always-on; 273 + regulator-boot-on; 274 + regulator-max-microvolt = <1800000>; 275 + regulator-min-microvolt = <1800000>; 276 + regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; 277 + }; 278 + }; 279 + }; 280 + 281 + sn65dsi83: bridge@2d { 282 + compatible = "ti,sn65dsi83"; 283 + enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 284 + pinctrl-names = "default"; 285 + pinctrl-0 = <&pinctrl_sn65dsi83>; 286 + reg = <0x2d>; 287 + status = "disabled"; 288 + }; 289 + 290 + eeprom@51 { 291 + compatible = "atmel,24c32"; 292 + pagesize = <32>; 293 + reg = <0x51>; 294 + vcc-supply = <&reg_vdd_3v3_s>; 295 + }; 296 + 297 + rv3028: rtc@52 { 298 + compatible = "microcrystal,rv3028"; 299 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 300 + interrupt-parent = <&gpio1>; 301 + pinctrl-names = "default"; 302 + pinctrl-0 = <&pinctrl_rtc>; 303 + reg = <0x52>; 304 + }; 305 + }; 306 + 307 + /* EMMC */ 308 + &usdhc3 { 309 + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 310 + assigned-clock-rates = <400000000>; 311 + bus-width = <8>; 312 + keep-power-in-suspend; 313 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 314 + pinctrl-0 = <&pinctrl_usdhc3>; 315 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 316 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 317 + non-removable; 318 + status = "okay"; 319 + }; 320 + 321 + /* Watchdog */ 322 + &wdog1 { 323 + fsl,ext-reset-output; 324 + pinctrl-names = "default"; 325 + pinctrl-0 = <&pinctrl_wdog>; 326 + status = "okay"; 327 + }; 328 + 329 + &iomuxc { 330 + pinctrl_fec1: fec1grp { 331 + fsl,pins = < 332 + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 333 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 334 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 335 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 336 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 337 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 338 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 339 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 340 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 341 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 342 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 343 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 344 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 345 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 346 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 347 + >; 348 + }; 349 + 350 + pinctrl_flexspi0: flexspi0grp { 351 + fsl,pins = < 352 + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 353 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 354 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 355 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 356 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 357 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 358 + >; 359 + }; 360 + 361 + pinctrl_i2c1: i2c1grp { 362 + fsl,pins = < 363 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 364 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 365 + >; 366 + }; 367 + 368 + pinctrl_i2c1_gpio: i2c1gpiogrp { 369 + fsl,pins = < 370 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 371 + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 372 + >; 373 + }; 374 + 375 + pinctrl_rtc: rtcgrp { 376 + fsl,pins = < 377 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 378 + >; 379 + }; 380 + 381 + pinctrl_sn65dsi83: sn65dsi83grp { 382 + fsl,pins = < 383 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 384 + >; 385 + }; 386 + 387 + pinctrl_usdhc3: usdhc3grp { 388 + fsl,pins = < 389 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 390 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 391 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 392 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 393 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 394 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 395 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 396 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 397 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 398 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 399 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 400 + >; 401 + }; 402 + 403 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 404 + fsl,pins = < 405 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 406 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 407 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 408 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 409 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 410 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 411 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 412 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 413 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 414 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 415 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 416 + >; 417 + }; 418 + 419 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 420 + fsl,pins = < 421 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 422 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 423 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 424 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 425 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 426 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 427 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 428 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 429 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 430 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 431 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 432 + >; 433 + }; 434 + 435 + pinctrl_wdog: wdoggrp { 436 + fsl,pins = < 437 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 438 + >; 439 + }; 440 + };
+3 -3
arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
··· 36 36 gpio-keys { 37 37 compatible = "gpio-keys"; 38 38 39 - back { 39 + key-back { 40 40 label = "Back"; 41 41 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; 42 42 linux,code = <KEY_BACK>; 43 43 }; 44 44 45 - home { 45 + key-home { 46 46 label = "Home"; 47 47 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; 48 48 linux,code = <KEY_HOME>; 49 49 }; 50 50 51 - menu { 51 + key-menu { 52 52 label = "Menu"; 53 53 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; 54 54 linux,code = <KEY_MENU>;
+12 -12
arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
··· 16 16 gpio-keys { 17 17 compatible = "gpio-keys"; 18 18 19 - user-pb { 19 + key-user-pb { 20 20 label = "user_pb"; 21 21 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 22 22 linux,code = <BTN_0>; 23 23 }; 24 24 25 - user-pb1x { 25 + key-user-pb1x { 26 26 label = "user_pb1x"; 27 27 linux,code = <BTN_1>; 28 28 interrupt-parent = <&gsc>; ··· 36 36 interrupts = <1>; 37 37 }; 38 38 39 - eeprom-wp { 39 + key-eeprom-wp { 40 40 label = "eeprom_wp"; 41 41 linux,code = <BTN_3>; 42 42 interrupt-parent = <&gsc>; 43 43 interrupts = <2>; 44 44 }; 45 45 46 - tamper { 46 + key-tamper { 47 47 label = "tamper"; 48 48 linux,code = <BTN_4>; 49 49 interrupt-parent = <&gsc>; ··· 286 286 regulator-name = "buck1"; 287 287 regulator-min-microvolt = <800000>; 288 288 regulator-max-microvolt = <1000000>; 289 - regulator-min-microamp = <3800000>; 290 - regulator-max-microamp = <6800000>; 289 + regulator-min-microamp = <3800000>; 290 + regulator-max-microamp = <6800000>; 291 291 regulator-boot-on; 292 292 regulator-always-on; 293 293 }; ··· 297 297 regulator-name = "buck2"; 298 298 regulator-min-microvolt = <800000>; 299 299 regulator-max-microvolt = <900000>; 300 - regulator-min-microamp = <2200000>; 301 - regulator-max-microamp = <5200000>; 300 + regulator-min-microamp = <2200000>; 301 + regulator-max-microamp = <5200000>; 302 302 regulator-boot-on; 303 303 regulator-always-on; 304 304 }; ··· 308 308 regulator-name = "buck3"; 309 309 regulator-min-microvolt = <800000>; 310 310 regulator-max-microvolt = <1000000>; 311 - regulator-min-microamp = <3800000>; 312 - regulator-max-microamp = <6800000>; 311 + regulator-min-microamp = <3800000>; 312 + regulator-max-microamp = <6800000>; 313 313 regulator-always-on; 314 314 }; 315 315 ··· 318 318 regulator-name = "buck4"; 319 319 regulator-min-microvolt = <1800000>; 320 320 regulator-max-microvolt = <1800000>; 321 - regulator-min-microamp = <2200000>; 322 - regulator-max-microamp = <5200000>; 321 + regulator-min-microamp = <2200000>; 322 + regulator-max-microamp = <5200000>; 323 323 regulator-boot-on; 324 324 regulator-always-on; 325 325 };
+4 -4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
··· 38 38 gpio-keys { 39 39 compatible = "gpio-keys"; 40 40 41 - user-pb { 41 + key-user-pb { 42 42 label = "user_pb"; 43 43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 44 44 linux,code = <BTN_0>; 45 45 }; 46 46 47 - user-pb1x { 47 + key-user-pb1x { 48 48 label = "user_pb1x"; 49 49 linux,code = <BTN_1>; 50 50 interrupt-parent = <&gsc>; ··· 58 58 interrupts = <1>; 59 59 }; 60 60 61 - eeprom-wp { 61 + key-eeprom-wp { 62 62 label = "eeprom_wp"; 63 63 linux,code = <BTN_3>; 64 64 interrupt-parent = <&gsc>; 65 65 interrupts = <2>; 66 66 }; 67 67 68 - tamper { 68 + key-tamper { 69 69 label = "tamper"; 70 70 linux,code = <BTN_4>; 71 71 interrupt-parent = <&gsc>;
+5 -5
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
··· 42 42 gpio-keys { 43 43 compatible = "gpio-keys"; 44 44 45 - user-pb { 45 + key-user-pb { 46 46 label = "user_pb"; 47 47 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 48 48 linux,code = <BTN_0>; 49 49 }; 50 50 51 - user-pb1x { 51 + key-user-pb1x { 52 52 label = "user_pb1x"; 53 53 linux,code = <BTN_1>; 54 54 interrupt-parent = <&gsc>; ··· 62 62 interrupts = <1>; 63 63 }; 64 64 65 - eeprom-wp { 65 + key-eeprom-wp { 66 66 label = "eeprom_wp"; 67 67 linux,code = <BTN_3>; 68 68 interrupt-parent = <&gsc>; 69 69 interrupts = <2>; 70 70 }; 71 71 72 - tamper { 72 + key-tamper { 73 73 label = "tamper"; 74 74 linux,code = <BTN_4>; 75 75 interrupt-parent = <&gsc>; ··· 651 651 pinctrl-names = "default"; 652 652 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 653 653 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 654 - cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; 654 + cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 655 655 uart-has-rtscts; 656 656 status = "okay"; 657 657 };
+3 -3
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
··· 33 33 gpio-keys { 34 34 compatible = "gpio-keys"; 35 35 36 - user-pb { 36 + key-user-pb { 37 37 label = "user_pb"; 38 38 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 39 39 linux,code = <BTN_0>; 40 40 }; 41 41 42 - user-pb1x { 42 + key-user-pb1x { 43 43 label = "user_pb1x"; 44 44 linux,code = <BTN_1>; 45 45 interrupt-parent = <&gsc>; ··· 53 53 interrupts = <1>; 54 54 }; 55 55 56 - eeprom-wp { 56 + key-eeprom-wp { 57 57 label = "eeprom_wp"; 58 58 linux,code = <BTN_3>; 59 59 interrupt-parent = <&gsc>;
+9 -1
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
··· 43 43 pinctrl-names = "default"; 44 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 45 46 - wakeup { 46 + key-wakeup { 47 47 debounce-interval = <10>; 48 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 49 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; ··· 152 152 153 153 &A53_3 { 154 154 cpu-supply = <&reg_vdd_arm>; 155 + }; 156 + 157 + &cpu_alert0 { 158 + temperature = <95000>; 159 + }; 160 + 161 + &cpu_crit0 { 162 + temperature = <105000>; 155 163 }; 156 164 157 165 &ddrc {
+11 -5
arch/arm64/boot/dts/freescale/imx8mm.dtsi
··· 212 212 clk_ext4: clock-ext4 { 213 213 compatible = "fixed-clock"; 214 214 #clock-cells = <0>; 215 - clock-frequency= <133000000>; 215 + clock-frequency = <133000000>; 216 216 clock-output-names = "clk_ext4"; 217 217 }; 218 218 ··· 287 287 clock-names = "main_clk"; 288 288 }; 289 289 290 - soc@0 { 290 + soc: soc@0 { 291 291 compatible = "fsl,imx8mm-soc", "simple-bus"; 292 292 #address-cells = <1>; 293 293 #size-cells = <1>; ··· 602 602 wakeup-source; 603 603 status = "disabled"; 604 604 }; 605 + 606 + snvs_lpgpr: snvs-lpgpr { 607 + compatible = "fsl,imx8mm-snvs-lpgpr", 608 + "fsl,imx7d-snvs-lpgpr"; 609 + }; 605 610 }; 606 611 607 612 clk: clock-controller@30380000 { ··· 916 911 compatible = "fsl,sec-v4.0-job-ring"; 917 912 reg = <0x1000 0x1000>; 918 913 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 914 + status = "disabled"; 919 915 }; 920 916 921 917 sec_jr1: jr@2000 { ··· 1001 995 <&clk IMX8MM_CLK_USDHC1_ROOT>; 1002 996 clock-names = "ipg", "ahb", "per"; 1003 997 fsl,tuning-start-tap = <20>; 1004 - fsl,tuning-step= <2>; 998 + fsl,tuning-step = <2>; 1005 999 bus-width = <4>; 1006 1000 status = "disabled"; 1007 1001 }; ··· 1015 1009 <&clk IMX8MM_CLK_USDHC2_ROOT>; 1016 1010 clock-names = "ipg", "ahb", "per"; 1017 1011 fsl,tuning-start-tap = <20>; 1018 - fsl,tuning-step= <2>; 1012 + fsl,tuning-step = <2>; 1019 1013 bus-width = <4>; 1020 1014 status = "disabled"; 1021 1015 }; ··· 1029 1023 <&clk IMX8MM_CLK_USDHC3_ROOT>; 1030 1024 clock-names = "ipg", "ahb", "per"; 1031 1025 fsl,tuning-start-tap = <20>; 1032 - fsl,tuning-step= <2>; 1026 + fsl,tuning-step = <2>; 1033 1027 bus-width = <4>; 1034 1028 status = "disabled"; 1035 1029 };
+2 -2
arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
··· 146 146 }; 147 147 148 148 &easrc { 149 - fsl,asrc-rate = <48000>; 149 + fsl,asrc-rate = <48000>; 150 150 status = "okay"; 151 151 }; 152 152 ··· 182 182 &usbotg1 { 183 183 vbus-supply = <&reg_usb_otg_vbus>; 184 184 disable-over-current; 185 - dr_mode="otg"; 185 + dr_mode = "otg"; 186 186 status = "okay"; 187 187 }; 188 188
+44 -1
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
··· 47 47 linux,autosuspend-period = <125>; 48 48 }; 49 49 50 + audio_codec_bt_sco: audio-codec-bt-sco { 51 + compatible = "linux,bt-sco"; 52 + #sound-dai-cells = <1>; 53 + }; 54 + 50 55 wm8524: audio-codec { 51 56 #sound-dai-cells = <0>; 52 57 compatible = "wlf,wm8524"; ··· 60 55 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 61 56 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; 62 57 clock-names = "mclk"; 58 + }; 59 + 60 + sound-bt-sco { 61 + compatible = "simple-audio-card"; 62 + simple-audio-card,name = "bt-sco-audio"; 63 + simple-audio-card,format = "dsp_a"; 64 + simple-audio-card,bitclock-inversion; 65 + simple-audio-card,frame-master = <&btcpu>; 66 + simple-audio-card,bitclock-master = <&btcpu>; 67 + 68 + btcpu: simple-audio-card,cpu { 69 + sound-dai = <&sai2>; 70 + dai-tdm-slot-num = <2>; 71 + dai-tdm-slot-width = <16>; 72 + }; 73 + 74 + simple-audio-card,codec { 75 + sound-dai = <&audio_codec_bt_sco 1>; 76 + }; 63 77 }; 64 78 65 79 sound-wm8524 { ··· 102 78 }; 103 79 104 80 &easrc { 105 - fsl,asrc-rate = <48000>; 81 + fsl,asrc-rate = <48000>; 106 82 status = "okay"; 107 83 }; 108 84 ··· 205 181 gpio-controller; 206 182 #gpio-cells = <2>; 207 183 }; 184 + }; 185 + 186 + &sai2 { 187 + #sound-dai-cells = <0>; 188 + pinctrl-names = "default"; 189 + pinctrl-0 = <&pinctrl_sai2>; 190 + assigned-clocks = <&clk IMX8MN_CLK_SAI2>; 191 + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 192 + assigned-clock-rates = <24576000>; 193 + status = "okay"; 208 194 }; 209 195 210 196 &sai3 { ··· 385 351 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 386 352 fsl,pins = < 387 353 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 354 + >; 355 + }; 356 + 357 + pinctrl_sai2: sai2grp { 358 + fsl,pins = < 359 + MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 360 + MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 361 + MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 362 + MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 388 363 >; 389 364 }; 390 365
+3 -3
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
··· 26 26 gpio-keys { 27 27 compatible = "gpio-keys"; 28 28 29 - back { 29 + key-back { 30 30 label = "Back"; 31 31 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; 32 32 linux,code = <KEY_BACK>; 33 33 }; 34 34 35 - home { 35 + key-home { 36 36 label = "Home"; 37 37 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; 38 38 linux,code = <KEY_HOME>; 39 39 }; 40 40 41 - menu { 41 + key-menu { 42 42 label = "Menu"; 43 43 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; 44 44 linux,code = <KEY_MENU>;
+4 -4
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
··· 39 39 gpio-keys { 40 40 compatible = "gpio-keys"; 41 41 42 - user-pb { 42 + key-user-pb { 43 43 label = "user_pb"; 44 44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 45 45 linux,code = <BTN_0>; 46 46 }; 47 47 48 - user-pb1x { 48 + key-user-pb1x { 49 49 label = "user_pb1x"; 50 50 linux,code = <BTN_1>; 51 51 interrupt-parent = <&gsc>; ··· 59 59 interrupts = <1>; 60 60 }; 61 61 62 - eeprom-wp { 62 + key-eeprom-wp { 63 63 label = "eeprom_wp"; 64 64 linux,code = <BTN_3>; 65 65 interrupt-parent = <&gsc>; 66 66 interrupts = <2>; 67 67 }; 68 68 69 - tamper { 69 + key-tamper { 70 70 label = "tamper"; 71 71 linux,code = <BTN_4>; 72 72 interrupt-parent = <&gsc>;
+7 -6
arch/arm64/boot/dts/freescale/imx8mn.dtsi
··· 212 212 clk_ext4: clock-ext4 { 213 213 compatible = "fixed-clock"; 214 214 #clock-cells = <0>; 215 - clock-frequency= <133000000>; 215 + clock-frequency = <133000000>; 216 216 clock-output-names = "clk_ext4"; 217 217 }; 218 218 ··· 269 269 arm,no-tick-in-suspend; 270 270 }; 271 271 272 - soc@0 { 272 + soc: soc@0 { 273 273 compatible = "fsl,imx8mn-soc", "simple-bus"; 274 274 #address-cells = <1>; 275 275 #size-cells = <1>; ··· 422 422 "ctx2_rx", "ctx2_tx", 423 423 "ctx3_rx", "ctx3_tx"; 424 424 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 425 - fsl,asrc-rate = <8000>; 425 + fsl,asrc-rate = <8000>; 426 426 fsl,asrc-format = <2>; 427 427 status = "disabled"; 428 428 }; ··· 857 857 compatible = "fsl,sec-v4.0-job-ring"; 858 858 reg = <0x1000 0x1000>; 859 859 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 860 + status = "disabled"; 860 861 }; 861 862 862 863 sec_jr1: jr@2000 { ··· 942 941 <&clk IMX8MN_CLK_USDHC1_ROOT>; 943 942 clock-names = "ipg", "ahb", "per"; 944 943 fsl,tuning-start-tap = <20>; 945 - fsl,tuning-step= <2>; 944 + fsl,tuning-step = <2>; 946 945 bus-width = <4>; 947 946 status = "disabled"; 948 947 }; ··· 956 955 <&clk IMX8MN_CLK_USDHC2_ROOT>; 957 956 clock-names = "ipg", "ahb", "per"; 958 957 fsl,tuning-start-tap = <20>; 959 - fsl,tuning-step= <2>; 958 + fsl,tuning-step = <2>; 960 959 bus-width = <4>; 961 960 status = "disabled"; 962 961 }; ··· 970 969 <&clk IMX8MN_CLK_USDHC3_ROOT>; 971 970 clock-names = "ipg", "ahb", "per"; 972 971 fsl,tuning-start-tap = <20>; 973 - fsl,tuning-step= <2>; 972 + fsl,tuning-step = <2>; 974 973 bus-width = <4>; 975 974 status = "disabled"; 976 975 };
+163
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (C) 2022 Marek Vasut <marex@denx.de> 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include <dt-bindings/leds/common.h> 9 + #include <dt-bindings/net/qca-ar803x.h> 10 + #include <dt-bindings/phy/phy-imx8-pcie.h> 11 + #include "imx8mp-dhcom-som.dtsi" 12 + 13 + / { 14 + model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)"; 15 + compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp"; 16 + 17 + chosen { 18 + stdout-path = &uart1; 19 + }; 20 + 21 + gpio-keys { 22 + compatible = "gpio-keys"; 23 + 24 + button-0 { 25 + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */ 26 + label = "TA1-GPIO-A"; 27 + linux,code = <KEY_A>; 28 + pinctrl-0 = <&pinctrl_dhcom_a>; 29 + pinctrl-names = "default"; 30 + wakeup-source; 31 + }; 32 + 33 + button-1 { 34 + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */ 35 + label = "TA2-GPIO-B"; 36 + linux,code = <KEY_B>; 37 + pinctrl-0 = <&pinctrl_dhcom_b>; 38 + pinctrl-names = "default"; 39 + wakeup-source; 40 + }; 41 + 42 + button-2 { 43 + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ 44 + label = "TA3-GPIO-C"; 45 + linux,code = <KEY_C>; 46 + pinctrl-0 = <&pinctrl_dhcom_c>; 47 + pinctrl-names = "default"; 48 + wakeup-source; 49 + }; 50 + 51 + button-3 { 52 + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */ 53 + label = "TA4-GPIO-D"; 54 + linux,code = <KEY_D>; 55 + pinctrl-0 = <&pinctrl_dhcom_d>; 56 + pinctrl-names = "default"; 57 + wakeup-source; 58 + }; 59 + }; 60 + 61 + led { 62 + compatible = "gpio-leds"; 63 + 64 + led-0 { 65 + color = <LED_COLOR_ID_GREEN>; 66 + default-state = "off"; 67 + function = LED_FUNCTION_INDICATOR; 68 + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */ 69 + pinctrl-0 = <&pinctrl_dhcom_e>; 70 + pinctrl-names = "default"; 71 + }; 72 + 73 + led-1 { 74 + color = <LED_COLOR_ID_GREEN>; 75 + default-state = "off"; 76 + function = LED_FUNCTION_INDICATOR; 77 + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */ 78 + pinctrl-0 = <&pinctrl_dhcom_f>; 79 + pinctrl-names = "default"; 80 + }; 81 + 82 + led-2 { 83 + color = <LED_COLOR_ID_GREEN>; 84 + default-state = "off"; 85 + function = LED_FUNCTION_INDICATOR; 86 + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */ 87 + pinctrl-0 = <&pinctrl_dhcom_h>; 88 + pinctrl-names = "default"; 89 + }; 90 + 91 + led-3 { 92 + color = <LED_COLOR_ID_GREEN>; 93 + default-state = "off"; 94 + function = LED_FUNCTION_INDICATOR; 95 + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ 96 + pinctrl-0 = <&pinctrl_dhcom_i>; 97 + pinctrl-names = "default"; 98 + }; 99 + }; 100 + }; 101 + 102 + /* 103 + * PDK2 carrier board uses SoM with KSZ9131 populated and connected to 104 + * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node. 105 + */ 106 + /delete-node/ &ethphy0f; 107 + 108 + /* 109 + * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC 110 + * ethernet RGMII interface. The SoM is not populated with second FEC PHY. 111 + */ 112 + /delete-node/ &ethphy1f; 113 + 114 + &fec { /* Second ethernet */ 115 + phy-handle = <&ethphypdk>; 116 + 117 + mdio { 118 + ethphypdk: ethernet-phy@7 { /* KSZ 9021 */ 119 + compatible = "ethernet-phy-ieee802.3-c22"; 120 + pinctrl-0 = <&pinctrl_ethphy1>; 121 + pinctrl-names = "default"; 122 + interrupt-parent = <&gpio4>; 123 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 124 + max-speed = <100>; 125 + reg = <7>; 126 + reset-assert-us = <1000>; 127 + reset-deassert-us = <1000>; 128 + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 129 + rxc-skew-ps = <3000>; 130 + rxd0-skew-ps = <0>; 131 + rxd1-skew-ps = <0>; 132 + rxd2-skew-ps = <0>; 133 + rxd3-skew-ps = <0>; 134 + rxdv-skew-ps = <0>; 135 + txc-skew-ps = <3000>; 136 + txd0-skew-ps = <0>; 137 + txd1-skew-ps = <0>; 138 + txd2-skew-ps = <0>; 139 + txd3-skew-ps = <0>; 140 + txen-skew-ps = <0>; 141 + }; 142 + }; 143 + }; 144 + 145 + &flexcan1 { 146 + status = "okay"; 147 + }; 148 + 149 + &usb3_1 { 150 + fsl,over-current-active-low; 151 + }; 152 + 153 + &iomuxc { 154 + /* 155 + * GPIO_A,B,C,D are connected to buttons. 156 + * GPIO_E,F,H,I are connected to LEDs. 157 + * GPIO_M is connected to CLKOUT2. 158 + */ 159 + pinctrl-0 = <&pinctrl_hog_base 160 + &pinctrl_dhcom_g &pinctrl_dhcom_j 161 + &pinctrl_dhcom_k &pinctrl_dhcom_l 162 + &pinctrl_dhcom_int>; 163 + };
+1030
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de> 4 + */ 5 + 6 + #include "imx8mp.dtsi" 7 + 8 + / { 9 + model = "DH electronics i.MX8M Plus DHCOM SoM"; 10 + compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp"; 11 + 12 + aliases { 13 + ethernet0 = &eqos; 14 + ethernet1 = &fec; 15 + rtc0 = &rv3032; 16 + rtc1 = &snvs_rtc; 17 + spi0 = &flexspi; 18 + }; 19 + 20 + memory@40000000 { 21 + device_type = "memory"; 22 + /* Memory size 512 MiB..8 GiB will be filled by U-Boot */ 23 + reg = <0x0 0x40000000 0 0x08000000>; 24 + }; 25 + 26 + reg_eth_vio: regulator-eth-vio { 27 + compatible = "regulator-fixed"; 28 + gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; 29 + pinctrl-0 = <&pinctrl_enet_vio>; 30 + pinctrl-names = "default"; 31 + regulator-always-on; 32 + regulator-boot-on; 33 + regulator-min-microvolt = <3300000>; 34 + regulator-max-microvolt = <3300000>; 35 + regulator-name = "eth_vio"; 36 + vin-supply = <&buck4>; 37 + }; 38 + 39 + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 40 + compatible = "regulator-fixed"; 41 + enable-active-high; 42 + gpio = <&gpio2 19 0>; /* SD2_RESET */ 43 + off-on-delay-us = <12000>; 44 + pinctrl-names = "default"; 45 + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 46 + regulator-max-microvolt = <3300000>; 47 + regulator-min-microvolt = <3300000>; 48 + regulator-name = "VDD_3V3_SD"; 49 + startup-delay-us = <100>; 50 + vin-supply = <&buck4>; 51 + }; 52 + }; 53 + 54 + &A53_0 { 55 + cpu-supply = <&buck2>; 56 + }; 57 + 58 + &A53_1 { 59 + cpu-supply = <&buck2>; 60 + }; 61 + 62 + &A53_2 { 63 + cpu-supply = <&buck2>; 64 + }; 65 + 66 + &A53_3 { 67 + cpu-supply = <&buck2>; 68 + }; 69 + 70 + &ecspi1 { 71 + pinctrl-names = "default"; 72 + pinctrl-0 = <&pinctrl_ecspi1>; 73 + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 74 + status = "disabled"; 75 + }; 76 + 77 + &ecspi2 { 78 + pinctrl-names = "default"; 79 + pinctrl-0 = <&pinctrl_ecspi2>; 80 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 81 + status = "disabled"; 82 + }; 83 + 84 + &eqos { /* First ethernet */ 85 + pinctrl-names = "default"; 86 + pinctrl-0 = <&pinctrl_eqos>; 87 + phy-handle = <&ethphy0g>; 88 + phy-mode = "rgmii-id"; 89 + status = "okay"; 90 + 91 + mdio { 92 + compatible = "snps,dwmac-mdio"; 93 + #address-cells = <1>; 94 + #size-cells = <0>; 95 + 96 + /* Up to one of these two PHYs may be populated. */ 97 + ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ 98 + compatible = "ethernet-phy-id0007.c110", 99 + "ethernet-phy-ieee802.3-c22"; 100 + interrupt-parent = <&gpio3>; 101 + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 102 + pinctrl-0 = <&pinctrl_ethphy0>; 103 + pinctrl-names = "default"; 104 + reg = <1>; 105 + reset-assert-us = <1000>; 106 + reset-deassert-us = <1000>; 107 + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 108 + /* Non-default PHY population option. */ 109 + status = "disabled"; 110 + }; 111 + 112 + ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */ 113 + compatible = "ethernet-phy-id0022.1642", 114 + "ethernet-phy-ieee802.3-c22"; 115 + interrupt-parent = <&gpio3>; 116 + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 117 + micrel,led-mode = <0>; 118 + pinctrl-0 = <&pinctrl_ethphy0>; 119 + pinctrl-names = "default"; 120 + reg = <5>; 121 + reset-assert-us = <1000>; 122 + reset-deassert-us = <1000>; 123 + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 124 + /* Default PHY population option. */ 125 + status = "okay"; 126 + }; 127 + }; 128 + }; 129 + 130 + &fec { /* Second ethernet */ 131 + pinctrl-names = "default"; 132 + pinctrl-0 = <&pinctrl_fec>; 133 + phy-handle = <&ethphy1f>; 134 + phy-mode = "rgmii"; 135 + fsl,magic-packet; 136 + status = "okay"; 137 + 138 + mdio { 139 + #address-cells = <1>; 140 + #size-cells = <0>; 141 + 142 + /* Up to one PHY may be populated. */ 143 + ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */ 144 + compatible = "ethernet-phy-id0007.c110", 145 + "ethernet-phy-ieee802.3-c22"; 146 + interrupt-parent = <&gpio4>; 147 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 148 + pinctrl-0 = <&pinctrl_ethphy1>; 149 + pinctrl-names = "default"; 150 + reg = <1>; 151 + reset-assert-us = <1000>; 152 + reset-deassert-us = <1000>; 153 + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 154 + /* Non-default PHY population option. */ 155 + status = "disabled"; 156 + }; 157 + }; 158 + }; 159 + 160 + &flexcan1 { 161 + pinctrl-names = "default"; 162 + pinctrl-0 = <&pinctrl_flexcan1>; 163 + status = "disabled"; 164 + }; 165 + 166 + &flexcan2 { 167 + pinctrl-names = "default"; 168 + pinctrl-0 = <&pinctrl_flexcan2>; 169 + status = "disabled"; 170 + }; 171 + 172 + &flexspi { 173 + pinctrl-names = "default"; 174 + pinctrl-0 = <&pinctrl_flexspi>; 175 + status = "okay"; 176 + 177 + flash@0 { /* W25Q128JWPIM */ 178 + compatible = "jedec,spi-nor"; 179 + reg = <0>; 180 + spi-max-frequency = <80000000>; 181 + spi-tx-bus-width = <4>; 182 + spi-rx-bus-width = <4>; 183 + }; 184 + }; 185 + 186 + &gpio1 { 187 + gpio-line-names = 188 + "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L", 189 + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", 190 + "", "", "", "", "", "", "", "", 191 + "", "", "", "", "", "", "", ""; 192 + }; 193 + 194 + &gpio2 { 195 + gpio-line-names = 196 + "", "", "", "", "", "", "", "", 197 + "", "", "", "DHCOM-K", "", "", "", "", 198 + "", "", "", "", "DHCOM-INT", "", "", "", 199 + "", "", "", "", "", "", "", ""; 200 + }; 201 + 202 + &gpio3 { 203 + gpio-line-names = 204 + "", "", "", "", "", "", "", "", 205 + "", "", "", "", "", "", "SOM-HW0", "", 206 + "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", 207 + "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; 208 + }; 209 + 210 + &gpio4 { 211 + gpio-line-names = 212 + "", "", "", "", "", "", "", "", 213 + "", "", "", "", "", "", "", "", 214 + "", "", "", "SOM-HW1", "", "", "", "", 215 + "", "", "", "DHCOM-D", "", "", "", ""; 216 + }; 217 + 218 + &gpio5 { 219 + gpio-line-names = 220 + "", "", "DHCOM-C", "", "", "", "", "", 221 + "", "", "", "", "", "", "", "", 222 + "", "", "", "", "", "", "DHCOM-E", "DHCOM-F", 223 + "", "", "", "", "", "", "", ""; 224 + }; 225 + 226 + &i2c3 { 227 + clock-frequency = <100000>; 228 + pinctrl-names = "default", "gpio"; 229 + pinctrl-0 = <&pinctrl_i2c3>; 230 + pinctrl-1 = <&pinctrl_i2c3_gpio>; 231 + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 232 + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 233 + status = "okay"; 234 + 235 + pmic: pmic@25 { 236 + compatible = "nxp,pca9450c"; 237 + reg = <0x25>; 238 + pinctrl-names = "default"; 239 + pinctrl-0 = <&pinctrl_pmic>; 240 + interrupt-parent = <&gpio1>; 241 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 242 + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 243 + 244 + /* 245 + * i.MX 8M Plus Data Sheet for Consumer Products 246 + * 3.1.4 Operating ranges 247 + * MIMX8ML8CVNKZAB 248 + */ 249 + regulators { 250 + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ 251 + regulator-compatible = "BUCK1"; 252 + regulator-min-microvolt = <850000>; 253 + regulator-max-microvolt = <1000000>; 254 + regulator-ramp-delay = <3125>; 255 + regulator-always-on; 256 + regulator-boot-on; 257 + }; 258 + 259 + buck2: BUCK2 { /* VDD_ARM */ 260 + regulator-compatible = "BUCK2"; 261 + regulator-min-microvolt = <850000>; 262 + regulator-max-microvolt = <1000000>; 263 + regulator-ramp-delay = <3125>; 264 + regulator-always-on; 265 + regulator-boot-on; 266 + }; 267 + 268 + buck4: BUCK4 { /* VDD_3V3 */ 269 + regulator-compatible = "BUCK4"; 270 + regulator-min-microvolt = <3300000>; 271 + regulator-max-microvolt = <3300000>; 272 + regulator-always-on; 273 + regulator-boot-on; 274 + }; 275 + 276 + buck5: BUCK5 { /* VDD_1V8 */ 277 + regulator-compatible = "BUCK5"; 278 + regulator-min-microvolt = <1800000>; 279 + regulator-max-microvolt = <1800000>; 280 + regulator-always-on; 281 + regulator-boot-on; 282 + }; 283 + 284 + buck6: BUCK6 { /* NVCC_DRAM_1V1 */ 285 + regulator-compatible = "BUCK6"; 286 + regulator-min-microvolt = <1100000>; 287 + regulator-max-microvolt = <1100000>; 288 + regulator-always-on; 289 + regulator-boot-on; 290 + }; 291 + 292 + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ 293 + regulator-compatible = "LDO1"; 294 + regulator-min-microvolt = <1800000>; 295 + regulator-max-microvolt = <1800000>; 296 + regulator-always-on; 297 + regulator-boot-on; 298 + }; 299 + 300 + ldo3: LDO3 { /* VDDA_1V8 */ 301 + regulator-compatible = "LDO3"; 302 + regulator-min-microvolt = <1800000>; 303 + regulator-max-microvolt = <1800000>; 304 + regulator-always-on; 305 + regulator-boot-on; 306 + }; 307 + 308 + ldo4: LDO4 { /* PMIC_LDO4 */ 309 + regulator-compatible = "LDO4"; 310 + regulator-min-microvolt = <3300000>; 311 + regulator-max-microvolt = <3300000>; 312 + }; 313 + 314 + ldo5: LDO5 { /* NVCC_SD2 */ 315 + regulator-compatible = "LDO5"; 316 + regulator-min-microvolt = <1800000>; 317 + regulator-max-microvolt = <3300000>; 318 + }; 319 + }; 320 + }; 321 + 322 + adc@48 { 323 + compatible = "ti,tla2024"; 324 + reg = <0x48>; 325 + #address-cells = <1>; 326 + #size-cells = <0>; 327 + 328 + channel@0 { /* Voltage over AIN0 and AIN1. */ 329 + reg = <0>; 330 + }; 331 + 332 + channel@1 { /* Voltage over AIN0 and AIN3. */ 333 + reg = <1>; 334 + }; 335 + 336 + channel@2 { /* Voltage over AIN1 and AIN3. */ 337 + reg = <2>; 338 + }; 339 + 340 + channel@3 { /* Voltage over AIN2 and AIN3. */ 341 + reg = <3>; 342 + }; 343 + 344 + channel@4 { /* Voltage over AIN0 and GND. */ 345 + reg = <4>; 346 + }; 347 + 348 + channel@5 { /* Voltage over AIN1 and GND. */ 349 + reg = <5>; 350 + }; 351 + 352 + channel@6 { /* Voltage over AIN2 and GND. */ 353 + reg = <6>; 354 + }; 355 + 356 + channel@7 { /* Voltage over AIN3 and GND. */ 357 + reg = <7>; 358 + }; 359 + }; 360 + 361 + touchscreen@49 { 362 + compatible = "ti,tsc2004"; 363 + reg = <0x49>; 364 + interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>; 365 + pinctrl-names = "default"; 366 + pinctrl-0 = <&pinctrl_touch>; 367 + vio-supply = <&buck4>; 368 + }; 369 + 370 + eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ 371 + compatible = "atmel,24c02"; 372 + pagesize = <16>; 373 + reg = <0x50>; 374 + }; 375 + 376 + rv3032: rtc@51 { 377 + compatible = "microcrystal,rv3032"; 378 + reg = <0x51>; 379 + interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; 380 + pinctrl-names = "default"; 381 + pinctrl-0 = <&pinctrl_rtc>; 382 + }; 383 + 384 + eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ 385 + compatible = "atmel,24c02"; 386 + pagesize = <16>; 387 + reg = <0x53>; 388 + }; 389 + }; 390 + 391 + &i2c4 { 392 + clock-frequency = <100000>; 393 + pinctrl-names = "default", "gpio"; 394 + pinctrl-0 = <&pinctrl_i2c4>; 395 + pinctrl-1 = <&pinctrl_i2c4_gpio>; 396 + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 397 + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 398 + status = "okay"; 399 + }; 400 + 401 + &i2c5 { /* HDMI EDID bus */ 402 + clock-frequency = <100000>; 403 + pinctrl-names = "default", "gpio"; 404 + pinctrl-0 = <&pinctrl_i2c5>; 405 + pinctrl-1 = <&pinctrl_i2c5_gpio>; 406 + scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 407 + sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 408 + status = "okay"; 409 + }; 410 + 411 + &pwm1 { 412 + pinctrl-0 = <&pinctrl_pwm1>; 413 + pinctrl-names = "default"; 414 + status = "disabled"; 415 + }; 416 + 417 + &uart1 { 418 + /* CA53 console */ 419 + pinctrl-names = "default"; 420 + pinctrl-0 = <&pinctrl_uart1>; 421 + status = "okay"; 422 + }; 423 + 424 + &uart2 { 425 + /* Bluetooth */ 426 + pinctrl-names = "default"; 427 + pinctrl-0 = <&pinctrl_uart2>; 428 + uart-has-rtscts; 429 + status = "okay"; 430 + }; 431 + 432 + &uart3 { 433 + pinctrl-names = "default"; 434 + pinctrl-0 = <&pinctrl_uart3>; 435 + uart-has-rtscts; 436 + status = "okay"; 437 + }; 438 + 439 + &uart4 { 440 + pinctrl-names = "default"; 441 + pinctrl-0 = <&pinctrl_uart4>; 442 + status = "okay"; 443 + }; 444 + 445 + &usb3_phy0 { 446 + status = "okay"; 447 + }; 448 + 449 + &usb3_0 { 450 + status = "okay"; 451 + }; 452 + 453 + &usb_dwc3_0 { 454 + pinctrl-names = "default"; 455 + pinctrl-0 = <&pinctrl_usb0_vbus>; 456 + dr_mode = "otg"; 457 + status = "okay"; 458 + }; 459 + 460 + &usb3_phy1 { 461 + status = "okay"; 462 + }; 463 + 464 + &usb3_1 { 465 + status = "okay"; 466 + }; 467 + 468 + &usb_dwc3_1 { 469 + pinctrl-names = "default"; 470 + pinctrl-0 = <&pinctrl_usb1_vbus>; 471 + dr_mode = "host"; 472 + status = "okay"; 473 + }; 474 + 475 + /* SDIO WiFi */ 476 + &usdhc1 { 477 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 478 + pinctrl-0 = <&pinctrl_usdhc1>; 479 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 480 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 481 + vmmc-supply = <&buck4>; 482 + bus-width = <4>; 483 + non-removable; 484 + cap-power-off-card; 485 + keep-power-in-suspend; 486 + status = "okay"; 487 + 488 + #address-cells = <1>; 489 + #size-cells = <0>; 490 + 491 + brcmf: bcrmf@1 { /* muRata 2AE */ 492 + reg = <1>; 493 + compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; 494 + /* 495 + * The "host-wake" interrupt output is by default not 496 + * connected to the SoC, but can be connected on to 497 + * SoC pin on the carrier board. 498 + */ 499 + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 500 + }; 501 + }; 502 + 503 + /* SD slot */ 504 + &usdhc2 { 505 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 506 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 507 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 508 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 509 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 510 + vmmc-supply = <&reg_usdhc2_vmmc>; 511 + bus-width = <4>; 512 + status = "okay"; 513 + }; 514 + 515 + /* eMMC */ 516 + &usdhc3 { 517 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 518 + pinctrl-0 = <&pinctrl_usdhc3>; 519 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 520 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 521 + vmmc-supply = <&buck4>; 522 + vqmmc-supply = <&buck5>; 523 + bus-width = <8>; 524 + non-removable; 525 + status = "okay"; 526 + }; 527 + 528 + &wdog1 { 529 + pinctrl-names = "default"; 530 + pinctrl-0 = <&pinctrl_wdog>; 531 + fsl,ext-reset-output; 532 + status = "okay"; 533 + }; 534 + 535 + &iomuxc { 536 + pinctrl-0 = <&pinctrl_hog_base 537 + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c 538 + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f 539 + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i 540 + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l 541 + /* GPIO_M is connected to CLKOUT2 */ 542 + &pinctrl_dhcom_int>; 543 + pinctrl-names = "default"; 544 + 545 + pinctrl_dhcom_a: dhcom-a-grp { 546 + fsl,pins = < 547 + /* ENET_QOS_EVENT0-OUT */ 548 + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2 549 + >; 550 + }; 551 + 552 + pinctrl_dhcom_b: dhcom-b-grp { 553 + fsl,pins = < 554 + /* ENET_QOS_EVENT0-IN */ 555 + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2 556 + >; 557 + }; 558 + 559 + pinctrl_dhcom_c: dhcom-c-grp { 560 + fsl,pins = < 561 + /* GPIO_C */ 562 + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2 563 + >; 564 + }; 565 + 566 + pinctrl_dhcom_d: dhcom-d-grp { 567 + fsl,pins = < 568 + /* GPIO_D */ 569 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2 570 + >; 571 + }; 572 + 573 + pinctrl_dhcom_e: dhcom-e-grp { 574 + fsl,pins = < 575 + /* GPIO_E */ 576 + MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2 577 + >; 578 + }; 579 + 580 + pinctrl_dhcom_f: dhcom-f-grp { 581 + fsl,pins = < 582 + /* GPIO_F */ 583 + MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2 584 + >; 585 + }; 586 + 587 + pinctrl_dhcom_g: dhcom-g-grp { 588 + fsl,pins = < 589 + /* GPIO_G */ 590 + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 591 + >; 592 + }; 593 + 594 + pinctrl_dhcom_h: dhcom-h-grp { 595 + fsl,pins = < 596 + /* GPIO_H */ 597 + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2 598 + >; 599 + }; 600 + 601 + pinctrl_dhcom_i: dhcom-i-grp { 602 + fsl,pins = < 603 + /* CSI1_SYNC */ 604 + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 605 + >; 606 + }; 607 + 608 + pinctrl_dhcom_j: dhcom-j-grp { 609 + fsl,pins = < 610 + /* CSIx_#RST */ 611 + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2 612 + >; 613 + }; 614 + 615 + pinctrl_dhcom_k: dhcom-k-grp { 616 + fsl,pins = < 617 + /* CSIx_PWDN */ 618 + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2 619 + >; 620 + }; 621 + 622 + pinctrl_dhcom_l: dhcom-l-grp { 623 + fsl,pins = < 624 + /* CSI2_SYNC */ 625 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2 626 + >; 627 + }; 628 + 629 + pinctrl_dhcom_int: dhcom-int-grp { 630 + fsl,pins = < 631 + /* INT_HIGHEST_PRIO */ 632 + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2 633 + >; 634 + }; 635 + 636 + pinctrl_hog_base: dhcom-hog-base-grp { 637 + fsl,pins = < 638 + /* GPIOs for memory coding */ 639 + MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080 640 + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080 641 + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080 642 + /* GPIOs for hardware coding */ 643 + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080 644 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080 645 + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080 646 + >; 647 + }; 648 + 649 + pinctrl_ecspi1: dhcom-ecspi1-grp { 650 + fsl,pins = < 651 + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 652 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 653 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 654 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 655 + >; 656 + }; 657 + 658 + pinctrl_ecspi2: dhcom-ecspi2-grp { 659 + fsl,pins = < 660 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 661 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 662 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 663 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 664 + >; 665 + }; 666 + 667 + pinctrl_eqos: dhcom-eqos-grp { /* RGMII */ 668 + fsl,pins = < 669 + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 670 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 671 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 672 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 673 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 674 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 675 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 676 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 677 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 678 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 679 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 680 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 681 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 682 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 683 + >; 684 + }; 685 + 686 + pinctrl_enet_vio: dhcom-enet-vio-grp { 687 + fsl,pins = < 688 + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 689 + >; 690 + }; 691 + 692 + pinctrl_ethphy0: dhcom-ethphy0-grp { 693 + fsl,pins = < 694 + /* ENET1_#RST Reset */ 695 + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 696 + /* ENET1_#INT Interrupt */ 697 + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 698 + >; 699 + }; 700 + 701 + pinctrl_ethphy1: dhcom-ethphy1-grp { 702 + fsl,pins = < 703 + /* ENET1_#RST Reset */ 704 + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11 705 + /* ENET1_#INT Interrupt */ 706 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11 707 + >; 708 + }; 709 + 710 + pinctrl_fec: dhcom-fec-grp { 711 + fsl,pins = < 712 + MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f 713 + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 714 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 715 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 716 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 717 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 718 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 719 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 720 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 721 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 722 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 723 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 724 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 725 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 726 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 727 + MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f 728 + >; 729 + }; 730 + 731 + pinctrl_flexcan1: dhcom-flexcan1-grp { 732 + fsl,pins = < 733 + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 734 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 735 + >; 736 + }; 737 + 738 + pinctrl_flexcan2: dhcom-flexcan2-grp { 739 + fsl,pins = < 740 + MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 741 + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 742 + >; 743 + }; 744 + 745 + pinctrl_flexspi: dhcom-flexspi-grp { 746 + fsl,pins = < 747 + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 748 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 749 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 750 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 751 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 752 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 753 + >; 754 + }; 755 + 756 + pinctrl_hdmi: dhcom-hdmi-grp { 757 + fsl,pins = < 758 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 759 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 760 + >; 761 + }; 762 + 763 + pinctrl_i2c3: dhcom-i2c3-grp { 764 + fsl,pins = < 765 + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 766 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 767 + >; 768 + }; 769 + 770 + pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp { 771 + fsl,pins = < 772 + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 773 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 774 + >; 775 + }; 776 + 777 + pinctrl_i2c4: dhcom-i2c4-grp { 778 + fsl,pins = < 779 + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 780 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 781 + >; 782 + }; 783 + 784 + pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp { 785 + fsl,pins = < 786 + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 787 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 788 + >; 789 + }; 790 + 791 + pinctrl_i2c5: dhcom-i2c5-grp { 792 + fsl,pins = < 793 + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 794 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 795 + >; 796 + }; 797 + 798 + pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp { 799 + fsl,pins = < 800 + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 801 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 802 + >; 803 + }; 804 + 805 + pinctrl_pmic: dhcom-pmic-grp { 806 + fsl,pins = < 807 + /* PMIC_nINT */ 808 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 809 + >; 810 + }; 811 + 812 + pinctrl_pwm1: dhcom-pwm1-grp { 813 + fsl,pins = < 814 + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6 815 + >; 816 + }; 817 + 818 + pinctrl_rtc: dhcom-rtc-grp { 819 + fsl,pins = < 820 + /* RTC_#INT Interrupt */ 821 + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 822 + >; 823 + }; 824 + 825 + pinctrl_touch: dhcom-touch-grp { 826 + fsl,pins = < 827 + /* #TOUCH_INT */ 828 + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080 829 + >; 830 + }; 831 + 832 + pinctrl_uart1: dhcom-uart1-grp { 833 + fsl,pins = < 834 + /* Console UART */ 835 + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49 836 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49 837 + MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 838 + MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49 839 + >; 840 + }; 841 + 842 + pinctrl_uart2: dhcom-uart2-grp { 843 + fsl,pins = < 844 + /* Bluetooth UART */ 845 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 846 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 847 + MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 848 + MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 849 + >; 850 + }; 851 + 852 + pinctrl_uart3: dhcom-uart3-grp { 853 + fsl,pins = < 854 + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 855 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49 856 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49 857 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49 858 + >; 859 + }; 860 + 861 + pinctrl_uart4: dhcom-uart4-grp { 862 + fsl,pins = < 863 + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 864 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 865 + >; 866 + }; 867 + 868 + pinctrl_usb0_vbus: dhcom-usb0-grp { 869 + fsl,pins = < 870 + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 871 + >; 872 + }; 873 + 874 + pinctrl_usb1_vbus: dhcom-usb1-grp { 875 + fsl,pins = < 876 + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 877 + MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80 878 + >; 879 + }; 880 + 881 + pinctrl_usdhc1: dhcom-usdhc1-grp { 882 + fsl,pins = < 883 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 884 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 885 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 886 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 887 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 888 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 889 + /* BT_REG_EN */ 890 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 891 + /* WL_REG_EN */ 892 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 893 + >; 894 + }; 895 + 896 + pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp { 897 + fsl,pins = < 898 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 899 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 900 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 901 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 902 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 903 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 904 + /* BT_REG_EN */ 905 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 906 + /* WL_REG_EN */ 907 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 908 + >; 909 + }; 910 + 911 + pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp { 912 + fsl,pins = < 913 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 914 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 915 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 916 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 917 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 918 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 919 + /* BT_REG_EN */ 920 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 921 + /* WL_REG_EN */ 922 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 923 + >; 924 + }; 925 + 926 + pinctrl_usdhc2: dhcom-usdhc2-grp { 927 + fsl,pins = < 928 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 929 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 930 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 931 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 932 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 933 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 934 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 935 + >; 936 + }; 937 + 938 + pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp { 939 + fsl,pins = < 940 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 941 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 942 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 943 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 944 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 945 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 946 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 947 + >; 948 + }; 949 + 950 + pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp { 951 + fsl,pins = < 952 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 953 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 954 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 955 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 956 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 957 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 958 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 959 + >; 960 + }; 961 + 962 + pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp { 963 + fsl,pins = < 964 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 965 + >; 966 + }; 967 + 968 + pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp { 969 + fsl,pins = < 970 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 971 + >; 972 + }; 973 + 974 + pinctrl_usdhc3: dhcom-usdhc3-grp { 975 + fsl,pins = < 976 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 977 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 978 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 979 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 980 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 981 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 982 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 983 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 984 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 985 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 986 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 987 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 988 + >; 989 + }; 990 + 991 + pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp { 992 + fsl,pins = < 993 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 994 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 995 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 996 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 997 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 998 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 999 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 1000 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 1001 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1002 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1003 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1004 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1005 + >; 1006 + }; 1007 + 1008 + pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp { 1009 + fsl,pins = < 1010 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1011 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1012 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1013 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1014 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1015 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1016 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1017 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1018 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1019 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1020 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1021 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1022 + >; 1023 + }; 1024 + 1025 + pinctrl_wdog: dhcom-wdog-grp { 1026 + fsl,pins = < 1027 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 1028 + >; 1029 + }; 1030 + };
+27 -11
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
··· 67 67 }; 68 68 }; 69 69 70 - &flexcan1 { 71 - pinctrl-names = "default"; 72 - pinctrl-0 = <&pinctrl_flexcan1>; 73 - xceiver-supply = <&reg_can1_stby>; 74 - status = "okay"; 70 + &A53_0 { 71 + cpu-supply = <&reg_arm>; 75 72 }; 76 73 77 - &flexcan2 { 78 - pinctrl-names = "default"; 79 - pinctrl-0 = <&pinctrl_flexcan2>; 80 - xceiver-supply = <&reg_can2_stby>; 81 - status = "disabled";/* can2 pin conflict with pdm */ 74 + &A53_1 { 75 + cpu-supply = <&reg_arm>; 76 + }; 77 + 78 + &A53_2 { 79 + cpu-supply = <&reg_arm>; 80 + }; 81 + 82 + &A53_3 { 83 + cpu-supply = <&reg_arm>; 82 84 }; 83 85 84 86 &eqos { ··· 199 197 }; 200 198 }; 201 199 200 + &flexcan1 { 201 + pinctrl-names = "default"; 202 + pinctrl-0 = <&pinctrl_flexcan1>; 203 + xceiver-supply = <&reg_can1_stby>; 204 + status = "okay"; 205 + }; 206 + 207 + &flexcan2 { 208 + pinctrl-names = "default"; 209 + pinctrl-0 = <&pinctrl_flexcan2>; 210 + xceiver-supply = <&reg_can2_stby>; 211 + status = "disabled";/* can2 pin conflict with pdm */ 212 + }; 213 + 202 214 &i2c1 { 203 215 clock-frequency = <400000>; 204 216 pinctrl-names = "default"; ··· 237 221 regulator-ramp-delay = <3125>; 238 222 }; 239 223 240 - BUCK2 { 224 + reg_arm: BUCK2 { 241 225 regulator-name = "BUCK2"; 242 226 regulator-min-microvolt = <720000>; 243 227 regulator-max-microvolt = <1025000>;
+702
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright 2021-2022 TQ-Systems GmbH 4 + * Author: Alexander Stein <alexander.stein@tq-group.com> 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include <dt-bindings/leds/common.h> 10 + #include <dt-bindings/net/ti-dp83867.h> 11 + #include <dt-bindings/pwm/pwm.h> 12 + #include "imx8mp-tqma8mpql.dtsi" 13 + 14 + / { 15 + model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; 16 + compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 17 + 18 + chosen { 19 + stdout-path = &uart4; 20 + }; 21 + 22 + iio-hwmon { 23 + compatible = "iio-hwmon"; 24 + io-channels = <&adc 0>, <&adc 1>; 25 + }; 26 + 27 + aliases { 28 + mmc0 = &usdhc3; 29 + mmc1 = &usdhc2; 30 + mmc2 = &usdhc1; 31 + rtc0 = &pcf85063; 32 + rtc1 = &snvs_rtc; 33 + spi0 = &flexspi; 34 + spi1 = &ecspi1; 35 + spi2 = &ecspi2; 36 + spi3 = &ecspi3; 37 + }; 38 + 39 + backlight_lvds: backlight { 40 + compatible = "pwm-backlight"; 41 + pinctrl-names = "default"; 42 + pinctrl-0 = <&pinctrl_backlight>; 43 + pwms = <&pwm2 0 5000000 0>; 44 + brightness-levels = <0 4 8 16 32 64 128 255>; 45 + default-brightness-level = <7>; 46 + power-supply = <&reg_vcc_12v0>; 47 + enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 48 + status = "disabled"; 49 + }; 50 + 51 + gpio-keys { 52 + compatible = "gpio-keys"; 53 + pinctrl-names = "default"; 54 + pinctrl-0 = <&pinctrl_gpiobutton>; 55 + autorepeat; 56 + 57 + switch-1 { 58 + label = "S12"; 59 + linux,code = <BTN_0>; 60 + gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 61 + }; 62 + 63 + switch-2 { 64 + label = "S13"; 65 + linux,code = <BTN_1>; 66 + gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 67 + }; 68 + }; 69 + 70 + gpio-leds { 71 + compatible = "gpio-leds"; 72 + pinctrl-names = "default"; 73 + pinctrl-0 = <&pinctrl_gpioled>; 74 + 75 + led-0 { 76 + color = <LED_COLOR_ID_GREEN>; 77 + function = LED_FUNCTION_STATUS; 78 + function-enumerator = <0>; 79 + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 80 + linux,default-trigger = "default-on"; 81 + }; 82 + 83 + led-1 { 84 + color = <LED_COLOR_ID_GREEN>; 85 + function = LED_FUNCTION_HEARTBEAT; 86 + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 87 + linux,default-trigger = "heartbeat"; 88 + }; 89 + 90 + led-2 { 91 + color = <LED_COLOR_ID_YELLOW>; 92 + function = LED_FUNCTION_STATUS; 93 + function-enumerator = <1>; 94 + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 95 + }; 96 + }; 97 + 98 + display: display { 99 + /* 100 + * Display is not fixed, so compatible has to be added from 101 + * DT overlay 102 + */ 103 + pinctrl-names = "default"; 104 + pinctrl-0 = <&pinctrl_lvdsdisplay>; 105 + power-supply = <&reg_vcc_3v3>; 106 + enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 107 + backlight = <&backlight_lvds>; 108 + status = "disabled"; 109 + }; 110 + 111 + reg_usdhc2_vmmc: regulator-usdhc2 { 112 + compatible = "regulator-fixed"; 113 + pinctrl-names = "default"; 114 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 115 + regulator-name = "VSD_3V3"; 116 + regulator-min-microvolt = <3300000>; 117 + regulator-max-microvolt = <3300000>; 118 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 119 + enable-active-high; 120 + startup-delay-us = <100>; 121 + off-on-delay-us = <12000>; 122 + }; 123 + 124 + reg_vcc_12v0: regulator-12v0 { 125 + compatible = "regulator-fixed"; 126 + pinctrl-names = "default"; 127 + pinctrl-0 = <&pinctrl_reg12v0>; 128 + regulator-name = "VCC_12V0"; 129 + regulator-min-microvolt = <12000000>; 130 + regulator-max-microvolt = <12000000>; 131 + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 132 + enable-active-high; 133 + }; 134 + 135 + reg_vcc_3v3: regulator-3v3 { 136 + compatible = "regulator-fixed"; 137 + regulator-name = "VCC_3V3"; 138 + regulator-min-microvolt = <3300000>; 139 + regulator-max-microvolt = <3300000>; 140 + }; 141 + 142 + reserved-memory { 143 + #address-cells = <2>; 144 + #size-cells = <2>; 145 + ranges; 146 + 147 + ocram: ocram@900000 { 148 + no-map; 149 + reg = <0 0x900000 0 0x70000>; 150 + }; 151 + 152 + /* global autoconfigured region for contiguous allocations */ 153 + linux,cma { 154 + compatible = "shared-dma-pool"; 155 + reusable; 156 + size = <0 0x38000000>; 157 + alloc-ranges = <0 0x40000000 0 0xB0000000>; 158 + linux,cma-default; 159 + }; 160 + }; 161 + }; 162 + 163 + &ecspi1 { 164 + pinctrl-names = "default"; 165 + pinctrl-0 = <&pinctrl_ecspi1>; 166 + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 167 + status = "okay"; 168 + }; 169 + 170 + &ecspi2 { 171 + pinctrl-names = "default"; 172 + pinctrl-0 = <&pinctrl_ecspi2>; 173 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 174 + status = "okay"; 175 + }; 176 + 177 + &ecspi3 { 178 + pinctrl-names = "default"; 179 + pinctrl-0 = <&pinctrl_ecspi3>; 180 + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 181 + status = "okay"; 182 + 183 + adc: adc@0 { 184 + reg = <0>; 185 + compatible = "microchip,mcp3202"; 186 + /* 100 ksps * 18 */ 187 + spi-max-frequency = <1800000>; 188 + vref-supply = <&reg_vcc_3v3>; 189 + #io-channel-cells = <1>; 190 + }; 191 + }; 192 + 193 + &eqos { 194 + pinctrl-names = "default"; 195 + pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; 196 + phy-mode = "rgmii-id"; 197 + phy-handle = <&ethphy3>; 198 + status = "okay"; 199 + 200 + mdio { 201 + compatible = "snps,dwmac-mdio"; 202 + #address-cells = <1>; 203 + #size-cells = <0>; 204 + 205 + ethphy3: ethernet-phy@3 { 206 + compatible = "ethernet-phy-ieee802.3-c22"; 207 + reg = <3>; 208 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 209 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 210 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 211 + ti,dp83867-rxctrl-strap-quirk; 212 + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 213 + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 214 + reset-assert-us = <500000>; 215 + reset-deassert-us = <50000>; 216 + enet-phy-lane-no-swap; 217 + interrupt-parent = <&gpio4>; 218 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 219 + }; 220 + }; 221 + }; 222 + 223 + &fec { 224 + pinctrl-names = "default"; 225 + pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; 226 + phy-mode = "rgmii-id"; 227 + phy-handle = <&ethphy0>; 228 + fsl,magic-packet; 229 + status = "okay"; 230 + 231 + mdio { 232 + #address-cells = <1>; 233 + #size-cells = <0>; 234 + 235 + ethphy0: ethernet-phy@0 { 236 + compatible = "ethernet-phy-ieee802.3-c22"; 237 + reg = <0>; 238 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 239 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 240 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 241 + ti,dp83867-rxctrl-strap-quirk; 242 + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 243 + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 244 + reset-assert-us = <500000>; 245 + reset-deassert-us = <50000>; 246 + enet-phy-lane-no-swap; 247 + interrupt-parent = <&gpio4>; 248 + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 249 + }; 250 + }; 251 + }; 252 + 253 + &flexcan1 { 254 + pinctrl-names = "default"; 255 + pinctrl-0 = <&pinctrl_flexcan1>; 256 + xceiver-supply = <&reg_vcc_3v3>; 257 + status = "okay"; 258 + }; 259 + 260 + &flexcan2 { 261 + pinctrl-names = "default"; 262 + pinctrl-0 = <&pinctrl_flexcan2>; 263 + xceiver-supply = <&reg_vcc_3v3>; 264 + status = "okay"; 265 + }; 266 + 267 + &gpio1 { 268 + pinctrl-names = "default"; 269 + pinctrl-0 = <&pinctrl_gpio1>; 270 + 271 + gpio-line-names = "GPO1", "GPO0", "", "GPO3", 272 + "", "", "GPO2", "GPI0", 273 + "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", 274 + "OTG_PWR", "", "GPI2", "GPI3", 275 + "", "", "", "", 276 + "", "", "", "", 277 + "", "", "", "", 278 + "", "", "", ""; 279 + }; 280 + 281 + &gpio2 { 282 + pinctrl-names = "default"; 283 + pinctrl-0 = <&pinctrl_hoggpio2>; 284 + 285 + gpio-line-names = "", "", "", "", 286 + "", "", "VCC12V_EN", "PERST#", 287 + "", "", "CLKREQ#", "PEWAKE#", 288 + "USDHC2_CD", "", "", "", 289 + "", "", "", "V_SD3V3_EN", 290 + "", "", "", "", 291 + "", "", "", "", 292 + "", "", "", ""; 293 + 294 + perst-hog { 295 + gpio-hog; 296 + gpios = <7 0>; 297 + output-high; 298 + line-name = "PERST#"; 299 + }; 300 + 301 + clkreq-hog { 302 + gpio-hog; 303 + gpios = <10 0>; 304 + input; 305 + line-name = "CLKREQ#"; 306 + }; 307 + 308 + pewake-hog { 309 + gpio-hog; 310 + gpios = <11 0>; 311 + input; 312 + line-name = "PEWAKE#"; 313 + }; 314 + }; 315 + 316 + &gpio3 { 317 + gpio-line-names = "", "", "", "", 318 + "", "", "", "", 319 + "", "", "", "", 320 + "", "", "LVDS0_RESET#", "", 321 + "", "", "", "LVDS0_BLT_EN", 322 + "LVDS0_PWR_EN", "", "", "", 323 + "", "", "", "", 324 + "", "", "", ""; 325 + }; 326 + 327 + &gpio4 { 328 + pinctrl-names = "default"; 329 + pinctrl-0 = <&pinctrl_gpio4>; 330 + 331 + gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", 332 + "", "", "", "", 333 + "", "", "", "", 334 + "", "", "", "", 335 + "", "", "DP_IRQ", "DSI_EN", 336 + "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "", 337 + "", "", "", "FAN_PWR", 338 + "RTC_EVENT#", "CODEC_RST#", "", ""; 339 + }; 340 + 341 + &gpio5 { 342 + gpio-line-names = "", "", "", "LED2", 343 + "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", 344 + "CSI0_TRIGGER", "CSI0_ENABLE", "", "", 345 + "", "ECSPI2_SS0", "", "", 346 + "", "", "", "", 347 + "", "", "", "", 348 + "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", 349 + "", "", "", ""; 350 + }; 351 + 352 + &i2c2 { 353 + clock-frequency = <384000>; 354 + pinctrl-names = "default", "gpio"; 355 + pinctrl-0 = <&pinctrl_i2c2>; 356 + pinctrl-1 = <&pinctrl_i2c2_gpio>; 357 + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 358 + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 359 + status = "okay"; 360 + 361 + /* NXP SE97BTP with temperature sensor + eeprom */ 362 + se97_1c: temperature-sensor-eeprom@1c { 363 + compatible = "nxp,se97", "jedec,jc-42.4-temp"; 364 + reg = <0x1c>; 365 + }; 366 + 367 + at24c02_54: eeprom@54 { 368 + compatible = "nxp,se97b", "atmel,24c02"; 369 + reg = <0x54>; 370 + pagesize = <16>; 371 + vcc-supply = <&reg_vcc_3v3>; 372 + }; 373 + }; 374 + 375 + &i2c4 { 376 + clock-frequency = <384000>; 377 + pinctrl-names = "default", "gpio"; 378 + pinctrl-0 = <&pinctrl_i2c4>; 379 + pinctrl-1 = <&pinctrl_i2c4_gpio>; 380 + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 381 + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 382 + status = "okay"; 383 + }; 384 + 385 + &i2c6 { 386 + clock-frequency = <384000>; 387 + pinctrl-names = "default", "gpio"; 388 + pinctrl-0 = <&pinctrl_i2c6>; 389 + pinctrl-1 = <&pinctrl_i2c6_gpio>; 390 + scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 391 + sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 392 + status = "okay"; 393 + }; 394 + 395 + &pcf85063 { 396 + /* RTC_EVENT# is connected on MBa8MPxL */ 397 + interrupt-parent = <&gpio4>; 398 + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 399 + }; 400 + 401 + &pwm2 { 402 + pinctrl-names = "default"; 403 + pinctrl-0 = <&pinctrl_pwm2>; 404 + status = "disabled"; 405 + }; 406 + 407 + &pwm3 { 408 + pinctrl-names = "default"; 409 + pinctrl-0 = <&pinctrl_pwm3>; 410 + status = "okay"; 411 + }; 412 + 413 + &snvs_pwrkey { 414 + status = "okay"; 415 + }; 416 + 417 + &uart1 { 418 + pinctrl-names = "default"; 419 + pinctrl-0 = <&pinctrl_uart1>; 420 + assigned-clocks = <&clk IMX8MP_CLK_UART1>; 421 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 422 + status = "okay"; 423 + }; 424 + 425 + &uart2 { 426 + pinctrl-names = "default"; 427 + pinctrl-0 = <&pinctrl_uart2>; 428 + assigned-clocks = <&clk IMX8MP_CLK_UART2>; 429 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 430 + status = "okay"; 431 + }; 432 + 433 + &uart3 { 434 + pinctrl-names = "default"; 435 + pinctrl-0 = <&pinctrl_uart3>; 436 + assigned-clocks = <&clk IMX8MP_CLK_UART3>; 437 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 438 + status = "okay"; 439 + }; 440 + 441 + &uart4 { 442 + /* console */ 443 + pinctrl-names = "default"; 444 + pinctrl-0 = <&pinctrl_uart4>; 445 + status = "okay"; 446 + }; 447 + 448 + &usdhc2 { 449 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 450 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 451 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 452 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 453 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 454 + vmmc-supply = <&reg_usdhc2_vmmc>; 455 + no-mmc; 456 + no-sdio; 457 + disable-wp; 458 + bus-width = <4>; 459 + status = "okay"; 460 + }; 461 + 462 + &iomuxc { 463 + pinctrl_backlight: backlightgrp { 464 + fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; 465 + }; 466 + 467 + pinctrl_flexcan1: flexcan1grp { 468 + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, 469 + <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; 470 + }; 471 + 472 + pinctrl_flexcan2: flexcan2grp { 473 + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, 474 + <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; 475 + }; 476 + 477 + /* only on X57, primary used as CSI0 control signals */ 478 + pinctrl_ecspi1: ecspi1grp { 479 + fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, 480 + <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, 481 + <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, 482 + <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; 483 + }; 484 + 485 + /* on X63 and optionally on X57, can also be used as CSI1 control signals */ 486 + pinctrl_ecspi2: ecspi2grp { 487 + fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, 488 + <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, 489 + <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, 490 + <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; 491 + }; 492 + 493 + pinctrl_ecspi3: ecspi3grp { 494 + fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, 495 + <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, 496 + <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, 497 + <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; 498 + }; 499 + 500 + pinctrl_eqos: eqosgrp { 501 + fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 502 + <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 503 + <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 504 + <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 505 + <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 506 + <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 507 + <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 508 + <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 509 + <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 510 + <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 511 + <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 512 + <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 513 + <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 514 + <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 515 + }; 516 + 517 + pinctrl_eqos_event: eqosevtgrp { 518 + fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, 519 + <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; 520 + }; 521 + 522 + pinctrl_eqos_phy: eqosphygrp { 523 + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, 524 + <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; 525 + }; 526 + 527 + pinctrl_fec: fecgrp { 528 + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, 529 + <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, 530 + <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 531 + <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 532 + <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 533 + <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 534 + <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 535 + <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 536 + <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 537 + <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 538 + <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 539 + <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 540 + <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 541 + <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 542 + }; 543 + 544 + pinctrl_fec_event: fecevtgrp { 545 + fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, 546 + <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; 547 + }; 548 + 549 + pinctrl_fec_phy: fecphygrp { 550 + fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, 551 + <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; 552 + }; 553 + 554 + pinctrl_fec_phyalt: fecphyaltgrp { 555 + fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, 556 + <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; 557 + }; 558 + 559 + pinctrl_gpiobutton: gpiobuttongrp { 560 + fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, 561 + <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; 562 + }; 563 + 564 + pinctrl_gpioled: gpioledgrp { 565 + fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, 566 + <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, 567 + <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; 568 + }; 569 + 570 + pinctrl_gpio1: gpio1grp { 571 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, 572 + <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, 573 + <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, 574 + <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, 575 + <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, 576 + <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, 577 + <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, 578 + <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; 579 + }; 580 + 581 + pinctrl_gpio4: gpio4grp { 582 + fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, 583 + <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; 584 + }; 585 + 586 + pinctrl_hdmi: hdmigrp { 587 + fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 588 + <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 589 + <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, 590 + <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; 591 + }; 592 + 593 + pinctrl_hoggpio2: hoggpio2grp { 594 + fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, 595 + <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, 596 + <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; 597 + }; 598 + 599 + pinctrl_i2c2: i2c2grp { 600 + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 601 + <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 602 + }; 603 + 604 + pinctrl_i2c2_gpio: i2c2-gpiogrp { 605 + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 606 + <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 607 + }; 608 + 609 + pinctrl_i2c4: i2c4grp { 610 + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, 611 + <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; 612 + }; 613 + 614 + pinctrl_i2c4_gpio: i2c4-gpiogrp { 615 + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, 616 + <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; 617 + }; 618 + 619 + pinctrl_i2c6: i2c6grp { 620 + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 621 + <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 622 + }; 623 + 624 + pinctrl_i2c6_gpio: i2c6-gpiogrp { 625 + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 626 + <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 627 + }; 628 + 629 + pinctrl_lvdsdisplay: lvdsdisplaygrp { 630 + fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ 631 + }; 632 + 633 + /* LVDS Backlight */ 634 + pinctrl_pwm2: pwm2grp { 635 + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; 636 + }; 637 + 638 + /* FAN */ 639 + pinctrl_pwm3: pwm3grp { 640 + fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; 641 + }; 642 + 643 + pinctrl_reg12v0: reg12v0grp { 644 + fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ 645 + }; 646 + 647 + /* X61 */ 648 + pinctrl_uart1: uart1grp { 649 + fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, 650 + <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; 651 + }; 652 + 653 + /* X61 */ 654 + pinctrl_uart2: uart2grp { 655 + fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, 656 + <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; 657 + }; 658 + 659 + pinctrl_uart3: uart3grp { 660 + fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 661 + <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 662 + }; 663 + 664 + pinctrl_uart4: uart4grp { 665 + fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, 666 + <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; 667 + }; 668 + 669 + pinctrl_usdhc2: usdhc2grp { 670 + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 671 + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 672 + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 673 + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 674 + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 675 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 676 + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 677 + }; 678 + 679 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 680 + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 681 + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 682 + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 683 + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 684 + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 685 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 686 + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 687 + }; 688 + 689 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 690 + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 691 + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 692 + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 693 + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 694 + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 695 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 696 + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 697 + }; 698 + 699 + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 700 + fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; 701 + }; 702 + };
+284
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright 2021-2022 TQ-Systems GmbH 4 + * Author: Alexander Stein <alexander.stein@tq-group.com> 5 + */ 6 + 7 + #include "imx8mp.dtsi" 8 + 9 + / { 10 + model = "TQ-Systems i.MX8MPlus TQMa8MPxL"; 11 + compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 12 + 13 + memory@40000000 { 14 + device_type = "memory"; 15 + reg = <0x0 0x40000000 0 0x80000000>; 16 + }; 17 + 18 + /* identical to buck4_reg, but should never change */ 19 + reg_vcc3v3: regulator-vcc3v3 { 20 + compatible = "regulator-fixed"; 21 + regulator-name = "VCC3V3"; 22 + regulator-min-microvolt = <3300000>; 23 + regulator-max-microvolt = <3300000>; 24 + regulator-always-on; 25 + }; 26 + 27 + /* e-MMC IO, needed for HS modes */ 28 + reg_vcc1v8: regulator-vcc1v8 { 29 + compatible = "regulator-fixed"; 30 + regulator-name = "VCC1V8"; 31 + regulator-min-microvolt = <1800000>; 32 + regulator-max-microvolt = <1800000>; 33 + regulator-always-on; 34 + }; 35 + }; 36 + 37 + &A53_0 { 38 + cpu-supply = <&buck2_reg>; 39 + }; 40 + 41 + &flexspi { 42 + pinctrl-names = "default"; 43 + pinctrl-0 = <&pinctrl_flexspi0>; 44 + status = "okay"; 45 + 46 + flash0: flash@0 { 47 + reg = <0>; 48 + #address-cells = <1>; 49 + #size-cells = <1>; 50 + compatible = "jedec,spi-nor"; 51 + spi-max-frequency = <80000000>; 52 + spi-tx-bus-width = <1>; 53 + spi-rx-bus-width = <4>; 54 + }; 55 + }; 56 + 57 + &i2c1 { 58 + clock-frequency = <384000>; 59 + pinctrl-names = "default", "gpio"; 60 + pinctrl-0 = <&pinctrl_i2c1>; 61 + pinctrl-1 = <&pinctrl_i2c1_gpio>; 62 + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 63 + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 64 + status = "okay"; 65 + 66 + /* NXP SE97BTP with temperature sensor + eeprom */ 67 + se97: temperature-sensor-eeprom@1b { 68 + compatible = "nxp,se97", "jedec,jc-42.4-temp"; 69 + reg = <0x1b>; 70 + }; 71 + 72 + pmic: pmic@25 { 73 + reg = <0x25>; 74 + compatible = "nxp,pca9450c"; 75 + 76 + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ 77 + pinctrl-0 = <&pinctrl_pmic>; 78 + pinctrl-names = "default"; 79 + interrupt-parent = <&gpio1>; 80 + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 81 + 82 + regulators { 83 + /* V_0V85_SOC: 0.85 .. 0.95 */ 84 + buck1_reg: BUCK1 { 85 + regulator-name = "BUCK1"; 86 + regulator-min-microvolt = <850000>; 87 + regulator-max-microvolt = <950000>; 88 + regulator-boot-on; 89 + regulator-always-on; 90 + regulator-ramp-delay = <3125>; 91 + }; 92 + 93 + /* VDD_ARM */ 94 + buck2_reg: BUCK2 { 95 + regulator-name = "BUCK2"; 96 + regulator-min-microvolt = <850000>; 97 + regulator-max-microvolt = <1000000>; 98 + regulator-boot-on; 99 + regulator-always-on; 100 + nxp,dvs-run-voltage = <950000>; 101 + nxp,dvs-standby-voltage = <850000>; 102 + regulator-ramp-delay = <3125>; 103 + }; 104 + 105 + /* VCC3V3 -> VMMC, ... must not be changed */ 106 + buck4_reg: BUCK4 { 107 + regulator-name = "BUCK4"; 108 + regulator-min-microvolt = <3300000>; 109 + regulator-max-microvolt = <3300000>; 110 + regulator-boot-on; 111 + regulator-always-on; 112 + }; 113 + 114 + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ 115 + buck5_reg: BUCK5 { 116 + regulator-name = "BUCK5"; 117 + regulator-min-microvolt = <1800000>; 118 + regulator-max-microvolt = <1800000>; 119 + regulator-boot-on; 120 + regulator-always-on; 121 + }; 122 + 123 + /* V_1V1 -> RAM, ... must not be changed */ 124 + buck6_reg: BUCK6 { 125 + regulator-name = "BUCK6"; 126 + regulator-min-microvolt = <1100000>; 127 + regulator-max-microvolt = <1100000>; 128 + regulator-boot-on; 129 + regulator-always-on; 130 + }; 131 + 132 + /* V_1V8_SNVS */ 133 + ldo1_reg: LDO1 { 134 + regulator-name = "LDO1"; 135 + regulator-min-microvolt = <1800000>; 136 + regulator-max-microvolt = <1800000>; 137 + regulator-boot-on; 138 + regulator-always-on; 139 + }; 140 + 141 + /* V_1V8_ANA */ 142 + ldo3_reg: LDO3 { 143 + regulator-name = "LDO3"; 144 + regulator-min-microvolt = <1800000>; 145 + regulator-max-microvolt = <1800000>; 146 + regulator-boot-on; 147 + regulator-always-on; 148 + }; 149 + 150 + /* unused */ 151 + ldo4_reg: LDO4 { 152 + regulator-name = "LDO4"; 153 + regulator-min-microvolt = <800000>; 154 + regulator-max-microvolt = <3300000>; 155 + }; 156 + 157 + /* VCC SD IO - switched using SD2 VSELECT */ 158 + ldo5_reg: LDO5 { 159 + regulator-name = "LDO5"; 160 + regulator-min-microvolt = <1800000>; 161 + regulator-max-microvolt = <3300000>; 162 + }; 163 + }; 164 + }; 165 + 166 + pcf85063: rtc@51 { 167 + compatible = "nxp,pcf85063a"; 168 + reg = <0x51>; 169 + }; 170 + 171 + at24c02: eeprom@53 { 172 + compatible = "nxp,se97b", "atmel,24c02"; 173 + read-only; 174 + reg = <0x53>; 175 + pagesize = <16>; 176 + vcc-supply = <&reg_vcc3v3>; 177 + }; 178 + 179 + m24c64: eeprom@57 { 180 + compatible = "atmel,24c64"; 181 + reg = <0x57>; 182 + pagesize = <32>; 183 + vcc-supply = <&reg_vcc3v3>; 184 + }; 185 + }; 186 + 187 + &usdhc3 { 188 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 189 + pinctrl-0 = <&pinctrl_usdhc3>; 190 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 191 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 192 + bus-width = <8>; 193 + non-removable; 194 + no-sd; 195 + no-sdio; 196 + vmmc-supply = <&reg_vcc3v3>; 197 + vqmmc-supply = <&reg_vcc1v8>; 198 + status = "okay"; 199 + }; 200 + 201 + &wdog1 { 202 + pinctrl-names = "default"; 203 + pinctrl-0 = <&pinctrl_wdog>; 204 + fsl,ext-reset-output; 205 + status = "okay"; 206 + }; 207 + 208 + &iomuxc { 209 + pinctrl_flexspi0: flexspi0grp { 210 + fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x142>, 211 + <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, 212 + <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, 213 + <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, 214 + <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, 215 + <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>; 216 + }; 217 + 218 + pinctrl_i2c1: i2c1grp { 219 + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e2>, 220 + <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e2>; 221 + }; 222 + 223 + pinctrl_i2c1_gpio: i2c1-gpiogrp { 224 + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001e2>, 225 + <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001e2>; 226 + }; 227 + 228 + pinctrl_pmic: pmicirqgrp { 229 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1c0>; 230 + }; 231 + 232 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 233 + fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>; 234 + }; 235 + 236 + pinctrl_usdhc3: usdhc3grp { 237 + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 238 + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, 239 + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 240 + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 241 + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 242 + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 243 + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 244 + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 245 + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 246 + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 247 + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, 248 + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; 249 + }; 250 + 251 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 252 + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 253 + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, 254 + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 255 + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 256 + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 257 + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 258 + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 259 + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 260 + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 261 + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 262 + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, 263 + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; 264 + }; 265 + 266 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 267 + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 268 + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, 269 + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 270 + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 271 + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 272 + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 273 + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 274 + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 275 + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 276 + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 277 + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, 278 + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; 279 + }; 280 + 281 + pinctrl_wdog: wdoggrp { 282 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x1c4>; 283 + }; 284 + };
+9 -1
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
··· 49 49 pinctrl-names = "default"; 50 50 pinctrl-0 = <&pinctrl_gpio_keys>; 51 51 52 - wakeup { 52 + button-wakeup { 53 53 debounce-interval = <10>; 54 54 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 55 55 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; ··· 144 144 /* Use the kernel configuration settings instead */ 145 145 /delete-node/ linux,cma; 146 146 }; 147 + }; 148 + 149 + &cpu_alert0 { 150 + temperature = <95000>; 151 + }; 152 + 153 + &cpu_crit0 { 154 + temperature = <105000>; 147 155 }; 148 156 149 157 /* Verdin SPI_1 */
+26 -5
arch/arm64/boot/dts/freescale/imx8mp.dtsi
··· 195 195 clk_ext4: clock-ext4 { 196 196 compatible = "fixed-clock"; 197 197 #clock-cells = <0>; 198 - clock-frequency= <133000000>; 198 + clock-frequency = <133000000>; 199 199 clock-output-names = "clk_ext4"; 200 200 }; 201 201 ··· 293 293 arm,no-tick-in-suspend; 294 294 }; 295 295 296 - soc@0 { 296 + soc: soc@0 { 297 297 compatible = "fsl,imx8mp-soc", "simple-bus"; 298 298 #address-cells = <1>; 299 299 #size-cells = <1>; ··· 791 791 compatible = "fsl,sec-v4.0-job-ring"; 792 792 reg = <0x1000 0x1000>; 793 793 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 794 + status = "disabled"; 794 795 }; 795 796 796 797 sec_jr1: jr@2000 { ··· 904 903 <&clk IMX8MP_CLK_USDHC1_ROOT>; 905 904 clock-names = "ipg", "ahb", "per"; 906 905 fsl,tuning-start-tap = <20>; 907 - fsl,tuning-step= <2>; 906 + fsl,tuning-step = <2>; 908 907 bus-width = <4>; 909 908 status = "disabled"; 910 909 }; ··· 918 917 <&clk IMX8MP_CLK_USDHC2_ROOT>; 919 918 clock-names = "ipg", "ahb", "per"; 920 919 fsl,tuning-start-tap = <20>; 921 - fsl,tuning-step= <2>; 920 + fsl,tuning-step = <2>; 922 921 bus-width = <4>; 923 922 status = "disabled"; 924 923 }; ··· 932 931 <&clk IMX8MP_CLK_USDHC3_ROOT>; 933 932 clock-names = "ipg", "ahb", "per"; 934 933 fsl,tuning-start-tap = <20>; 935 - fsl,tuning-step= <2>; 934 + fsl,tuning-step = <2>; 936 935 bus-width = <4>; 937 936 status = "disabled"; 938 937 }; ··· 1016 1015 nvmem-cell-names = "mac-address"; 1017 1016 intf_mode = <&gpr 0x4>; 1018 1017 status = "disabled"; 1018 + }; 1019 + }; 1020 + 1021 + noc: interconnect@32700000 { 1022 + compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1023 + reg = <0x32700000 0x100000>; 1024 + clocks = <&clk IMX8MP_CLK_NOC>; 1025 + #interconnect-cells = <1>; 1026 + operating-points-v2 = <&noc_opp_table>; 1027 + 1028 + noc_opp_table: opp-table { 1029 + compatible = "operating-points-v2"; 1030 + 1031 + opp-200M { 1032 + opp-hz = /bits/ 64 <200000000>; 1033 + }; 1034 + 1035 + opp-1000M { 1036 + opp-hz = /bits/ 64 <1000000000>; 1037 + }; 1019 1038 }; 1020 1039 }; 1021 1040
+43
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
··· 71 71 linux,autosuspend-period = <125>; 72 72 }; 73 73 74 + audio_codec_bt_sco: audio-codec-bt-sco { 75 + compatible = "linux,bt-sco"; 76 + #sound-dai-cells = <1>; 77 + }; 78 + 74 79 wm8524: audio-codec { 75 80 #sound-dai-cells = <0>; 76 81 compatible = "wlf,wm8524"; 77 82 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 83 + }; 84 + 85 + sound-bt-sco { 86 + compatible = "simple-audio-card"; 87 + simple-audio-card,name = "bt-sco-audio"; 88 + simple-audio-card,format = "dsp_a"; 89 + simple-audio-card,bitclock-inversion; 90 + simple-audio-card,frame-master = <&btcpu>; 91 + simple-audio-card,bitclock-master = <&btcpu>; 92 + 93 + btcpu: simple-audio-card,cpu { 94 + sound-dai = <&sai3>; 95 + dai-tdm-slot-num = <2>; 96 + dai-tdm-slot-width = <16>; 97 + }; 98 + 99 + simple-audio-card,codec { 100 + sound-dai = <&audio_codec_bt_sco 1>; 101 + }; 78 102 }; 79 103 80 104 sound-wm8524 { ··· 410 386 status = "okay"; 411 387 }; 412 388 389 + &sai3 { 390 + #sound-dai-cells = <0>; 391 + pinctrl-names = "default"; 392 + pinctrl-0 = <&pinctrl_sai3>; 393 + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; 394 + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 395 + assigned-clock-rates = <24576000>; 396 + status = "okay"; 397 + }; 398 + 413 399 &snvs_pwrkey { 414 400 status = "okay"; 415 401 }; ··· 579 545 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 580 546 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 581 547 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 548 + >; 549 + }; 550 + 551 + pinctrl_sai3: sai3grp { 552 + fsl,pins = < 553 + MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 554 + MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 555 + MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 556 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 582 557 >; 583 558 }; 584 559
+3 -3
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
··· 36 36 pinctrl-names = "default"; 37 37 pinctrl-0 = <&pinctrl_gpio_keys>; 38 38 39 - btn1 { 39 + button-1 { 40 40 label = "VOL_UP"; 41 41 gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 42 42 wakeup-source; 43 43 linux,code = <KEY_VOLUMEUP>; 44 44 }; 45 45 46 - btn2 { 46 + button-2 { 47 47 label = "VOL_DOWN"; 48 48 gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 49 49 wakeup-source; 50 50 linux,code = <KEY_VOLUMEDOWN>; 51 51 }; 52 52 53 - wwan-wake { 53 + button-3 { 54 54 label = "WWAN_WAKE"; 55 55 gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; 56 56 interrupt-parent = <&gpio3>;
+2 -2
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
··· 37 37 pinctrl-names = "default"; 38 38 pinctrl-0 = <&pinctrl_keys>; 39 39 40 - vol-down { 40 + key-vol-down { 41 41 label = "VOL_DOWN"; 42 42 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; 43 43 linux,code = <KEY_VOLUMEDOWN>; ··· 45 45 wakeup-source; 46 46 }; 47 47 48 - vol-up { 48 + key-vol-up { 49 49 label = "VOL_UP"; 50 50 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 51 51 linux,code = <KEY_VOLUMEUP>;
+3 -3
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
··· 26 26 pinctrl-names = "default"; 27 27 pinctrl-0 = <&pinctrl_gpio_keys>; 28 28 29 - power { 29 + button-power { 30 30 label = "Power Button"; 31 31 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; 32 32 linux,code = <KEY_POWER>; ··· 152 152 pinctrl-names = "default"; 153 153 pinctrl-0 = <&pinctrl_reg_arm_dram>; 154 154 reg = <0x60>; 155 - regulator-min-microvolt = <900000>; 155 + regulator-min-microvolt = <900000>; 156 156 regulator-max-microvolt = <1000000>; 157 157 regulator-always-on; 158 158 vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; ··· 186 186 pinctrl-names = "default"; 187 187 pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>; 188 188 reg = <0x60>; 189 - regulator-min-microvolt = <900000>; 189 + regulator-min-microvolt = <900000>; 190 190 regulator-max-microvolt = <1000000>; 191 191 regulator-always-on; 192 192 vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+1 -1
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
··· 443 443 status = "okay"; 444 444 445 445 usbhub: usbhub@2c { 446 - compatible ="microchip,usb2513b"; 446 + compatible = "microchip,usb2513b"; 447 447 pinctrl-names = "default"; 448 448 pinctrl-0 = <&pinctrl_usbhub>; 449 449 reg = <0x2c>;
+8 -7
arch/arm64/boot/dts/freescale/imx8mq.dtsi
··· 94 94 clk_ext4: clock-ext4 { 95 95 compatible = "fixed-clock"; 96 96 #clock-cells = <0>; 97 - clock-frequency= <133000000>; 97 + clock-frequency = <133000000>; 98 98 clock-output-names = "clk_ext4"; 99 99 }; 100 100 ··· 320 320 arm,no-tick-in-suspend; 321 321 }; 322 322 323 - soc@0 { 323 + soc: soc@0 { 324 324 compatible = "fsl,imx8mq-soc", "simple-bus"; 325 325 #address-cells = <1>; 326 326 #size-cells = <1>; ··· 329 329 nvmem-cells = <&imx8mq_uid>; 330 330 nvmem-cell-names = "soc_unique_id"; 331 331 332 - bus@30000000 { /* AIPS1 */ 332 + aips1: bus@30000000 { /* AIPS1 */ 333 333 compatible = "fsl,aips-bus", "simple-bus"; 334 334 reg = <0x30000000 0x400000>; 335 335 #address-cells = <1>; ··· 507 507 <0x00030005 0x00000053>, 508 508 <0x00030006 0x0000005f>, 509 509 <0x00030007 0x00000071>; 510 - #thermal-sensor-cells = <1>; 510 + #thermal-sensor-cells = <1>; 511 511 }; 512 512 513 513 wdog1: watchdog@30280000 { ··· 784 784 }; 785 785 }; 786 786 787 - bus@30400000 { /* AIPS2 */ 787 + aips2: bus@30400000 { /* AIPS2 */ 788 788 compatible = "fsl,aips-bus", "simple-bus"; 789 789 reg = <0x30400000 0x400000>; 790 790 #address-cells = <1>; ··· 844 844 }; 845 845 }; 846 846 847 - bus@30800000 { /* AIPS3 */ 847 + aips3: bus@30800000 { /* AIPS3 */ 848 848 compatible = "fsl,aips-bus", "simple-bus"; 849 849 reg = <0x30800000 0x400000>; 850 850 #address-cells = <1>; ··· 1018 1018 compatible = "fsl,sec-v4.0-job-ring"; 1019 1019 reg = <0x1000 0x1000>; 1020 1020 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1021 + status = "disabled"; 1021 1022 }; 1022 1023 1023 1024 sec_jr1: jr@2000 { ··· 1370 1369 }; 1371 1370 }; 1372 1371 1373 - bus@32c00000 { /* AIPS4 */ 1372 + aips4: bus@32c00000 { /* AIPS4 */ 1374 1373 compatible = "fsl,aips-bus", "simple-bus"; 1375 1374 reg = <0x32c00000 0x400000>; 1376 1375 #address-cells = <1>;
+2 -2
arch/arm64/boot/dts/freescale/imx8qm.dtsi
··· 181 181 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 182 182 }; 183 183 184 - scu { 184 + system-controller { 185 185 compatible = "fsl,imx-scu"; 186 186 mbox-names = "tx0", 187 187 "rx0", ··· 190 190 &lsio_mu1 1 0 191 191 &lsio_mu1 3 3>; 192 192 193 - pd: imx8qx-pd { 193 + pd: power-controller { 194 194 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; 195 195 #power-domain-cells = <1>; 196 196 };
+4 -4
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
··· 16 16 pinctrl-names = "default"; 17 17 pinctrl-0 = <&pinctrl_gpiokeys>; 18 18 19 - wakeup { 19 + key-wakeup { 20 20 label = "Wake-Up"; 21 21 gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; 22 22 linux,code = <KEY_WAKEUP>; ··· 38 38 39 39 /* Colibri UART_B */ 40 40 &lpuart0 { 41 - status= "okay"; 41 + status = "okay"; 42 42 }; 43 43 44 44 /* Colibri UART_C */ 45 45 &lpuart2 { 46 - status= "okay"; 46 + status = "okay"; 47 47 }; 48 48 49 49 /* Colibri UART_A */ 50 50 &lpuart3 { 51 - status= "okay"; 51 + status = "okay"; 52 52 }; 53 53 54 54 /* Colibri FastEthernet */
+6 -8
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
··· 201 201 method = "smc"; 202 202 }; 203 203 204 - scu { 204 + system-controller { 205 205 compatible = "fsl,imx-scu"; 206 206 mbox-names = "tx0", 207 207 "rx0", ··· 210 210 &lsio_mu1 1 0 211 211 &lsio_mu1 3 3>; 212 212 213 - pd: imx8qx-pd { 213 + pd: power-controller { 214 214 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 215 215 #power-domain-cells = <1>; 216 216 }; 217 217 218 218 clk: clock-controller { 219 - compatible = "fsl,imx8qxp-clk"; 219 + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 220 220 #clock-cells = <2>; 221 - clocks = <&xtal32k &xtal24m>; 222 - clock-names = "xtal_32KHz", "xtal_24Mhz"; 223 221 }; 224 222 225 223 iomuxc: pinctrl { 226 224 compatible = "fsl,imx8qxp-iomuxc"; 227 225 }; 228 226 229 - ocotp: imx8qx-ocotp { 227 + ocotp: ocotp { 230 228 compatible = "fsl,imx8qxp-scu-ocotp"; 231 229 #address-cells = <1>; 232 230 #size-cells = <1>; 233 231 }; 234 232 235 - scu_key: scu-key { 233 + scu_key: keys { 236 234 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 237 235 linux,keycodes = <KEY_POWER>; 238 236 status = "disabled"; ··· 274 276 }; 275 277 276 278 thermal_zones: thermal-zones { 277 - cpu-thermal0 { 279 + cpu0-thermal { 278 280 polling-delay-passive = <250>; 279 281 polling-delay = <2000>; 280 282 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
+7 -7
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
··· 137 137 }; 138 138 }; 139 139 140 - soc@0 { 140 + soc: soc@0 { 141 141 compatible = "simple-bus"; 142 142 #address-cells = <1>; 143 143 #size-cells = <1>; ··· 331 331 clock-names = "ipg", "ahb", "per"; 332 332 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; 333 333 fsl,tuning-start-tap = <20>; 334 - fsl,tuning-step= <2>; 334 + fsl,tuning-step = <2>; 335 335 bus-width = <4>; 336 336 status = "disabled"; 337 337 }; ··· 346 346 clock-names = "ipg", "ahb", "per"; 347 347 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; 348 348 fsl,tuning-start-tap = <20>; 349 - fsl,tuning-step= <2>; 349 + fsl,tuning-step = <2>; 350 350 bus-width = <4>; 351 351 status = "disabled"; 352 352 }; ··· 361 361 clock-names = "ipg", "ahb", "per"; 362 362 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 363 363 fsl,tuning-start-tap = <20>; 364 - fsl,tuning-step= <2>; 364 + fsl,tuning-step = <2>; 365 365 bus-width = <4>; 366 366 status = "disabled"; 367 367 }; 368 368 }; 369 369 370 - gpioe: gpio@2d000000 { 370 + gpioe: gpio@2d000080 { 371 371 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 372 372 reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; 373 373 gpio-controller; ··· 381 381 gpio-ranges = <&iomuxc1 0 32 24>; 382 382 }; 383 383 384 - gpiof: gpio@2d010000 { 384 + gpiof: gpio@2d010080 { 385 385 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 386 386 reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; 387 387 gpio-controller; ··· 417 417 }; 418 418 }; 419 419 420 - gpiod: gpio@2e200000 { 420 + gpiod: gpio@2e200080 { 421 421 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 422 422 reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; 423 423 gpio-controller;
+114
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 NXP 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx93.dtsi" 9 + 10 + / { 11 + model = "NXP i.MX93 11X11 EVK board"; 12 + compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 13 + 14 + chosen { 15 + stdout-path = &lpuart1; 16 + }; 17 + 18 + reg_usdhc2_vmmc: regulator-usdhc2 { 19 + compatible = "regulator-fixed"; 20 + pinctrl-names = "default"; 21 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 22 + regulator-name = "VSD_3V3"; 23 + regulator-min-microvolt = <3300000>; 24 + regulator-max-microvolt = <3300000>; 25 + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 26 + enable-active-high; 27 + }; 28 + }; 29 + 30 + &mu1 { 31 + status = "okay"; 32 + }; 33 + 34 + &mu2 { 35 + status = "okay"; 36 + }; 37 + 38 + &lpuart1 { /* console */ 39 + pinctrl-names = "default"; 40 + pinctrl-0 = <&pinctrl_uart1>; 41 + status = "okay"; 42 + }; 43 + 44 + &usdhc1 { 45 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 46 + pinctrl-0 = <&pinctrl_usdhc1>; 47 + pinctrl-1 = <&pinctrl_usdhc1>; 48 + pinctrl-2 = <&pinctrl_usdhc1>; 49 + bus-width = <8>; 50 + non-removable; 51 + status = "okay"; 52 + }; 53 + 54 + &usdhc2 { 55 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 56 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 57 + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 58 + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 59 + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 60 + vmmc-supply = <&reg_usdhc2_vmmc>; 61 + bus-width = <4>; 62 + status = "okay"; 63 + no-sdio; 64 + no-mmc; 65 + }; 66 + 67 + &iomuxc { 68 + pinctrl_uart1: uart1grp { 69 + fsl,pins = < 70 + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 71 + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 72 + >; 73 + }; 74 + 75 + pinctrl_usdhc1: usdhc1grp { 76 + fsl,pins = < 77 + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe 78 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe 79 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 80 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 81 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 82 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 83 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 84 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 85 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 86 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 87 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe 88 + >; 89 + }; 90 + 91 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 92 + fsl,pins = < 93 + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 94 + >; 95 + }; 96 + 97 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 98 + fsl,pins = < 99 + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 100 + >; 101 + }; 102 + 103 + pinctrl_usdhc2: usdhc2grp { 104 + fsl,pins = < 105 + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe 106 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe 107 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 108 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 109 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 110 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 111 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 112 + >; 113 + }; 114 + };
+623
arch/arm64/boot/dts/freescale/imx93-pinfunc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 + /* 3 + * Copyright 2022 NXP 4 + */ 5 + 6 + #ifndef __DTS_IMX93_PINFUNC_H 7 + #define __DTS_IMX93_PINFUNC_H 8 + 9 + /* 10 + * The pin function ID is a tuple of 11 + * <mux_reg conf_reg input_reg mux_mode input_val> 12 + */ 13 + #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 14 + #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 15 + #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 16 + #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 17 + #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 18 + #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 19 + #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 20 + #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 21 + #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 22 + #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 23 + #define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 24 + #define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 25 + #define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 26 + #define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 27 + #define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 28 + #define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 29 + #define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 30 + #define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 31 + #define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 32 + #define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 33 + #define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 34 + #define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 35 + #define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 36 + #define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 37 + #define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 38 + #define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 39 + #define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 40 + #define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 41 + #define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 42 + #define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 43 + #define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 44 + #define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 45 + #define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 46 + #define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 47 + #define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 48 + #define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 49 + #define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 50 + #define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 51 + #define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 52 + #define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 53 + #define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 54 + #define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 55 + #define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 56 + #define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 57 + #define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 58 + #define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 59 + #define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 60 + #define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 61 + #define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 62 + #define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 63 + #define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 64 + #define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 65 + #define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 66 + #define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 67 + #define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0 68 + #define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 69 + #define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 70 + #define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 71 + #define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 72 + #define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 73 + #define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 74 + #define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 75 + #define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 76 + #define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 77 + #define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 78 + #define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 79 + #define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 80 + #define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 81 + #define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 82 + #define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 83 + #define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 84 + #define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 85 + #define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 86 + #define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 87 + #define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 88 + #define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 89 + #define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 90 + #define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 91 + #define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0 92 + #define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 93 + #define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 94 + #define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 95 + #define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 96 + #define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 97 + #define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 98 + #define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 99 + #define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0 100 + #define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 101 + #define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 102 + #define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 103 + #define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 104 + #define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 105 + #define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 106 + #define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 107 + #define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0 108 + #define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 109 + #define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 110 + #define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 111 + #define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 112 + #define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 113 + #define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 114 + #define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 115 + #define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0 116 + #define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 117 + #define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 118 + #define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 119 + #define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 120 + #define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 121 + #define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 122 + #define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 123 + #define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0 124 + #define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 125 + #define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 126 + #define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 127 + #define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 128 + #define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 129 + #define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 130 + #define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 131 + #define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 132 + #define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 133 + #define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 134 + #define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 135 + #define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 136 + #define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 137 + #define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 138 + #define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 139 + #define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 140 + #define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 141 + #define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 142 + #define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 143 + #define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 144 + #define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 145 + #define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 146 + #define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 147 + #define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 148 + #define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 149 + #define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 150 + #define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 151 + #define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 152 + #define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 153 + #define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 154 + #define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 155 + #define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 156 + #define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 157 + #define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 158 + #define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 159 + #define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 160 + #define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 161 + #define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 162 + #define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 163 + #define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 164 + #define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 165 + #define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 166 + #define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 167 + #define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 168 + #define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 169 + #define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 170 + #define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 171 + #define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0 172 + #define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0 173 + #define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0 174 + #define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0 175 + #define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 176 + #define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 177 + #define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 178 + #define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 179 + #define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 180 + #define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 181 + #define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 182 + #define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0 183 + #define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 184 + #define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 185 + #define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 186 + #define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 187 + #define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 188 + #define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 189 + #define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 190 + #define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 191 + #define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0 192 + #define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 193 + #define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 194 + #define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 195 + #define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 196 + #define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 197 + #define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 198 + #define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 199 + #define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0 200 + #define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0 201 + #define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0 202 + #define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0 203 + #define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0 204 + #define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0 205 + #define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 206 + #define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 207 + #define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 208 + #define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 209 + #define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 210 + #define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 211 + #define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 212 + #define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 213 + #define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 214 + #define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 215 + #define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 216 + #define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 217 + #define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 218 + #define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 219 + #define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 220 + #define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 221 + #define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 222 + #define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 223 + #define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 224 + #define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 225 + #define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 226 + #define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 227 + #define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 228 + #define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 229 + #define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 230 + #define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 231 + #define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 232 + #define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 233 + #define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 234 + #define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 235 + #define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 236 + #define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 237 + #define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 238 + #define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 239 + #define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 240 + #define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 241 + #define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 242 + #define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 243 + #define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 244 + #define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 245 + #define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 246 + #define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 247 + #define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 248 + #define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 249 + #define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 250 + #define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 251 + #define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 252 + #define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 253 + #define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 254 + #define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 255 + #define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 256 + #define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 257 + #define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 258 + #define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 259 + #define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 260 + #define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 261 + #define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 262 + #define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 263 + #define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0 264 + #define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0 265 + #define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0 266 + #define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 267 + #define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 268 + #define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 269 + #define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 270 + #define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 271 + #define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 272 + #define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 273 + #define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 274 + #define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 275 + #define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 276 + #define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 277 + #define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 278 + #define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 279 + #define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 280 + #define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 281 + #define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 282 + #define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 283 + #define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 284 + #define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 285 + #define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0 286 + #define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0 287 + #define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0 288 + #define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0 289 + #define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0 290 + #define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0 291 + #define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0 292 + #define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2 293 + #define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0 294 + #define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0 295 + #define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0 296 + #define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0 297 + #define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0 298 + #define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0 299 + #define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0 300 + #define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0 301 + #define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 302 + #define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 303 + #define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 304 + #define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 305 + #define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 306 + #define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 307 + #define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 308 + #define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0 309 + #define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0 310 + #define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0 311 + #define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0 312 + #define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0 313 + #define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0 314 + #define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0 315 + #define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0 316 + #define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0 317 + #define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0 318 + #define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0 319 + #define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0 320 + #define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0 321 + #define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0 322 + #define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 323 + #define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 324 + #define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 325 + #define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 326 + #define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 327 + #define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 328 + #define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 329 + #define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 330 + #define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 331 + #define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 332 + #define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 333 + #define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 334 + #define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 335 + #define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 336 + #define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 337 + #define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 338 + #define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 339 + #define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 340 + #define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 341 + #define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 342 + #define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 343 + #define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0 344 + #define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0 345 + #define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0 346 + #define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0 347 + #define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0 348 + #define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0 349 + #define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0 350 + #define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0 351 + #define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0 352 + #define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0 353 + #define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0 354 + #define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0 355 + #define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0 356 + #define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0 357 + #define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0 358 + #define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0 359 + #define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0 360 + #define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0 361 + #define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0 362 + #define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0 363 + #define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0 364 + #define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 365 + #define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 366 + #define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 367 + #define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 368 + #define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 369 + #define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 370 + #define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 371 + #define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0 372 + #define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0 373 + #define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0 374 + #define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0 375 + #define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0 376 + #define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0 377 + #define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0 378 + #define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0 379 + #define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0 380 + #define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0 381 + #define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0 382 + #define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0 383 + #define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0 384 + #define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0 385 + #define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0 386 + #define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0 387 + #define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0 388 + #define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0 389 + #define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 390 + #define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 391 + #define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 392 + #define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 393 + #define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 394 + #define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 395 + #define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 396 + #define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 397 + #define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 398 + #define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 399 + #define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 400 + #define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 401 + #define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 402 + #define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 403 + #define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 404 + #define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 405 + #define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 406 + #define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 407 + #define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 408 + #define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 409 + #define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 410 + #define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 411 + #define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 412 + #define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 413 + #define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1 414 + #define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0 415 + #define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0 416 + #define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0 417 + #define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1 418 + #define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0 419 + #define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0 420 + #define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1 421 + #define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0 422 + #define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0 423 + #define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1 424 + #define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0 425 + #define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0 426 + #define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0 427 + #define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0 428 + #define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0 429 + #define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0 430 + #define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0 431 + #define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0 432 + #define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1 433 + #define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0 434 + #define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0 435 + #define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0 436 + #define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1 437 + #define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0 438 + #define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0 439 + #define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0 440 + #define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0 441 + #define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1 442 + #define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0 443 + #define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0 444 + #define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0 445 + #define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0 446 + #define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1 447 + #define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0 448 + #define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0 449 + #define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0 450 + #define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0 451 + #define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1 452 + #define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0 453 + #define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0 454 + #define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0 455 + #define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1 456 + #define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 457 + #define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 458 + #define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 459 + #define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 460 + #define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 461 + #define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 462 + #define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 463 + #define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 464 + #define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 465 + #define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 466 + #define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 467 + #define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 468 + #define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 469 + #define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 470 + #define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 471 + #define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 472 + #define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 473 + #define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 474 + #define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 475 + #define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 476 + #define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 477 + #define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 478 + #define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 479 + #define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 480 + #define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 481 + #define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 482 + #define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 483 + #define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 484 + #define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 485 + #define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 486 + #define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 487 + #define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 488 + #define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 489 + #define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 490 + #define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 491 + #define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 492 + #define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 493 + #define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 494 + #define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 495 + #define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 496 + #define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 497 + #define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 498 + #define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0 499 + #define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0 500 + #define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0 501 + #define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0 502 + #define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1 503 + #define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0 504 + #define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0 505 + #define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0 506 + #define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0 507 + #define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0 508 + #define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1 509 + #define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0 510 + #define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0 511 + #define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0 512 + #define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0 513 + #define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3 514 + #define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1 515 + #define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0 516 + #define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0 517 + #define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0 518 + #define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0 519 + #define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0 520 + #define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1 521 + #define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 522 + #define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 523 + #define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 524 + #define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 525 + #define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 526 + #define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 527 + #define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 528 + #define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 529 + #define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 530 + #define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 531 + #define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 532 + #define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 533 + #define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 534 + #define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 535 + #define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 536 + #define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 537 + #define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 538 + #define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 539 + #define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 540 + #define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 541 + #define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 542 + #define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 543 + #define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 544 + #define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 545 + #define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 546 + #define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 547 + #define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 548 + #define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 549 + #define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 550 + #define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 551 + #define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 552 + #define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 553 + #define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 554 + #define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 555 + #define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0 556 + #define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0 557 + #define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0 558 + #define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0 559 + #define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0 560 + #define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0 561 + #define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0 562 + #define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0 563 + #define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0 564 + #define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0 565 + #define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0 566 + #define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0 567 + #define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 568 + #define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 569 + #define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 570 + #define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 571 + #define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 572 + #define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 573 + #define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 574 + #define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0 575 + #define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0 576 + #define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0 577 + #define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0 578 + #define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0 579 + #define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 580 + #define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 581 + #define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 582 + #define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 583 + #define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 584 + #define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 585 + #define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 586 + #define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 587 + #define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 588 + #define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 589 + #define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 590 + #define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 591 + #define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 592 + #define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 593 + #define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0 594 + #define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0 595 + #define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1 596 + #define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0 597 + #define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0 598 + #define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0 599 + #define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0 600 + #define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0 601 + #define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0 602 + #define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0 603 + #define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0 604 + #define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0 605 + #define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0 606 + #define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1 607 + #define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0 608 + #define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0 609 + #define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0 610 + #define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0 611 + #define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0 612 + #define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 613 + #define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 614 + #define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 615 + #define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 616 + #define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 617 + #define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 618 + #define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 619 + #define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0 620 + #define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0 621 + #define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0 622 + 623 + #endif /* __DTS_IMX93_PINFUNC_H */
+334
arch/arm64/boot/dts/freescale/imx93.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2022 NXP 4 + */ 5 + 6 + #include <dt-bindings/clock/imx93-clock.h> 7 + #include <dt-bindings/gpio/gpio.h> 8 + #include <dt-bindings/input/input.h> 9 + #include <dt-bindings/interrupt-controller/arm-gic.h> 10 + 11 + #include "imx93-pinfunc.h" 12 + 13 + / { 14 + interrupt-parent = <&gic>; 15 + #address-cells = <2>; 16 + #size-cells = <2>; 17 + 18 + aliases { 19 + mmc0 = &usdhc1; 20 + mmc1 = &usdhc2; 21 + mmc2 = &usdhc3; 22 + serial0 = &lpuart1; 23 + serial1 = &lpuart2; 24 + serial2 = &lpuart3; 25 + serial3 = &lpuart4; 26 + serial4 = &lpuart5; 27 + serial5 = &lpuart6; 28 + serial6 = &lpuart7; 29 + serial7 = &lpuart8; 30 + }; 31 + 32 + cpus { 33 + #address-cells = <1>; 34 + #size-cells = <0>; 35 + 36 + A55_0: cpu@0 { 37 + device_type = "cpu"; 38 + compatible = "arm,cortex-a55"; 39 + reg = <0x0>; 40 + enable-method = "psci"; 41 + #cooling-cells = <2>; 42 + }; 43 + 44 + A55_1: cpu@100 { 45 + device_type = "cpu"; 46 + compatible = "arm,cortex-a55"; 47 + reg = <0x100>; 48 + enable-method = "psci"; 49 + #cooling-cells = <2>; 50 + }; 51 + 52 + }; 53 + 54 + osc_32k: clock-osc-32k { 55 + compatible = "fixed-clock"; 56 + #clock-cells = <0>; 57 + clock-frequency = <32768>; 58 + clock-output-names = "osc_32k"; 59 + }; 60 + 61 + osc_24m: clock-osc-24m { 62 + compatible = "fixed-clock"; 63 + #clock-cells = <0>; 64 + clock-frequency = <24000000>; 65 + clock-output-names = "osc_24m"; 66 + }; 67 + 68 + clk_ext1: clock-ext1 { 69 + compatible = "fixed-clock"; 70 + #clock-cells = <0>; 71 + clock-frequency = <133000000>; 72 + clock-output-names = "clk_ext1"; 73 + }; 74 + 75 + psci { 76 + compatible = "arm,psci-1.0"; 77 + method = "smc"; 78 + }; 79 + 80 + timer { 81 + compatible = "arm,armv8-timer"; 82 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 83 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 84 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 85 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 86 + clock-frequency = <24000000>; 87 + arm,no-tick-in-suspend; 88 + interrupt-parent = <&gic>; 89 + }; 90 + 91 + gic: interrupt-controller@48000000 { 92 + compatible = "arm,gic-v3"; 93 + reg = <0 0x48000000 0 0x10000>, 94 + <0 0x48040000 0 0xc0000>; 95 + #interrupt-cells = <3>; 96 + interrupt-controller; 97 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 98 + interrupt-parent = <&gic>; 99 + }; 100 + 101 + soc@0 { 102 + compatible = "simple-bus"; 103 + #address-cells = <1>; 104 + #size-cells = <1>; 105 + ranges = <0x0 0x0 0x0 0x80000000>, 106 + <0x28000000 0x0 0x28000000 0x10000000>; 107 + 108 + aips1: bus@44000000 { 109 + compatible = "fsl,aips-bus", "simple-bus"; 110 + reg = <0x44000000 0x800000>; 111 + #address-cells = <1>; 112 + #size-cells = <1>; 113 + ranges; 114 + 115 + mu1: mailbox@44230000 { 116 + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 117 + reg = <0x44230000 0x10000>; 118 + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 119 + #mbox-cells = <2>; 120 + status = "disabled"; 121 + }; 122 + 123 + system_counter: timer@44290000 { 124 + compatible = "nxp,sysctr-timer"; 125 + reg = <0x44290000 0x30000>; 126 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 127 + clocks = <&osc_24m>; 128 + clock-names = "per"; 129 + }; 130 + 131 + lpuart1: serial@44380000 { 132 + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 133 + reg = <0x44380000 0x1000>; 134 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 135 + clocks = <&clk IMX93_CLK_LPUART1_GATE>; 136 + clock-names = "ipg"; 137 + status = "disabled"; 138 + }; 139 + 140 + lpuart2: serial@44390000 { 141 + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 142 + reg = <0x44390000 0x1000>; 143 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 144 + clocks = <&clk IMX93_CLK_LPUART2_GATE>; 145 + clock-names = "ipg"; 146 + status = "disabled"; 147 + }; 148 + 149 + iomuxc: pinctrl@443c0000 { 150 + compatible = "fsl,imx93-iomuxc"; 151 + reg = <0x443c0000 0x10000>; 152 + status = "okay"; 153 + }; 154 + 155 + clk: clock-controller@44450000 { 156 + compatible = "fsl,imx93-ccm"; 157 + reg = <0x44450000 0x10000>; 158 + #clock-cells = <1>; 159 + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 160 + clock-names = "osc_32k", "osc_24m", "clk_ext1"; 161 + status = "okay"; 162 + }; 163 + 164 + anatop: anatop@44480000 { 165 + compatible = "fsl,imx93-anatop", "syscon"; 166 + reg = <0x44480000 0x10000>; 167 + }; 168 + }; 169 + 170 + aips2: bus@42000000 { 171 + compatible = "fsl,aips-bus", "simple-bus"; 172 + reg = <0x42000000 0x800000>; 173 + #address-cells = <1>; 174 + #size-cells = <1>; 175 + ranges; 176 + 177 + mu2: mailbox@42440000 { 178 + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 179 + reg = <0x42440000 0x10000>; 180 + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 181 + #mbox-cells = <2>; 182 + status = "disabled"; 183 + }; 184 + 185 + lpuart3: serial@42570000 { 186 + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 187 + reg = <0x42570000 0x1000>; 188 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 189 + clocks = <&clk IMX93_CLK_LPUART3_GATE>; 190 + clock-names = "ipg"; 191 + status = "disabled"; 192 + }; 193 + 194 + lpuart4: serial@42580000 { 195 + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 196 + reg = <0x42580000 0x1000>; 197 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 198 + clocks = <&clk IMX93_CLK_LPUART4_GATE>; 199 + clock-names = "ipg"; 200 + status = "disabled"; 201 + }; 202 + 203 + lpuart5: serial@42590000 { 204 + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 205 + reg = <0x42590000 0x1000>; 206 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 207 + clocks = <&clk IMX93_CLK_LPUART5_GATE>; 208 + clock-names = "ipg"; 209 + status = "disabled"; 210 + }; 211 + 212 + lpuart6: serial@425a0000 { 213 + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 214 + reg = <0x425a0000 0x1000>; 215 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 216 + clocks = <&clk IMX93_CLK_LPUART6_GATE>; 217 + clock-names = "ipg"; 218 + status = "disabled"; 219 + }; 220 + 221 + lpuart7: serial@42690000 { 222 + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 223 + reg = <0x42690000 0x1000>; 224 + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 225 + clocks = <&clk IMX93_CLK_LPUART7_GATE>; 226 + clock-names = "ipg"; 227 + status = "disabled"; 228 + }; 229 + 230 + lpuart8: serial@426a0000 { 231 + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 232 + reg = <0x426a0000 0x1000>; 233 + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 234 + clocks = <&clk IMX93_CLK_LPUART8_GATE>; 235 + clock-names = "ipg"; 236 + status = "disabled"; 237 + }; 238 + }; 239 + 240 + aips3: bus@42800000 { 241 + compatible = "fsl,aips-bus", "simple-bus"; 242 + reg = <0x42800000 0x800000>; 243 + #address-cells = <1>; 244 + #size-cells = <1>; 245 + ranges; 246 + 247 + usdhc1: mmc@42850000 { 248 + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 249 + reg = <0x42850000 0x10000>; 250 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 251 + clocks = <&clk IMX93_CLK_DUMMY>, 252 + <&clk IMX93_CLK_DUMMY>, 253 + <&clk IMX93_CLK_USDHC1_GATE>; 254 + clock-names = "ipg", "ahb", "per"; 255 + bus-width = <8>; 256 + fsl,tuning-start-tap = <20>; 257 + fsl,tuning-step= <2>; 258 + status = "disabled"; 259 + }; 260 + 261 + usdhc2: mmc@42860000 { 262 + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 263 + reg = <0x42860000 0x10000>; 264 + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 265 + clocks = <&clk IMX93_CLK_DUMMY>, 266 + <&clk IMX93_CLK_DUMMY>, 267 + <&clk IMX93_CLK_USDHC2_GATE>; 268 + clock-names = "ipg", "ahb", "per"; 269 + bus-width = <4>; 270 + fsl,tuning-start-tap = <20>; 271 + fsl,tuning-step= <2>; 272 + status = "disabled"; 273 + }; 274 + 275 + usdhc3: mmc@428b0000 { 276 + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 277 + reg = <0x428b0000 0x10000>; 278 + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 279 + clocks = <&clk IMX93_CLK_DUMMY>, 280 + <&clk IMX93_CLK_DUMMY>, 281 + <&clk IMX93_CLK_USDHC3_GATE>; 282 + clock-names = "ipg", "ahb", "per"; 283 + bus-width = <4>; 284 + fsl,tuning-start-tap = <20>; 285 + fsl,tuning-step= <2>; 286 + status = "disabled"; 287 + }; 288 + }; 289 + 290 + gpio2: gpio@43810080 { 291 + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 292 + reg = <0x43810080 0x1000>, <0x43810040 0x40>; 293 + gpio-controller; 294 + #gpio-cells = <2>; 295 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 296 + interrupt-controller; 297 + #interrupt-cells = <2>; 298 + gpio-ranges = <&iomuxc 0 32 32>; 299 + }; 300 + 301 + gpio3: gpio@43820080 { 302 + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 303 + reg = <0x43820080 0x1000>, <0x43820040 0x40>; 304 + gpio-controller; 305 + #gpio-cells = <2>; 306 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 307 + interrupt-controller; 308 + #interrupt-cells = <2>; 309 + gpio-ranges = <&iomuxc 0 64 32>; 310 + }; 311 + 312 + gpio4: gpio@43830080 { 313 + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 314 + reg = <0x43830080 0x1000>, <0x43830040 0x40>; 315 + gpio-controller; 316 + #gpio-cells = <2>; 317 + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 318 + interrupt-controller; 319 + #interrupt-cells = <2>; 320 + gpio-ranges = <&iomuxc 0 96 32>; 321 + }; 322 + 323 + gpio1: gpio@47400080 { 324 + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 325 + reg = <0x47400080 0x1000>, <0x47400040 0x40>; 326 + gpio-controller; 327 + #gpio-cells = <2>; 328 + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 329 + interrupt-controller; 330 + #interrupt-cells = <2>; 331 + gpio-ranges = <&iomuxc 0 0 32>; 332 + }; 333 + }; 334 + };
+3 -5
arch/arm64/boot/dts/freescale/mba8mx.dtsi
··· 16 16 }; 17 17 18 18 chosen { 19 - // bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200"; 20 19 stdout-path = &uart3; 21 20 }; 22 21 ··· 25 26 pinctrl-0 = <&pinctrl_gpiobutton>; 26 27 autorepeat; 27 28 28 - switch1 { 29 + switch-1 { 29 30 label = "switch1"; 30 31 linux,code = <BTN_0>; 31 32 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 32 33 wakeup-source; 33 34 }; 34 35 35 - btn2: switch2 { 36 + btn2: switch-2 { 36 37 label = "switch2"; 37 38 linux,code = <BTN_1>; 38 39 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 39 40 wakeup-source; 40 41 }; 41 42 42 - switch3 { 43 + switch-3 { 43 44 label = "switch3"; 44 45 linux,code = <BTN_2>; 45 46 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; ··· 271 272 status = "okay"; 272 273 }; 273 274 274 - /* UART4 is assigned to Cortex-M4 */ 275 275 &usdhc2 { 276 276 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 277 277 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;