Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus-20170904' of git://git.infradead.org/linux-mtd
Pull MTD updates from Boris Brezillon:
"General updates:
- Constify pci_device_id in various drivers
- Constify device_type
- Remove pad control code from the Gemini driver
- Use %pOF to print OF node full_name
- Various fixes in the physmap_of driver
- Remove unused vars in mtdswap
- Check devm_kzalloc() return value in the spear_smi driver
- Check clk_prepare_enable() return code in the st_spi_fsm driver
- Create per MTD device debugfs enties
NAND updates, from Boris Brezillon:
- Fix memory leaks in the core
- Remove unused NAND locking support
- Rename nand.h into rawnand.h (preparing support for spi NANDs)
- Use NAND_MAX_ID_LEN where appropriate
- Fix support for 20nm Hynix chips
- Fix support for Samsung and Hynix SLC NANDs
- Various cleanup, improvements and fixes in the qcom driver
- Fixes for bugs detected by various static code analysis tools
- Fix mxc ooblayout definition
- Add a new part_parsers to tmio and sharpsl platform data in order
to define a custom list of partition parsers
- Request the reset line in exclusive mode in the sunxi driver
- Fix a build error in the orion-nand driver when compiled for ARMv4
- Allow 64-bit mvebu platforms to select the PXA3XX driver
SPI NOR updates, from Cyrille Pitchen and Marek Vasut:
- add support to the JEDEC JESD216B specification (SFDP tables).
- add support to the Intel Denverton SPI flash controller.
- fix error recovery for Spansion/Cypress SPI NOR memories.
- fix 4-byte address management for the Aspeed SPI controller.
- add support to some Microchip SST26 memory parts
- remove unneeded pinctrl header Write a message for tag:"
* tag 'for-linus-20170904' of git://git.infradead.org/linux-mtd: (74 commits)
mtd: nand: complain loudly when chip->bits_per_cell is not correctly initialized
mtd: nand: make Samsung SLC NAND usable again
mtd: nand: tmio: Register partitions using the parsers
mfd: tmio: Add partition parsers platform data
mtd: nand: sharpsl: Register partitions using the parsers
mtd: nand: sharpsl: Add partition parsers platform data
mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller
mtd: nand: qcom: support for IPQ4019 QPIC NAND controller
dt-bindings: qcom_nandc: IPQ8074 QPIC NAND documentation
dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation
dt-bindings: qcom_nandc: fix the ipq806x device tree example
mtd: nand: qcom: support for different DEV_CMD register offsets
mtd: nand: qcom: QPIC data descriptors handling
mtd: nand: qcom: enable BAM or ADM mode
mtd: nand: qcom: erased codeword detection configuration
mtd: nand: qcom: support for read location registers
mtd: nand: qcom: support for passing flags in DMA helper functions
mtd: nand: qcom: add BAM DMA descriptor handling
mtd: nand: qcom: allocate BAM transaction
mtd: nand: qcom: DMA mapping support for register read buffer
...
+2113
-765
+59
-6
Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+59
-6
Documentation/devicetree/bindings/mtd/qcom_nandc.txt
···
1
1
* Qualcomm NAND controller
2
2
3
3
Required properties:
4
-
- compatible: should be "qcom,ipq806x-nand"
4
+
- compatible: must be one of the following:
5
+
* "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
6
+
SoC and it uses ADM DMA
7
+
* "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
8
+
IPQ4019 SoC and it uses BAM DMA
9
+
* "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
10
+
IPQ8074 SoC and it uses BAM DMA
11
+
5
12
- reg: MMIO address range
6
13
- clocks: must contain core clock and always on clock
7
14
- clock-names: must contain "core" for the core clock and "aon" for the
8
15
always on clock
16
+
17
+
EBI2 specific properties:
9
18
- dmas: DMA specifier, consisting of a phandle to the ADM DMA
10
19
controller node and the channel number to be used for
11
20
NAND. Refer to dma.txt and qcom_adm.txt for more details
···
25
16
- qcom,data-crci: must contain the ADM data type CRCI block instance
26
17
number specified for the NAND controller on the given
27
18
platform
19
+
20
+
QPIC specific properties:
21
+
- dmas: DMA specifier, consisting of a phandle to the BAM DMA
22
+
and the channel number to be used for NAND. Refer to
23
+
dma.txt, qcom_bam_dma.txt for more details
24
+
- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
28
25
- #address-cells: <1> - subnodes give the chip-select number
29
26
- #size-cells: <0>
30
27
···
41
26
follows.
42
27
43
28
Required properties:
44
-
- compatible: should contain "qcom,nandcs"
45
29
- reg: a single integer representing the chip-select
46
30
number (e.g., 0, 1, 2, etc.)
47
31
- #address-cells: see partition.txt
···
57
43
58
44
Example:
59
45
60
-
nand@1ac00000 {
61
-
compatible = "qcom,ebi2-nandc";
46
+
nand-controller@1ac00000 {
47
+
compatible = "qcom,ipq806x-nand";
62
48
reg = <0x1ac00000 0x800>;
63
49
64
50
clocks = <&gcc EBI2_CLK>,
···
73
59
#address-cells = <1>;
74
60
#size-cells = <0>;
75
61
76
-
nandcs@0 {
77
-
compatible = "qcom,nandcs";
62
+
nand@0 {
78
63
reg = <0>;
79
64
65
+
nand-ecc-strength = <4>;
66
+
nand-ecc-step-size = <512>;
67
+
nand-bus-width = <8>;
68
+
69
+
partitions {
70
+
compatible = "fixed-partitions";
71
+
#address-cells = <1>;
72
+
#size-cells = <1>;
73
+
74
+
partition@0 {
75
+
label = "boot-nand";
76
+
reg = <0 0x58a0000>;
77
+
};
78
+
79
+
partition@58a0000 {
80
+
label = "fs-nand";
81
+
reg = <0x58a0000 0x4000000>;
82
+
};
83
+
};
84
+
};
85
+
};
86
+
87
+
nand-controller@79b0000 {
88
+
compatible = "qcom,ipq4019-nand";
89
+
reg = <0x79b0000 0x1000>;
90
+
91
+
clocks = <&gcc GCC_QPIC_CLK>,
92
+
<&gcc GCC_QPIC_AHB_CLK>;
93
+
clock-names = "core", "aon";
94
+
95
+
dmas = <&qpicbam 0>,
96
+
<&qpicbam 1>,
97
+
<&qpicbam 2>;
98
+
dma-names = "tx", "rx", "cmd";
99
+
100
+
#address-cells = <1>;
101
+
#size-cells = <0>;
102
+
103
+
nand@0 {
104
+
reg = <0>;
80
105
nand-ecc-strength = <4>;
81
106
nand-ecc-step-size = <512>;
82
107
nand-bus-width = <8>;
+4
-4
Documentation/driver-api/mtdnand.rst
+4
-4
Documentation/driver-api/mtdnand.rst
···
516
516
517
517
The most important field in the nand_bbt_descr structure is the
518
518
options field. The options define most of the table properties. Use the
519
-
predefined constants from nand.h to define the options.
519
+
predefined constants from rawnand.h to define the options.
520
520
521
521
- Number of bits per block
522
522
···
843
843
Constants for chip id table
844
844
~~~~~~~~~~~~~~~~~~~~~~~~~~~
845
845
846
-
These constants are defined in nand.h. They are OR-ed together to
846
+
These constants are defined in rawnand.h. They are OR-ed together to
847
847
describe the chip functionality::
848
848
849
849
/* Buswitdh is 16 bit */
···
865
865
Constants for runtime options
866
866
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
867
867
868
-
These constants are defined in nand.h. They are OR-ed together to
868
+
These constants are defined in rawnand.h. They are OR-ed together to
869
869
describe the functionality::
870
870
871
871
/* The hw ecc generator provides a syndrome instead a ecc value on read
···
956
956
with an [XXX] identifier. See the chapter "Documentation hints" for an
957
957
explanation.
958
958
959
-
.. kernel-doc:: include/linux/mtd/nand.h
959
+
.. kernel-doc:: include/linux/mtd/rawnand.h
960
960
:internal:
961
961
962
962
Public Functions Provided
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
9184
9184
T: git git://git.infradead.org/l2-mtd.git nand/next
9185
9185
S: Maintained
9186
9186
F: drivers/mtd/nand/
9187
-
F: include/linux/mtd/nand*.h
9187
+
F: include/linux/mtd/*nand*.h
9188
9188
9189
9189
NATIVE INSTRUMENTS USB SOUND INTERFACE DRIVER
9190
9190
M: Daniel Mack <zonque@gmail.com>
+1
-1
arch/arm/mach-davinci/board-da850-evm.c
+1
-1
arch/arm/mach-davinci/board-da850-evm.c
···
26
26
#include <linux/input/tps6507x-ts.h>
27
27
#include <linux/mfd/tps6507x.h>
28
28
#include <linux/mtd/mtd.h>
29
-
#include <linux/mtd/nand.h>
29
+
#include <linux/mtd/rawnand.h>
30
30
#include <linux/mtd/partitions.h>
31
31
#include <linux/mtd/physmap.h>
32
32
#include <linux/platform_device.h>
+1
-1
arch/arm/mach-davinci/board-dm355-evm.c
+1
-1
arch/arm/mach-davinci/board-dm355-evm.c
+1
-1
arch/arm/mach-davinci/board-dm355-leopard.c
+1
-1
arch/arm/mach-davinci/board-dm355-leopard.c
+1
-1
arch/arm/mach-davinci/board-dm365-evm.c
+1
-1
arch/arm/mach-davinci/board-dm365-evm.c
+1
-1
arch/arm/mach-davinci/board-dm644x-evm.c
+1
-1
arch/arm/mach-davinci/board-dm644x-evm.c
···
17
17
#include <linux/platform_data/pcf857x.h>
18
18
#include <linux/platform_data/at24.h>
19
19
#include <linux/mtd/mtd.h>
20
-
#include <linux/mtd/nand.h>
20
+
#include <linux/mtd/rawnand.h>
21
21
#include <linux/mtd/partitions.h>
22
22
#include <linux/mtd/physmap.h>
23
23
#include <linux/phy.h>
+1
-1
arch/arm/mach-davinci/board-dm646x-evm.c
+1
-1
arch/arm/mach-davinci/board-dm646x-evm.c
+1
-1
arch/arm/mach-davinci/board-sffsdr.c
+1
-1
arch/arm/mach-davinci/board-sffsdr.c
+1
-1
arch/arm/mach-dove/dove-db-setup.c
+1
-1
arch/arm/mach-dove/dove-db-setup.c
+1
-1
arch/arm/mach-ep93xx/snappercl15.c
+1
-1
arch/arm/mach-ep93xx/snappercl15.c
+1
-1
arch/arm/mach-ep93xx/ts72xx.c
+1
-1
arch/arm/mach-ep93xx/ts72xx.c
+1
-1
arch/arm/mach-imx/mach-qong.c
+1
-1
arch/arm/mach-imx/mach-qong.c
+1
-1
arch/arm/mach-ixp4xx/ixdp425-setup.c
+1
-1
arch/arm/mach-ixp4xx/ixdp425-setup.c
+1
-1
arch/arm/mach-mmp/aspenite.c
+1
-1
arch/arm/mach-mmp/aspenite.c
+1
-1
arch/arm/mach-omap1/board-fsample.c
+1
-1
arch/arm/mach-omap1/board-fsample.c
+1
-1
arch/arm/mach-omap1/board-h2.c
+1
-1
arch/arm/mach-omap1/board-h2.c
+1
-1
arch/arm/mach-omap1/board-h3.c
+1
-1
arch/arm/mach-omap1/board-h3.c
+1
-1
arch/arm/mach-omap1/board-nand.c
+1
-1
arch/arm/mach-omap1/board-nand.c
+1
-1
arch/arm/mach-omap1/board-perseus2.c
+1
-1
arch/arm/mach-omap1/board-perseus2.c
+1
-1
arch/arm/mach-orion5x/db88f5281-setup.c
+1
-1
arch/arm/mach-orion5x/db88f5281-setup.c
+1
-1
arch/arm/mach-orion5x/kurobox_pro-setup.c
+1
-1
arch/arm/mach-orion5x/kurobox_pro-setup.c
+1
-1
arch/arm/mach-orion5x/ts209-setup.c
+1
-1
arch/arm/mach-orion5x/ts209-setup.c
+1
-1
arch/arm/mach-orion5x/ts78xx-setup.c
+1
-1
arch/arm/mach-orion5x/ts78xx-setup.c
···
16
16
#include <linux/platform_device.h>
17
17
#include <linux/mv643xx_eth.h>
18
18
#include <linux/ata_platform.h>
19
-
#include <linux/mtd/nand.h>
19
+
#include <linux/mtd/rawnand.h>
20
20
#include <linux/mtd/partitions.h>
21
21
#include <linux/timeriomem-rng.h>
22
22
#include <asm/mach-types.h>
+1
-1
arch/arm/mach-pxa/balloon3.c
+1
-1
arch/arm/mach-pxa/balloon3.c
+1
-1
arch/arm/mach-pxa/em-x270.c
+1
-1
arch/arm/mach-pxa/em-x270.c
+1
-1
arch/arm/mach-pxa/eseries.c
+1
-1
arch/arm/mach-pxa/eseries.c
+1
-1
arch/arm/mach-pxa/palmtx.c
+1
-1
arch/arm/mach-pxa/palmtx.c
+1
-1
arch/arm/mach-pxa/tosa.c
+1
-1
arch/arm/mach-pxa/tosa.c
+1
-1
arch/arm/mach-s3c24xx/common-smdk.c
+1
-1
arch/arm/mach-s3c24xx/common-smdk.c
+1
-1
arch/arm/mach-s3c24xx/mach-anubis.c
+1
-1
arch/arm/mach-s3c24xx/mach-anubis.c
+1
-1
arch/arm/mach-s3c24xx/mach-at2440evb.c
+1
-1
arch/arm/mach-s3c24xx/mach-at2440evb.c
+1
-1
arch/arm/mach-s3c24xx/mach-bast.c
+1
-1
arch/arm/mach-s3c24xx/mach-bast.c
+1
-1
arch/arm/mach-s3c24xx/mach-gta02.c
+1
-1
arch/arm/mach-s3c24xx/mach-gta02.c
+1
-1
arch/arm/mach-s3c24xx/mach-jive.c
+1
-1
arch/arm/mach-s3c24xx/mach-jive.c
+1
-1
arch/arm/mach-s3c24xx/mach-mini2440.c
+1
-1
arch/arm/mach-s3c24xx/mach-mini2440.c
+1
-1
arch/arm/mach-s3c24xx/mach-osiris.c
+1
-1
arch/arm/mach-s3c24xx/mach-osiris.c
+1
-1
arch/arm/mach-s3c24xx/mach-qt2410.c
+1
-1
arch/arm/mach-s3c24xx/mach-qt2410.c
+1
-1
arch/arm/mach-s3c24xx/mach-rx3715.c
+1
-1
arch/arm/mach-s3c24xx/mach-rx3715.c
+1
-1
arch/arm/mach-s3c24xx/mach-vstms.c
+1
-1
arch/arm/mach-s3c24xx/mach-vstms.c
+1
-1
arch/blackfin/mach-bf537/boards/dnp5370.c
+1
-1
arch/blackfin/mach-bf537/boards/dnp5370.c
+1
-1
arch/blackfin/mach-bf537/boards/stamp.c
+1
-1
arch/blackfin/mach-bf537/boards/stamp.c
+1
-1
arch/blackfin/mach-bf561/boards/acvilon.c
+1
-1
arch/blackfin/mach-bf561/boards/acvilon.c
+1
-1
arch/cris/arch-v32/drivers/mach-a3/nandflash.c
+1
-1
arch/cris/arch-v32/drivers/mach-a3/nandflash.c
+1
-1
arch/cris/arch-v32/drivers/mach-fs/nandflash.c
+1
-1
arch/cris/arch-v32/drivers/mach-fs/nandflash.c
+1
-1
arch/mips/alchemy/devboards/db1200.c
+1
-1
arch/mips/alchemy/devboards/db1200.c
+1
-1
arch/mips/alchemy/devboards/db1300.c
+1
-1
arch/mips/alchemy/devboards/db1300.c
+1
-1
arch/mips/alchemy/devboards/db1550.c
+1
-1
arch/mips/alchemy/devboards/db1550.c
+1
-1
arch/mips/include/asm/mach-jz4740/jz4740_nand.h
+1
-1
arch/mips/include/asm/mach-jz4740/jz4740_nand.h
+1
-1
arch/mips/netlogic/xlr/platform-flash.c
+1
-1
arch/mips/netlogic/xlr/platform-flash.c
+1
-1
arch/mips/pnx833x/common/platform.c
+1
-1
arch/mips/pnx833x/common/platform.c
+1
-1
arch/mips/rb532/devices.c
+1
-1
arch/mips/rb532/devices.c
+1
-1
arch/sh/boards/mach-migor/setup.c
+1
-1
arch/sh/boards/mach-migor/setup.c
+15
-30
drivers/mtd/devices/docg3.c
+15
-30
drivers/mtd/devices/docg3.c
···
1809
1809
}
1810
1810
DEBUGFS_RO_ATTR(protection, dbg_protection_show);
1811
1811
1812
-
static int __init doc_dbg_register(struct docg3 *docg3)
1812
+
static void __init doc_dbg_register(struct mtd_info *floor)
1813
1813
{
1814
-
struct dentry *root, *entry;
1814
+
struct dentry *root = floor->dbg.dfs_dir;
1815
+
struct docg3 *docg3 = floor->priv;
1815
1816
1816
-
root = debugfs_create_dir("docg3", NULL);
1817
-
if (!root)
1818
-
return -ENOMEM;
1817
+
if (IS_ERR_OR_NULL(root))
1818
+
return;
1819
1819
1820
-
entry = debugfs_create_file("flashcontrol", S_IRUSR, root, docg3,
1821
-
&flashcontrol_fops);
1822
-
if (entry)
1823
-
entry = debugfs_create_file("asic_mode", S_IRUSR, root,
1824
-
docg3, &asic_mode_fops);
1825
-
if (entry)
1826
-
entry = debugfs_create_file("device_id", S_IRUSR, root,
1827
-
docg3, &device_id_fops);
1828
-
if (entry)
1829
-
entry = debugfs_create_file("protection", S_IRUSR, root,
1830
-
docg3, &protection_fops);
1831
-
if (entry) {
1832
-
docg3->debugfs_root = root;
1833
-
return 0;
1834
-
} else {
1835
-
debugfs_remove_recursive(root);
1836
-
return -ENOMEM;
1837
-
}
1838
-
}
1839
-
1840
-
static void doc_dbg_unregister(struct docg3 *docg3)
1841
-
{
1842
-
debugfs_remove_recursive(docg3->debugfs_root);
1820
+
debugfs_create_file("docg3_flashcontrol", S_IRUSR, root, docg3,
1821
+
&flashcontrol_fops);
1822
+
debugfs_create_file("docg3_asic_mode", S_IRUSR, root, docg3,
1823
+
&asic_mode_fops);
1824
+
debugfs_create_file("docg3_device_id", S_IRUSR, root, docg3,
1825
+
&device_id_fops);
1826
+
debugfs_create_file("docg3_protection", S_IRUSR, root, docg3,
1827
+
&protection_fops);
1843
1828
}
1844
1829
1845
1830
/**
···
2099
2114
0);
2100
2115
if (ret)
2101
2116
goto err_probe;
2117
+
2118
+
doc_dbg_register(cascade->floors[floor]);
2102
2119
}
2103
2120
2104
2121
ret = doc_register_sysfs(pdev, cascade);
···
2108
2121
goto err_probe;
2109
2122
2110
2123
platform_set_drvdata(pdev, cascade);
2111
-
doc_dbg_register(cascade->floors[0]->priv);
2112
2124
return 0;
2113
2125
2114
2126
notfound:
···
2134
2148
int floor;
2135
2149
2136
2150
doc_unregister_sysfs(pdev, cascade);
2137
-
doc_dbg_unregister(docg3);
2138
2151
for (floor = 0; floor < DOC_MAX_NBFLOORS; floor++)
2139
2152
if (cascade->floors[floor])
2140
2153
doc_release_device(cascade->floors[floor]);
-2
drivers/mtd/devices/docg3.h
-2
drivers/mtd/devices/docg3.h
···
299
299
* @oob_autoecc: if 1, use only bytes 0-7, 15, and fill the others with HW ECC
300
300
* if 0, use all the 16 bytes.
301
301
* @oob_write_buf: prepared OOB for next page_write
302
-
* @debugfs_root: debugfs root node
303
302
*/
304
303
struct docg3 {
305
304
struct device *dev;
···
311
312
loff_t oob_write_ofs;
312
313
int oob_autoecc;
313
314
u8 oob_write_buf[DOC_LAYOUT_OOB_SIZE];
314
-
struct dentry *debugfs_root;
315
315
};
316
316
317
317
#define doc_err(fmt, arg...) dev_err(docg3->dev, (fmt), ## arg)
+2
drivers/mtd/devices/spear_smi.c
+2
drivers/mtd/devices/spear_smi.c
···
775
775
pdata->board_flash_info = devm_kzalloc(&pdev->dev,
776
776
sizeof(*pdata->board_flash_info),
777
777
GFP_KERNEL);
778
+
if (!pdata->board_flash_info)
779
+
return -ENOMEM;
778
780
779
781
/* Fill structs for each subnode (flash device) */
780
782
while ((pp = of_get_next_child(np, pp))) {
+12
-8
drivers/mtd/devices/st_spi_fsm.c
+12
-8
drivers/mtd/devices/st_spi_fsm.c
···
2073
2073
ret = stfsm_init(fsm);
2074
2074
if (ret) {
2075
2075
dev_err(&pdev->dev, "Failed to initialise FSM Controller\n");
2076
-
return ret;
2076
+
goto err_clk_unprepare;
2077
2077
}
2078
2078
2079
2079
stfsm_fetch_platform_configs(pdev);
2080
2080
2081
2081
/* Detect SPI FLASH device */
2082
2082
info = stfsm_jedec_probe(fsm);
2083
-
if (!info)
2084
-
return -ENODEV;
2083
+
if (!info) {
2084
+
ret = -ENODEV;
2085
+
goto err_clk_unprepare;
2086
+
}
2085
2087
fsm->info = info;
2086
2088
2087
2089
/* Use device size to determine address width */
···
2097
2095
if (info->config) {
2098
2096
ret = info->config(fsm);
2099
2097
if (ret)
2100
-
return ret;
2098
+
goto err_clk_unprepare;
2101
2099
} else {
2102
2100
ret = stfsm_prepare_rwe_seqs_default(fsm);
2103
2101
if (ret)
2104
-
return ret;
2102
+
goto err_clk_unprepare;
2105
2103
}
2106
2104
2107
2105
fsm->mtd.name = info->name;
···
2126
2124
fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10));
2127
2125
2128
2126
return mtd_device_register(&fsm->mtd, NULL, 0);
2127
+
2128
+
err_clk_unprepare:
2129
+
clk_disable_unprepare(fsm->clk);
2130
+
return ret;
2129
2131
}
2130
2132
2131
2133
static int stfsm_remove(struct platform_device *pdev)
···
2153
2147
{
2154
2148
struct stfsm *fsm = dev_get_drvdata(dev);
2155
2149
2156
-
clk_prepare_enable(fsm->clk);
2157
-
2158
-
return 0;
2150
+
return clk_prepare_enable(fsm->clk);
2159
2151
}
2160
2152
#endif
2161
2153
+1
-1
drivers/mtd/inftlcore.c
+1
-1
drivers/mtd/inftlcore.c
+2
-2
drivers/mtd/maps/amd76xrom.c
+2
-2
drivers/mtd/maps/amd76xrom.c
···
296
296
amd76xrom_cleanup(window);
297
297
}
298
298
299
-
static struct pci_device_id amd76xrom_pci_tbl[] = {
299
+
static const struct pci_device_id amd76xrom_pci_tbl[] = {
300
300
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410,
301
301
PCI_ANY_ID, PCI_ANY_ID, },
302
302
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7440,
···
319
319
static int __init init_amd76xrom(void)
320
320
{
321
321
struct pci_dev *pdev;
322
-
struct pci_device_id *id;
322
+
const struct pci_device_id *id;
323
323
pdev = NULL;
324
324
for(id = amd76xrom_pci_tbl; id->vendor; id++) {
325
325
pdev = pci_get_device(id->vendor, id->device, NULL);
+2
-2
drivers/mtd/maps/ck804xrom.c
+2
-2
drivers/mtd/maps/ck804xrom.c
···
326
326
ck804xrom_cleanup(window);
327
327
}
328
328
329
-
static struct pci_device_id ck804xrom_pci_tbl[] = {
329
+
static const struct pci_device_id ck804xrom_pci_tbl[] = {
330
330
{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0051), .driver_data = DEV_CK804 },
331
331
{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0360), .driver_data = DEV_MCP55 },
332
332
{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0361), .driver_data = DEV_MCP55 },
···
353
353
static int __init init_ck804xrom(void)
354
354
{
355
355
struct pci_dev *pdev;
356
-
struct pci_device_id *id;
356
+
const struct pci_device_id *id;
357
357
int retVal;
358
358
pdev = NULL;
359
359
+2
-2
drivers/mtd/maps/esb2rom.c
+2
-2
drivers/mtd/maps/esb2rom.c
···
384
384
esb2rom_cleanup(window);
385
385
}
386
386
387
-
static struct pci_device_id esb2rom_pci_tbl[] = {
387
+
static const struct pci_device_id esb2rom_pci_tbl[] = {
388
388
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
389
389
PCI_ANY_ID, PCI_ANY_ID, },
390
390
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
···
414
414
static int __init init_esb2rom(void)
415
415
{
416
416
struct pci_dev *pdev;
417
-
struct pci_device_id *id;
417
+
const struct pci_device_id *id;
418
418
int retVal;
419
419
420
420
pdev = NULL;
+2
-2
drivers/mtd/maps/ichxrom.c
+2
-2
drivers/mtd/maps/ichxrom.c
···
323
323
ichxrom_cleanup(window);
324
324
}
325
325
326
-
static struct pci_device_id ichxrom_pci_tbl[] = {
326
+
static const struct pci_device_id ichxrom_pci_tbl[] = {
327
327
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
328
328
PCI_ANY_ID, PCI_ANY_ID, },
329
329
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
···
351
351
static int __init init_ichxrom(void)
352
352
{
353
353
struct pci_dev *pdev;
354
-
struct pci_device_id *id;
354
+
const struct pci_device_id *id;
355
355
356
356
pdev = NULL;
357
357
for (id = ichxrom_pci_tbl; id->vendor; id++) {
+1
-1
drivers/mtd/maps/intel_vr_nor.c
+1
-1
drivers/mtd/maps/intel_vr_nor.c
+1
-1
drivers/mtd/maps/pci.c
+1
-1
drivers/mtd/maps/pci.c
+4
-4
drivers/mtd/maps/physmap_of_core.c
+4
-4
drivers/mtd/maps/physmap_of_core.c
···
178
178
*/
179
179
p = of_get_property(dp, "reg", &count);
180
180
if (!p || count % reg_tuple_size != 0) {
181
-
dev_err(&dev->dev, "Malformed reg property on %s\n",
182
-
dev->dev.of_node->full_name);
181
+
dev_err(&dev->dev, "Malformed reg property on %pOF\n",
182
+
dev->dev.of_node);
183
183
err = -EINVAL;
184
184
goto err_flash_remove;
185
185
}
···
235
235
236
236
err = of_flash_probe_gemini(dev, dp, &info->list[i].map);
237
237
if (err)
238
-
return err;
238
+
goto err_out;
239
239
err = of_flash_probe_versatile(dev, dp, &info->list[i].map);
240
240
if (err)
241
-
return err;
241
+
goto err_out;
242
242
243
243
err = -ENOMEM;
244
244
info->list[i].map.virt = ioremap(info->list[i].map.phys,
-16
drivers/mtd/maps/physmap_of_gemini.c
-16
drivers/mtd/maps/physmap_of_gemini.c
···
43
43
44
44
#define FLASH_PARALLEL_HIGH_PIN_CNT (1 << 20) /* else low pin cnt */
45
45
46
-
/* Miscellaneous Control Register */
47
-
#define GLOBAL_MISC_CTRL 0x30
48
-
#define FLASH_PADS_MASK 0x07
49
-
#define NAND_PADS_DISABLE BIT(2)
50
-
#define PFLASH_PADS_DISABLE BIT(1)
51
-
#define SFLASH_PADS_DISABLE BIT(0)
52
-
53
46
static const struct of_device_id syscon_match[] = {
54
47
{ .compatible = "cortina,gemini-syscon" },
55
48
{ },
···
93
100
if (map->bankwidth != 1)
94
101
dev_warn(dev, "flash hardware say flash is 8 bit wide but DT says it is %d bits wide\n",
95
102
map->bankwidth * 8);
96
-
}
97
-
98
-
/* Activate parallel (NOR flash) mode */
99
-
ret = regmap_update_bits(rmap, GLOBAL_MISC_CTRL,
100
-
FLASH_PADS_MASK,
101
-
SFLASH_PADS_DISABLE | NAND_PADS_DISABLE);
102
-
if (ret) {
103
-
dev_err(dev, "unable to set up physmap pads\n");
104
-
return -ENODEV;
105
103
}
106
104
107
105
dev_info(&pdev->dev, "initialized Gemini-specific physmap control\n");
+1
-1
drivers/mtd/maps/physmap_of_versatile.c
+1
-1
drivers/mtd/maps/physmap_of_versatile.c
+2
-2
drivers/mtd/maps/sun_uflash.c
+2
-2
drivers/mtd/maps/sun_uflash.c
···
55
55
/* Non-CFI userflash device-- once I find one we
56
56
* can work on supporting it.
57
57
*/
58
-
printk(KERN_ERR PFX "Unsupported device at %s, 0x%llx\n",
59
-
dp->full_name, (unsigned long long)op->resource[0].start);
58
+
printk(KERN_ERR PFX "Unsupported device at %pOF, 0x%llx\n",
59
+
dp, (unsigned long long)op->resource[0].start);
60
60
61
61
return -ENODEV;
62
62
}
+17
-1
drivers/mtd/mtdcore.c
+17
-1
drivers/mtd/mtdcore.c
···
40
40
#include <linux/slab.h>
41
41
#include <linux/reboot.h>
42
42
#include <linux/leds.h>
43
+
#include <linux/debugfs.h>
43
44
44
45
#include <linux/mtd/mtd.h>
45
46
#include <linux/mtd/partitions.h>
···
340
339
};
341
340
ATTRIBUTE_GROUPS(mtd);
342
341
343
-
static struct device_type mtd_devtype = {
342
+
static const struct device_type mtd_devtype = {
344
343
.name = "mtd",
345
344
.groups = mtd_groups,
346
345
.release = mtd_release,
···
478
477
}
479
478
EXPORT_SYMBOL_GPL(mtd_pairing_groups);
480
479
480
+
static struct dentry *dfs_dir_mtd;
481
+
481
482
/**
482
483
* add_mtd_device - register an MTD device
483
484
* @mtd: pointer to new MTD device info structure
···
555
552
if (error)
556
553
goto fail_added;
557
554
555
+
if (!IS_ERR_OR_NULL(dfs_dir_mtd)) {
556
+
mtd->dbg.dfs_dir = debugfs_create_dir(dev_name(&mtd->dev), dfs_dir_mtd);
557
+
if (IS_ERR_OR_NULL(mtd->dbg.dfs_dir)) {
558
+
pr_debug("mtd device %s won't show data in debugfs\n",
559
+
dev_name(&mtd->dev));
560
+
}
561
+
}
562
+
558
563
device_create(&mtd_class, mtd->dev.parent, MTD_DEVT(i) + 1, NULL,
559
564
"mtd%dro", i);
560
565
···
604
593
struct mtd_notifier *not;
605
594
606
595
mutex_lock(&mtd_table_mutex);
596
+
597
+
debugfs_remove_recursive(mtd->dbg.dfs_dir);
607
598
608
599
if (idr_find(&mtd_idr, mtd->index) != mtd) {
609
600
ret = -ENODEV;
···
1824
1811
if (ret)
1825
1812
goto out_procfs;
1826
1813
1814
+
dfs_dir_mtd = debugfs_create_dir("mtd", NULL);
1815
+
1827
1816
return 0;
1828
1817
1829
1818
out_procfs:
···
1841
1826
1842
1827
static void __exit cleanup_mtd(void)
1843
1828
{
1829
+
debugfs_remove_recursive(dfs_dir_mtd);
1844
1830
cleanup_mtdchar();
1845
1831
if (proc_mtd)
1846
1832
remove_proc_entry("mtd", NULL);
+4
-17
drivers/mtd/mtdswap.c
+4
-17
drivers/mtd/mtdswap.c
···
138
138
139
139
char *page_buf;
140
140
char *oob_buf;
141
-
142
-
struct dentry *debugfs_root;
143
141
};
144
142
145
143
struct mtdswap_oobdata {
···
1313
1315
1314
1316
static int mtdswap_add_debugfs(struct mtdswap_dev *d)
1315
1317
{
1316
-
struct gendisk *gd = d->mbd_dev->disk;
1317
-
struct device *dev = disk_to_dev(gd);
1318
-
1319
-
struct dentry *root;
1318
+
struct dentry *root = d->mtd->dbg.dfs_dir;
1320
1319
struct dentry *dent;
1321
1320
1322
-
root = debugfs_create_dir(gd->disk_name, NULL);
1323
-
if (IS_ERR(root))
1321
+
if (!IS_ENABLED(CONFIG_DEBUG_FS))
1324
1322
return 0;
1325
1323
1326
-
if (!root) {
1327
-
dev_err(dev, "failed to initialize debugfs\n");
1324
+
if (IS_ERR_OR_NULL(root))
1328
1325
return -1;
1329
-
}
1330
1326
1331
-
d->debugfs_root = root;
1332
-
1333
-
dent = debugfs_create_file("stats", S_IRUSR, root, d,
1327
+
dent = debugfs_create_file("mtdswap_stats", S_IRUSR, root, d,
1334
1328
&mtdswap_fops);
1335
1329
if (!dent) {
1336
1330
dev_err(d->dev, "debugfs_create_file failed\n");
1337
-
debugfs_remove_recursive(root);
1338
-
d->debugfs_root = NULL;
1339
1331
return -1;
1340
1332
}
1341
1333
···
1528
1540
{
1529
1541
struct mtdswap_dev *d = MTDSWAP_MBD_TO_MTDSWAP(dev);
1530
1542
1531
-
debugfs_remove_recursive(d->debugfs_root);
1532
1543
del_mtd_blktrans_dev(dev);
1533
1544
mtdswap_cleanup(d);
1534
1545
kfree(d);
+1
-1
drivers/mtd/nand/Kconfig
+1
-1
drivers/mtd/nand/Kconfig
···
315
315
316
316
config MTD_NAND_PXA3xx
317
317
tristate "NAND support on PXA3xx and Armada 370/XP"
318
-
depends on PXA3xx || ARCH_MMP || PLAT_ORION
318
+
depends on PXA3xx || ARCH_MMP || PLAT_ORION || ARCH_MVEBU
319
319
help
320
320
This enables the driver for the NAND flash device found on
321
321
PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
+1
-1
drivers/mtd/nand/ams-delta.c
+1
-1
drivers/mtd/nand/ams-delta.c
+8
-7
drivers/mtd/nand/atmel/nand-controller.c
+8
-7
drivers/mtd/nand/atmel/nand-controller.c
···
59
59
#include <linux/mfd/syscon/atmel-matrix.h>
60
60
#include <linux/mfd/syscon/atmel-smc.h>
61
61
#include <linux/module.h>
62
-
#include <linux/mtd/nand.h>
62
+
#include <linux/mtd/rawnand.h>
63
63
#include <linux/of_address.h>
64
64
#include <linux/of_irq.h>
65
65
#include <linux/of_platform.h>
···
2091
2091
}
2092
2092
2093
2093
nc->irq = of_irq_get(nand_np, 0);
2094
-
if (nc->irq < 0) {
2095
-
ret = nc->irq;
2094
+
if (nc->irq <= 0) {
2095
+
ret = nc->irq ?: -ENXIO;
2096
2096
if (ret != -EPROBE_DEFER)
2097
2097
dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2098
2098
ret);
···
2183
2183
2184
2184
nc->irq = of_irq_get(np, 0);
2185
2185
of_node_put(np);
2186
-
if (nc->irq < 0) {
2187
-
if (nc->irq != -EPROBE_DEFER)
2186
+
if (nc->irq <= 0) {
2187
+
ret = nc->irq ?: -ENXIO;
2188
+
if (ret != -EPROBE_DEFER)
2188
2189
dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2189
-
nc->irq);
2190
-
return nc->irq;
2190
+
ret);
2191
+
return ret;
2191
2192
}
2192
2193
2193
2194
np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
+1
-1
drivers/mtd/nand/atmel/pmecc.c
+1
-1
drivers/mtd/nand/atmel/pmecc.c
+1
-1
drivers/mtd/nand/au1550nd.c
+1
-1
drivers/mtd/nand/au1550nd.c
+1
-1
drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
+1
-1
drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
+1
-1
drivers/mtd/nand/bf5xx_nand.c
+1
-1
drivers/mtd/nand/bf5xx_nand.c
+1
-1
drivers/mtd/nand/brcmnand/brcmnand.c
+1
-1
drivers/mtd/nand/brcmnand/brcmnand.c
+1
-1
drivers/mtd/nand/cafe_nand.c
+1
-1
drivers/mtd/nand/cafe_nand.c
+1
-1
drivers/mtd/nand/cmx270_nand.c
+1
-1
drivers/mtd/nand/cmx270_nand.c
+1
-1
drivers/mtd/nand/cs553x_nand.c
+1
-1
drivers/mtd/nand/cs553x_nand.c
+1
-1
drivers/mtd/nand/davinci_nand.c
+1
-1
drivers/mtd/nand/davinci_nand.c
+1
-1
drivers/mtd/nand/denali.h
+1
-1
drivers/mtd/nand/denali.h
+3
-1
drivers/mtd/nand/denali_dt.c
+3
-1
drivers/mtd/nand/denali_dt.c
+1
-1
drivers/mtd/nand/diskonchip.c
+1
-1
drivers/mtd/nand/diskonchip.c
+1
-1
drivers/mtd/nand/docg4.c
+1
-1
drivers/mtd/nand/docg4.c
+1
-1
drivers/mtd/nand/fsl_elbc_nand.c
+1
-1
drivers/mtd/nand/fsl_elbc_nand.c
+1
-1
drivers/mtd/nand/fsl_ifc_nand.c
+1
-1
drivers/mtd/nand/fsl_ifc_nand.c
+1
-1
drivers/mtd/nand/fsl_upm.c
+1
-1
drivers/mtd/nand/fsl_upm.c
+1
-1
drivers/mtd/nand/fsmc_nand.c
+1
-1
drivers/mtd/nand/fsmc_nand.c
+1
-1
drivers/mtd/nand/gpio.c
+1
-1
drivers/mtd/nand/gpio.c
+1
-1
drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+1
-1
drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+1
-1
drivers/mtd/nand/hisi504_nand.c
+1
-1
drivers/mtd/nand/hisi504_nand.c
+1
-1
drivers/mtd/nand/jz4740_nand.c
+1
-1
drivers/mtd/nand/jz4740_nand.c
+1
-1
drivers/mtd/nand/jz4780_nand.c
+1
-1
drivers/mtd/nand/jz4780_nand.c
+8
-3
drivers/mtd/nand/lpc32xx_mlc.c
+8
-3
drivers/mtd/nand/lpc32xx_mlc.c
···
27
27
#include <linux/module.h>
28
28
#include <linux/platform_device.h>
29
29
#include <linux/mtd/mtd.h>
30
-
#include <linux/mtd/nand.h>
30
+
#include <linux/mtd/rawnand.h>
31
31
#include <linux/mtd/partitions.h>
32
32
#include <linux/clk.h>
33
33
#include <linux/err.h>
···
705
705
res = -ENOENT;
706
706
goto err_exit1;
707
707
}
708
-
clk_prepare_enable(host->clk);
708
+
res = clk_prepare_enable(host->clk);
709
+
if (res)
710
+
goto err_exit1;
709
711
710
712
nand_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
711
713
nand_chip->dev_ready = lpc32xx_nand_device_ready;
···
848
846
static int lpc32xx_nand_resume(struct platform_device *pdev)
849
847
{
850
848
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
849
+
int ret;
851
850
852
851
/* Re-enable NAND clock */
853
-
clk_prepare_enable(host->clk);
852
+
ret = clk_prepare_enable(host->clk);
853
+
if (ret)
854
+
return ret;
854
855
855
856
/* Fresh init of NAND controller */
856
857
lpc32xx_nand_setup(host);
+8
-3
drivers/mtd/nand/lpc32xx_slc.c
+8
-3
drivers/mtd/nand/lpc32xx_slc.c
···
23
23
#include <linux/module.h>
24
24
#include <linux/platform_device.h>
25
25
#include <linux/mtd/mtd.h>
26
-
#include <linux/mtd/nand.h>
26
+
#include <linux/mtd/rawnand.h>
27
27
#include <linux/mtd/partitions.h>
28
28
#include <linux/clk.h>
29
29
#include <linux/err.h>
···
840
840
res = -ENOENT;
841
841
goto err_exit1;
842
842
}
843
-
clk_prepare_enable(host->clk);
843
+
res = clk_prepare_enable(host->clk);
844
+
if (res)
845
+
goto err_exit1;
844
846
845
847
/* Set NAND IO addresses and command/ready functions */
846
848
chip->IO_ADDR_R = SLC_DATA(host->io_base);
···
974
972
static int lpc32xx_nand_resume(struct platform_device *pdev)
975
973
{
976
974
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
975
+
int ret;
977
976
978
977
/* Re-enable NAND clock */
979
-
clk_prepare_enable(host->clk);
978
+
ret = clk_prepare_enable(host->clk);
979
+
if (ret)
980
+
return ret;
980
981
981
982
/* Fresh init of NAND controller */
982
983
lpc32xx_nand_setup(host);
+1
-1
drivers/mtd/nand/mpc5121_nfc.c
+1
-1
drivers/mtd/nand/mpc5121_nfc.c
+2
-2
drivers/mtd/nand/mtk_ecc.c
+2
-2
drivers/mtd/nand/mtk_ecc.c
+1
-1
drivers/mtd/nand/mtk_nand.c
+1
-1
drivers/mtd/nand/mtk_nand.c
+5
-4
drivers/mtd/nand/mxc_nand.c
+5
-4
drivers/mtd/nand/mxc_nand.c
···
22
22
#include <linux/init.h>
23
23
#include <linux/module.h>
24
24
#include <linux/mtd/mtd.h>
25
-
#include <linux/mtd/nand.h>
25
+
#include <linux/mtd/rawnand.h>
26
26
#include <linux/mtd/partitions.h>
27
27
#include <linux/interrupt.h>
28
28
#include <linux/device.h>
···
876
876
}
877
877
}
878
878
879
+
#define MXC_V1_ECCBYTES 5
880
+
879
881
static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
880
882
struct mtd_oob_region *oobregion)
881
883
{
···
887
885
return -ERANGE;
888
886
889
887
oobregion->offset = (section * 16) + 6;
890
-
oobregion->length = nand_chip->ecc.bytes;
888
+
oobregion->length = MXC_V1_ECCBYTES;
891
889
892
890
return 0;
893
891
}
···
909
907
oobregion->length = 4;
910
908
}
911
909
} else {
912
-
oobregion->offset = ((section - 1) * 16) +
913
-
nand_chip->ecc.bytes + 6;
910
+
oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
914
911
if (section < nand_chip->ecc.steps)
915
912
oobregion->length = (section * 16) + 6 -
916
913
oobregion->offset;
+1
-1
drivers/mtd/nand/nand_amd.c
+1
-1
drivers/mtd/nand/nand_amd.c
+64
-240
drivers/mtd/nand/nand_base.c
+64
-240
drivers/mtd/nand/nand_base.c
···
39
39
#include <linux/nmi.h>
40
40
#include <linux/types.h>
41
41
#include <linux/mtd/mtd.h>
42
-
#include <linux/mtd/nand.h>
42
+
#include <linux/mtd/rawnand.h>
43
43
#include <linux/mtd/nand_ecc.h>
44
44
#include <linux/mtd/nand_bch.h>
45
45
#include <linux/interrupt.h>
···
1246
1246
1247
1247
return 0;
1248
1248
}
1249
-
1250
-
/**
1251
-
* __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1252
-
* @mtd: mtd info
1253
-
* @ofs: offset to start unlock from
1254
-
* @len: length to unlock
1255
-
* @invert:
1256
-
* - when = 0, unlock the range of blocks within the lower and
1257
-
* upper boundary address
1258
-
* - when = 1, unlock the range of blocks outside the boundaries
1259
-
* of the lower and upper boundary address
1260
-
*
1261
-
* Returs unlock status.
1262
-
*/
1263
-
static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1264
-
uint64_t len, int invert)
1265
-
{
1266
-
int ret = 0;
1267
-
int status, page;
1268
-
struct nand_chip *chip = mtd_to_nand(mtd);
1269
-
1270
-
/* Submit address of first page to unlock */
1271
-
page = ofs >> chip->page_shift;
1272
-
chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1273
-
1274
-
/* Submit address of last page to unlock */
1275
-
page = (ofs + len) >> chip->page_shift;
1276
-
chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1277
-
(page | invert) & chip->pagemask);
1278
-
1279
-
/* Call wait ready function */
1280
-
status = chip->waitfunc(mtd, chip);
1281
-
/* See if device thinks it succeeded */
1282
-
if (status & NAND_STATUS_FAIL) {
1283
-
pr_debug("%s: error status = 0x%08x\n",
1284
-
__func__, status);
1285
-
ret = -EIO;
1286
-
}
1287
-
1288
-
return ret;
1289
-
}
1290
-
1291
-
/**
1292
-
* nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1293
-
* @mtd: mtd info
1294
-
* @ofs: offset to start unlock from
1295
-
* @len: length to unlock
1296
-
*
1297
-
* Returns unlock status.
1298
-
*/
1299
-
int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1300
-
{
1301
-
int ret = 0;
1302
-
int chipnr;
1303
-
struct nand_chip *chip = mtd_to_nand(mtd);
1304
-
1305
-
pr_debug("%s: start = 0x%012llx, len = %llu\n",
1306
-
__func__, (unsigned long long)ofs, len);
1307
-
1308
-
if (check_offs_len(mtd, ofs, len))
1309
-
return -EINVAL;
1310
-
1311
-
/* Align to last block address if size addresses end of the device */
1312
-
if (ofs + len == mtd->size)
1313
-
len -= mtd->erasesize;
1314
-
1315
-
nand_get_device(mtd, FL_UNLOCKING);
1316
-
1317
-
/* Shift to get chip number */
1318
-
chipnr = ofs >> chip->chip_shift;
1319
-
1320
-
/*
1321
-
* Reset the chip.
1322
-
* If we want to check the WP through READ STATUS and check the bit 7
1323
-
* we must reset the chip
1324
-
* some operation can also clear the bit 7 of status register
1325
-
* eg. erase/program a locked block
1326
-
*/
1327
-
nand_reset(chip, chipnr);
1328
-
1329
-
chip->select_chip(mtd, chipnr);
1330
-
1331
-
/* Check, if it is write protected */
1332
-
if (nand_check_wp(mtd)) {
1333
-
pr_debug("%s: device is write protected!\n",
1334
-
__func__);
1335
-
ret = -EIO;
1336
-
goto out;
1337
-
}
1338
-
1339
-
ret = __nand_unlock(mtd, ofs, len, 0);
1340
-
1341
-
out:
1342
-
chip->select_chip(mtd, -1);
1343
-
nand_release_device(mtd);
1344
-
1345
-
return ret;
1346
-
}
1347
-
EXPORT_SYMBOL(nand_unlock);
1348
-
1349
-
/**
1350
-
* nand_lock - [REPLACEABLE] locks all blocks present in the device
1351
-
* @mtd: mtd info
1352
-
* @ofs: offset to start unlock from
1353
-
* @len: length to unlock
1354
-
*
1355
-
* This feature is not supported in many NAND parts. 'Micron' NAND parts do
1356
-
* have this feature, but it allows only to lock all blocks, not for specified
1357
-
* range for block. Implementing 'lock' feature by making use of 'unlock', for
1358
-
* now.
1359
-
*
1360
-
* Returns lock status.
1361
-
*/
1362
-
int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1363
-
{
1364
-
int ret = 0;
1365
-
int chipnr, status, page;
1366
-
struct nand_chip *chip = mtd_to_nand(mtd);
1367
-
1368
-
pr_debug("%s: start = 0x%012llx, len = %llu\n",
1369
-
__func__, (unsigned long long)ofs, len);
1370
-
1371
-
if (check_offs_len(mtd, ofs, len))
1372
-
return -EINVAL;
1373
-
1374
-
nand_get_device(mtd, FL_LOCKING);
1375
-
1376
-
/* Shift to get chip number */
1377
-
chipnr = ofs >> chip->chip_shift;
1378
-
1379
-
/*
1380
-
* Reset the chip.
1381
-
* If we want to check the WP through READ STATUS and check the bit 7
1382
-
* we must reset the chip
1383
-
* some operation can also clear the bit 7 of status register
1384
-
* eg. erase/program a locked block
1385
-
*/
1386
-
nand_reset(chip, chipnr);
1387
-
1388
-
chip->select_chip(mtd, chipnr);
1389
-
1390
-
/* Check, if it is write protected */
1391
-
if (nand_check_wp(mtd)) {
1392
-
pr_debug("%s: device is write protected!\n",
1393
-
__func__);
1394
-
status = MTD_ERASE_FAILED;
1395
-
ret = -EIO;
1396
-
goto out;
1397
-
}
1398
-
1399
-
/* Submit address of first page to lock */
1400
-
page = ofs >> chip->page_shift;
1401
-
chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1402
-
1403
-
/* Call wait ready function */
1404
-
status = chip->waitfunc(mtd, chip);
1405
-
/* See if device thinks it succeeded */
1406
-
if (status & NAND_STATUS_FAIL) {
1407
-
pr_debug("%s: error status = 0x%08x\n",
1408
-
__func__, status);
1409
-
ret = -EIO;
1410
-
goto out;
1411
-
}
1412
-
1413
-
ret = __nand_unlock(mtd, ofs, len, 0x1);
1414
-
1415
-
out:
1416
-
chip->select_chip(mtd, -1);
1417
-
nand_release_device(mtd);
1418
-
1419
-
return ret;
1420
-
}
1421
-
EXPORT_SYMBOL(nand_lock);
1422
1249
1423
1250
/**
1424
1251
* nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
···
3820
3993
* nand_decode_ext_id() otherwise.
3821
3994
*/
3822
3995
if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
3823
-
chip->manufacturer.desc->ops->detect)
3996
+
chip->manufacturer.desc->ops->detect) {
3997
+
/* The 3rd id byte holds MLC / multichip data */
3998
+
chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
3824
3999
chip->manufacturer.desc->ops->detect(chip);
3825
-
else
4000
+
} else {
3826
4001
nand_decode_ext_id(chip);
4002
+
}
3827
4003
}
3828
4004
3829
4005
/*
···
3866
4036
const struct nand_manufacturer *manufacturer;
3867
4037
struct mtd_info *mtd = nand_to_mtd(chip);
3868
4038
int busw;
3869
-
int i, ret;
4039
+
int i;
3870
4040
u8 *id_data = chip->id.data;
3871
4041
u8 maf_id, dev_id;
3872
4042
···
3896
4066
chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3897
4067
3898
4068
/* Read entire ID string */
3899
-
for (i = 0; i < 8; i++)
4069
+
for (i = 0; i < ARRAY_SIZE(chip->id.data); i++)
3900
4070
id_data[i] = chip->read_byte(mtd);
3901
4071
3902
4072
if (id_data[0] != maf_id || id_data[1] != dev_id) {
···
3905
4075
return -ENODEV;
3906
4076
}
3907
4077
3908
-
chip->id.len = nand_id_len(id_data, 8);
4078
+
chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
3909
4079
3910
4080
/* Try to identify manufacturer */
3911
4081
manufacturer = nand_get_manufacturer(maf_id);
···
4006
4176
/* Do not replace user supplied command function! */
4007
4177
if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
4008
4178
chip->cmdfunc = nand_command_lp;
4009
-
4010
-
ret = nand_manufacturer_init(chip);
4011
-
if (ret)
4012
-
return ret;
4013
4179
4014
4180
pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4015
4181
maf_id, dev_id);
···
4214
4388
return ret;
4215
4389
}
4216
4390
4217
-
/* Initialize the ->data_interface field. */
4218
-
ret = nand_init_data_interface(chip);
4219
-
if (ret)
4220
-
goto err_nand_init;
4221
-
4222
-
/*
4223
-
* Setup the data interface correctly on the chip and controller side.
4224
-
* This explicit call to nand_setup_data_interface() is only required
4225
-
* for the first die, because nand_reset() has been called before
4226
-
* ->data_interface and ->default_onfi_timing_mode were set.
4227
-
* For the other dies, nand_reset() will automatically switch to the
4228
-
* best mode for us.
4229
-
*/
4230
-
ret = nand_setup_data_interface(chip, 0);
4231
-
if (ret)
4232
-
goto err_nand_init;
4233
-
4234
4391
nand_maf_id = chip->id.data[0];
4235
4392
nand_dev_id = chip->id.data[1];
4236
4393
···
4243
4434
mtd->size = i * chip->chipsize;
4244
4435
4245
4436
return 0;
4246
-
4247
-
err_nand_init:
4248
-
/* Free manufacturer priv data. */
4249
-
nand_manufacturer_cleanup(chip);
4250
-
4251
-
return ret;
4252
4437
}
4253
4438
EXPORT_SYMBOL(nand_scan_ident);
4254
4439
···
4629
4826
struct nand_chip *chip = mtd_to_nand(mtd);
4630
4827
struct nand_ecc_ctrl *ecc = &chip->ecc;
4631
4828
struct nand_buffers *nbuf = NULL;
4632
-
int ret;
4829
+
int ret, i;
4633
4830
4634
4831
/* New bad blocks should be marked in OOB, flash-based BBT, or both */
4635
4832
if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4636
4833
!(chip->bbt_options & NAND_BBT_USE_FLASH))) {
4637
-
ret = -EINVAL;
4638
-
goto err_ident;
4834
+
return -EINVAL;
4639
4835
}
4640
4836
4641
4837
if (invalid_ecc_page_accessors(chip)) {
4642
4838
pr_err("Invalid ECC page accessors setup\n");
4643
-
ret = -EINVAL;
4644
-
goto err_ident;
4839
+
return -EINVAL;
4645
4840
}
4646
4841
4647
4842
if (!(chip->options & NAND_OWN_BUFFERS)) {
4648
4843
nbuf = kzalloc(sizeof(*nbuf), GFP_KERNEL);
4649
-
if (!nbuf) {
4650
-
ret = -ENOMEM;
4651
-
goto err_ident;
4652
-
}
4844
+
if (!nbuf)
4845
+
return -ENOMEM;
4653
4846
4654
4847
nbuf->ecccalc = kmalloc(mtd->oobsize, GFP_KERNEL);
4655
4848
if (!nbuf->ecccalc) {
4656
4849
ret = -ENOMEM;
4657
-
goto err_free;
4850
+
goto err_free_nbuf;
4658
4851
}
4659
4852
4660
4853
nbuf->ecccode = kmalloc(mtd->oobsize, GFP_KERNEL);
4661
4854
if (!nbuf->ecccode) {
4662
4855
ret = -ENOMEM;
4663
-
goto err_free;
4856
+
goto err_free_nbuf;
4664
4857
}
4665
4858
4666
4859
nbuf->databuf = kmalloc(mtd->writesize + mtd->oobsize,
4667
4860
GFP_KERNEL);
4668
4861
if (!nbuf->databuf) {
4669
4862
ret = -ENOMEM;
4670
-
goto err_free;
4863
+
goto err_free_nbuf;
4671
4864
}
4672
4865
4673
4866
chip->buffers = nbuf;
4674
-
} else {
4675
-
if (!chip->buffers) {
4676
-
ret = -ENOMEM;
4677
-
goto err_ident;
4678
-
}
4867
+
} else if (!chip->buffers) {
4868
+
return -ENOMEM;
4679
4869
}
4870
+
4871
+
/*
4872
+
* FIXME: some NAND manufacturer drivers expect the first die to be
4873
+
* selected when manufacturer->init() is called. They should be fixed
4874
+
* to explictly select the relevant die when interacting with the NAND
4875
+
* chip.
4876
+
*/
4877
+
chip->select_chip(mtd, 0);
4878
+
ret = nand_manufacturer_init(chip);
4879
+
chip->select_chip(mtd, -1);
4880
+
if (ret)
4881
+
goto err_free_nbuf;
4680
4882
4681
4883
/* Set the internal oob buffer location, just after the page data */
4682
4884
chip->oob_poi = chip->buffers->databuf + mtd->writesize;
···
4704
4896
WARN(1, "No oob scheme defined for oobsize %d\n",
4705
4897
mtd->oobsize);
4706
4898
ret = -EINVAL;
4707
-
goto err_free;
4899
+
goto err_nand_manuf_cleanup;
4708
4900
}
4709
4901
}
4710
4902
···
4719
4911
if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4720
4912
WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4721
4913
ret = -EINVAL;
4722
-
goto err_free;
4914
+
goto err_nand_manuf_cleanup;
4723
4915
}
4724
4916
if (!ecc->read_page)
4725
4917
ecc->read_page = nand_read_page_hwecc_oob_first;
···
4751
4943
ecc->write_page == nand_write_page_hwecc)) {
4752
4944
WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4753
4945
ret = -EINVAL;
4754
-
goto err_free;
4946
+
goto err_nand_manuf_cleanup;
4755
4947
}
4756
4948
/* Use standard syndrome read/write page function? */
4757
4949
if (!ecc->read_page)
···
4771
4963
if (!ecc->strength) {
4772
4964
WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4773
4965
ret = -EINVAL;
4774
-
goto err_free;
4966
+
goto err_nand_manuf_cleanup;
4775
4967
}
4776
4968
break;
4777
4969
}
···
4784
4976
ret = nand_set_ecc_soft_ops(mtd);
4785
4977
if (ret) {
4786
4978
ret = -EINVAL;
4787
-
goto err_free;
4979
+
goto err_nand_manuf_cleanup;
4788
4980
}
4789
4981
break;
4790
4982
···
4792
4984
if (!ecc->read_page || !ecc->write_page) {
4793
4985
WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
4794
4986
ret = -EINVAL;
4795
-
goto err_free;
4987
+
goto err_nand_manuf_cleanup;
4796
4988
}
4797
4989
if (!ecc->read_oob)
4798
4990
ecc->read_oob = nand_read_oob_std;
···
4816
5008
default:
4817
5009
WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
4818
5010
ret = -EINVAL;
4819
-
goto err_free;
5011
+
goto err_nand_manuf_cleanup;
4820
5012
}
4821
5013
4822
5014
/* For many systems, the standard OOB write also works for raw */
···
4837
5029
if (ecc->steps * ecc->size != mtd->writesize) {
4838
5030
WARN(1, "Invalid ECC parameters\n");
4839
5031
ret = -EINVAL;
4840
-
goto err_free;
5032
+
goto err_nand_manuf_cleanup;
4841
5033
}
4842
5034
ecc->total = ecc->steps * ecc->bytes;
4843
5035
if (ecc->total > mtd->oobsize) {
4844
5036
WARN(1, "Total number of ECC bytes exceeded oobsize\n");
4845
5037
ret = -EINVAL;
4846
-
goto err_free;
5038
+
goto err_nand_manuf_cleanup;
4847
5039
}
4848
5040
4849
5041
/*
···
4925
5117
if (!mtd->bitflip_threshold)
4926
5118
mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4927
5119
5120
+
/* Initialize the ->data_interface field. */
5121
+
ret = nand_init_data_interface(chip);
5122
+
if (ret)
5123
+
goto err_nand_manuf_cleanup;
5124
+
5125
+
/* Enter fastest possible mode on all dies. */
5126
+
for (i = 0; i < chip->numchips; i++) {
5127
+
chip->select_chip(mtd, i);
5128
+
ret = nand_setup_data_interface(chip, i);
5129
+
chip->select_chip(mtd, -1);
5130
+
5131
+
if (ret)
5132
+
goto err_nand_data_iface_cleanup;
5133
+
}
5134
+
4928
5135
/* Check, if we should skip the bad block table scan */
4929
5136
if (chip->options & NAND_SKIP_BBTSCAN)
4930
5137
return 0;
···
4947
5124
/* Build bad block table */
4948
5125
ret = chip->scan_bbt(mtd);
4949
5126
if (ret)
4950
-
goto err_free;
5127
+
goto err_nand_data_iface_cleanup;
5128
+
4951
5129
return 0;
4952
5130
4953
-
err_free:
5131
+
err_nand_data_iface_cleanup:
5132
+
nand_release_data_interface(chip);
5133
+
5134
+
err_nand_manuf_cleanup:
5135
+
nand_manufacturer_cleanup(chip);
5136
+
5137
+
err_free_nbuf:
4954
5138
if (nbuf) {
4955
5139
kfree(nbuf->databuf);
4956
5140
kfree(nbuf->ecccode);
4957
5141
kfree(nbuf->ecccalc);
4958
5142
kfree(nbuf);
4959
5143
}
4960
-
4961
-
err_ident:
4962
-
/* Clean up nand_scan_ident(). */
4963
-
4964
-
/* Free manufacturer priv data. */
4965
-
nand_manufacturer_cleanup(chip);
4966
5144
4967
5145
return ret;
4968
5146
}
+1
-1
drivers/mtd/nand/nand_bbt.c
+1
-1
drivers/mtd/nand/nand_bbt.c
+1
-1
drivers/mtd/nand/nand_bch.c
+1
-1
drivers/mtd/nand/nand_bch.c
+1
-1
drivers/mtd/nand/nand_ecc.c
+1
-1
drivers/mtd/nand/nand_ecc.c
+3
-3
drivers/mtd/nand/nand_hynix.c
+3
-3
drivers/mtd/nand/nand_hynix.c
···
15
15
* GNU General Public License for more details.
16
16
*/
17
17
18
-
#include <linux/mtd/nand.h>
18
+
#include <linux/mtd/rawnand.h>
19
19
#include <linux/sizes.h>
20
20
#include <linux/slab.h>
21
21
···
477
477
* The ECC requirements field meaning depends on the
478
478
* NAND technology.
479
479
*/
480
-
u8 nand_tech = chip->id.data[5] & 0x3;
480
+
u8 nand_tech = chip->id.data[5] & 0x7;
481
481
482
482
if (nand_tech < 3) {
483
483
/* > 26nm, reference: H27UBG8T2A datasheet */
···
533
533
if (nand_tech > 0)
534
534
chip->options |= NAND_NEED_SCRAMBLING;
535
535
} else {
536
-
nand_tech = chip->id.data[5] & 0x3;
536
+
nand_tech = chip->id.data[5] & 0x7;
537
537
538
538
/* < 32nm */
539
539
if (nand_tech > 2)
+1
-1
drivers/mtd/nand/nand_ids.c
+1
-1
drivers/mtd/nand/nand_ids.c
+1
-1
drivers/mtd/nand/nand_macronix.c
+1
-1
drivers/mtd/nand/nand_macronix.c
+1
-1
drivers/mtd/nand/nand_micron.c
+1
-1
drivers/mtd/nand/nand_micron.c
+1
-1
drivers/mtd/nand/nand_samsung.c
+1
-1
drivers/mtd/nand/nand_samsung.c
+1
-1
drivers/mtd/nand/nand_timings.c
+1
-1
drivers/mtd/nand/nand_timings.c
+1
-1
drivers/mtd/nand/nand_toshiba.c
+1
-1
drivers/mtd/nand/nand_toshiba.c
+13
-38
drivers/mtd/nand/nandsim.c
+13
-38
drivers/mtd/nand/nandsim.c
···
33
33
#include <linux/errno.h>
34
34
#include <linux/string.h>
35
35
#include <linux/mtd/mtd.h>
36
-
#include <linux/mtd/nand.h>
36
+
#include <linux/mtd/rawnand.h>
37
37
#include <linux/mtd/nand_bch.h>
38
38
#include <linux/mtd/partitions.h>
39
39
#include <linux/delay.h>
···
287
287
/* Maximum page cache pages needed to read or write a NAND page to the cache_file */
288
288
#define NS_MAX_HELD_PAGES 16
289
289
290
-
struct nandsim_debug_info {
291
-
struct dentry *dfs_root;
292
-
struct dentry *dfs_wear_report;
293
-
};
294
-
295
290
/*
296
291
* A union to represent flash memory contents and flash buffer.
297
292
*/
···
365
370
void *file_buf;
366
371
struct page *held_pages[NS_MAX_HELD_PAGES];
367
372
int held_cnt;
368
-
369
-
struct nandsim_debug_info dbg;
370
373
};
371
374
372
375
/*
···
517
524
*/
518
525
static int nandsim_debugfs_create(struct nandsim *dev)
519
526
{
520
-
struct nandsim_debug_info *dbg = &dev->dbg;
527
+
struct dentry *root = nsmtd->dbg.dfs_dir;
521
528
struct dentry *dent;
522
529
523
530
if (!IS_ENABLED(CONFIG_DEBUG_FS))
524
531
return 0;
525
532
526
-
dent = debugfs_create_dir("nandsim", NULL);
527
-
if (!dent) {
528
-
NS_ERR("cannot create \"nandsim\" debugfs directory\n");
529
-
return -ENODEV;
530
-
}
531
-
dbg->dfs_root = dent;
533
+
if (IS_ERR_OR_NULL(root))
534
+
return -1;
532
535
533
-
dent = debugfs_create_file("wear_report", S_IRUSR,
534
-
dbg->dfs_root, dev, &dfs_fops);
535
-
if (!dent)
536
-
goto out_remove;
537
-
dbg->dfs_wear_report = dent;
536
+
dent = debugfs_create_file("nandsim_wear_report", S_IRUSR,
537
+
root, dev, &dfs_fops);
538
+
if (IS_ERR_OR_NULL(dent)) {
539
+
NS_ERR("cannot create \"nandsim_wear_report\" debugfs entry\n");
540
+
return -1;
541
+
}
538
542
539
543
return 0;
540
-
541
-
out_remove:
542
-
debugfs_remove_recursive(dbg->dfs_root);
543
-
return -ENODEV;
544
-
}
545
-
546
-
/**
547
-
* nandsim_debugfs_remove - destroy all debugfs files
548
-
*/
549
-
static void nandsim_debugfs_remove(struct nandsim *ns)
550
-
{
551
-
if (IS_ENABLED(CONFIG_DEBUG_FS))
552
-
debugfs_remove_recursive(ns->dbg.dfs_root);
553
544
}
554
545
555
546
/*
···
2329
2352
if ((retval = setup_wear_reporting(nsmtd)) != 0)
2330
2353
goto err_exit;
2331
2354
2332
-
if ((retval = nandsim_debugfs_create(nand)) != 0)
2333
-
goto err_exit;
2334
-
2335
2355
if ((retval = init_nandsim(nsmtd)) != 0)
2336
2356
goto err_exit;
2337
2357
···
2344
2370
if (retval != 0)
2345
2371
goto err_exit;
2346
2372
2373
+
if ((retval = nandsim_debugfs_create(nand)) != 0)
2374
+
goto err_exit;
2375
+
2347
2376
return 0;
2348
2377
2349
2378
err_exit:
2350
-
nandsim_debugfs_remove(nand);
2351
2379
free_nandsim(nand);
2352
2380
nand_release(nsmtd);
2353
2381
for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i)
···
2372
2396
struct nandsim *ns = nand_get_controller_data(chip);
2373
2397
int i;
2374
2398
2375
-
nandsim_debugfs_remove(ns);
2376
2399
free_nandsim(ns); /* Free nandsim private resources */
2377
2400
nand_release(nsmtd); /* Unregister driver */
2378
2401
for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i)
+1
-1
drivers/mtd/nand/ndfc.c
+1
-1
drivers/mtd/nand/ndfc.c
+1
-1
drivers/mtd/nand/nuc900_nand.c
+1
-1
drivers/mtd/nand/nuc900_nand.c
+1
-1
drivers/mtd/nand/omap2.c
+1
-1
drivers/mtd/nand/omap2.c
+8
-1
drivers/mtd/nand/orion_nand.c
+8
-1
drivers/mtd/nand/orion_nand.c
···
15
15
#include <linux/platform_device.h>
16
16
#include <linux/of.h>
17
17
#include <linux/mtd/mtd.h>
18
-
#include <linux/mtd/nand.h>
18
+
#include <linux/mtd/rawnand.h>
19
19
#include <linux/mtd/partitions.h>
20
20
#include <linux/clk.h>
21
21
#include <linux/err.h>
···
54
54
{
55
55
struct nand_chip *chip = mtd_to_nand(mtd);
56
56
void __iomem *io_base = chip->IO_ADDR_R;
57
+
#if __LINUX_ARM_ARCH__ >= 5
57
58
uint64_t *buf64;
59
+
#endif
58
60
int i = 0;
59
61
60
62
while (len && (unsigned long)buf & 7) {
61
63
*buf++ = readb(io_base);
62
64
len--;
63
65
}
66
+
#if __LINUX_ARM_ARCH__ >= 5
64
67
buf64 = (uint64_t *)buf;
65
68
while (i < len/8) {
66
69
/*
···
77
74
buf64[i++] = x;
78
75
}
79
76
i *= 8;
77
+
#else
78
+
readsl(io_base, buf, len/4);
79
+
i = len / 4 * 4;
80
+
#endif
80
81
while (i < len)
81
82
buf[i++] = readb(io_base);
82
83
}
+19
-8
drivers/mtd/nand/oxnas_nand.c
+19
-8
drivers/mtd/nand/oxnas_nand.c
···
21
21
#include <linux/clk.h>
22
22
#include <linux/reset.h>
23
23
#include <linux/mtd/mtd.h>
24
-
#include <linux/mtd/nand.h>
24
+
#include <linux/mtd/rawnand.h>
25
25
#include <linux/mtd/partitions.h>
26
26
#include <linux/of.h>
27
27
···
112
112
if (count > 1)
113
113
return -EINVAL;
114
114
115
-
clk_prepare_enable(oxnas->clk);
115
+
err = clk_prepare_enable(oxnas->clk);
116
+
if (err)
117
+
return err;
118
+
116
119
device_reset_optional(&pdev->dev);
117
120
118
121
for_each_child_of_node(np, nand_np) {
119
122
chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
120
123
GFP_KERNEL);
121
-
if (!chip)
122
-
return -ENOMEM;
124
+
if (!chip) {
125
+
err = -ENOMEM;
126
+
goto err_clk_unprepare;
127
+
}
123
128
124
129
chip->controller = &oxnas->base;
125
130
···
144
139
/* Scan to find existence of the device */
145
140
err = nand_scan(mtd, 1);
146
141
if (err)
147
-
return err;
142
+
goto err_clk_unprepare;
148
143
149
144
err = mtd_device_register(mtd, NULL, 0);
150
145
if (err) {
151
146
nand_release(mtd);
152
-
return err;
147
+
goto err_clk_unprepare;
153
148
}
154
149
155
150
oxnas->chips[nchips] = chip;
···
157
152
}
158
153
159
154
/* Exit if no chips found */
160
-
if (!nchips)
161
-
return -ENODEV;
155
+
if (!nchips) {
156
+
err = -ENODEV;
157
+
goto err_clk_unprepare;
158
+
}
162
159
163
160
platform_set_drvdata(pdev, oxnas);
164
161
165
162
return 0;
163
+
164
+
err_clk_unprepare:
165
+
clk_disable_unprepare(oxnas->clk);
166
+
return err;
166
167
}
167
168
168
169
static int oxnas_nand_remove(struct platform_device *pdev)
+1
-1
drivers/mtd/nand/pasemi_nand.c
+1
-1
drivers/mtd/nand/pasemi_nand.c
+1
-1
drivers/mtd/nand/plat_nand.c
+1
-1
drivers/mtd/nand/plat_nand.c
+1
-1
drivers/mtd/nand/pxa3xx_nand.c
+1
-1
drivers/mtd/nand/pxa3xx_nand.c
+767
-156
drivers/mtd/nand/qcom_nandc.c
+767
-156
drivers/mtd/nand/qcom_nandc.c
···
17
17
#include <linux/dma-mapping.h>
18
18
#include <linux/dmaengine.h>
19
19
#include <linux/module.h>
20
-
#include <linux/mtd/nand.h>
20
+
#include <linux/mtd/rawnand.h>
21
21
#include <linux/mtd/partitions.h>
22
22
#include <linux/of.h>
23
23
#include <linux/of_device.h>
···
53
53
#define NAND_VERSION 0xf08
54
54
#define NAND_READ_LOCATION_0 0xf20
55
55
#define NAND_READ_LOCATION_1 0xf24
56
+
#define NAND_READ_LOCATION_2 0xf28
57
+
#define NAND_READ_LOCATION_3 0xf2c
56
58
57
59
/* dummy register offsets, used by write_reg_dma */
58
60
#define NAND_DEV_CMD1_RESTORE 0xdead
···
111
109
#define READ_ADDR 0
112
110
113
111
/* NAND_DEV_CMD_VLD bits */
114
-
#define READ_START_VLD 0
112
+
#define READ_START_VLD BIT(0)
113
+
#define READ_STOP_VLD BIT(1)
114
+
#define WRITE_START_VLD BIT(2)
115
+
#define ERASE_START_VLD BIT(3)
116
+
#define SEQ_READ_START_VLD BIT(4)
115
117
116
118
/* NAND_EBI2_ECC_BUF_CFG bits */
117
119
#define NUM_STEPS 0
···
137
131
#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
138
132
#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
139
133
134
+
/* NAND_READ_LOCATION_n bits */
135
+
#define READ_LOCATION_OFFSET 0
136
+
#define READ_LOCATION_SIZE 16
137
+
#define READ_LOCATION_LAST 31
138
+
140
139
/* Version Mask */
141
140
#define NAND_VERSION_MAJOR_MASK 0xf0000000
142
141
#define NAND_VERSION_MAJOR_SHIFT 28
···
158
147
#define BLOCK_ERASE 0xa
159
148
#define FETCH_ID 0xb
160
149
#define RESET_DEVICE 0xd
150
+
151
+
/* Default Value for NAND_DEV_CMD_VLD */
152
+
#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
153
+
ERASE_START_VLD | SEQ_READ_START_VLD)
154
+
155
+
/* NAND_CTRL bits */
156
+
#define BAM_MODE_EN BIT(0)
161
157
162
158
/*
163
159
* the NAND controller performs reads/writes with ECC in 516 byte chunks.
···
187
169
#define ECC_BCH_4BIT BIT(2)
188
170
#define ECC_BCH_8BIT BIT(3)
189
171
172
+
#define nandc_set_read_loc(nandc, reg, offset, size, is_last) \
173
+
nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \
174
+
((offset) << READ_LOCATION_OFFSET) | \
175
+
((size) << READ_LOCATION_SIZE) | \
176
+
((is_last) << READ_LOCATION_LAST))
177
+
178
+
/*
179
+
* Returns the actual register address for all NAND_DEV_ registers
180
+
* (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
181
+
*/
182
+
#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
183
+
184
+
#define QPIC_PER_CW_CMD_SGL 32
185
+
#define QPIC_PER_CW_DATA_SGL 8
186
+
187
+
/*
188
+
* Flags used in DMA descriptor preparation helper functions
189
+
* (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
190
+
*/
191
+
/* Don't set the EOT in current tx BAM sgl */
192
+
#define NAND_BAM_NO_EOT BIT(0)
193
+
/* Set the NWD flag in current BAM sgl */
194
+
#define NAND_BAM_NWD BIT(1)
195
+
/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
196
+
#define NAND_BAM_NEXT_SGL BIT(2)
197
+
/*
198
+
* Erased codeword status is being used two times in single transfer so this
199
+
* flag will determine the current value of erased codeword status register
200
+
*/
201
+
#define NAND_ERASED_CW_SET BIT(4)
202
+
203
+
/*
204
+
* This data type corresponds to the BAM transaction which will be used for all
205
+
* NAND transfers.
206
+
* @cmd_sgl - sgl for NAND BAM command pipe
207
+
* @data_sgl - sgl for NAND BAM consumer/producer pipe
208
+
* @cmd_sgl_pos - current index in command sgl.
209
+
* @cmd_sgl_start - start index in command sgl.
210
+
* @tx_sgl_pos - current index in data sgl for tx.
211
+
* @tx_sgl_start - start index in data sgl for tx.
212
+
* @rx_sgl_pos - current index in data sgl for rx.
213
+
* @rx_sgl_start - start index in data sgl for rx.
214
+
*/
215
+
struct bam_transaction {
216
+
struct scatterlist *cmd_sgl;
217
+
struct scatterlist *data_sgl;
218
+
u32 cmd_sgl_pos;
219
+
u32 cmd_sgl_start;
220
+
u32 tx_sgl_pos;
221
+
u32 tx_sgl_start;
222
+
u32 rx_sgl_pos;
223
+
u32 rx_sgl_start;
224
+
};
225
+
226
+
/*
227
+
* This data type corresponds to the nand dma descriptor
228
+
* @list - list for desc_info
229
+
* @dir - DMA transfer direction
230
+
* @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
231
+
* ADM
232
+
* @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
233
+
* @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
234
+
* @dma_desc - low level DMA engine descriptor
235
+
*/
190
236
struct desc_info {
191
237
struct list_head node;
192
238
193
239
enum dma_data_direction dir;
194
-
struct scatterlist sgl;
240
+
union {
241
+
struct scatterlist adm_sgl;
242
+
struct {
243
+
struct scatterlist *bam_sgl;
244
+
int sgl_cnt;
245
+
};
246
+
};
195
247
struct dma_async_tx_descriptor *dma_desc;
196
248
};
197
249
···
290
202
__le32 orig_vld;
291
203
292
204
__le32 ecc_buf_cfg;
205
+
__le32 read_location0;
206
+
__le32 read_location1;
207
+
__le32 read_location2;
208
+
__le32 read_location3;
209
+
210
+
__le32 erased_cw_detect_cfg_clr;
211
+
__le32 erased_cw_detect_cfg_set;
293
212
};
294
213
295
214
/*
···
321
226
* by upper layers directly
322
227
* @buf_size/count/start: markers for chip->read_buf/write_buf functions
323
228
* @reg_read_buf: local buffer for reading back registers via DMA
229
+
* @reg_read_dma: contains dma address for register read buffer
324
230
* @reg_read_pos: marker for data read in reg_read_buf
325
231
*
326
232
* @regs: a contiguous chunk of memory for DMA register
327
233
* writes. contains the register values to be
328
234
* written to controller
329
235
* @cmd1/vld: some fixed controller register values
330
-
* @ecc_modes: supported ECC modes by the current controller,
236
+
* @props: properties of current NAND controller,
331
237
* initialized via DT match data
238
+
* @max_cwperpage: maximum QPIC codewords required. calculated
239
+
* from all connected NAND devices pagesize
332
240
*/
333
241
struct qcom_nand_controller {
334
242
struct nand_hw_control controller;
···
345
247
struct clk *core_clk;
346
248
struct clk *aon_clk;
347
249
348
-
struct dma_chan *chan;
349
-
unsigned int cmd_crci;
350
-
unsigned int data_crci;
250
+
union {
251
+
/* will be used only by QPIC for BAM DMA */
252
+
struct {
253
+
struct dma_chan *tx_chan;
254
+
struct dma_chan *rx_chan;
255
+
struct dma_chan *cmd_chan;
256
+
};
257
+
258
+
/* will be used only by EBI2 for ADM DMA */
259
+
struct {
260
+
struct dma_chan *chan;
261
+
unsigned int cmd_crci;
262
+
unsigned int data_crci;
263
+
};
264
+
};
265
+
351
266
struct list_head desc_list;
267
+
struct bam_transaction *bam_txn;
352
268
353
269
u8 *data_buffer;
354
270
int buf_size;
355
271
int buf_count;
356
272
int buf_start;
273
+
unsigned int max_cwperpage;
357
274
358
275
__le32 *reg_read_buf;
276
+
dma_addr_t reg_read_dma;
359
277
int reg_read_pos;
360
278
361
279
struct nandc_regs *regs;
362
280
363
281
u32 cmd1, vld;
364
-
u32 ecc_modes;
282
+
const struct qcom_nandc_props *props;
365
283
};
366
284
367
285
/*
···
430
316
u32 clrreadstatus;
431
317
};
432
318
319
+
/*
320
+
* This data type corresponds to the NAND controller properties which varies
321
+
* among different NAND controllers.
322
+
* @ecc_modes - ecc mode for NAND
323
+
* @is_bam - whether NAND controller is using BAM
324
+
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
325
+
*/
326
+
struct qcom_nandc_props {
327
+
u32 ecc_modes;
328
+
bool is_bam;
329
+
u32 dev_cmd_reg_start;
330
+
};
331
+
332
+
/* Frees the BAM transaction memory */
333
+
static void free_bam_transaction(struct qcom_nand_controller *nandc)
334
+
{
335
+
struct bam_transaction *bam_txn = nandc->bam_txn;
336
+
337
+
devm_kfree(nandc->dev, bam_txn);
338
+
}
339
+
340
+
/* Allocates and Initializes the BAM transaction */
341
+
static struct bam_transaction *
342
+
alloc_bam_transaction(struct qcom_nand_controller *nandc)
343
+
{
344
+
struct bam_transaction *bam_txn;
345
+
size_t bam_txn_size;
346
+
unsigned int num_cw = nandc->max_cwperpage;
347
+
void *bam_txn_buf;
348
+
349
+
bam_txn_size =
350
+
sizeof(*bam_txn) + num_cw *
351
+
((sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
352
+
(sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
353
+
354
+
bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
355
+
if (!bam_txn_buf)
356
+
return NULL;
357
+
358
+
bam_txn = bam_txn_buf;
359
+
bam_txn_buf += sizeof(*bam_txn);
360
+
361
+
bam_txn->cmd_sgl = bam_txn_buf;
362
+
bam_txn_buf +=
363
+
sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
364
+
365
+
bam_txn->data_sgl = bam_txn_buf;
366
+
367
+
return bam_txn;
368
+
}
369
+
370
+
/* Clears the BAM transaction indexes */
371
+
static void clear_bam_transaction(struct qcom_nand_controller *nandc)
372
+
{
373
+
struct bam_transaction *bam_txn = nandc->bam_txn;
374
+
375
+
if (!nandc->props->is_bam)
376
+
return;
377
+
378
+
bam_txn->cmd_sgl_pos = 0;
379
+
bam_txn->cmd_sgl_start = 0;
380
+
bam_txn->tx_sgl_pos = 0;
381
+
bam_txn->tx_sgl_start = 0;
382
+
bam_txn->rx_sgl_pos = 0;
383
+
bam_txn->rx_sgl_start = 0;
384
+
385
+
sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
386
+
QPIC_PER_CW_CMD_SGL);
387
+
sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
388
+
QPIC_PER_CW_DATA_SGL);
389
+
}
390
+
433
391
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
434
392
{
435
393
return container_of(chip, struct qcom_nand_host, chip);
···
523
337
u32 val)
524
338
{
525
339
iowrite32(val, nandc->base + offset);
340
+
}
341
+
342
+
static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
343
+
bool is_cpu)
344
+
{
345
+
if (!nandc->props->is_bam)
346
+
return;
347
+
348
+
if (is_cpu)
349
+
dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
350
+
MAX_REG_RD *
351
+
sizeof(*nandc->reg_read_buf),
352
+
DMA_FROM_DEVICE);
353
+
else
354
+
dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
355
+
MAX_REG_RD *
356
+
sizeof(*nandc->reg_read_buf),
357
+
DMA_FROM_DEVICE);
526
358
}
527
359
528
360
static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
···
576
372
return ®s->orig_vld;
577
373
case NAND_EBI2_ECC_BUF_CFG:
578
374
return ®s->ecc_buf_cfg;
375
+
case NAND_READ_LOCATION_0:
376
+
return ®s->read_location0;
377
+
case NAND_READ_LOCATION_1:
378
+
return ®s->read_location1;
379
+
case NAND_READ_LOCATION_2:
380
+
return ®s->read_location2;
381
+
case NAND_READ_LOCATION_3:
382
+
return ®s->read_location3;
579
383
default:
580
384
return NULL;
581
385
}
···
658
446
nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
659
447
nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
660
448
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
449
+
450
+
if (read)
451
+
nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
452
+
host->cw_data : host->cw_size, 1);
661
453
}
662
454
663
-
static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
664
-
int reg_off, const void *vaddr, int size,
665
-
bool flow_control)
455
+
/*
456
+
* Maps the scatter gather list for DMA transfer and forms the DMA descriptor
457
+
* for BAM. This descriptor will be added in the NAND DMA descriptor queue
458
+
* which will be submitted to DMA engine.
459
+
*/
460
+
static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
461
+
struct dma_chan *chan,
462
+
unsigned long flags)
463
+
{
464
+
struct desc_info *desc;
465
+
struct scatterlist *sgl;
466
+
unsigned int sgl_cnt;
467
+
int ret;
468
+
struct bam_transaction *bam_txn = nandc->bam_txn;
469
+
enum dma_transfer_direction dir_eng;
470
+
struct dma_async_tx_descriptor *dma_desc;
471
+
472
+
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
473
+
if (!desc)
474
+
return -ENOMEM;
475
+
476
+
if (chan == nandc->cmd_chan) {
477
+
sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
478
+
sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
479
+
bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
480
+
dir_eng = DMA_MEM_TO_DEV;
481
+
desc->dir = DMA_TO_DEVICE;
482
+
} else if (chan == nandc->tx_chan) {
483
+
sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
484
+
sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
485
+
bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
486
+
dir_eng = DMA_MEM_TO_DEV;
487
+
desc->dir = DMA_TO_DEVICE;
488
+
} else {
489
+
sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
490
+
sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
491
+
bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
492
+
dir_eng = DMA_DEV_TO_MEM;
493
+
desc->dir = DMA_FROM_DEVICE;
494
+
}
495
+
496
+
sg_mark_end(sgl + sgl_cnt - 1);
497
+
ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
498
+
if (ret == 0) {
499
+
dev_err(nandc->dev, "failure in mapping desc\n");
500
+
kfree(desc);
501
+
return -ENOMEM;
502
+
}
503
+
504
+
desc->sgl_cnt = sgl_cnt;
505
+
desc->bam_sgl = sgl;
506
+
507
+
dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
508
+
flags);
509
+
510
+
if (!dma_desc) {
511
+
dev_err(nandc->dev, "failure in prep desc\n");
512
+
dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
513
+
kfree(desc);
514
+
return -EINVAL;
515
+
}
516
+
517
+
desc->dma_desc = dma_desc;
518
+
519
+
list_add_tail(&desc->node, &nandc->desc_list);
520
+
521
+
return 0;
522
+
}
523
+
524
+
/*
525
+
* Prepares the data descriptor for BAM DMA which will be used for NAND
526
+
* data reads and writes.
527
+
*/
528
+
static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
529
+
const void *vaddr,
530
+
int size, unsigned int flags)
531
+
{
532
+
int ret;
533
+
struct bam_transaction *bam_txn = nandc->bam_txn;
534
+
535
+
if (read) {
536
+
sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
537
+
vaddr, size);
538
+
bam_txn->rx_sgl_pos++;
539
+
} else {
540
+
sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
541
+
vaddr, size);
542
+
bam_txn->tx_sgl_pos++;
543
+
544
+
/*
545
+
* BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
546
+
* is not set, form the DMA descriptor
547
+
*/
548
+
if (!(flags & NAND_BAM_NO_EOT)) {
549
+
ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
550
+
DMA_PREP_INTERRUPT);
551
+
if (ret)
552
+
return ret;
553
+
}
554
+
}
555
+
556
+
return 0;
557
+
}
558
+
559
+
static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
560
+
int reg_off, const void *vaddr, int size,
561
+
bool flow_control)
666
562
{
667
563
struct desc_info *desc;
668
564
struct dma_async_tx_descriptor *dma_desc;
···
783
463
if (!desc)
784
464
return -ENOMEM;
785
465
786
-
sgl = &desc->sgl;
466
+
sgl = &desc->adm_sgl;
787
467
788
468
sg_init_one(sgl, vaddr, size);
789
469
···
844
524
*
845
525
* @first: offset of the first register in the contiguous block
846
526
* @num_regs: number of registers to read
527
+
* @flags: flags to control DMA descriptor preparation
847
528
*/
848
529
static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
849
-
int num_regs)
530
+
int num_regs, unsigned int flags)
850
531
{
851
532
bool flow_control = false;
852
533
void *vaddr;
···
856
535
if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
857
536
flow_control = true;
858
537
538
+
if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
539
+
first = dev_cmd_reg_addr(nandc, first);
540
+
859
541
size = num_regs * sizeof(u32);
860
542
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
861
543
nandc->reg_read_pos += num_regs;
862
544
863
-
return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
545
+
return prep_adm_dma_desc(nandc, true, first, vaddr, size, flow_control);
864
546
}
865
547
866
548
/*
···
872
548
*
873
549
* @first: offset of the first register in the contiguous block
874
550
* @num_regs: number of registers to write
551
+
* @flags: flags to control DMA descriptor preparation
875
552
*/
876
553
static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
877
-
int num_regs)
554
+
int num_regs, unsigned int flags)
878
555
{
879
556
bool flow_control = false;
880
557
struct nandc_regs *regs = nandc->regs;
···
887
562
if (first == NAND_FLASH_CMD)
888
563
flow_control = true;
889
564
890
-
if (first == NAND_DEV_CMD1_RESTORE)
891
-
first = NAND_DEV_CMD1;
565
+
if (first == NAND_ERASED_CW_DETECT_CFG) {
566
+
if (flags & NAND_ERASED_CW_SET)
567
+
vaddr = ®s->erased_cw_detect_cfg_set;
568
+
else
569
+
vaddr = ®s->erased_cw_detect_cfg_clr;
570
+
}
892
571
893
-
if (first == NAND_DEV_CMD_VLD_RESTORE)
894
-
first = NAND_DEV_CMD_VLD;
572
+
if (first == NAND_EXEC_CMD)
573
+
flags |= NAND_BAM_NWD;
574
+
575
+
if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
576
+
first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
577
+
578
+
if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
579
+
first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
895
580
896
581
size = num_regs * sizeof(u32);
897
582
898
-
return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
583
+
return prep_adm_dma_desc(nandc, false, first, vaddr, size,
584
+
flow_control);
899
585
}
900
586
901
587
/*
···
916
580
* @reg_off: offset within the controller's data buffer
917
581
* @vaddr: virtual address of the buffer we want to write to
918
582
* @size: DMA transaction size in bytes
583
+
* @flags: flags to control DMA descriptor preparation
919
584
*/
920
585
static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
921
-
const u8 *vaddr, int size)
586
+
const u8 *vaddr, int size, unsigned int flags)
922
587
{
923
-
return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
588
+
if (nandc->props->is_bam)
589
+
return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
590
+
591
+
return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
924
592
}
925
593
926
594
/*
···
934
594
* @reg_off: offset within the controller's data buffer
935
595
* @vaddr: virtual address of the buffer we want to read from
936
596
* @size: DMA transaction size in bytes
597
+
* @flags: flags to control DMA descriptor preparation
937
598
*/
938
599
static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
939
-
const u8 *vaddr, int size)
600
+
const u8 *vaddr, int size, unsigned int flags)
940
601
{
941
-
return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
602
+
if (nandc->props->is_bam)
603
+
return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
604
+
605
+
return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
942
606
}
943
607
944
608
/*
945
-
* helper to prepare dma descriptors to configure registers needed for reading a
946
-
* codeword/step in a page
609
+
* Helper to prepare DMA descriptors for configuring registers
610
+
* before reading a NAND page.
947
611
*/
948
-
static void config_cw_read(struct qcom_nand_controller *nandc)
612
+
static void config_nand_page_read(struct qcom_nand_controller *nandc)
949
613
{
950
-
write_reg_dma(nandc, NAND_FLASH_CMD, 3);
951
-
write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
952
-
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
953
-
954
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1);
955
-
956
-
read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
957
-
read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1);
614
+
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
615
+
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
616
+
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
617
+
write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
618
+
write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
619
+
NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
958
620
}
959
621
960
622
/*
961
-
* helpers to prepare dma descriptors used to configure registers needed for
962
-
* writing a codeword/step in a page
623
+
* Helper to prepare DMA descriptors for configuring registers
624
+
* before reading each codeword in NAND page.
963
625
*/
964
-
static void config_cw_write_pre(struct qcom_nand_controller *nandc)
626
+
static void config_nand_cw_read(struct qcom_nand_controller *nandc)
965
627
{
966
-
write_reg_dma(nandc, NAND_FLASH_CMD, 3);
967
-
write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
968
-
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
628
+
if (nandc->props->is_bam)
629
+
write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
630
+
NAND_BAM_NEXT_SGL);
631
+
632
+
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
633
+
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
634
+
635
+
read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
636
+
read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
637
+
NAND_BAM_NEXT_SGL);
969
638
}
970
639
971
-
static void config_cw_write_post(struct qcom_nand_controller *nandc)
640
+
/*
641
+
* Helper to prepare dma descriptors to configure registers needed for reading a
642
+
* single codeword in page
643
+
*/
644
+
static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
972
645
{
973
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1);
646
+
config_nand_page_read(nandc);
647
+
config_nand_cw_read(nandc);
648
+
}
974
649
975
-
read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
650
+
/*
651
+
* Helper to prepare DMA descriptors used to configure registers needed for
652
+
* before writing a NAND page.
653
+
*/
654
+
static void config_nand_page_write(struct qcom_nand_controller *nandc)
655
+
{
656
+
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
657
+
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
658
+
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
659
+
NAND_BAM_NEXT_SGL);
660
+
}
976
661
977
-
write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
978
-
write_reg_dma(nandc, NAND_READ_STATUS, 1);
662
+
/*
663
+
* Helper to prepare DMA descriptors for configuring registers
664
+
* before writing each codeword in NAND page.
665
+
*/
666
+
static void config_nand_cw_write(struct qcom_nand_controller *nandc)
667
+
{
668
+
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
669
+
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
670
+
671
+
read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
672
+
673
+
write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
674
+
write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
979
675
}
980
676
981
677
/*
···
1048
672
1049
673
/* configure CMD1 and VLD for ONFI param probing */
1050
674
nandc_set_reg(nandc, NAND_DEV_CMD_VLD,
1051
-
(nandc->vld & ~(1 << READ_START_VLD))
1052
-
| 0 << READ_START_VLD);
675
+
(nandc->vld & ~READ_START_VLD));
1053
676
nandc_set_reg(nandc, NAND_DEV_CMD1,
1054
677
(nandc->cmd1 & ~(0xFF << READ_ADDR))
1055
678
| NAND_CMD_PARAM << READ_ADDR);
···
1057
682
1058
683
nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
1059
684
nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
685
+
nandc_set_read_loc(nandc, 0, 0, 512, 1);
1060
686
1061
-
write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1);
1062
-
write_reg_dma(nandc, NAND_DEV_CMD1, 1);
687
+
write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
688
+
write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
1063
689
1064
690
nandc->buf_count = 512;
1065
691
memset(nandc->data_buffer, 0xff, nandc->buf_count);
1066
692
1067
-
config_cw_read(nandc);
693
+
config_nand_single_cw_page_read(nandc);
1068
694
1069
695
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
1070
-
nandc->buf_count);
696
+
nandc->buf_count, 0);
1071
697
1072
698
/* restore CMD1 and VLD regs */
1073
-
write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1);
1074
-
write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1);
699
+
write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
700
+
write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
1075
701
1076
702
return 0;
1077
703
}
···
1094
718
nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
1095
719
nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
1096
720
1097
-
write_reg_dma(nandc, NAND_FLASH_CMD, 3);
1098
-
write_reg_dma(nandc, NAND_DEV0_CFG0, 2);
1099
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1);
721
+
write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
722
+
write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
723
+
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1100
724
1101
-
read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
725
+
read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1102
726
1103
-
write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
1104
-
write_reg_dma(nandc, NAND_READ_STATUS, 1);
727
+
write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
728
+
write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
1105
729
1106
730
return 0;
1107
731
}
···
1118
742
nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
1119
743
nandc_set_reg(nandc, NAND_ADDR0, column);
1120
744
nandc_set_reg(nandc, NAND_ADDR1, 0);
1121
-
nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
745
+
nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
746
+
nandc->props->is_bam ? 0 : DM_EN);
1122
747
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1123
748
1124
-
write_reg_dma(nandc, NAND_FLASH_CMD, 4);
1125
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1);
749
+
write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
750
+
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1126
751
1127
-
read_reg_dma(nandc, NAND_READ_ID, 1);
752
+
read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1128
753
1129
754
return 0;
1130
755
}
···
1139
762
nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
1140
763
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1141
764
1142
-
write_reg_dma(nandc, NAND_FLASH_CMD, 1);
1143
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1);
765
+
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
766
+
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1144
767
1145
-
read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
768
+
read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1146
769
1147
770
return 0;
1148
771
}
···
1152
775
{
1153
776
struct desc_info *desc;
1154
777
dma_cookie_t cookie = 0;
778
+
struct bam_transaction *bam_txn = nandc->bam_txn;
779
+
int r;
780
+
781
+
if (nandc->props->is_bam) {
782
+
if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
783
+
r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
784
+
if (r)
785
+
return r;
786
+
}
787
+
788
+
if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
789
+
r = prepare_bam_async_desc(nandc, nandc->tx_chan,
790
+
DMA_PREP_INTERRUPT);
791
+
if (r)
792
+
return r;
793
+
}
794
+
795
+
if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
796
+
r = prepare_bam_async_desc(nandc, nandc->cmd_chan, 0);
797
+
if (r)
798
+
return r;
799
+
}
800
+
}
1155
801
1156
802
list_for_each_entry(desc, &nandc->desc_list, node)
1157
803
cookie = dmaengine_submit(desc->dma_desc);
1158
804
1159
-
if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
1160
-
return -ETIMEDOUT;
805
+
if (nandc->props->is_bam) {
806
+
dma_async_issue_pending(nandc->tx_chan);
807
+
dma_async_issue_pending(nandc->rx_chan);
808
+
809
+
if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
810
+
return -ETIMEDOUT;
811
+
} else {
812
+
if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
813
+
return -ETIMEDOUT;
814
+
}
1161
815
1162
816
return 0;
1163
817
}
···
1199
791
1200
792
list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
1201
793
list_del(&desc->node);
1202
-
dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
794
+
795
+
if (nandc->props->is_bam)
796
+
dma_unmap_sg(nandc->dev, desc->bam_sgl,
797
+
desc->sgl_cnt, desc->dir);
798
+
else
799
+
dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
800
+
desc->dir);
801
+
1203
802
kfree(desc);
1204
803
}
1205
804
}
···
1215
800
static void clear_read_regs(struct qcom_nand_controller *nandc)
1216
801
{
1217
802
nandc->reg_read_pos = 0;
1218
-
memset(nandc->reg_read_buf, 0,
1219
-
MAX_REG_RD * sizeof(*nandc->reg_read_buf));
803
+
nandc_read_buffer_sync(nandc, false);
1220
804
}
1221
805
1222
806
static void pre_command(struct qcom_nand_host *host, int command)
···
1229
815
host->last_command = command;
1230
816
1231
817
clear_read_regs(nandc);
818
+
819
+
if (command == NAND_CMD_RESET || command == NAND_CMD_READID ||
820
+
command == NAND_CMD_PARAM || command == NAND_CMD_ERASE1)
821
+
clear_bam_transaction(nandc);
1232
822
}
1233
823
1234
824
/*
···
1249
831
int i;
1250
832
1251
833
num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
834
+
nandc_read_buffer_sync(nandc, true);
1252
835
1253
836
for (i = 0; i < num_cw; i++) {
1254
837
u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
···
1271
852
1272
853
switch (command) {
1273
854
case NAND_CMD_READID:
855
+
nandc_read_buffer_sync(nandc, true);
1274
856
memcpy(nandc->data_buffer, nandc->reg_read_buf,
1275
857
nandc->buf_count);
1276
858
break;
···
1435
1015
int i;
1436
1016
1437
1017
buf = (struct read_stats *)nandc->reg_read_buf;
1018
+
nandc_read_buffer_sync(nandc, true);
1438
1019
1439
1020
for (i = 0; i < ecc->steps; i++, buf++) {
1440
1021
u32 flash, buffer, erased_cw;
···
1523
1102
struct nand_ecc_ctrl *ecc = &chip->ecc;
1524
1103
int i, ret;
1525
1104
1105
+
config_nand_page_read(nandc);
1106
+
1526
1107
/* queue cmd descs for each codeword */
1527
1108
for (i = 0; i < ecc->steps; i++) {
1528
1109
int data_size, oob_size;
···
1538
1115
oob_size = host->ecc_bytes_hw + host->spare_bytes;
1539
1116
}
1540
1117
1541
-
config_cw_read(nandc);
1118
+
if (nandc->props->is_bam) {
1119
+
if (data_buf && oob_buf) {
1120
+
nandc_set_read_loc(nandc, 0, 0, data_size, 0);
1121
+
nandc_set_read_loc(nandc, 1, data_size,
1122
+
oob_size, 1);
1123
+
} else if (data_buf) {
1124
+
nandc_set_read_loc(nandc, 0, 0, data_size, 1);
1125
+
} else {
1126
+
nandc_set_read_loc(nandc, 0, data_size,
1127
+
oob_size, 1);
1128
+
}
1129
+
}
1130
+
1131
+
config_nand_cw_read(nandc);
1542
1132
1543
1133
if (data_buf)
1544
1134
read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
1545
-
data_size);
1135
+
data_size, 0);
1546
1136
1547
1137
/*
1548
1138
* when ecc is enabled, the controller doesn't read the real
···
1571
1135
*oob_buf++ = 0xff;
1572
1136
1573
1137
read_data_dma(nandc, FLASH_BUF_ACC + data_size,
1574
-
oob_buf, oob_size);
1138
+
oob_buf, oob_size, 0);
1575
1139
}
1576
1140
1577
1141
if (data_buf)
···
1611
1175
set_address(host, host->cw_size * (ecc->steps - 1), page);
1612
1176
update_rw_regs(host, 1, true);
1613
1177
1614
-
config_cw_read(nandc);
1178
+
config_nand_single_cw_page_read(nandc);
1615
1179
1616
-
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
1180
+
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
1617
1181
1618
1182
ret = submit_descs(nandc);
1619
1183
if (ret)
···
1636
1200
data_buf = buf;
1637
1201
oob_buf = oob_required ? chip->oob_poi : NULL;
1638
1202
1203
+
clear_bam_transaction(nandc);
1639
1204
ret = read_page_ecc(host, data_buf, oob_buf);
1640
1205
if (ret) {
1641
1206
dev_err(nandc->dev, "failure to read page\n");
···
1656
1219
u8 *data_buf, *oob_buf;
1657
1220
struct nand_ecc_ctrl *ecc = &chip->ecc;
1658
1221
int i, ret;
1222
+
int read_loc;
1659
1223
1660
1224
data_buf = buf;
1661
1225
oob_buf = chip->oob_poi;
1662
1226
1663
1227
host->use_ecc = false;
1228
+
1229
+
clear_bam_transaction(nandc);
1664
1230
update_rw_regs(host, ecc->steps, true);
1231
+
config_nand_page_read(nandc);
1665
1232
1666
1233
for (i = 0; i < ecc->steps; i++) {
1667
1234
int data_size1, data_size2, oob_size1, oob_size2;
···
1684
1243
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
1685
1244
}
1686
1245
1687
-
config_cw_read(nandc);
1246
+
if (nandc->props->is_bam) {
1247
+
read_loc = 0;
1248
+
nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
1249
+
read_loc += data_size1;
1688
1250
1689
-
read_data_dma(nandc, reg_off, data_buf, data_size1);
1251
+
nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
1252
+
read_loc += oob_size1;
1253
+
1254
+
nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
1255
+
read_loc += data_size2;
1256
+
1257
+
nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
1258
+
}
1259
+
1260
+
config_nand_cw_read(nandc);
1261
+
1262
+
read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
1690
1263
reg_off += data_size1;
1691
1264
data_buf += data_size1;
1692
1265
1693
-
read_data_dma(nandc, reg_off, oob_buf, oob_size1);
1266
+
read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
1694
1267
reg_off += oob_size1;
1695
1268
oob_buf += oob_size1;
1696
1269
1697
-
read_data_dma(nandc, reg_off, data_buf, data_size2);
1270
+
read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
1698
1271
reg_off += data_size2;
1699
1272
data_buf += data_size2;
1700
1273
1701
-
read_data_dma(nandc, reg_off, oob_buf, oob_size2);
1274
+
read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
1702
1275
oob_buf += oob_size2;
1703
1276
}
1704
1277
···
1735
1280
int ret;
1736
1281
1737
1282
clear_read_regs(nandc);
1283
+
clear_bam_transaction(nandc);
1738
1284
1739
1285
host->use_ecc = true;
1740
1286
set_address(host, 0, page);
···
1759
1303
int i, ret;
1760
1304
1761
1305
clear_read_regs(nandc);
1306
+
clear_bam_transaction(nandc);
1762
1307
1763
1308
data_buf = (u8 *)buf;
1764
1309
oob_buf = chip->oob_poi;
1765
1310
1766
1311
host->use_ecc = true;
1767
1312
update_rw_regs(host, ecc->steps, false);
1313
+
config_nand_page_write(nandc);
1768
1314
1769
1315
for (i = 0; i < ecc->steps; i++) {
1770
1316
int data_size, oob_size;
···
1780
1322
oob_size = ecc->bytes;
1781
1323
}
1782
1324
1783
-
config_cw_write_pre(nandc);
1784
1325
1785
-
write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
1326
+
write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
1327
+
i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
1786
1328
1787
1329
/*
1788
1330
* when ECC is enabled, we don't really need to write anything
···
1795
1337
oob_buf += host->bbm_size;
1796
1338
1797
1339
write_data_dma(nandc, FLASH_BUF_ACC + data_size,
1798
-
oob_buf, oob_size);
1340
+
oob_buf, oob_size, 0);
1799
1341
}
1800
1342
1801
-
config_cw_write_post(nandc);
1343
+
config_nand_cw_write(nandc);
1802
1344
1803
1345
data_buf += data_size;
1804
1346
oob_buf += oob_size;
···
1825
1367
int i, ret;
1826
1368
1827
1369
clear_read_regs(nandc);
1370
+
clear_bam_transaction(nandc);
1828
1371
1829
1372
data_buf = (u8 *)buf;
1830
1373
oob_buf = chip->oob_poi;
1831
1374
1832
1375
host->use_ecc = false;
1833
1376
update_rw_regs(host, ecc->steps, false);
1377
+
config_nand_page_write(nandc);
1834
1378
1835
1379
for (i = 0; i < ecc->steps; i++) {
1836
1380
int data_size1, data_size2, oob_size1, oob_size2;
···
1851
1391
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
1852
1392
}
1853
1393
1854
-
config_cw_write_pre(nandc);
1855
-
1856
-
write_data_dma(nandc, reg_off, data_buf, data_size1);
1394
+
write_data_dma(nandc, reg_off, data_buf, data_size1,
1395
+
NAND_BAM_NO_EOT);
1857
1396
reg_off += data_size1;
1858
1397
data_buf += data_size1;
1859
1398
1860
-
write_data_dma(nandc, reg_off, oob_buf, oob_size1);
1399
+
write_data_dma(nandc, reg_off, oob_buf, oob_size1,
1400
+
NAND_BAM_NO_EOT);
1861
1401
reg_off += oob_size1;
1862
1402
oob_buf += oob_size1;
1863
1403
1864
-
write_data_dma(nandc, reg_off, data_buf, data_size2);
1404
+
write_data_dma(nandc, reg_off, data_buf, data_size2,
1405
+
NAND_BAM_NO_EOT);
1865
1406
reg_off += data_size2;
1866
1407
data_buf += data_size2;
1867
1408
1868
-
write_data_dma(nandc, reg_off, oob_buf, oob_size2);
1409
+
write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
1869
1410
oob_buf += oob_size2;
1870
1411
1871
-
config_cw_write_post(nandc);
1412
+
config_nand_cw_write(nandc);
1872
1413
}
1873
1414
1874
1415
ret = submit_descs(nandc);
···
1902
1441
1903
1442
host->use_ecc = true;
1904
1443
1444
+
clear_bam_transaction(nandc);
1905
1445
ret = copy_last_cw(host, page);
1906
1446
if (ret)
1907
1447
return ret;
1908
1448
1909
1449
clear_read_regs(nandc);
1450
+
clear_bam_transaction(nandc);
1910
1451
1911
1452
/* calculate the data and oob size for the last codeword/step */
1912
1453
data_size = ecc->size - ((ecc->steps - 1) << 2);
···
1921
1458
set_address(host, host->cw_size * (ecc->steps - 1), page);
1922
1459
update_rw_regs(host, 1, false);
1923
1460
1924
-
config_cw_write_pre(nandc);
1925
-
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
1926
-
data_size + oob_size);
1927
-
config_cw_write_post(nandc);
1461
+
config_nand_page_write(nandc);
1462
+
write_data_dma(nandc, FLASH_BUF_ACC,
1463
+
nandc->data_buffer, data_size + oob_size, 0);
1464
+
config_nand_cw_write(nandc);
1928
1465
1929
1466
ret = submit_descs(nandc);
1930
1467
···
1961
1498
*/
1962
1499
host->use_ecc = false;
1963
1500
1501
+
clear_bam_transaction(nandc);
1964
1502
ret = copy_last_cw(host, page);
1965
1503
if (ret)
1966
1504
goto err;
···
1992
1528
int page, ret, status = 0;
1993
1529
1994
1530
clear_read_regs(nandc);
1531
+
clear_bam_transaction(nandc);
1995
1532
1996
1533
/*
1997
1534
* to mark the BBM as bad, we flash the entire last codeword with 0s.
···
2008
1543
set_address(host, host->cw_size * (ecc->steps - 1), page);
2009
1544
update_rw_regs(host, 1, false);
2010
1545
2011
-
config_cw_write_pre(nandc);
2012
-
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
2013
-
config_cw_write_post(nandc);
1546
+
config_nand_page_write(nandc);
1547
+
write_data_dma(nandc, FLASH_BUF_ACC,
1548
+
nandc->data_buffer, host->cw_size, 0);
1549
+
config_nand_cw_write(nandc);
2014
1550
2015
1551
ret = submit_descs(nandc);
2016
1552
···
2260
1794
* uses lesser bytes for ECC. If RS is used, the ECC bytes is
2261
1795
* always 10 bytes
2262
1796
*/
2263
-
if (nandc->ecc_modes & ECC_BCH_4BIT) {
1797
+
if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
2264
1798
/* BCH */
2265
1799
host->bch_enabled = true;
2266
1800
ecc_mode = 0;
···
2308
1842
mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
2309
1843
2310
1844
cwperpage = mtd->writesize / ecc->size;
1845
+
nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
1846
+
cwperpage);
2311
1847
2312
1848
/*
2313
1849
* DATA_UD_BYTES varies based on whether the read/write command protects
···
2361
1893
| wide_bus << WIDE_FLASH
2362
1894
| 1 << DEV0_CFG1_ECC_DISABLE;
2363
1895
2364
-
host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
1896
+
host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
2365
1897
| 0 << ECC_SW_RESET
2366
1898
| host->cw_data << ECC_NUM_DATA_BYTES
2367
1899
| 1 << ECC_FORCE_CLK_OPEN
···
2372
1904
2373
1905
host->clrflashstatus = FS_READY_BSY_N;
2374
1906
host->clrreadstatus = 0xc0;
1907
+
nandc->regs->erased_cw_detect_cfg_clr =
1908
+
cpu_to_le32(CLR_ERASED_PAGE_DET);
1909
+
nandc->regs->erased_cw_detect_cfg_set =
1910
+
cpu_to_le32(SET_ERASED_PAGE_DET);
2375
1911
2376
1912
dev_dbg(nandc->dev,
2377
1913
"cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
···
2420
1948
if (!nandc->reg_read_buf)
2421
1949
return -ENOMEM;
2422
1950
2423
-
nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
2424
-
if (!nandc->chan) {
2425
-
dev_err(nandc->dev, "failed to request slave channel\n");
2426
-
return -ENODEV;
1951
+
if (nandc->props->is_bam) {
1952
+
nandc->reg_read_dma =
1953
+
dma_map_single(nandc->dev, nandc->reg_read_buf,
1954
+
MAX_REG_RD *
1955
+
sizeof(*nandc->reg_read_buf),
1956
+
DMA_FROM_DEVICE);
1957
+
if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
1958
+
dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
1959
+
return -EIO;
1960
+
}
1961
+
1962
+
nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
1963
+
if (!nandc->tx_chan) {
1964
+
dev_err(nandc->dev, "failed to request tx channel\n");
1965
+
return -ENODEV;
1966
+
}
1967
+
1968
+
nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
1969
+
if (!nandc->rx_chan) {
1970
+
dev_err(nandc->dev, "failed to request rx channel\n");
1971
+
return -ENODEV;
1972
+
}
1973
+
1974
+
nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
1975
+
if (!nandc->cmd_chan) {
1976
+
dev_err(nandc->dev, "failed to request cmd channel\n");
1977
+
return -ENODEV;
1978
+
}
1979
+
1980
+
/*
1981
+
* Initially allocate BAM transaction to read ONFI param page.
1982
+
* After detecting all the devices, this BAM transaction will
1983
+
* be freed and the next BAM tranasction will be allocated with
1984
+
* maximum codeword size
1985
+
*/
1986
+
nandc->max_cwperpage = 1;
1987
+
nandc->bam_txn = alloc_bam_transaction(nandc);
1988
+
if (!nandc->bam_txn) {
1989
+
dev_err(nandc->dev,
1990
+
"failed to allocate bam transaction\n");
1991
+
return -ENOMEM;
1992
+
}
1993
+
} else {
1994
+
nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
1995
+
if (!nandc->chan) {
1996
+
dev_err(nandc->dev,
1997
+
"failed to request slave channel\n");
1998
+
return -ENODEV;
1999
+
}
2427
2000
}
2428
2001
2429
2002
INIT_LIST_HEAD(&nandc->desc_list);
···
2481
1964
2482
1965
static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
2483
1966
{
2484
-
dma_release_channel(nandc->chan);
1967
+
if (nandc->props->is_bam) {
1968
+
if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
1969
+
dma_unmap_single(nandc->dev, nandc->reg_read_dma,
1970
+
MAX_REG_RD *
1971
+
sizeof(*nandc->reg_read_buf),
1972
+
DMA_FROM_DEVICE);
1973
+
1974
+
if (nandc->tx_chan)
1975
+
dma_release_channel(nandc->tx_chan);
1976
+
1977
+
if (nandc->rx_chan)
1978
+
dma_release_channel(nandc->rx_chan);
1979
+
1980
+
if (nandc->cmd_chan)
1981
+
dma_release_channel(nandc->cmd_chan);
1982
+
} else {
1983
+
if (nandc->chan)
1984
+
dma_release_channel(nandc->chan);
1985
+
}
2485
1986
}
2486
1987
2487
1988
/* one time setup of a few nand controller registers */
2488
1989
static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
2489
1990
{
1991
+
u32 nand_ctrl;
1992
+
2490
1993
/* kill onenand */
2491
1994
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
1995
+
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
1996
+
NAND_DEV_CMD_VLD_VAL);
2492
1997
2493
-
/* enable ADM DMA */
2494
-
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
1998
+
/* enable ADM or BAM DMA */
1999
+
if (nandc->props->is_bam) {
2000
+
nand_ctrl = nandc_read(nandc, NAND_CTRL);
2001
+
nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
2002
+
} else {
2003
+
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
2004
+
}
2495
2005
2496
2006
/* save the original values of these registers */
2497
-
nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
2498
-
nandc->vld = nandc_read(nandc, NAND_DEV_CMD_VLD);
2007
+
nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1));
2008
+
nandc->vld = NAND_DEV_CMD_VLD_VAL;
2499
2009
2500
2010
return 0;
2501
2011
}
···
2578
2034
return ret;
2579
2035
2580
2036
ret = qcom_nand_host_setup(host);
2581
-
if (ret)
2582
-
return ret;
2037
+
2038
+
return ret;
2039
+
}
2040
+
2041
+
static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
2042
+
struct qcom_nand_host *host,
2043
+
struct device_node *dn)
2044
+
{
2045
+
struct nand_chip *chip = &host->chip;
2046
+
struct mtd_info *mtd = nand_to_mtd(chip);
2047
+
int ret;
2583
2048
2584
2049
ret = nand_scan_tail(mtd);
2585
2050
if (ret)
2586
2051
return ret;
2587
2052
2588
-
return mtd_device_register(mtd, NULL, 0);
2053
+
ret = mtd_device_register(mtd, NULL, 0);
2054
+
if (ret)
2055
+
nand_cleanup(mtd_to_nand(mtd));
2056
+
2057
+
return ret;
2058
+
}
2059
+
2060
+
static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
2061
+
{
2062
+
struct device *dev = nandc->dev;
2063
+
struct device_node *dn = dev->of_node, *child;
2064
+
struct qcom_nand_host *host, *tmp;
2065
+
int ret;
2066
+
2067
+
for_each_available_child_of_node(dn, child) {
2068
+
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2069
+
if (!host) {
2070
+
of_node_put(child);
2071
+
return -ENOMEM;
2072
+
}
2073
+
2074
+
ret = qcom_nand_host_init(nandc, host, child);
2075
+
if (ret) {
2076
+
devm_kfree(dev, host);
2077
+
continue;
2078
+
}
2079
+
2080
+
list_add_tail(&host->node, &nandc->host_list);
2081
+
}
2082
+
2083
+
if (list_empty(&nandc->host_list))
2084
+
return -ENODEV;
2085
+
2086
+
if (nandc->props->is_bam) {
2087
+
free_bam_transaction(nandc);
2088
+
nandc->bam_txn = alloc_bam_transaction(nandc);
2089
+
if (!nandc->bam_txn) {
2090
+
dev_err(nandc->dev,
2091
+
"failed to allocate bam transaction\n");
2092
+
return -ENOMEM;
2093
+
}
2094
+
}
2095
+
2096
+
list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
2097
+
ret = qcom_nand_mtd_register(nandc, host, child);
2098
+
if (ret) {
2099
+
list_del(&host->node);
2100
+
devm_kfree(dev, host);
2101
+
}
2102
+
}
2103
+
2104
+
if (list_empty(&nandc->host_list))
2105
+
return -ENODEV;
2106
+
2107
+
return 0;
2589
2108
}
2590
2109
2591
2110
/* parse custom DT properties here */
···
2658
2051
struct device_node *np = nandc->dev->of_node;
2659
2052
int ret;
2660
2053
2661
-
ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
2662
-
if (ret) {
2663
-
dev_err(nandc->dev, "command CRCI unspecified\n");
2664
-
return ret;
2665
-
}
2054
+
if (!nandc->props->is_bam) {
2055
+
ret = of_property_read_u32(np, "qcom,cmd-crci",
2056
+
&nandc->cmd_crci);
2057
+
if (ret) {
2058
+
dev_err(nandc->dev, "command CRCI unspecified\n");
2059
+
return ret;
2060
+
}
2666
2061
2667
-
ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
2668
-
if (ret) {
2669
-
dev_err(nandc->dev, "data CRCI unspecified\n");
2670
-
return ret;
2062
+
ret = of_property_read_u32(np, "qcom,data-crci",
2063
+
&nandc->data_crci);
2064
+
if (ret) {
2065
+
dev_err(nandc->dev, "data CRCI unspecified\n");
2066
+
return ret;
2067
+
}
2671
2068
}
2672
2069
2673
2070
return 0;
···
2680
2069
static int qcom_nandc_probe(struct platform_device *pdev)
2681
2070
{
2682
2071
struct qcom_nand_controller *nandc;
2683
-
struct qcom_nand_host *host;
2684
2072
const void *dev_data;
2685
2073
struct device *dev = &pdev->dev;
2686
-
struct device_node *dn = dev->of_node, *child;
2687
2074
struct resource *res;
2688
2075
int ret;
2689
2076
···
2698
2089
return -ENODEV;
2699
2090
}
2700
2091
2701
-
nandc->ecc_modes = (unsigned long)dev_data;
2092
+
nandc->props = dev_data;
2702
2093
2703
2094
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2704
2095
nandc->base = devm_ioremap_resource(dev, res);
···
2721
2112
2722
2113
ret = qcom_nandc_alloc(nandc);
2723
2114
if (ret)
2724
-
return ret;
2115
+
goto err_core_clk;
2725
2116
2726
2117
ret = clk_prepare_enable(nandc->core_clk);
2727
2118
if (ret)
···
2735
2126
if (ret)
2736
2127
goto err_setup;
2737
2128
2738
-
for_each_available_child_of_node(dn, child) {
2739
-
if (of_device_is_compatible(child, "qcom,nandcs")) {
2740
-
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2741
-
if (!host) {
2742
-
of_node_put(child);
2743
-
ret = -ENOMEM;
2744
-
goto err_cs_init;
2745
-
}
2746
-
2747
-
ret = qcom_nand_host_init(nandc, host, child);
2748
-
if (ret) {
2749
-
devm_kfree(dev, host);
2750
-
continue;
2751
-
}
2752
-
2753
-
list_add_tail(&host->node, &nandc->host_list);
2754
-
}
2755
-
}
2756
-
2757
-
if (list_empty(&nandc->host_list)) {
2758
-
ret = -ENODEV;
2759
-
goto err_cs_init;
2760
-
}
2129
+
ret = qcom_probe_nand_devices(nandc);
2130
+
if (ret)
2131
+
goto err_setup;
2761
2132
2762
2133
return 0;
2763
2134
2764
-
err_cs_init:
2765
-
list_for_each_entry(host, &nandc->host_list, node)
2766
-
nand_release(nand_to_mtd(&host->chip));
2767
2135
err_setup:
2768
2136
clk_disable_unprepare(nandc->aon_clk);
2769
2137
err_aon_clk:
···
2767
2181
return 0;
2768
2182
}
2769
2183
2770
-
#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
2184
+
static const struct qcom_nandc_props ipq806x_nandc_props = {
2185
+
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
2186
+
.is_bam = false,
2187
+
.dev_cmd_reg_start = 0x0,
2188
+
};
2189
+
2190
+
static const struct qcom_nandc_props ipq4019_nandc_props = {
2191
+
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
2192
+
.is_bam = true,
2193
+
.dev_cmd_reg_start = 0x0,
2194
+
};
2195
+
2196
+
static const struct qcom_nandc_props ipq8074_nandc_props = {
2197
+
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
2198
+
.is_bam = true,
2199
+
.dev_cmd_reg_start = 0x7000,
2200
+
};
2771
2201
2772
2202
/*
2773
2203
* data will hold a struct pointer containing more differences once we support
2774
2204
* more controller variants
2775
2205
*/
2776
2206
static const struct of_device_id qcom_nandc_of_match[] = {
2777
-
{ .compatible = "qcom,ipq806x-nand",
2778
-
.data = (void *)EBI2_NANDC_ECC_MODES,
2207
+
{
2208
+
.compatible = "qcom,ipq806x-nand",
2209
+
.data = &ipq806x_nandc_props,
2210
+
},
2211
+
{
2212
+
.compatible = "qcom,ipq4019-nand",
2213
+
.data = &ipq4019_nandc_props,
2214
+
},
2215
+
{
2216
+
.compatible = "qcom,ipq8074-nand",
2217
+
.data = &ipq8074_nandc_props,
2779
2218
},
2780
2219
{}
2781
2220
};
+1
-1
drivers/mtd/nand/r852.h
+1
-1
drivers/mtd/nand/r852.h
+1
-1
drivers/mtd/nand/s3c2410.c
+1
-1
drivers/mtd/nand/s3c2410.c
+4
-4
drivers/mtd/nand/sh_flctl.c
+4
-4
drivers/mtd/nand/sh_flctl.c
···
38
38
#include <linux/string.h>
39
39
40
40
#include <linux/mtd/mtd.h>
41
-
#include <linux/mtd/nand.h>
41
+
#include <linux/mtd/rawnand.h>
42
42
#include <linux/mtd/partitions.h>
43
43
#include <linux/mtd/sh_flctl.h>
44
44
···
411
411
412
412
dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
413
413
414
-
if (dma_addr)
414
+
if (!dma_mapping_error(chan->device->dev, dma_addr))
415
415
desc = dmaengine_prep_slave_single(chan, dma_addr, len,
416
416
tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
417
417
···
1141
1141
1142
1142
irq = platform_get_irq(pdev, 0);
1143
1143
if (irq < 0) {
1144
-
dev_err(&pdev->dev, "failed to get flste irq data\n");
1145
-
return -ENXIO;
1144
+
dev_err(&pdev->dev, "failed to get flste irq data: %d\n", irq);
1145
+
return irq;
1146
1146
}
1147
1147
1148
1148
ret = devm_request_irq(&pdev->dev, irq, flctl_handle_flste, IRQF_SHARED,
+2
-2
drivers/mtd/nand/sharpsl.c
+2
-2
drivers/mtd/nand/sharpsl.c
···
17
17
#include <linux/module.h>
18
18
#include <linux/delay.h>
19
19
#include <linux/mtd/mtd.h>
20
-
#include <linux/mtd/nand.h>
20
+
#include <linux/mtd/rawnand.h>
21
21
#include <linux/mtd/nand_ecc.h>
22
22
#include <linux/mtd/partitions.h>
23
23
#include <linux/mtd/sharpsl.h>
···
183
183
/* Register the partitions */
184
184
mtd->name = "sharpsl-nand";
185
185
186
-
err = mtd_device_parse_register(mtd, NULL, NULL,
186
+
err = mtd_device_parse_register(mtd, data->part_parsers, NULL,
187
187
data->partitions, data->nr_partitions);
188
188
if (err)
189
189
goto err_add;
+1
-1
drivers/mtd/nand/sm_common.c
+1
-1
drivers/mtd/nand/sm_common.c
+1
-1
drivers/mtd/nand/socrates_nand.c
+1
-1
drivers/mtd/nand/socrates_nand.c
+2
-2
drivers/mtd/nand/sunxi_nand.c
+2
-2
drivers/mtd/nand/sunxi_nand.c
···
31
31
#include <linux/of_device.h>
32
32
#include <linux/of_gpio.h>
33
33
#include <linux/mtd/mtd.h>
34
-
#include <linux/mtd/nand.h>
34
+
#include <linux/mtd/rawnand.h>
35
35
#include <linux/mtd/partitions.h>
36
36
#include <linux/clk.h>
37
37
#include <linux/delay.h>
···
2212
2212
if (ret)
2213
2213
goto out_ahb_clk_unprepare;
2214
2214
2215
-
nfc->reset = devm_reset_control_get_optional(dev, "ahb");
2215
+
nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
2216
2216
if (IS_ERR(nfc->reset)) {
2217
2217
ret = PTR_ERR(nfc->reset);
2218
2218
goto out_mod_clk_unprepare;
+1
-1
drivers/mtd/nand/tango_nand.c
+1
-1
drivers/mtd/nand/tango_nand.c
+4
-2
drivers/mtd/nand/tmio_nand.c
+4
-2
drivers/mtd/nand/tmio_nand.c
···
34
34
#include <linux/interrupt.h>
35
35
#include <linux/ioport.h>
36
36
#include <linux/mtd/mtd.h>
37
-
#include <linux/mtd/nand.h>
37
+
#include <linux/mtd/rawnand.h>
38
38
#include <linux/mtd/nand_ecc.h>
39
39
#include <linux/mtd/partitions.h>
40
40
#include <linux/slab.h>
···
440
440
goto err_irq;
441
441
442
442
/* Register the partitions */
443
-
retval = mtd_device_parse_register(mtd, NULL, NULL,
443
+
retval = mtd_device_parse_register(mtd,
444
+
data ? data->part_parsers : NULL,
445
+
NULL,
444
446
data ? data->partition : NULL,
445
447
data ? data->num_partitions : 0);
446
448
if (!retval)
+1
-1
drivers/mtd/nand/txx9ndfmc.c
+1
-1
drivers/mtd/nand/txx9ndfmc.c
+6
-5
drivers/mtd/nand/vf610_nfc.c
+6
-5
drivers/mtd/nand/vf610_nfc.c
···
31
31
#include <linux/interrupt.h>
32
32
#include <linux/io.h>
33
33
#include <linux/mtd/mtd.h>
34
-
#include <linux/mtd/nand.h>
34
+
#include <linux/mtd/rawnand.h>
35
35
#include <linux/mtd/partitions.h>
36
36
#include <linux/of_device.h>
37
-
#include <linux/pinctrl/consumer.h>
38
37
#include <linux/platform_device.h>
39
38
#include <linux/slab.h>
40
39
···
813
814
814
815
static int vf610_nfc_resume(struct device *dev)
815
816
{
817
+
int err;
818
+
816
819
struct mtd_info *mtd = dev_get_drvdata(dev);
817
820
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
818
821
819
-
pinctrl_pm_select_default_state(dev);
820
-
821
-
clk_prepare_enable(nfc->clk);
822
+
err = clk_prepare_enable(nfc->clk);
823
+
if (err)
824
+
return err;
822
825
823
826
vf610_nfc_preinit_controller(nfc);
824
827
vf610_nfc_init_controller(nfc);
+1
-1
drivers/mtd/nand/xway_nand.c
+1
-1
drivers/mtd/nand/xway_nand.c
+1
-1
drivers/mtd/nftlcore.c
+1
-1
drivers/mtd/nftlcore.c
+1
-1
drivers/mtd/nftlmount.c
+1
-1
drivers/mtd/nftlmount.c
+11
-12
drivers/mtd/ofpart.c
+11
-12
drivers/mtd/ofpart.c
···
50
50
* when using another parser), so don't be louder than
51
51
* KERN_DEBUG
52
52
*/
53
-
pr_debug("%s: 'partitions' subnode not found on %s. Trying to parse direct subnodes as partitions.\n",
54
-
master->name, mtd_node->full_name);
53
+
pr_debug("%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\n",
54
+
master->name, mtd_node);
55
55
ofpart_node = mtd_node;
56
56
dedicated = false;
57
57
} else if (!of_device_is_compatible(ofpart_node, "fixed-partitions")) {
···
87
87
reg = of_get_property(pp, "reg", &len);
88
88
if (!reg) {
89
89
if (dedicated) {
90
-
pr_debug("%s: ofpart partition %s (%s) missing reg property.\n",
91
-
master->name, pp->full_name,
92
-
mtd_node->full_name);
90
+
pr_debug("%s: ofpart partition %pOF (%pOF) missing reg property.\n",
91
+
master->name, pp,
92
+
mtd_node);
93
93
goto ofpart_fail;
94
94
} else {
95
95
nr_parts--;
···
100
100
a_cells = of_n_addr_cells(pp);
101
101
s_cells = of_n_size_cells(pp);
102
102
if (len / 4 != a_cells + s_cells) {
103
-
pr_debug("%s: ofpart partition %s (%s) error parsing reg property.\n",
104
-
master->name, pp->full_name,
105
-
mtd_node->full_name);
103
+
pr_debug("%s: ofpart partition %pOF (%pOF) error parsing reg property.\n",
104
+
master->name, pp,
105
+
mtd_node);
106
106
goto ofpart_fail;
107
107
}
108
108
···
131
131
return nr_parts;
132
132
133
133
ofpart_fail:
134
-
pr_err("%s: error parsing ofpart partition %s (%s)\n",
135
-
master->name, pp->full_name, mtd_node->full_name);
134
+
pr_err("%s: error parsing ofpart partition %pOF (%pOF)\n",
135
+
master->name, pp, mtd_node);
136
136
ret = -EINVAL;
137
137
ofpart_none:
138
138
of_node_put(pp);
···
166
166
if (!part)
167
167
return 0; /* No partitions found */
168
168
169
-
pr_warn("Device tree uses obsolete partition map binding: %s\n",
170
-
dp->full_name);
169
+
pr_warn("Device tree uses obsolete partition map binding: %pOF\n", dp);
171
170
172
171
nr_parts = plen / sizeof(part[0]);
173
172
+16
drivers/mtd/spi-nor/Kconfig
+16
drivers/mtd/spi-nor/Kconfig
···
89
89
config SPI_INTEL_SPI
90
90
tristate
91
91
92
+
config SPI_INTEL_SPI_PCI
93
+
tristate "Intel PCH/PCU SPI flash PCI driver" if EXPERT
94
+
depends on X86 && PCI
95
+
select SPI_INTEL_SPI
96
+
help
97
+
This enables PCI support for the Intel PCH/PCU SPI controller in
98
+
master mode. This controller is present in modern Intel hardware
99
+
and is used to hold BIOS and other persistent settings. Using
100
+
this driver it is possible to upgrade BIOS directly from Linux.
101
+
102
+
Say N here unless you know what you are doing. Overwriting the
103
+
SPI flash may render the system unbootable.
104
+
105
+
To compile this driver as a module, choose M here: the module
106
+
will be called intel-spi-pci.
107
+
92
108
config SPI_INTEL_SPI_PLATFORM
93
109
tristate "Intel PCH/PCU SPI flash platform driver" if EXPERT
94
110
depends on X86
+1
drivers/mtd/spi-nor/Makefile
+1
drivers/mtd/spi-nor/Makefile
···
7
7
obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
8
8
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
9
9
obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
10
+
obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
10
11
obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
11
12
obj-$(CONFIG_SPI_STM32_QUADSPI) += stm32-quadspi.o
+6
-7
drivers/mtd/spi-nor/aspeed-smc.c
+6
-7
drivers/mtd/spi-nor/aspeed-smc.c
···
621
621
}
622
622
623
623
/*
624
-
* The AST2500 FMC flash controller should be strapped by hardware, or
625
-
* autodetected, but the AST2500 SPI flash needs to be set.
624
+
* The first chip of the AST2500 FMC flash controller is strapped by
625
+
* hardware, or autodetected, but other chips need to be set. Enforce
626
+
* the 4B setting for all chips.
626
627
*/
627
628
static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip)
628
629
{
629
630
struct aspeed_smc_controller *controller = chip->controller;
630
631
u32 reg;
631
632
632
-
if (chip->controller->info == &spi_2500_info) {
633
-
reg = readl(controller->regs + CE_CONTROL_REG);
634
-
reg |= 1 << chip->cs;
635
-
writel(reg, controller->regs + CE_CONTROL_REG);
636
-
}
633
+
reg = readl(controller->regs + CE_CONTROL_REG);
634
+
reg |= 1 << chip->cs;
635
+
writel(reg, controller->regs + CE_CONTROL_REG);
637
636
}
638
637
639
638
/*
-1
drivers/mtd/spi-nor/atmel-quadspi.c
-1
drivers/mtd/spi-nor/atmel-quadspi.c
+4
-4
drivers/mtd/spi-nor/hisi-sfc.c
+4
-4
drivers/mtd/spi-nor/hisi-sfc.c
···
355
355
356
356
ret = of_property_read_u32(np, "reg", &priv->chipselect);
357
357
if (ret) {
358
-
dev_err(dev, "There's no reg property for %s\n",
359
-
np->full_name);
358
+
dev_err(dev, "There's no reg property for %pOF\n",
359
+
np);
360
360
return ret;
361
361
}
362
362
363
363
ret = of_property_read_u32(np, "spi-max-frequency",
364
364
&priv->clkrate);
365
365
if (ret) {
366
-
dev_err(dev, "There's no spi-max-frequency property for %s\n",
367
-
np->full_name);
366
+
dev_err(dev, "There's no spi-max-frequency property for %pOF\n",
367
+
np);
368
368
return ret;
369
369
}
370
370
priv->host = host;
+82
drivers/mtd/spi-nor/intel-spi-pci.c
+82
drivers/mtd/spi-nor/intel-spi-pci.c
···
1
+
/*
2
+
* Intel PCH/PCU SPI flash PCI driver.
3
+
*
4
+
* Copyright (C) 2016, Intel Corporation
5
+
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*/
11
+
12
+
#include <linux/ioport.h>
13
+
#include <linux/kernel.h>
14
+
#include <linux/module.h>
15
+
#include <linux/pci.h>
16
+
17
+
#include "intel-spi.h"
18
+
19
+
#define BCR 0xdc
20
+
#define BCR_WPD BIT(0)
21
+
22
+
static const struct intel_spi_boardinfo bxt_info = {
23
+
.type = INTEL_SPI_BXT,
24
+
};
25
+
26
+
static int intel_spi_pci_probe(struct pci_dev *pdev,
27
+
const struct pci_device_id *id)
28
+
{
29
+
struct intel_spi_boardinfo *info;
30
+
struct intel_spi *ispi;
31
+
u32 bcr;
32
+
int ret;
33
+
34
+
ret = pcim_enable_device(pdev);
35
+
if (ret)
36
+
return ret;
37
+
38
+
info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
39
+
GFP_KERNEL);
40
+
if (!info)
41
+
return -ENOMEM;
42
+
43
+
/* Try to make the chip read/write */
44
+
pci_read_config_dword(pdev, BCR, &bcr);
45
+
if (!(bcr & BCR_WPD)) {
46
+
bcr |= BCR_WPD;
47
+
pci_write_config_dword(pdev, BCR, bcr);
48
+
pci_read_config_dword(pdev, BCR, &bcr);
49
+
}
50
+
info->writeable = !!(bcr & BCR_WPD);
51
+
52
+
ispi = intel_spi_probe(&pdev->dev, &pdev->resource[0], info);
53
+
if (IS_ERR(ispi))
54
+
return PTR_ERR(ispi);
55
+
56
+
pci_set_drvdata(pdev, ispi);
57
+
return 0;
58
+
}
59
+
60
+
static void intel_spi_pci_remove(struct pci_dev *pdev)
61
+
{
62
+
intel_spi_remove(pci_get_drvdata(pdev));
63
+
}
64
+
65
+
static const struct pci_device_id intel_spi_pci_ids[] = {
66
+
{ PCI_VDEVICE(INTEL, 0x19e0), (unsigned long)&bxt_info },
67
+
{ },
68
+
};
69
+
MODULE_DEVICE_TABLE(pci, intel_spi_pci_ids);
70
+
71
+
static struct pci_driver intel_spi_pci_driver = {
72
+
.name = "intel-spi",
73
+
.id_table = intel_spi_pci_ids,
74
+
.probe = intel_spi_pci_probe,
75
+
.remove = intel_spi_pci_remove,
76
+
};
77
+
78
+
module_pci_driver(intel_spi_pci_driver);
79
+
80
+
MODULE_DESCRIPTION("Intel PCH/PCU SPI flash PCI driver");
81
+
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
82
+
MODULE_LICENSE("GPL v2");
-1
drivers/mtd/spi-nor/mtk-quadspi.c
-1
drivers/mtd/spi-nor/mtk-quadspi.c
+784
-21
drivers/mtd/spi-nor/spi-nor.c
+784
-21
drivers/mtd/spi-nor/spi-nor.c
···
17
17
#include <linux/mutex.h>
18
18
#include <linux/math64.h>
19
19
#include <linux/sizes.h>
20
+
#include <linux/slab.h>
20
21
21
22
#include <linux/mtd/mtd.h>
22
23
#include <linux/of_platform.h>
···
87
86
* to support memory size above 128Mib.
88
87
*/
89
88
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
89
+
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
90
+
#define USE_CLSR BIT(14) /* use CLSR command */
90
91
};
91
92
92
93
#define JEDEC_MFR(info) ((info)->id[0])
···
309
306
int sr = read_sr(nor);
310
307
if (sr < 0)
311
308
return sr;
312
-
else
313
-
return !(sr & SR_WIP);
309
+
310
+
if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
311
+
if (sr & SR_E_ERR)
312
+
dev_err(nor->dev, "Erase Error occurred\n");
313
+
else
314
+
dev_err(nor->dev, "Programming Error occurred\n");
315
+
316
+
nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
317
+
return -EIO;
318
+
}
319
+
320
+
return !(sr & SR_WIP);
314
321
}
315
322
316
323
static inline int spi_nor_fsr_ready(struct spi_nor *nor)
···
1054
1041
*/
1055
1042
{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1056
1043
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1057
-
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
1058
-
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1059
-
{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1044
+
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
1045
+
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1046
+
{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1060
1047
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
1061
1048
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
1062
1049
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
1063
-
{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1064
-
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1065
-
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1050
+
{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1051
+
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1052
+
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1066
1053
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
1067
1054
{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
1068
1055
{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
···
1092
1079
{ "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
1093
1080
{ "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1094
1081
{ "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1082
+
{ "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1095
1083
1096
1084
/* ST Microelectronics -- newer production may have feature updates */
1097
1085
{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
···
1394
1380
return ret;
1395
1381
}
1396
1382
1383
+
/**
1384
+
* macronix_quad_enable() - set QE bit in Status Register.
1385
+
* @nor: pointer to a 'struct spi_nor'
1386
+
*
1387
+
* Set the Quad Enable (QE) bit in the Status Register.
1388
+
*
1389
+
* bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1390
+
*
1391
+
* Return: 0 on success, -errno otherwise.
1392
+
*/
1397
1393
static int macronix_quad_enable(struct spi_nor *nor)
1398
1394
{
1399
1395
int ret, val;
···
1437
1413
* second byte will be written to the configuration register.
1438
1414
* Return negative if error occurred.
1439
1415
*/
1440
-
static int write_sr_cr(struct spi_nor *nor, u16 val)
1441
-
{
1442
-
nor->cmd_buf[0] = val & 0xff;
1443
-
nor->cmd_buf[1] = (val >> 8);
1444
-
1445
-
return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
1446
-
}
1447
-
1448
-
static int spansion_quad_enable(struct spi_nor *nor)
1416
+
static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1449
1417
{
1450
1418
int ret;
1451
-
int quad_en = CR_QUAD_EN_SPAN << 8;
1452
1419
1453
1420
write_enable(nor);
1454
1421
1455
-
ret = write_sr_cr(nor, quad_en);
1422
+
ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1456
1423
if (ret < 0) {
1457
1424
dev_err(nor->dev,
1458
1425
"error while writing configuration register\n");
···
1457
1442
return ret;
1458
1443
}
1459
1444
1445
+
return 0;
1446
+
}
1447
+
1448
+
/**
1449
+
* spansion_quad_enable() - set QE bit in Configuraiton Register.
1450
+
* @nor: pointer to a 'struct spi_nor'
1451
+
*
1452
+
* Set the Quad Enable (QE) bit in the Configuration Register.
1453
+
* This function is kept for legacy purpose because it has been used for a
1454
+
* long time without anybody complaining but it should be considered as
1455
+
* deprecated and maybe buggy.
1456
+
* First, this function doesn't care about the previous values of the Status
1457
+
* and Configuration Registers when it sets the QE bit (bit 1) in the
1458
+
* Configuration Register: all other bits are cleared, which may have unwanted
1459
+
* side effects like removing some block protections.
1460
+
* Secondly, it uses the Read Configuration Register (35h) instruction though
1461
+
* some very old and few memories don't support this instruction. If a pull-up
1462
+
* resistor is present on the MISO/IO1 line, we might still be able to pass the
1463
+
* "read back" test because the QSPI memory doesn't recognize the command,
1464
+
* so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0xFF.
1465
+
*
1466
+
* bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1467
+
* memories.
1468
+
*
1469
+
* Return: 0 on success, -errno otherwise.
1470
+
*/
1471
+
static int spansion_quad_enable(struct spi_nor *nor)
1472
+
{
1473
+
u8 sr_cr[2] = {0, CR_QUAD_EN_SPAN};
1474
+
int ret;
1475
+
1476
+
ret = write_sr_cr(nor, sr_cr);
1477
+
if (ret)
1478
+
return ret;
1479
+
1460
1480
/* read back and check it */
1461
1481
ret = read_cr(nor);
1462
1482
if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1463
1483
dev_err(nor->dev, "Spansion Quad bit not set\n");
1484
+
return -EINVAL;
1485
+
}
1486
+
1487
+
return 0;
1488
+
}
1489
+
1490
+
/**
1491
+
* spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1492
+
* @nor: pointer to a 'struct spi_nor'
1493
+
*
1494
+
* Set the Quad Enable (QE) bit in the Configuration Register.
1495
+
* This function should be used with QSPI memories not supporting the Read
1496
+
* Configuration Register (35h) instruction.
1497
+
*
1498
+
* bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1499
+
* memories.
1500
+
*
1501
+
* Return: 0 on success, -errno otherwise.
1502
+
*/
1503
+
static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1504
+
{
1505
+
u8 sr_cr[2];
1506
+
int ret;
1507
+
1508
+
/* Keep the current value of the Status Register. */
1509
+
ret = read_sr(nor);
1510
+
if (ret < 0) {
1511
+
dev_err(nor->dev, "error while reading status register\n");
1512
+
return -EINVAL;
1513
+
}
1514
+
sr_cr[0] = ret;
1515
+
sr_cr[1] = CR_QUAD_EN_SPAN;
1516
+
1517
+
return write_sr_cr(nor, sr_cr);
1518
+
}
1519
+
1520
+
/**
1521
+
* spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1522
+
* @nor: pointer to a 'struct spi_nor'
1523
+
*
1524
+
* Set the Quad Enable (QE) bit in the Configuration Register.
1525
+
* This function should be used with QSPI memories supporting the Read
1526
+
* Configuration Register (35h) instruction.
1527
+
*
1528
+
* bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1529
+
* memories.
1530
+
*
1531
+
* Return: 0 on success, -errno otherwise.
1532
+
*/
1533
+
static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1534
+
{
1535
+
struct device *dev = nor->dev;
1536
+
u8 sr_cr[2];
1537
+
int ret;
1538
+
1539
+
/* Check current Quad Enable bit value. */
1540
+
ret = read_cr(nor);
1541
+
if (ret < 0) {
1542
+
dev_err(dev, "error while reading configuration register\n");
1543
+
return -EINVAL;
1544
+
}
1545
+
1546
+
if (ret & CR_QUAD_EN_SPAN)
1547
+
return 0;
1548
+
1549
+
sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1550
+
1551
+
/* Keep the current value of the Status Register. */
1552
+
ret = read_sr(nor);
1553
+
if (ret < 0) {
1554
+
dev_err(dev, "error while reading status register\n");
1555
+
return -EINVAL;
1556
+
}
1557
+
sr_cr[0] = ret;
1558
+
1559
+
ret = write_sr_cr(nor, sr_cr);
1560
+
if (ret)
1561
+
return ret;
1562
+
1563
+
/* Read back and check it. */
1564
+
ret = read_cr(nor);
1565
+
if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1566
+
dev_err(nor->dev, "Spansion Quad bit not set\n");
1567
+
return -EINVAL;
1568
+
}
1569
+
1570
+
return 0;
1571
+
}
1572
+
1573
+
/**
1574
+
* sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1575
+
* @nor: pointer to a 'struct spi_nor'
1576
+
*
1577
+
* Set the Quad Enable (QE) bit in the Status Register 2.
1578
+
*
1579
+
* This is one of the procedures to set the QE bit described in the SFDP
1580
+
* (JESD216 rev B) specification but no manufacturer using this procedure has
1581
+
* been identified yet, hence the name of the function.
1582
+
*
1583
+
* Return: 0 on success, -errno otherwise.
1584
+
*/
1585
+
static int sr2_bit7_quad_enable(struct spi_nor *nor)
1586
+
{
1587
+
u8 sr2;
1588
+
int ret;
1589
+
1590
+
/* Check current Quad Enable bit value. */
1591
+
ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1592
+
if (ret)
1593
+
return ret;
1594
+
if (sr2 & SR2_QUAD_EN_BIT7)
1595
+
return 0;
1596
+
1597
+
/* Update the Quad Enable bit. */
1598
+
sr2 |= SR2_QUAD_EN_BIT7;
1599
+
1600
+
write_enable(nor);
1601
+
1602
+
ret = nor->write_reg(nor, SPINOR_OP_WRSR2, &sr2, 1);
1603
+
if (ret < 0) {
1604
+
dev_err(nor->dev, "error while writing status register 2\n");
1605
+
return -EINVAL;
1606
+
}
1607
+
1608
+
ret = spi_nor_wait_till_ready(nor);
1609
+
if (ret < 0) {
1610
+
dev_err(nor->dev, "timeout while writing status register 2\n");
1611
+
return ret;
1612
+
}
1613
+
1614
+
/* Read back and check it. */
1615
+
ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
1616
+
if (!(ret > 0 && (sr2 & SR2_QUAD_EN_BIT7))) {
1617
+
dev_err(nor->dev, "SR2 Quad bit not set\n");
1464
1618
return -EINVAL;
1465
1619
}
1466
1620
···
1775
1591
pp->proto = proto;
1776
1592
}
1777
1593
1594
+
/*
1595
+
* Serial Flash Discoverable Parameters (SFDP) parsing.
1596
+
*/
1597
+
1598
+
/**
1599
+
* spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1600
+
* @nor: pointer to a 'struct spi_nor'
1601
+
* @addr: offset in the SFDP area to start reading data from
1602
+
* @len: number of bytes to read
1603
+
* @buf: buffer where the SFDP data are copied into
1604
+
*
1605
+
* Whatever the actual numbers of bytes for address and dummy cycles are
1606
+
* for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1607
+
* followed by a 3-byte address and 8 dummy clock cycles.
1608
+
*
1609
+
* Return: 0 on success, -errno otherwise.
1610
+
*/
1611
+
static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1612
+
size_t len, void *buf)
1613
+
{
1614
+
u8 addr_width, read_opcode, read_dummy;
1615
+
int ret;
1616
+
1617
+
read_opcode = nor->read_opcode;
1618
+
addr_width = nor->addr_width;
1619
+
read_dummy = nor->read_dummy;
1620
+
1621
+
nor->read_opcode = SPINOR_OP_RDSFDP;
1622
+
nor->addr_width = 3;
1623
+
nor->read_dummy = 8;
1624
+
1625
+
while (len) {
1626
+
ret = nor->read(nor, addr, len, (u8 *)buf);
1627
+
if (!ret || ret > len) {
1628
+
ret = -EIO;
1629
+
goto read_err;
1630
+
}
1631
+
if (ret < 0)
1632
+
goto read_err;
1633
+
1634
+
buf += ret;
1635
+
addr += ret;
1636
+
len -= ret;
1637
+
}
1638
+
ret = 0;
1639
+
1640
+
read_err:
1641
+
nor->read_opcode = read_opcode;
1642
+
nor->addr_width = addr_width;
1643
+
nor->read_dummy = read_dummy;
1644
+
1645
+
return ret;
1646
+
}
1647
+
1648
+
struct sfdp_parameter_header {
1649
+
u8 id_lsb;
1650
+
u8 minor;
1651
+
u8 major;
1652
+
u8 length; /* in double words */
1653
+
u8 parameter_table_pointer[3]; /* byte address */
1654
+
u8 id_msb;
1655
+
};
1656
+
1657
+
#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
1658
+
#define SFDP_PARAM_HEADER_PTP(p) \
1659
+
(((p)->parameter_table_pointer[2] << 16) | \
1660
+
((p)->parameter_table_pointer[1] << 8) | \
1661
+
((p)->parameter_table_pointer[0] << 0))
1662
+
1663
+
#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
1664
+
#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
1665
+
1666
+
#define SFDP_SIGNATURE 0x50444653U
1667
+
#define SFDP_JESD216_MAJOR 1
1668
+
#define SFDP_JESD216_MINOR 0
1669
+
#define SFDP_JESD216A_MINOR 5
1670
+
#define SFDP_JESD216B_MINOR 6
1671
+
1672
+
struct sfdp_header {
1673
+
u32 signature; /* Ox50444653U <=> "SFDP" */
1674
+
u8 minor;
1675
+
u8 major;
1676
+
u8 nph; /* 0-base number of parameter headers */
1677
+
u8 unused;
1678
+
1679
+
/* Basic Flash Parameter Table. */
1680
+
struct sfdp_parameter_header bfpt_header;
1681
+
};
1682
+
1683
+
/* Basic Flash Parameter Table */
1684
+
1685
+
/*
1686
+
* JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
1687
+
* They are indexed from 1 but C arrays are indexed from 0.
1688
+
*/
1689
+
#define BFPT_DWORD(i) ((i) - 1)
1690
+
#define BFPT_DWORD_MAX 16
1691
+
1692
+
/* The first version of JESB216 defined only 9 DWORDs. */
1693
+
#define BFPT_DWORD_MAX_JESD216 9
1694
+
1695
+
/* 1st DWORD. */
1696
+
#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
1697
+
#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
1698
+
#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
1699
+
#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
1700
+
#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
1701
+
#define BFPT_DWORD1_DTR BIT(19)
1702
+
#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
1703
+
#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
1704
+
#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
1705
+
1706
+
/* 5th DWORD. */
1707
+
#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
1708
+
#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
1709
+
1710
+
/* 11th DWORD. */
1711
+
#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
1712
+
#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
1713
+
1714
+
/* 15th DWORD. */
1715
+
1716
+
/*
1717
+
* (from JESD216 rev B)
1718
+
* Quad Enable Requirements (QER):
1719
+
* - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
1720
+
* reads based on instruction. DQ3/HOLD# functions are hold during
1721
+
* instruction phase.
1722
+
* - 001b: QE is bit 1 of status register 2. It is set via Write Status with
1723
+
* two data bytes where bit 1 of the second byte is one.
1724
+
* [...]
1725
+
* Writing only one byte to the status register has the side-effect of
1726
+
* clearing status register 2, including the QE bit. The 100b code is
1727
+
* used if writing one byte to the status register does not modify
1728
+
* status register 2.
1729
+
* - 010b: QE is bit 6 of status register 1. It is set via Write Status with
1730
+
* one data byte where bit 6 is one.
1731
+
* [...]
1732
+
* - 011b: QE is bit 7 of status register 2. It is set via Write status
1733
+
* register 2 instruction 3Eh with one data byte where bit 7 is one.
1734
+
* [...]
1735
+
* The status register 2 is read using instruction 3Fh.
1736
+
* - 100b: QE is bit 1 of status register 2. It is set via Write Status with
1737
+
* two data bytes where bit 1 of the second byte is one.
1738
+
* [...]
1739
+
* In contrast to the 001b code, writing one byte to the status
1740
+
* register does not modify status register 2.
1741
+
* - 101b: QE is bit 1 of status register 2. Status register 1 is read using
1742
+
* Read Status instruction 05h. Status register2 is read using
1743
+
* instruction 35h. QE is set via Writ Status instruction 01h with
1744
+
* two data bytes where bit 1 of the second byte is one.
1745
+
* [...]
1746
+
*/
1747
+
#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
1748
+
#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
1749
+
#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
1750
+
#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
1751
+
#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
1752
+
#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
1753
+
#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
1754
+
1755
+
struct sfdp_bfpt {
1756
+
u32 dwords[BFPT_DWORD_MAX];
1757
+
};
1758
+
1759
+
/* Fast Read settings. */
1760
+
1761
+
static inline void
1762
+
spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
1763
+
u16 half,
1764
+
enum spi_nor_protocol proto)
1765
+
{
1766
+
read->num_mode_clocks = (half >> 5) & 0x07;
1767
+
read->num_wait_states = (half >> 0) & 0x1f;
1768
+
read->opcode = (half >> 8) & 0xff;
1769
+
read->proto = proto;
1770
+
}
1771
+
1772
+
struct sfdp_bfpt_read {
1773
+
/* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
1774
+
u32 hwcaps;
1775
+
1776
+
/*
1777
+
* The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
1778
+
* whether the Fast Read x-y-z command is supported.
1779
+
*/
1780
+
u32 supported_dword;
1781
+
u32 supported_bit;
1782
+
1783
+
/*
1784
+
* The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
1785
+
* encodes the op code, the number of mode clocks and the number of wait
1786
+
* states to be used by Fast Read x-y-z command.
1787
+
*/
1788
+
u32 settings_dword;
1789
+
u32 settings_shift;
1790
+
1791
+
/* The SPI protocol for this Fast Read x-y-z command. */
1792
+
enum spi_nor_protocol proto;
1793
+
};
1794
+
1795
+
static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
1796
+
/* Fast Read 1-1-2 */
1797
+
{
1798
+
SNOR_HWCAPS_READ_1_1_2,
1799
+
BFPT_DWORD(1), BIT(16), /* Supported bit */
1800
+
BFPT_DWORD(4), 0, /* Settings */
1801
+
SNOR_PROTO_1_1_2,
1802
+
},
1803
+
1804
+
/* Fast Read 1-2-2 */
1805
+
{
1806
+
SNOR_HWCAPS_READ_1_2_2,
1807
+
BFPT_DWORD(1), BIT(20), /* Supported bit */
1808
+
BFPT_DWORD(4), 16, /* Settings */
1809
+
SNOR_PROTO_1_2_2,
1810
+
},
1811
+
1812
+
/* Fast Read 2-2-2 */
1813
+
{
1814
+
SNOR_HWCAPS_READ_2_2_2,
1815
+
BFPT_DWORD(5), BIT(0), /* Supported bit */
1816
+
BFPT_DWORD(6), 16, /* Settings */
1817
+
SNOR_PROTO_2_2_2,
1818
+
},
1819
+
1820
+
/* Fast Read 1-1-4 */
1821
+
{
1822
+
SNOR_HWCAPS_READ_1_1_4,
1823
+
BFPT_DWORD(1), BIT(22), /* Supported bit */
1824
+
BFPT_DWORD(3), 16, /* Settings */
1825
+
SNOR_PROTO_1_1_4,
1826
+
},
1827
+
1828
+
/* Fast Read 1-4-4 */
1829
+
{
1830
+
SNOR_HWCAPS_READ_1_4_4,
1831
+
BFPT_DWORD(1), BIT(21), /* Supported bit */
1832
+
BFPT_DWORD(3), 0, /* Settings */
1833
+
SNOR_PROTO_1_4_4,
1834
+
},
1835
+
1836
+
/* Fast Read 4-4-4 */
1837
+
{
1838
+
SNOR_HWCAPS_READ_4_4_4,
1839
+
BFPT_DWORD(5), BIT(4), /* Supported bit */
1840
+
BFPT_DWORD(7), 16, /* Settings */
1841
+
SNOR_PROTO_4_4_4,
1842
+
},
1843
+
};
1844
+
1845
+
struct sfdp_bfpt_erase {
1846
+
/*
1847
+
* The half-word at offset <shift> in DWORD <dwoard> encodes the
1848
+
* op code and erase sector size to be used by Sector Erase commands.
1849
+
*/
1850
+
u32 dword;
1851
+
u32 shift;
1852
+
};
1853
+
1854
+
static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
1855
+
/* Erase Type 1 in DWORD8 bits[15:0] */
1856
+
{BFPT_DWORD(8), 0},
1857
+
1858
+
/* Erase Type 2 in DWORD8 bits[31:16] */
1859
+
{BFPT_DWORD(8), 16},
1860
+
1861
+
/* Erase Type 3 in DWORD9 bits[15:0] */
1862
+
{BFPT_DWORD(9), 0},
1863
+
1864
+
/* Erase Type 4 in DWORD9 bits[31:16] */
1865
+
{BFPT_DWORD(9), 16},
1866
+
};
1867
+
1868
+
static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
1869
+
1870
+
/**
1871
+
* spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
1872
+
* @nor: pointer to a 'struct spi_nor'
1873
+
* @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
1874
+
* the Basic Flash Parameter Table length and version
1875
+
* @params: pointer to the 'struct spi_nor_flash_parameter' to be
1876
+
* filled
1877
+
*
1878
+
* The Basic Flash Parameter Table is the main and only mandatory table as
1879
+
* defined by the SFDP (JESD216) specification.
1880
+
* It provides us with the total size (memory density) of the data array and
1881
+
* the number of address bytes for Fast Read, Page Program and Sector Erase
1882
+
* commands.
1883
+
* For Fast READ commands, it also gives the number of mode clock cycles and
1884
+
* wait states (regrouped in the number of dummy clock cycles) for each
1885
+
* supported instruction op code.
1886
+
* For Page Program, the page size is now available since JESD216 rev A, however
1887
+
* the supported instruction op codes are still not provided.
1888
+
* For Sector Erase commands, this table stores the supported instruction op
1889
+
* codes and the associated sector sizes.
1890
+
* Finally, the Quad Enable Requirements (QER) are also available since JESD216
1891
+
* rev A. The QER bits encode the manufacturer dependent procedure to be
1892
+
* executed to set the Quad Enable (QE) bit in some internal register of the
1893
+
* Quad SPI memory. Indeed the QE bit, when it exists, must be set before
1894
+
* sending any Quad SPI command to the memory. Actually, setting the QE bit
1895
+
* tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
1896
+
* and IO3 hence enabling 4 (Quad) I/O lines.
1897
+
*
1898
+
* Return: 0 on success, -errno otherwise.
1899
+
*/
1900
+
static int spi_nor_parse_bfpt(struct spi_nor *nor,
1901
+
const struct sfdp_parameter_header *bfpt_header,
1902
+
struct spi_nor_flash_parameter *params)
1903
+
{
1904
+
struct mtd_info *mtd = &nor->mtd;
1905
+
struct sfdp_bfpt bfpt;
1906
+
size_t len;
1907
+
int i, cmd, err;
1908
+
u32 addr;
1909
+
u16 half;
1910
+
1911
+
/* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
1912
+
if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
1913
+
return -EINVAL;
1914
+
1915
+
/* Read the Basic Flash Parameter Table. */
1916
+
len = min_t(size_t, sizeof(bfpt),
1917
+
bfpt_header->length * sizeof(u32));
1918
+
addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
1919
+
memset(&bfpt, 0, sizeof(bfpt));
1920
+
err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
1921
+
if (err < 0)
1922
+
return err;
1923
+
1924
+
/* Fix endianness of the BFPT DWORDs. */
1925
+
for (i = 0; i < BFPT_DWORD_MAX; i++)
1926
+
bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
1927
+
1928
+
/* Number of address bytes. */
1929
+
switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
1930
+
case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
1931
+
nor->addr_width = 3;
1932
+
break;
1933
+
1934
+
case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
1935
+
nor->addr_width = 4;
1936
+
break;
1937
+
1938
+
default:
1939
+
break;
1940
+
}
1941
+
1942
+
/* Flash Memory Density (in bits). */
1943
+
params->size = bfpt.dwords[BFPT_DWORD(2)];
1944
+
if (params->size & BIT(31)) {
1945
+
params->size &= ~BIT(31);
1946
+
params->size = 1ULL << params->size;
1947
+
} else {
1948
+
params->size++;
1949
+
}
1950
+
params->size >>= 3; /* Convert to bytes. */
1951
+
1952
+
/* Fast Read settings. */
1953
+
for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
1954
+
const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
1955
+
struct spi_nor_read_command *read;
1956
+
1957
+
if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
1958
+
params->hwcaps.mask &= ~rd->hwcaps;
1959
+
continue;
1960
+
}
1961
+
1962
+
params->hwcaps.mask |= rd->hwcaps;
1963
+
cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
1964
+
read = ¶ms->reads[cmd];
1965
+
half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
1966
+
spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
1967
+
}
1968
+
1969
+
/* Sector Erase settings. */
1970
+
for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
1971
+
const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
1972
+
u32 erasesize;
1973
+
u8 opcode;
1974
+
1975
+
half = bfpt.dwords[er->dword] >> er->shift;
1976
+
erasesize = half & 0xff;
1977
+
1978
+
/* erasesize == 0 means this Erase Type is not supported. */
1979
+
if (!erasesize)
1980
+
continue;
1981
+
1982
+
erasesize = 1U << erasesize;
1983
+
opcode = (half >> 8) & 0xff;
1984
+
#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1985
+
if (erasesize == SZ_4K) {
1986
+
nor->erase_opcode = opcode;
1987
+
mtd->erasesize = erasesize;
1988
+
break;
1989
+
}
1990
+
#endif
1991
+
if (!mtd->erasesize || mtd->erasesize < erasesize) {
1992
+
nor->erase_opcode = opcode;
1993
+
mtd->erasesize = erasesize;
1994
+
}
1995
+
}
1996
+
1997
+
/* Stop here if not JESD216 rev A or later. */
1998
+
if (bfpt_header->length < BFPT_DWORD_MAX)
1999
+
return 0;
2000
+
2001
+
/* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2002
+
params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2003
+
params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2004
+
params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2005
+
params->page_size = 1U << params->page_size;
2006
+
2007
+
/* Quad Enable Requirements. */
2008
+
switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2009
+
case BFPT_DWORD15_QER_NONE:
2010
+
params->quad_enable = NULL;
2011
+
break;
2012
+
2013
+
case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2014
+
case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2015
+
params->quad_enable = spansion_no_read_cr_quad_enable;
2016
+
break;
2017
+
2018
+
case BFPT_DWORD15_QER_SR1_BIT6:
2019
+
params->quad_enable = macronix_quad_enable;
2020
+
break;
2021
+
2022
+
case BFPT_DWORD15_QER_SR2_BIT7:
2023
+
params->quad_enable = sr2_bit7_quad_enable;
2024
+
break;
2025
+
2026
+
case BFPT_DWORD15_QER_SR2_BIT1:
2027
+
params->quad_enable = spansion_read_cr_quad_enable;
2028
+
break;
2029
+
2030
+
default:
2031
+
return -EINVAL;
2032
+
}
2033
+
2034
+
return 0;
2035
+
}
2036
+
2037
+
/**
2038
+
* spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2039
+
* @nor: pointer to a 'struct spi_nor'
2040
+
* @params: pointer to the 'struct spi_nor_flash_parameter' to be
2041
+
* filled
2042
+
*
2043
+
* The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2044
+
* specification. This is a standard which tends to supported by almost all
2045
+
* (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2046
+
* runtime the main parameters needed to perform basic SPI flash operations such
2047
+
* as Fast Read, Page Program or Sector Erase commands.
2048
+
*
2049
+
* Return: 0 on success, -errno otherwise.
2050
+
*/
2051
+
static int spi_nor_parse_sfdp(struct spi_nor *nor,
2052
+
struct spi_nor_flash_parameter *params)
2053
+
{
2054
+
const struct sfdp_parameter_header *param_header, *bfpt_header;
2055
+
struct sfdp_parameter_header *param_headers = NULL;
2056
+
struct sfdp_header header;
2057
+
struct device *dev = nor->dev;
2058
+
size_t psize;
2059
+
int i, err;
2060
+
2061
+
/* Get the SFDP header. */
2062
+
err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
2063
+
if (err < 0)
2064
+
return err;
2065
+
2066
+
/* Check the SFDP header version. */
2067
+
if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2068
+
header.major != SFDP_JESD216_MAJOR ||
2069
+
header.minor < SFDP_JESD216_MINOR)
2070
+
return -EINVAL;
2071
+
2072
+
/*
2073
+
* Verify that the first and only mandatory parameter header is a
2074
+
* Basic Flash Parameter Table header as specified in JESD216.
2075
+
*/
2076
+
bfpt_header = &header.bfpt_header;
2077
+
if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2078
+
bfpt_header->major != SFDP_JESD216_MAJOR)
2079
+
return -EINVAL;
2080
+
2081
+
/*
2082
+
* Allocate memory then read all parameter headers with a single
2083
+
* Read SFDP command. These parameter headers will actually be parsed
2084
+
* twice: a first time to get the latest revision of the basic flash
2085
+
* parameter table, then a second time to handle the supported optional
2086
+
* tables.
2087
+
* Hence we read the parameter headers once for all to reduce the
2088
+
* processing time. Also we use kmalloc() instead of devm_kmalloc()
2089
+
* because we don't need to keep these parameter headers: the allocated
2090
+
* memory is always released with kfree() before exiting this function.
2091
+
*/
2092
+
if (header.nph) {
2093
+
psize = header.nph * sizeof(*param_headers);
2094
+
2095
+
param_headers = kmalloc(psize, GFP_KERNEL);
2096
+
if (!param_headers)
2097
+
return -ENOMEM;
2098
+
2099
+
err = spi_nor_read_sfdp(nor, sizeof(header),
2100
+
psize, param_headers);
2101
+
if (err < 0) {
2102
+
dev_err(dev, "failed to read SFDP parameter headers\n");
2103
+
goto exit;
2104
+
}
2105
+
}
2106
+
2107
+
/*
2108
+
* Check other parameter headers to get the latest revision of
2109
+
* the basic flash parameter table.
2110
+
*/
2111
+
for (i = 0; i < header.nph; i++) {
2112
+
param_header = ¶m_headers[i];
2113
+
2114
+
if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2115
+
param_header->major == SFDP_JESD216_MAJOR &&
2116
+
(param_header->minor > bfpt_header->minor ||
2117
+
(param_header->minor == bfpt_header->minor &&
2118
+
param_header->length > bfpt_header->length)))
2119
+
bfpt_header = param_header;
2120
+
}
2121
+
2122
+
err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2123
+
if (err)
2124
+
goto exit;
2125
+
2126
+
/* Parse other parameter headers. */
2127
+
for (i = 0; i < header.nph; i++) {
2128
+
param_header = ¶m_headers[i];
2129
+
2130
+
switch (SFDP_PARAM_HEADER_ID(param_header)) {
2131
+
case SFDP_SECTOR_MAP_ID:
2132
+
dev_info(dev, "non-uniform erase sector maps are not supported yet.\n");
2133
+
break;
2134
+
2135
+
default:
2136
+
break;
2137
+
}
2138
+
2139
+
if (err)
2140
+
goto exit;
2141
+
}
2142
+
2143
+
exit:
2144
+
kfree(param_headers);
2145
+
return err;
2146
+
}
2147
+
1778
2148
static int spi_nor_init_params(struct spi_nor *nor,
1779
2149
const struct flash_info *info,
1780
2150
struct spi_nor_flash_parameter *params)
···
2384
1646
break;
2385
1647
2386
1648
default:
1649
+
/* Kept only for backward compatibility purpose. */
2387
1650
params->quad_enable = spansion_quad_enable;
2388
1651
break;
1652
+
}
1653
+
}
1654
+
1655
+
/* Override the parameters with data read from SFDP tables. */
1656
+
nor->addr_width = 0;
1657
+
nor->mtd.erasesize = 0;
1658
+
if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
1659
+
!(info->flags & SPI_NOR_SKIP_SFDP)) {
1660
+
struct spi_nor_flash_parameter sfdp_params;
1661
+
1662
+
memcpy(&sfdp_params, params, sizeof(sfdp_params));
1663
+
if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
1664
+
nor->addr_width = 0;
1665
+
nor->mtd.erasesize = 0;
1666
+
} else {
1667
+
memcpy(params, &sfdp_params, sizeof(*params));
2389
1668
}
2390
1669
}
2391
1670
···
2516
1761
const struct flash_info *info)
2517
1762
{
2518
1763
struct mtd_info *mtd = &nor->mtd;
1764
+
1765
+
/* Do nothing if already configured from SFDP. */
1766
+
if (mtd->erasesize)
1767
+
return 0;
2519
1768
2520
1769
#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2521
1770
/* prefer "small sector" erase if possible */
···
2719
1960
nor->flags |= SNOR_F_HAS_SR_TB;
2720
1961
if (info->flags & NO_CHIP_ERASE)
2721
1962
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
1963
+
if (info->flags & USE_CLSR)
1964
+
nor->flags |= SNOR_F_USE_CLSR;
2722
1965
2723
1966
if (info->flags & SPI_NOR_NO_ERASE)
2724
1967
mtd->flags |= MTD_NO_ERASE;
···
2755
1994
if (ret)
2756
1995
return ret;
2757
1996
2758
-
if (info->addr_width)
1997
+
if (nor->addr_width) {
1998
+
/* already configured from SFDP */
1999
+
} else if (info->addr_width) {
2759
2000
nor->addr_width = info->addr_width;
2760
-
else if (mtd->size > 0x1000000) {
2001
+
} else if (mtd->size > 0x1000000) {
2761
2002
/* enable 4-byte addressing if the device exceeds 16MiB */
2762
2003
nor->addr_width = 4;
2763
2004
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
+1
-1
drivers/mtd/ssfdc.c
+1
-1
drivers/mtd/ssfdc.c
+1
-1
drivers/mtd/tests/nandbiterrs.c
+1
-1
drivers/mtd/tests/nandbiterrs.c
+1
-1
drivers/staging/mt29f_spinand/mt29f_spinand.c
+1
-1
drivers/staging/mt29f_spinand/mt29f_spinand.c
+1
-1
fs/jffs2/wbuf.c
+1
-1
fs/jffs2/wbuf.c
+1
include/asm-generic/vmlinux.lds.h
+1
include/asm-generic/vmlinux.lds.h
+1
include/linux/mfd/tmio.h
+1
include/linux/mfd/tmio.h
+10
include/linux/mtd/mtd.h
+10
include/linux/mtd/mtd.h
···
206
206
207
207
struct module; /* only needed for owner field in mtd_info */
208
208
209
+
/**
210
+
* struct mtd_debug_info - debugging information for an MTD device.
211
+
*
212
+
* @dfs_dir: direntry object of the MTD device debugfs directory
213
+
*/
214
+
struct mtd_debug_info {
215
+
struct dentry *dfs_dir;
216
+
};
217
+
209
218
struct mtd_info {
210
219
u_char type;
211
220
uint32_t flags;
···
355
346
struct module *owner;
356
347
struct device dev;
357
348
int usecount;
349
+
struct mtd_debug_info dbg;
358
350
};
359
351
360
352
int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+1
-1
include/linux/mtd/nand-gpio.h
+1
-1
include/linux/mtd/nand-gpio.h
+10
-20
include/linux/mtd/nand.h
include/linux/mtd/rawnand.h
+10
-20
include/linux/mtd/nand.h
include/linux/mtd/rawnand.h
···
1
1
/*
2
-
* linux/include/linux/mtd/nand.h
3
-
*
4
2
* Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5
3
* Steven J. Hill <sjhill@realitydiluted.com>
6
4
* Thomas Gleixner <tglx@linutronix.de>
···
13
15
* Changelog:
14
16
* See git changelog.
15
17
*/
16
-
#ifndef __LINUX_MTD_NAND_H
17
-
#define __LINUX_MTD_NAND_H
18
+
#ifndef __LINUX_MTD_RAWNAND_H
19
+
#define __LINUX_MTD_RAWNAND_H
18
20
19
21
#include <linux/wait.h>
20
22
#include <linux/spinlock.h>
···
41
43
42
44
/* Internal helper for board drivers which need to override command function */
43
45
void nand_wait_ready(struct mtd_info *mtd);
44
-
45
-
/* locks all blocks present in the device */
46
-
int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
47
-
48
-
/* unlocks specified locked blocks */
49
-
int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
50
46
51
47
/* The maximum number of NAND chips in an array */
52
48
#define NAND_MAX_CHIPS 8
···
80
88
#define NAND_CMD_GET_FEATURES 0xee
81
89
#define NAND_CMD_SET_FEATURES 0xef
82
90
#define NAND_CMD_RESET 0xff
83
-
84
-
#define NAND_CMD_LOCK 0x2a
85
-
#define NAND_CMD_UNLOCK1 0x23
86
-
#define NAND_CMD_UNLOCK2 0x24
87
91
88
92
/* Extended commands for large page devices */
89
93
#define NAND_CMD_READSTART 0x30
···
437
449
__le16 crc;
438
450
} __packed;
439
451
452
+
/* The maximum expected count of bytes in the NAND ID sequence */
453
+
#define NAND_MAX_ID_LEN 8
454
+
440
455
/**
441
456
* struct nand_id - NAND id structure
442
-
* @data: buffer containing the id bytes. Currently 8 bytes large, but can
443
-
* be extended if required.
457
+
* @data: buffer containing the id bytes.
444
458
* @len: ID length.
445
459
*/
446
460
struct nand_id {
447
-
u8 data[8];
461
+
u8 data[NAND_MAX_ID_LEN];
448
462
int len;
449
463
};
450
464
···
1018
1028
#define NAND_MFR_ATO 0x9b
1019
1029
#define NAND_MFR_WINBOND 0xef
1020
1030
1021
-
/* The maximum expected count of bytes in the NAND ID sequence */
1022
-
#define NAND_MAX_ID_LEN 8
1023
1031
1024
1032
/*
1025
1033
* A helper for defining older NAND chips where the second ID byte fully
···
1234
1246
*/
1235
1247
static inline bool nand_is_slc(struct nand_chip *chip)
1236
1248
{
1249
+
WARN(chip->bits_per_cell == 0,
1250
+
"chip->bits_per_cell is used uninitialized\n");
1237
1251
return chip->bits_per_cell == 1;
1238
1252
}
1239
1253
···
1318
1328
1319
1329
/* Default extended ID decoding function */
1320
1330
void nand_decode_ext_id(struct nand_chip *chip);
1321
-
#endif /* __LINUX_MTD_NAND_H */
1331
+
#endif /* __LINUX_MTD_RAWNAND_H */
+1
-1
include/linux/mtd/sh_flctl.h
+1
-1
include/linux/mtd/sh_flctl.h
+2
-1
include/linux/mtd/sharpsl.h
+2
-1
include/linux/mtd/sharpsl.h
···
8
8
* published by the Free Software Foundation.
9
9
*/
10
10
11
-
#include <linux/mtd/nand.h>
11
+
#include <linux/mtd/rawnand.h>
12
12
#include <linux/mtd/nand_ecc.h>
13
13
#include <linux/mtd/partitions.h>
14
14
···
17
17
const struct mtd_ooblayout_ops *ecc_layout;
18
18
struct mtd_partition *partitions;
19
19
unsigned int nr_partitions;
20
+
const char *const *part_parsers;
20
21
};
+11
include/linux/mtd/spi-nor.h
+11
include/linux/mtd/spi-nor.h
···
41
41
#define SPINOR_OP_WREN 0x06 /* Write enable */
42
42
#define SPINOR_OP_RDSR 0x05 /* Read status register */
43
43
#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
44
+
#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
45
+
#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
44
46
#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
45
47
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
46
48
#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
···
58
56
#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
59
57
#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
60
58
#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
59
+
#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
61
60
#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
62
61
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
63
62
···
105
102
106
103
/* Used for Spansion flashes only. */
107
104
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
105
+
#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
108
106
109
107
/* Used for Micron flashes only. */
110
108
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
···
120
116
#define SR_BP2 BIT(4) /* Block protect 2 */
121
117
#define SR_TB BIT(5) /* Top/Bottom protect */
122
118
#define SR_SRWD BIT(7) /* SR write protect */
119
+
/* Spansion/Cypress specific status bits */
120
+
#define SR_E_ERR BIT(5)
121
+
#define SR_P_ERR BIT(6)
123
122
124
123
#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
125
124
···
134
127
135
128
/* Configuration Register bits. */
136
129
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
130
+
131
+
/* Status Register 2 bits. */
132
+
#define SR2_QUAD_EN_BIT7 BIT(7)
137
133
138
134
/* Supported SPI protocols */
139
135
#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
···
228
218
SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
229
219
SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
230
220
SNOR_F_READY_XSR_RDY = BIT(4),
221
+
SNOR_F_USE_CLSR = BIT(5),
231
222
};
232
223
233
224
/**
+7
-5
include/linux/mtd/xip.h
+7
-5
include/linux/mtd/xip.h
···
30
30
* obviously not be running from flash. The __xipram is therefore marking
31
31
* those functions so they get relocated to ram.
32
32
*/
33
-
#define __xipram noinline __attribute__ ((__section__ (".data")))
33
+
#ifdef CONFIG_XIP_KERNEL
34
+
#define __xipram noinline __attribute__ ((__section__ (".xiptext")))
35
+
#endif
34
36
35
37
/*
36
38
* Each architecture has to provide the following macros. They must access
···
92
90
#define xip_cpu_idle() do { } while (0)
93
91
#endif
94
92
95
-
#else
96
-
97
-
#define __xipram
98
-
99
93
#endif /* CONFIG_MTD_XIP */
94
+
95
+
#ifndef __xipram
96
+
#define __xipram
97
+
#endif
100
98
101
99
#endif /* __LINUX_MTD_XIP_H__ */
+1
-1
include/linux/platform_data/mtd-davinci.h
+1
-1
include/linux/platform_data/mtd-davinci.h