phy: cadence: Sierra: Use clk_parent_data to provide parent information

Rather than requesting the parent reference clocks for the sierra PHY PLLs
and then assigning the parents as a struct clk. Use the clk_parent_data
feature for the clock framework and only specify the firmware names of the
parent clocks.

The clock framework internally will then translate this to the actual
clocks. This allows to remove a bit of boilerplate code.

It also allows to only specify a single reference clock for both PLLs,
which is a valid use case. The clock framework can handle the case where
not all inputs for a clock mux are connected, while the custom
implementation in the driver could not.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230326011416.363318-2-lars@metafoo.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Lars-Peter Clausen and committed by

Vinod Koul 3 years ago a59f6006 6ef7aa32

+15 -42

1 changed file

expand all

drivers

phy

cadence

phy-cadence-sierra.c

+15 -42

drivers/phy/cadence/phy-cadence-sierra.c

··· 206 206 #define PLL_LOCK_TIME 100000 207 207 208 208 #define CDNS_SIERRA_OUTPUT_CLOCKS 3 209 - #define CDNS_SIERRA_INPUT_CLOCKS 5 209 + #define CDNS_SIERRA_INPUT_CLOCKS 3 210 210 enum cdns_sierra_clock_input { 211 211 PHY_CLK, 212 212 CMN_REFCLK_DIG_DIV, 213 213 CMN_REFCLK1_DIG_DIV, 214 - PLL0_REFCLK, 215 - PLL1_REFCLK, 216 214 }; 217 215 218 216 #define SIERRA_NUM_CMN_PLLC 2 ··· 272 274 #define to_cdns_sierra_pll_mux(_hw) \ 273 275 container_of(_hw, struct cdns_sierra_pll_mux, hw) 274 276 275 - static const int pll_mux_parent_index[][SIERRA_NUM_CMN_PLLC_PARENTS] = { 276 - [CMN_PLLLC] = { PLL0_REFCLK, PLL1_REFCLK }, 277 - [CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK }, 277 + #define PLL0_REFCLK_NAME "pll0_refclk" 278 + #define PLL1_REFCLK_NAME "pll1_refclk" 279 + 280 + static const struct clk_parent_data pll_mux_parent_data[][SIERRA_NUM_CMN_PLLC_PARENTS] = { 281 + [CMN_PLLLC] = { 282 + { .fw_name = PLL0_REFCLK_NAME }, 283 + { .fw_name = PLL1_REFCLK_NAME } 284 + }, 285 + [CMN_PLLLC1] = { 286 + { .fw_name = PLL1_REFCLK_NAME }, 287 + { .fw_name = PLL0_REFCLK_NAME } 288 + }, 278 289 }; 279 290 280 291 static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = { ··· 729 722 struct cdns_sierra_pll_mux *mux; 730 723 struct device *dev = sp->dev; 731 724 struct clk_init_data *init; 732 - const char **parent_names; 733 - unsigned int num_parents; 734 725 char clk_name[100]; 735 - struct clk *clk; 736 726 int ret; 737 - int i; 738 727 739 728 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 740 729 if (!mux) 741 730 return -ENOMEM; 742 - 743 - num_parents = SIERRA_NUM_CMN_PLLC_PARENTS; 744 - parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL); 745 - if (!parent_names) 746 - return -ENOMEM; 747 - 748 - for (i = 0; i < num_parents; i++) { 749 - clk = sp->input_clks[pll_mux_parent_index[clk_index][i]]; 750 - if (IS_ERR_OR_NULL(clk)) { 751 - dev_err(dev, "No parent clock for PLL mux clocks\n"); 752 - return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT; 753 - } 754 - parent_names[i] = __clk_get_name(clk); 755 - } 756 731 757 732 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]); 758 733 ··· 742 753 743 754 init->ops = &cdns_sierra_pll_mux_ops; 744 755 init->flags = CLK_SET_RATE_NO_REPARENT; 745 - init->parent_names = parent_names; 746 - init->num_parents = num_parents; 756 + init->parent_data = pll_mux_parent_data[clk_index]; 757 + init->num_parents = SIERRA_NUM_CMN_PLLC_PARENTS; 747 758 init->name = clk_name; 748 759 749 760 mux->pfdclk_sel_preg = pfdclk1_sel_field; ··· 1139 1150 return ret; 1140 1151 } 1141 1152 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; 1142 - 1143 - clk = devm_clk_get_optional(dev, "pll0_refclk"); 1144 - if (IS_ERR(clk)) { 1145 - dev_err(dev, "pll0_refclk clock not found\n"); 1146 - ret = PTR_ERR(clk); 1147 - return ret; 1148 - } 1149 - sp->input_clks[PLL0_REFCLK] = clk; 1150 - 1151 - clk = devm_clk_get_optional(dev, "pll1_refclk"); 1152 - if (IS_ERR(clk)) { 1153 - dev_err(dev, "pll1_refclk clock not found\n"); 1154 - ret = PTR_ERR(clk); 1155 - return ret; 1156 - } 1157 - sp->input_clks[PLL1_REFCLK] = clk; 1158 1153 1159 1154 return 0; 1160 1155 }

Configure Feed

Configure Feed