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media: rcar-csi2: Add documentation for PHY_EN and PHY_MODE registers

Later datasheets add documentation for two magic value used for V4H
support. The same registers will also be used for V4M support, document
them.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

authored by

Niklas Söderlund and committed by
Mauro Carvalho Chehab
a59f7ffd a8c916ed

+12 -2
+12 -2
drivers/media/platform/renesas/rcar-csi2.c
··· 135 135 /* V4H BASE registers */ 136 136 #define V4H_N_LANES_REG 0x0004 137 137 #define V4H_CSI2_RESETN_REG 0x0008 138 + 138 139 #define V4H_PHY_MODE_REG 0x001c 140 + #define V4H_PHY_MODE_DPHY 0 141 + #define V4H_PHY_MODE_CPHY 1 142 + 139 143 #define V4H_PHY_SHUTDOWNZ_REG 0x0040 140 144 #define V4H_DPHY_RSTZ_REG 0x0044 141 145 #define V4H_FLDC_REG 0x0804 142 146 #define V4H_FLDD_REG 0x0808 143 147 #define V4H_IDIC_REG 0x0810 148 + 144 149 #define V4H_PHY_EN_REG 0x2000 150 + #define V4H_PHY_EN_ENABLE_3 BIT(7) 151 + #define V4H_PHY_EN_ENABLE_2 BIT(6) 152 + #define V4H_PHY_EN_ENABLE_1 BIT(5) 153 + #define V4H_PHY_EN_ENABLE_0 BIT(4) 154 + #define V4H_PHY_EN_ENABLE_CLK BIT(0) 145 155 146 156 #define V4H_ST_PHYST_REG 0x2814 147 157 #define V4H_ST_PHYST_ST_PHY_READY BIT(31) ··· 1156 1146 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); 1157 1147 1158 1148 /* PHY static setting */ 1159 - rcsi2_write(priv, V4H_PHY_EN_REG, BIT(0)); 1149 + rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); 1160 1150 rcsi2_write(priv, V4H_FLDC_REG, 0); 1161 1151 rcsi2_write(priv, V4H_FLDD_REG, 0); 1162 1152 rcsi2_write(priv, V4H_IDIC_REG, 0); 1163 - rcsi2_write(priv, V4H_PHY_MODE_REG, BIT(0)); 1153 + rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_CPHY); 1164 1154 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); 1165 1155 1166 1156 /* Reset CSI2 */