Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/lt_phy: Add xe3plpd Thunderbolt PLL hooks
Add the PLL hooks for the TBT PLL on xe3plpd. These are simple stubs
similar to the TBT PLL on earlier platforms, since this PLL is always
on from the display POV - so no PLL enable/disable programming is
required as opposed to the non-TBT PLLs - and the clocks for different
link rates are enabled/disabled at a different level, via the
intel_encoder::enable_clock()/disable_clock() interface.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-22-mika.kahola@intel.com
+33
-2
+11
-2
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+11
-2
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
4618
4618
intel_xe3plpd_pll_disable(encoder);
4619
4619
}
4620
4620
4621
+
static const struct intel_dpll_funcs xe3plpd_tbt_pll_funcs = {
4622
+
.enable = mtl_tbt_pll_enable,
4623
+
.disable = mtl_tbt_pll_disable,
4624
+
.get_hw_state = intel_lt_phy_tbt_pll_readout_hw_state,
4625
+
.get_freq = mtl_tbt_pll_get_freq,
4626
+
};
4627
+
4621
4628
static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
4622
4629
.enable = xe3plpd_pll_enable,
4623
4630
.disable = xe3plpd_pll_disable,
···
4635
4628
static const struct dpll_info xe3plpd_plls[] = {
4636
4629
{ .name = "DPLL 0", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4637
4630
{ .name = "DPLL 1", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4638
-
/* TODO: Add TBT */
4631
+
{ .name = "TBT PLL", .funcs = &xe3plpd_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4632
+
.is_alt_port_dpll = true, .always_on = true },
4639
4633
{ .name = "TC PLL 1", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4640
4634
{ .name = "TC PLL 2", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4641
4635
{ .name = "TC PLL 3", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
···
4679
4671
struct icl_port_dpll *port_dpll;
4680
4672
int ret;
4681
4673
4682
-
/* TODO: Add state calculation for TBT PLL */
4674
+
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
4675
+
intel_lt_phy_tbt_pll_calc_state(&port_dpll->hw_state);
4683
4676
4684
4677
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
4685
4678
ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
+18
drivers/gpu/drm/i915/display/intel_lt_phy.c
+18
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
1784
1784
return -EINVAL;
1785
1785
}
1786
1786
1787
+
void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state)
1788
+
{
1789
+
memset(hw_state, 0, sizeof(*hw_state));
1790
+
1791
+
hw_state->ltpll.tbt_mode = true;
1792
+
}
1793
+
1787
1794
static void
1788
1795
intel_lt_phy_program_pll(struct intel_encoder *encoder,
1789
1796
const struct intel_lt_phy_pll_state *ltpll)
···
2218
2211
2219
2212
return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
2220
2213
XELPDP_LANE_PCLK_PLL_ACK(0);
2214
+
}
2215
+
2216
+
bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
2217
+
struct intel_dpll *pll,
2218
+
struct intel_dpll_hw_state *hw_state)
2219
+
{
2220
+
memset(hw_state, 0, sizeof(*hw_state));
2221
+
2222
+
hw_state->ltpll.tbt_mode = true;
2223
+
2224
+
return true;
2221
2225
}
2222
2226
2223
2227
bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
+4
drivers/gpu/drm/i915/display/intel_lt_phy.h
+4
drivers/gpu/drm/i915/display/intel_lt_phy.h
···
26
26
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
27
27
struct intel_encoder *encoder,
28
28
struct intel_dpll_hw_state *hw_state);
29
+
void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state);
29
30
int intel_lt_phy_calc_port_clock(struct intel_display *display,
30
31
const struct intel_lt_phy_pll_state *lt_state);
31
32
void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
···
36
35
bool
37
36
intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
38
37
const struct intel_lt_phy_pll_state *b);
38
+
bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
39
+
struct intel_dpll *pll,
40
+
struct intel_dpll_hw_state *hw_state);
39
41
bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
40
42
struct intel_lt_phy_pll_state *pll_state);
41
43
void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,