Merge tag 'amd-drm-next-6.20-2026-01-30' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

+8

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 1239 1239 struct amdgpu_kfd_dev kfd; 1240 1240 }; 1241 1241 1242 + /* 1243 + * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 1244 + * as fence address and writes a 32 bit fence value to this address. 1245 + * Driver needs to allocate at least 4 DWs extra memory in addition to 1246 + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 1247 + */ 1248 + #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 1249 + 1242 1250 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1243 1251 uint8_t ip, uint8_t inst) 1244 1252 {

+3 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c

··· 60 60 { 61 61 const struct amdgpu_bo_list_entry *a = _a, *b = _b; 62 62 63 - if (a->priority > b->priority) 64 - return 1; 65 - if (a->priority < b->priority) 66 - return -1; 67 - return 0; 63 + BUILD_BUG_ON(AMDGPU_BO_LIST_MAX_PRIORITY >= INT_MAX); 64 + 65 + return (int)a->priority - (int)b->priority; 68 66 } 69 67 70 68 int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,

+10 -8

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

··· 385 385 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 386 386 struct amdgpu_ring *ring = &kiq->ring; 387 387 u32 domain = AMDGPU_GEM_DOMAIN_GTT; 388 + u32 gfx_mqd_size = max(adev->mqds[AMDGPU_HW_IP_GFX].mqd_size, mqd_size); 389 + u32 compute_mqd_size = max(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size, mqd_size); 388 390 389 391 #if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) 390 392 /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */ ··· 426 424 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 427 425 ring = &adev->gfx.gfx_ring[i]; 428 426 if (!ring->mqd_obj) { 429 - r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 430 - domain, &ring->mqd_obj, 427 + r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(gfx_mqd_size), 428 + PAGE_SIZE, domain, &ring->mqd_obj, 431 429 &ring->mqd_gpu_addr, &ring->mqd_ptr); 432 430 if (r) { 433 431 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 434 432 return r; 435 433 } 436 434 437 - ring->mqd_size = mqd_size; 435 + ring->mqd_size = gfx_mqd_size; 438 436 /* prepare MQD backup */ 439 - adev->gfx.me.mqd_backup[i] = kzalloc(mqd_size, GFP_KERNEL); 437 + adev->gfx.me.mqd_backup[i] = kzalloc(gfx_mqd_size, GFP_KERNEL); 440 438 if (!adev->gfx.me.mqd_backup[i]) { 441 439 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 442 440 return -ENOMEM; ··· 450 448 j = i + xcc_id * adev->gfx.num_compute_rings; 451 449 ring = &adev->gfx.compute_ring[j]; 452 450 if (!ring->mqd_obj) { 453 - r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 454 - domain, &ring->mqd_obj, 451 + r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(compute_mqd_size), 452 + PAGE_SIZE, domain, &ring->mqd_obj, 455 453 &ring->mqd_gpu_addr, &ring->mqd_ptr); 456 454 if (r) { 457 455 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 458 456 return r; 459 457 } 460 458 461 - ring->mqd_size = mqd_size; 459 + ring->mqd_size = compute_mqd_size; 462 460 /* prepare MQD backup */ 463 - adev->gfx.mec.mqd_backup[j] = kzalloc(mqd_size, GFP_KERNEL); 461 + adev->gfx.mec.mqd_backup[j] = kzalloc(compute_mqd_size, GFP_KERNEL); 464 462 if (!adev->gfx.mec.mqd_backup[j]) { 465 463 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 466 464 return -ENOMEM;

+6 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

··· 498 498 499 499 if (adev->irq.retry_cam_enabled) 500 500 return; 501 + else if (adev->irq.ih1.ring_size) 502 + ih = &adev->irq.ih1; 503 + else if (adev->irq.ih_soft.enabled) 504 + ih = &adev->irq.ih_soft; 505 + else 506 + return; 501 507 502 - ih = &adev->irq.ih1; 503 508 /* Get the WPTR of the last entry in IH ring */ 504 509 last_wptr = amdgpu_ih_get_wptr(adev, ih); 505 510 /* Order wptr with ring data. */

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

··· 235 235 236 236 amdgpu_ring_ib_begin(ring); 237 237 238 - if (ring->funcs->emit_gfx_shadow) 238 + if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow) 239 239 amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, 240 240 init_shadow, vmid); 241 241 ··· 291 291 fence_flags | AMDGPU_FENCE_FLAG_64BIT); 292 292 } 293 293 294 - if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) { 294 + if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec && 295 + adev->gfx.cp_gfx_shadow) { 295 296 amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0); 296 297 amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); 297 298 }

-9

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

··· 115 115 116 116 adev->mes.adev = adev; 117 117 118 - idr_init(&adev->mes.pasid_idr); 119 - idr_init(&adev->mes.gang_id_idr); 120 - idr_init(&adev->mes.queue_id_idr); 121 118 ida_init(&adev->mes.doorbell_ida); 122 119 spin_lock_init(&adev->mes.queue_id_lock); 123 120 mutex_init(&adev->mes.mutex_hidden); ··· 249 252 &adev->mes.hung_queue_db_array_cpu_addr[i]); 250 253 } 251 254 252 - idr_destroy(&adev->mes.pasid_idr); 253 - idr_destroy(&adev->mes.gang_id_idr); 254 - idr_destroy(&adev->mes.queue_id_idr); 255 255 ida_destroy(&adev->mes.doorbell_ida); 256 256 mutex_destroy(&adev->mes.mutex_hidden); 257 257 return r; ··· 277 283 278 284 amdgpu_mes_doorbell_free(adev); 279 285 280 - idr_destroy(&adev->mes.pasid_idr); 281 - idr_destroy(&adev->mes.gang_id_idr); 282 - idr_destroy(&adev->mes.queue_id_idr); 283 286 ida_destroy(&adev->mes.doorbell_ida); 284 287 mutex_destroy(&adev->mes.mutex_hidden); 285 288 }

-3

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

··· 77 77 78 78 struct mutex mutex_hidden; 79 79 80 - struct idr pasid_idr; 81 - struct idr gang_id_idr; 82 - struct idr queue_id_idr; 83 80 struct ida doorbell_ida; 84 81 85 82 spinlock_t queue_id_lock;

+4

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

··· 1712 1712 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1713 1713 control->ras_num_bad_pages, 1714 1714 ras->bad_page_cnt_threshold); 1715 + if (amdgpu_bad_page_threshold != 0 && 1716 + control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) 1717 + amdgpu_dpm_send_rma_reason(adev); 1718 + 1715 1719 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1716 1720 amdgpu_bad_page_threshold != 0) { 1717 1721 if (hdr->version >= RAS_TABLE_VER_V2_1) {

+11

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c

··· 932 932 drm_file_err(filp, "invalidate userq queue va or size\n"); 933 933 return -EINVAL; 934 934 } 935 + 936 + if (!is_power_of_2(args->in.queue_size)) { 937 + drm_file_err(filp, "Queue size must be a power of 2\n"); 938 + return -EINVAL; 939 + } 940 + 941 + if (args->in.queue_size < AMDGPU_GPU_PAGE_SIZE) { 942 + drm_file_err(filp, "Queue size smaller than AMDGPU_GPU_PAGE_SIZE\n"); 943 + return -EINVAL; 944 + } 945 + 935 946 if (!args->in.wptr_va || !args->in.rptr_va) { 936 947 drm_file_err(filp, "invalidate userq queue rptr or wptr\n"); 937 948 return -EINVAL;

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

··· 6880 6880 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6881 6881 /* reset the ring */ 6882 6882 ring->wptr = 0; 6883 - *ring->wptr_cpu_addr = 0; 6883 + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6884 6884 amdgpu_ring_clear_ring(ring); 6885 6885 } 6886 6886

+14 -11

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

··· 4214 4214 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 4215 4215 /* reset the ring */ 4216 4216 ring->wptr = 0; 4217 - *ring->wptr_cpu_addr = 0; 4217 + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4218 4218 amdgpu_ring_clear_ring(ring); 4219 4219 } 4220 4220 ··· 6828 6828 struct amdgpu_fence *timedout_fence) 6829 6829 { 6830 6830 struct amdgpu_device *adev = ring->adev; 6831 + bool use_mmio = false; 6831 6832 int r; 6832 6833 6833 6834 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 6834 6835 6835 - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0); 6836 + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); 6836 6837 if (r) { 6837 6838 6838 6839 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); ··· 6842 6841 return r; 6843 6842 } 6844 6843 6845 - r = gfx_v11_0_kgq_init_queue(ring, true); 6846 - if (r) { 6847 - dev_err(adev->dev, "failed to init kgq\n"); 6848 - return r; 6849 - } 6844 + if (use_mmio) { 6845 + r = gfx_v11_0_kgq_init_queue(ring, true); 6846 + if (r) { 6847 + dev_err(adev->dev, "failed to init kgq\n"); 6848 + return r; 6849 + } 6850 6850 6851 - r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 6852 - if (r) { 6853 - dev_err(adev->dev, "failed to remap kgq\n"); 6854 - return r; 6851 + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 6852 + if (r) { 6853 + dev_err(adev->dev, "failed to remap kgq\n"); 6854 + return r; 6855 + } 6855 6856 } 6856 6857 6857 6858 return amdgpu_ring_reset_helper_end(ring, timedout_fence);

+14 -11

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

··· 3085 3085 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3086 3086 /* reset the ring */ 3087 3087 ring->wptr = 0; 3088 - *ring->wptr_cpu_addr = 0; 3088 + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3089 3089 amdgpu_ring_clear_ring(ring); 3090 3090 } 3091 3091 ··· 5292 5292 struct amdgpu_fence *timedout_fence) 5293 5293 { 5294 5294 struct amdgpu_device *adev = ring->adev; 5295 + bool use_mmio = false; 5295 5296 int r; 5296 5297 5297 5298 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5298 5299 5299 - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0); 5300 + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); 5300 5301 if (r) { 5301 5302 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5302 5303 r = gfx_v12_reset_gfx_pipe(ring); ··· 5305 5304 return r; 5306 5305 } 5307 5306 5308 - r = gfx_v12_0_kgq_init_queue(ring, true); 5309 - if (r) { 5310 - dev_err(adev->dev, "failed to init kgq\n"); 5311 - return r; 5312 - } 5307 + if (use_mmio) { 5308 + r = gfx_v12_0_kgq_init_queue(ring, true); 5309 + if (r) { 5310 + dev_err(adev->dev, "failed to init kgq\n"); 5311 + return r; 5312 + } 5313 5313 5314 - r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 5315 - if (r) { 5316 - dev_err(adev->dev, "failed to remap kgq\n"); 5317 - return r; 5314 + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 5315 + if (r) { 5316 + dev_err(adev->dev, "failed to remap kgq\n"); 5317 + return r; 5318 + } 5318 5319 } 5319 5320 5320 5321 return amdgpu_ring_reset_helper_end(ring, timedout_fence);

+13 -14

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

··· 30 30 #include "amdgpu_psp.h" 31 31 #include "amdgpu_smu.h" 32 32 #include "amdgpu_atomfirmware.h" 33 + #include "amdgpu_userq_fence.h" 33 34 #include "imu_v12_1.h" 34 35 #include "soc_v1_0.h" 35 36 #include "gfx_v12_1_pkt.h" ··· 2236 2235 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 2237 2236 2238 2237 mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : 2239 - sizeof(struct v12_1_compute_mqd); 2238 + AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); 2240 2239 2241 2240 mqd->cp_hqd_active = prop->hqd_active; 2242 2241 ··· 3603 3602 struct amdgpu_irq_src *source, 3604 3603 struct amdgpu_iv_entry *entry) 3605 3604 { 3606 - int i, xcc_id; 3605 + u32 doorbell_offset = entry->src_data[0]; 3607 3606 u8 me_id, pipe_id, queue_id; 3608 3607 struct amdgpu_ring *ring; 3609 - uint32_t mes_queue_id = entry->src_data[0]; 3608 + int i, xcc_id; 3610 3609 3611 3610 DRM_DEBUG("IH: CP EOP\n"); 3612 3611 3613 - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 3614 - struct amdgpu_mes_queue *queue; 3612 + if (adev->enable_mes && doorbell_offset) { 3613 + struct amdgpu_userq_fence_driver *fence_drv = NULL; 3614 + struct xarray *xa = &adev->userq_xa; 3615 + unsigned long flags; 3615 3616 3616 - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 3617 - 3618 - spin_lock(&adev->mes.queue_id_lock); 3619 - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 3620 - if (queue) { 3621 - DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 3622 - amdgpu_fence_process(queue->ring); 3623 - } 3624 - spin_unlock(&adev->mes.queue_id_lock); 3617 + xa_lock_irqsave(xa, flags); 3618 + fence_drv = xa_load(xa, doorbell_offset); 3619 + if (fence_drv) 3620 + amdgpu_userq_fence_driver_process(fence_drv); 3621 + xa_unlock_irqrestore(xa, flags); 3625 3622 } else { 3626 3623 me_id = (entry->ring_id & 0x0c) >> 2; 3627 3624 pipe_id = (entry->ring_id & 0x03) >> 0;

+2 -1

drivers/gpu/drm/amd/amdgpu/mes_userqueue.c

··· 289 289 return -ENOMEM; 290 290 } 291 291 292 - r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, mqd_hw_default->mqd_size); 292 + r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, 293 + AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); 293 294 if (r) { 294 295 DRM_ERROR("Failed to create MQD object for userqueue\n"); 295 296 goto free_props;

+3 -15

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

··· 1704 1704 struct amdgpu_irq_src *source, 1705 1705 struct amdgpu_iv_entry *entry) 1706 1706 { 1707 - uint32_t mes_queue_id = entry->src_data[0]; 1708 - 1709 1707 DRM_DEBUG("IH: SDMA trap\n"); 1710 1708 1711 - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1712 - struct amdgpu_mes_queue *queue; 1713 - 1714 - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1715 - 1716 - spin_lock(&adev->mes.queue_id_lock); 1717 - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1718 - if (queue) { 1719 - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1720 - amdgpu_fence_process(queue->ring); 1721 - } 1722 - spin_unlock(&adev->mes.queue_id_lock); 1709 + if (drm_WARN_ON_ONCE(&adev->ddev, 1710 + adev->enable_mes && 1711 + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) 1723 1712 return 0; 1724 - } 1725 1713 1726 1714 switch (entry->client_id) { 1727 1715 case SOC15_IH_CLIENTID_SDMA0:

+3 -15

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

··· 1617 1617 struct amdgpu_irq_src *source, 1618 1618 struct amdgpu_iv_entry *entry) 1619 1619 { 1620 - uint32_t mes_queue_id = entry->src_data[0]; 1621 - 1622 1620 DRM_DEBUG("IH: SDMA trap\n"); 1623 1621 1624 - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1625 - struct amdgpu_mes_queue *queue; 1626 - 1627 - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1628 - 1629 - spin_lock(&adev->mes.queue_id_lock); 1630 - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1631 - if (queue) { 1632 - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1633 - amdgpu_fence_process(queue->ring); 1634 - } 1635 - spin_unlock(&adev->mes.queue_id_lock); 1622 + if (drm_WARN_ON_ONCE(&adev->ddev, 1623 + adev->enable_mes && 1624 + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) 1636 1625 return 0; 1637 - } 1638 1626 1639 1627 switch (entry->client_id) { 1640 1628 case SOC15_IH_CLIENTID_SDMA0:

+3 -14

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

··· 1494 1494 struct amdgpu_iv_entry *entry) 1495 1495 { 1496 1496 int inst, instances, queue, xcc_id = 0; 1497 - uint32_t mes_queue_id = entry->src_data[0]; 1498 1497 1499 1498 DRM_DEBUG("IH: SDMA trap\n"); 1500 1499 1501 - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1502 - struct amdgpu_mes_queue *queue; 1503 - 1504 - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1505 - 1506 - spin_lock(&adev->mes.queue_id_lock); 1507 - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1508 - if (queue) { 1509 - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1510 - amdgpu_fence_process(queue->ring); 1511 - } 1512 - spin_unlock(&adev->mes.queue_id_lock); 1500 + if (drm_WARN_ON_ONCE(&adev->ddev, 1501 + adev->enable_mes && 1502 + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) 1513 1503 return 0; 1514 - } 1515 1504 1516 1505 queue = entry->ring_id & 0xf; 1517 1506 if (adev->gfx.funcs && adev->gfx.funcs->ih_node_to_logical_xcc)

+7 -1

drivers/gpu/drm/amd/amdgpu/soc21.c

··· 256 256 257 257 static u32 soc21_get_xclk(struct amdgpu_device *adev) 258 258 { 259 - return adev->clock.spll.reference_freq; 259 + u32 reference_clock = adev->clock.spll.reference_freq; 260 + 261 + /* reference clock is actually 99.81 Mhz rather than 100 Mhz */ 262 + if ((adev->flags & AMD_IS_APU) && reference_clock == 10000) 263 + return 9981; 264 + 265 + return reference_clock; 260 266 } 261 267 262 268

+1 -1

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

··· 1742 1742 goto unlock; 1743 1743 } 1744 1744 1745 - r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); 1746 1745 if (pg_state) 1747 1746 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, 1748 1747 AMD_PG_STATE_GATE); 1749 1748 mutex_unlock(&adev->jpeg.jpeg_pg_lock); 1749 + r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); 1750 1750 1751 1751 unlock: 1752 1752 mutex_unlock(&vinst->engine_reset_mutex);

+105 -96

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h

··· 4587 4587 }; 4588 4588 4589 4589 static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 4590 - 0xbfa00001, 0xbfa003ac, 4590 + 0xbfa00001, 0xbfa003be, 4591 4591 0xb0804009, 0xb8f8f804, 4592 4592 0x9178ff78, 0x00008c00, 4593 4593 0xb8fbf811, 0x8b6eff78, 4594 4594 0x00004000, 0xbfa10008, 4595 4595 0x8b6eff7b, 0x00000080, 4596 4596 0xbfa20018, 0x8b6ea07b, 4597 - 0xbfa200d1, 0xbf830010, 4597 + 0xbfa200da, 0xbf830010, 4598 4598 0xb8fbf811, 0xbfa0fffb, 4599 4599 0x8b6eff7b, 0x00000bd0, 4600 4600 0xbfa20010, 0xb8eef812, ··· 4605 4605 0xf0000000, 0xbfa20005, 4606 4606 0x8b6fff6f, 0x00000200, 4607 4607 0xbfa20002, 0x8b6ea07b, 4608 - 0xbfa200bb, 0x9177ff77, 4608 + 0xbfa200c4, 0x9177ff77, 4609 4609 0x007fc000, 0xb8fa04a1, 4610 4610 0x847a967a, 0x8c777a77, 4611 4611 0xb8fa0421, 0x847a957a, ··· 4632 4632 0xbfa00002, 0x806c846c, 4633 4633 0x826d806d, 0x8b6dff6d, 4634 4634 0x01ffffff, 0xb8fbf811, 4635 - 0xbf0d847b, 0xbfa20078, 4635 + 0xbf0d847b, 0xbfa20081, 4636 4636 0xf4003eb6, 0xf8000000, 4637 4637 0xbfc70000, 0xf4003bb6, 4638 4638 0xf8000008, 0x8b76ff7a, 4639 4639 0x80000000, 0xbfa20027, 4640 4640 0x9376ff7a, 0x00060019, 4641 4641 0x81f9a376, 0xbf0b8179, 4642 - 0xbfa20068, 0x81f9ac76, 4643 - 0xbf0b8179, 0xbfa20062, 4642 + 0xbfa2006e, 0x81f9ac76, 4643 + 0xbf0b8179, 0xbfa20068, 4644 4644 0x81f9b776, 0xbf0b8179, 4645 - 0xbfa2005f, 0x8b76ff7a, 4645 + 0xbfa20065, 0x8b76ff7a, 4646 4646 0x000001ff, 0xbf06ff76, 4647 - 0x000000fe, 0xbfa2005d, 4647 + 0x000000fe, 0xbfa20063, 4648 4648 0xbf06ff76, 0x000000ff, 4649 - 0xbfa20057, 0xbf06ff76, 4650 - 0x000000fa, 0xbfa20054, 4649 + 0xbfa2005d, 0xbf06ff76, 4650 + 0x000000fa, 0xbfa2005a, 4651 4651 0x81f9ff76, 0x000000e9, 4652 - 0xbf0b8179, 0xbfa20050, 4652 + 0xbf0b8179, 0xbfa20056, 4653 4653 0x8b76ff7b, 0xffff0000, 4654 4654 0xbf06ff76, 0xbf860000, 4655 - 0xbfa10051, 0x9376ff7b, 4655 + 0xbfa1005a, 0x9376ff7b, 4656 4656 0x0002000e, 0x8b79ff7b, 4657 4657 0x00003f00, 0x85798679, 4658 4658 0x8c767976, 0xb9763b01, 4659 - 0xbfa00049, 0x8b76ff7a, 4659 + 0xbfa00052, 0x8b76ff7a, 4660 4660 0xfc000000, 0xbf06ff76, 4661 - 0xd4000000, 0xbfa20013, 4661 + 0xd4000000, 0xbfa20019, 4662 4662 0xbf06ff76, 0xc8000000, 4663 - 0xbfa20027, 0x8b76ff7a, 4663 + 0xbfa2002d, 0x8b76ff7a, 4664 4664 0xff000000, 0xbf06ff76, 4665 - 0xcf000000, 0xbfa20039, 4665 + 0xcf000000, 0xbfa2003f, 4666 4666 0x8b79ff7a, 0xffff0000, 4667 + 0xbf06ff79, 0xcc330000, 4668 + 0xbfa2003d, 0xbf06ff79, 4669 + 0xcc880000, 0xbfa2003a, 4667 4670 0xbf06ff79, 0xcc350000, 4668 - 0xbfa20037, 0xbf06ff79, 4669 - 0xcc3a0000, 0xbfa20034, 4671 + 0xbfa2003a, 0xbf06ff79, 4672 + 0xcc3a0000, 0xbfa20037, 4670 4673 0xbf06ff76, 0xcc000000, 4671 - 0xbfa10031, 0x8b76ff7b, 4674 + 0xbfa10034, 0x8b76ff7b, 4672 4675 0x000001ff, 0xbf06ff76, 4673 4676 0x000000ff, 0xbfa20029, 4674 4677 0xbf06ff76, 0x000000fa, ··· 4694 4691 0x000001ff, 0xbf06ff76, 4695 4692 0x000000ff, 0xbfa20003, 4696 4693 0xbfc70000, 0xbefb006e, 4697 - 0xbfa0ffad, 0xbfc70000, 4698 - 0xbefb006f, 0xbfa0ffaa, 4699 - 0xbfc70000, 0x857a9677, 4700 - 0xb97a04a1, 0x857a9577, 4701 - 0xb97a0421, 0x857a8e77, 4702 - 0xb97a3021, 0x8bfe7e7e, 4703 - 0x8bea6a6a, 0x85788978, 4704 - 0xb9783244, 0xbe804a6c, 4705 - 0xb8faf802, 0xbf0d987a, 4706 - 0xbfa10001, 0xbfb00000, 4707 - 0x8b6dff6d, 0x01ffffff, 4708 - 0xbefa0080, 0xb97a0151, 4709 - 0x9177ff77, 0x007fc000, 4710 - 0xb8fa04a1, 0x847a967a, 4711 - 0x8c777a77, 0xb8fa0421, 4712 - 0x847a957a, 0x8c777a77, 4713 - 0xb8fa3021, 0x847a8e7a, 4714 - 0x8c777a77, 0xb980f821, 4715 - 0x00000000, 0xbf0d847b, 4716 - 0xbfa20078, 0xf4003eb6, 4717 - 0xf8000000, 0xbfc70000, 4718 - 0xf4003bb6, 0xf8000008, 4719 - 0x8b76ff7a, 0x80000000, 4720 - 0xbfa20027, 0x9376ff7a, 4721 - 0x00060019, 0x81f9a376, 4694 + 0xbfa0ffa7, 0xbfc70000, 4695 + 0xbefb006f, 0xbfa0ffa4, 4696 + 0x80ec886c, 0x82ed806d, 4697 + 0xbfa0fff7, 0xbfc70000, 4698 + 0x857a9677, 0xb97a04a1, 4699 + 0x857a9577, 0xb97a0421, 4700 + 0x857a8e77, 0xb97a3021, 4701 + 0x8bfe7e7e, 0x8bea6a6a, 4702 + 0x85788978, 0xb9783244, 4703 + 0xbe804a6c, 0xb8faf802, 4704 + 0xbf0d987a, 0xbfa10001, 4705 + 0xbfb00000, 0x8b6dff6d, 4706 + 0x01ffffff, 0xbefa0080, 4707 + 0xb97a0151, 0x9177ff77, 4708 + 0x007fc000, 0xb8fa04a1, 4709 + 0x847a967a, 0x8c777a77, 4710 + 0xb8fa0421, 0x847a957a, 4711 + 0x8c777a77, 0xb8fa3021, 4712 + 0x847a8e7a, 0x8c777a77, 4713 + 0xb980f821, 0x00000000, 4714 + 0xbf0d847b, 0xbfa20081, 4715 + 0xf4003eb6, 0xf8000000, 4716 + 0xbfc70000, 0xf4003bb6, 4717 + 0xf8000008, 0x8b76ff7a, 4718 + 0x80000000, 0xbfa20027, 4719 + 0x9376ff7a, 0x00060019, 4720 + 0x81f9a376, 0xbf0b8179, 4721 + 0xbfa2006e, 0x81f9ac76, 4722 4722 0xbf0b8179, 0xbfa20068, 4723 - 0x81f9ac76, 0xbf0b8179, 4724 - 0xbfa20062, 0x81f9b776, 4725 - 0xbf0b8179, 0xbfa2005f, 4726 - 0x8b76ff7a, 0x000001ff, 4727 - 0xbf06ff76, 0x000000fe, 4728 - 0xbfa2005d, 0xbf06ff76, 4729 - 0x000000ff, 0xbfa20057, 4730 - 0xbf06ff76, 0x000000fa, 4731 - 0xbfa20054, 0x81f9ff76, 4732 - 0x000000e9, 0xbf0b8179, 4733 - 0xbfa20050, 0x8b76ff7b, 4734 - 0xffff0000, 0xbf06ff76, 4735 - 0xbf860000, 0xbfa10051, 4736 - 0x9376ff7b, 0x0002000e, 4737 - 0x8b79ff7b, 0x00003f00, 4738 - 0x85798679, 0x8c767976, 4739 - 0xb9763b01, 0xbfa00049, 4740 - 0x8b76ff7a, 0xfc000000, 4741 - 0xbf06ff76, 0xd4000000, 4742 - 0xbfa20013, 0xbf06ff76, 4743 - 0xc8000000, 0xbfa20027, 4744 - 0x8b76ff7a, 0xff000000, 4745 - 0xbf06ff76, 0xcf000000, 4746 - 0xbfa20039, 0x8b79ff7a, 4747 - 0xffff0000, 0xbf06ff79, 4748 - 0xcc350000, 0xbfa20037, 4749 - 0xbf06ff79, 0xcc3a0000, 4750 - 0xbfa20034, 0xbf06ff76, 4751 - 0xcc000000, 0xbfa10031, 4752 - 0x8b76ff7b, 0x000001ff, 4753 - 0xbf06ff76, 0x000000ff, 4754 - 0xbfa20029, 0xbf06ff76, 4755 - 0x000000fa, 0xbfa20026, 4756 - 0x81f6ff76, 0x000000e9, 4757 - 0xbf0b8176, 0xbfa20022, 4758 - 0x8b76ff7b, 0x0003fe00, 4759 - 0xbf06ff76, 0x0001fe00, 4760 - 0xbfa2001d, 0x8b76ff7b, 4761 - 0x07fc0000, 0xbf06ff76, 4762 - 0x03fc0000, 0xbfa20018, 4763 - 0xbfa00014, 0x9376ff7a, 4764 - 0x00040016, 0x81f68176, 4765 - 0xbf0b8176, 0xbfa20012, 4766 - 0x9376ff7a, 0x00050011, 4767 - 0x81f68176, 0xbf0b8176, 4768 - 0xbfa2000d, 0x8b76ff7a, 4723 + 0x81f9b776, 0xbf0b8179, 4724 + 0xbfa20065, 0x8b76ff7a, 4769 4725 0x000001ff, 0xbf06ff76, 4770 - 0x000000ff, 0xbfa20008, 4771 - 0x8b76ff7b, 0x000001ff, 4726 + 0x000000fe, 0xbfa20063, 4772 4727 0xbf06ff76, 0x000000ff, 4773 - 0xbfa20003, 0xbfc70000, 4774 - 0xbefb006e, 0xbfa0ffad, 4775 - 0xbfc70000, 0xbefb006f, 4776 - 0xbfa0ffaa, 0xbfc70000, 4728 + 0xbfa2005d, 0xbf06ff76, 4729 + 0x000000fa, 0xbfa2005a, 4730 + 0x81f9ff76, 0x000000e9, 4731 + 0xbf0b8179, 0xbfa20056, 4732 + 0x8b76ff7b, 0xffff0000, 4733 + 0xbf06ff76, 0xbf860000, 4734 + 0xbfa1005a, 0x9376ff7b, 4735 + 0x0002000e, 0x8b79ff7b, 4736 + 0x00003f00, 0x85798679, 4737 + 0x8c767976, 0xb9763b01, 4738 + 0xbfa00052, 0x8b76ff7a, 4739 + 0xfc000000, 0xbf06ff76, 4740 + 0xd4000000, 0xbfa20019, 4741 + 0xbf06ff76, 0xc8000000, 4742 + 0xbfa2002d, 0x8b76ff7a, 4743 + 0xff000000, 0xbf06ff76, 4744 + 0xcf000000, 0xbfa2003f, 4745 + 0x8b79ff7a, 0xffff0000, 4746 + 0xbf06ff79, 0xcc330000, 4747 + 0xbfa2003d, 0xbf06ff79, 4748 + 0xcc880000, 0xbfa2003a, 4749 + 0xbf06ff79, 0xcc350000, 4750 + 0xbfa2003a, 0xbf06ff79, 4751 + 0xcc3a0000, 0xbfa20037, 4752 + 0xbf06ff76, 0xcc000000, 4753 + 0xbfa10034, 0x8b76ff7b, 4754 + 0x000001ff, 0xbf06ff76, 4755 + 0x000000ff, 0xbfa20029, 4756 + 0xbf06ff76, 0x000000fa, 4757 + 0xbfa20026, 0x81f6ff76, 4758 + 0x000000e9, 0xbf0b8176, 4759 + 0xbfa20022, 0x8b76ff7b, 4760 + 0x0003fe00, 0xbf06ff76, 4761 + 0x0001fe00, 0xbfa2001d, 4762 + 0x8b76ff7b, 0x07fc0000, 4763 + 0xbf06ff76, 0x03fc0000, 4764 + 0xbfa20018, 0xbfa00014, 4765 + 0x9376ff7a, 0x00040016, 4766 + 0x81f68176, 0xbf0b8176, 4767 + 0xbfa20012, 0x9376ff7a, 4768 + 0x00050011, 0x81f68176, 4769 + 0xbf0b8176, 0xbfa2000d, 4770 + 0x8b76ff7a, 0x000001ff, 4771 + 0xbf06ff76, 0x000000ff, 4772 + 0xbfa20008, 0x8b76ff7b, 4773 + 0x000001ff, 0xbf06ff76, 4774 + 0x000000ff, 0xbfa20003, 4775 + 0xbfc70000, 0xbefb006e, 4776 + 0xbfa0ffa7, 0xbfc70000, 4777 + 0xbefb006f, 0xbfa0ffa4, 4778 + 0x80ec886c, 0x82ed806d, 4779 + 0xbfa0fff7, 0xbfc70000, 4777 4780 0xbeee007e, 0xbeef007f, 4778 4781 0xbefe0180, 0xbefe4d84, 4779 4782 0xbf8a0000, 0x8b7aff7f,

+18 -7

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm

··· 37 37 #define HAVE_CLUSTER_BARRIER (ASIC_FAMILY == CHIP_GC_12_0_3) 38 38 #define CLUSTER_BARRIER_SERIALIZE_WORKAROUND (ASIC_FAMILY == CHIP_GC_12_0_3) 39 39 #define RELAXED_SCHEDULING_IN_TRAP (ASIC_FAMILY == CHIP_GFX12) 40 + #define HAVE_INSTRUCTION_FIXUP (ASIC_FAMILY == CHIP_GC_12_0_3) 40 41 41 42 #define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised 42 43 #define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12) ··· 376 375 L_EXIT_TRAP: 377 376 s_and_b32 ttmp1, ttmp1, ADDRESS_HI32_MASK 378 377 379 - #if HAVE_BANKED_VGPRS 378 + #if HAVE_INSTRUCTION_FIXUP 380 379 s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) 381 - fixup_vgpr_bank_selection() 380 + fixup_instruction() 382 381 #endif 383 382 384 383 #if HAVE_XNACK ··· 419 418 save_and_clear_xnack_state_priv(s_save_tmp) 420 419 #endif 421 420 422 - #if HAVE_BANKED_VGPRS 423 - fixup_vgpr_bank_selection() 421 + #if HAVE_INSTRUCTION_FIXUP 422 + fixup_instruction() 424 423 #endif 425 424 426 425 /* inform SPI the readiness and wait for SPI's go signal */ ··· 1401 1400 L_BARRIER_RESTORE_DONE: 1402 1401 end 1403 1402 1404 - #if HAVE_BANKED_VGPRS 1405 - function fixup_vgpr_bank_selection 1403 + #if HAVE_INSTRUCTION_FIXUP 1404 + function fixup_instruction 1406 1405 // PC read may fault if memory violation has been asserted. 1407 1406 // In this case no further progress is expected so fixup is not needed. 1408 1407 s_bitcmp1_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_SHIFT ··· 1481 1480 s_cmp_eq_u32 ttmp10, 0xcf000000 // If 31:24 = 0xcf, this is VOPD3 1482 1481 s_cbranch_scc1 L_FIXUP_THREE_DWORD // If VOPD3, 3 DWORD inst 1483 1482 // Not VOP1, VOP2, VOPC, VOP3, VOP3SD, VOPD, or VOPD3. 1484 - // Might be in VOP3P, but we must ensure we are not VOP3PX2 1483 + // Check if we are in the middle of VOP3PX. 1485 1484 s_and_b32 ttmp13, ttmp14, 0xffff0000 // Bits 31:16 1485 + s_cmp_eq_u32 ttmp13, 0xcc330000 // If 31:16 = 0xcc33, this is 8 bytes past VOP3PX 1486 + s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE 1487 + s_cmp_eq_u32 ttmp13, 0xcc880000 // If 31:16 = 0xcc88, this is 8 bytes past VOP3PX 1488 + s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE 1489 + // Might be in VOP3P, but we must ensure we are not VOP3PX2 1486 1490 s_cmp_eq_u32 ttmp13, 0xcc350000 // If 31:16 = 0xcc35, this is VOP3PX2 1487 1491 s_cbranch_scc1 L_FIXUP_DONE // If VOP3PX2, no fixup needed 1488 1492 s_cmp_eq_u32 ttmp13, 0xcc3a0000 // If 31:16 = 0xcc3a, this is VOP3PX2 ··· 1547 1541 s_wait_kmcnt 0 // Wait for PC+2 and PC+3 to arrive in ttmp2 and ttmp3 1548 1542 s_mov_b32 ttmp15, ttmp3 // Move possible S_SET_VGPR_MSB into ttmp15 1549 1543 s_branch L_FIXUP_ONE_DWORD // Go to common logic that checks if it is S_SET_VGPR_MSB 1544 + 1545 + L_FIXUP_VOP3PX_MIDDLE: 1546 + s_sub_co_u32 ttmp0, ttmp0, 8 // Rewind PC 8 bytes to beginning of instruction 1547 + s_sub_co_ci_u32 ttmp1, ttmp1, 0 1548 + s_branch L_FIXUP_TWO_DWORD // 2 DWORD inst (2nd half of a 4 DWORD inst) 1550 1549 1551 1550 L_FIXUP_DONE: 1552 1551 s_wait_kmcnt 0 // Ensure load of ttmp2 and ttmp3 is done

+1

drivers/gpu/drm/amd/amdkfd/kfd_debug.c

··· 1108 1108 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); 1109 1109 device_info.capability = topo_dev->node_props.capability; 1110 1110 device_info.debug_prop = topo_dev->node_props.debug_prop; 1111 + device_info.capability2 = topo_dev->node_props.capability2; 1111 1112 1112 1113 if (exception_clear_mask) 1113 1114 pdd->exception_status &= ~exception_clear_mask;

+2 -2

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

··· 676 676 677 677 /* Temporarily release dqm lock to avoid a circular lock dependency */ 678 678 dqm_unlock(dqm); 679 - q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 679 + q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); 680 680 dqm_lock(dqm); 681 681 682 682 if (!q->mqd_mem_obj) { ··· 2002 2002 dqm->asic_ops.init_sdma_vm(dqm, q, qpd); 2003 2003 q->properties.tba_addr = qpd->tba_addr; 2004 2004 q->properties.tma_addr = qpd->tma_addr; 2005 - q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); 2005 + q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); 2006 2006 if (!q->mqd_mem_obj) { 2007 2007 retval = -ENOMEM; 2008 2008 goto out_deallocate_doorbell;

+1 -1

drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c

··· 130 130 131 131 kq->queue->device = dev; 132 132 133 - kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr->dev, 133 + kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr, 134 134 &kq->queue->properties); 135 135 if (!kq->queue->mqd_mem_obj) 136 136 goto err_allocate_mqd;

+7 -2

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c

··· 46 46 KFD_PIPE_PRIORITY_CS_HIGH 47 47 }; 48 48 49 - struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properties *q) 49 + struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q) 50 50 { 51 51 struct kfd_mem_obj *mqd_mem_obj; 52 + struct kfd_node *dev = mm->dev; 52 53 53 54 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 54 55 if (!mqd_mem_obj) ··· 62 61 return mqd_mem_obj; 63 62 } 64 63 65 - struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, 64 + struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm, 66 65 struct queue_properties *q) 67 66 { 68 67 struct kfd_mem_obj *mqd_mem_obj; 68 + struct kfd_node *dev = mm->dev; 69 69 uint64_t offset; 70 70 71 71 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); ··· 292 290 uint64_t kfd_mqd_stride(struct mqd_manager *mm, 293 291 struct queue_properties *q) 294 292 { 293 + if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0)) 294 + return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 295 + 295 296 return mm->mqd_size; 296 297 } 297 298

+3 -3

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h

··· 68 68 */ 69 69 extern int pipe_priority_map[]; 70 70 struct mqd_manager { 71 - struct kfd_mem_obj* (*allocate_mqd)(struct kfd_node *kfd, 71 + struct kfd_mem_obj* (*allocate_mqd)(struct mqd_manager *mm, 72 72 struct queue_properties *q); 73 73 74 74 void (*init_mqd)(struct mqd_manager *mm, void **mqd, ··· 153 153 uint32_t wave_state_size; 154 154 }; 155 155 156 - struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, 156 + struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, 157 157 struct queue_properties *q); 158 158 159 - struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, 159 + struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm, 160 160 struct queue_properties *q); 161 161 void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, 162 162 struct kfd_mem_obj *mqd_mem_obj);

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c

··· 73 73 m->cp_hqd_queue_priority = q->priority; 74 74 } 75 75 76 - static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, 76 + static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 77 77 struct queue_properties *q) 78 78 { 79 + struct kfd_node *kfd = mm->dev; 79 80 struct kfd_mem_obj *mqd_mem_obj; 80 81 81 82 if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd),

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c

··· 73 73 m->cp_hqd_queue_priority = q->priority; 74 74 } 75 75 76 - static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, 76 + static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 77 77 struct queue_properties *q) 78 78 { 79 + struct kfd_node *kfd = mm->dev; 79 80 struct kfd_mem_obj *mqd_mem_obj; 80 81 81 82 if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd),

+6 -19

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c

··· 99 99 m->cp_hqd_queue_priority = q->priority; 100 100 } 101 101 102 - static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 102 + static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 103 103 struct queue_properties *q) 104 104 { 105 + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 106 + struct kfd_node *node = mm->dev; 105 107 struct kfd_mem_obj *mqd_mem_obj; 106 - int size; 107 108 108 - /* 109 - * MES write to areas beyond MQD size. So allocate 110 - * 1 PAGE_SIZE memory for MQD is MES is enabled. 111 - */ 112 - if (node->kfd->shared_resources.enable_mes) 113 - size = PAGE_SIZE; 114 - else 115 - size = sizeof(struct v11_compute_mqd); 116 - 117 - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj)) 109 + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) 118 110 return NULL; 119 111 120 112 return mqd_mem_obj; ··· 118 126 { 119 127 uint64_t addr; 120 128 struct v11_compute_mqd *m; 121 - int size; 129 + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 122 130 uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff; 123 131 124 132 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; 125 133 addr = mqd_mem_obj->gpu_addr; 126 134 127 - if (mm->dev->kfd->shared_resources.enable_mes) 128 - size = PAGE_SIZE; 129 - else 130 - size = sizeof(struct v11_compute_mqd); 131 - 132 - memset(m, 0, size); 135 + memset(m, 0, mqd_size); 133 136 134 137 m->header = 0xC0310800; 135 138 m->compute_pipelinestat_enable = 1;

+6 -7

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c

··· 80 80 m->cp_hqd_queue_priority = q->priority; 81 81 } 82 82 83 - static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 83 + static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 84 84 struct queue_properties *q) 85 85 { 86 + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 87 + struct kfd_node *node = mm->dev; 86 88 struct kfd_mem_obj *mqd_mem_obj; 87 89 88 - /* 89 - * Allocate one PAGE_SIZE memory for MQD as MES writes to areas beyond 90 - * struct MQD size. 91 - */ 92 - if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj)) 90 + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) 93 91 return NULL; 94 92 95 93 return mqd_mem_obj; ··· 99 101 { 100 102 uint64_t addr; 101 103 struct v12_compute_mqd *m; 104 + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 102 105 103 106 m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr; 104 107 addr = mqd_mem_obj->gpu_addr; 105 108 106 - memset(m, 0, PAGE_SIZE); 109 + memset(m, 0, mqd_size); 107 110 108 111 m->header = 0xC0310800; 109 112 m->compute_pipelinestat_enable = 1;

+8 -24

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c

··· 32 32 #include "amdgpu_amdkfd.h" 33 33 #include "kfd_device_queue_manager.h" 34 34 35 - #define MQD_SIZE (2 * PAGE_SIZE) 36 - 37 - static uint64_t mqd_stride_v12_1(struct mqd_manager *mm, 38 - struct queue_properties *q) 39 - { 40 - if (q->type == KFD_QUEUE_TYPE_COMPUTE) 41 - return MQD_SIZE; 42 - else 43 - return PAGE_SIZE; 44 - } 45 - 46 35 static inline struct v12_1_compute_mqd *get_mqd(void *mqd) 47 36 { 48 37 return (struct v12_1_compute_mqd *)mqd; ··· 134 145 m->cp_hqd_queue_priority = q->priority; 135 146 } 136 147 137 - static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 148 + static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 138 149 struct queue_properties *q) 139 150 { 151 + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 152 + struct kfd_node *node = mm->dev; 140 153 struct kfd_mem_obj *mqd_mem_obj; 141 - unsigned int size; 142 154 143 - /* 144 - * Allocate two PAGE_SIZE memory for Compute MQD as MES writes to areas beyond 145 - * struct MQD size. Size of the Compute MQD is 1 PAGE_SIZE. 146 - * For SDMA MQD, we allocate 1 Page_size. 147 - */ 148 155 if (q->type == KFD_QUEUE_TYPE_COMPUTE) 149 - size = MQD_SIZE * NUM_XCC(node->xcc_mask); 150 - else 151 - size = PAGE_SIZE; 156 + mqd_size *= NUM_XCC(node->xcc_mask); 152 157 153 - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj)) 158 + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) 154 159 return NULL; 155 160 156 161 return mqd_mem_obj; ··· 156 173 { 157 174 uint64_t addr; 158 175 struct v12_1_compute_mqd *m; 176 + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 159 177 160 178 m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr; 161 179 addr = mqd_mem_obj->gpu_addr; 162 180 163 - memset(m, 0, MQD_SIZE); 181 + memset(m, 0, mqd_size); 164 182 165 183 m->header = 0xC0310800; 166 184 m->compute_pipelinestat_enable = 1; ··· 664 680 mqd->is_occupied = kfd_is_occupied_cp; 665 681 mqd->mqd_size = sizeof(struct v12_1_compute_mqd); 666 682 mqd->get_wave_state = get_wave_state_v12_1; 667 - mqd->mqd_stride = mqd_stride_v12_1; 683 + mqd->mqd_stride = kfd_mqd_stride; 668 684 #if defined(CONFIG_DEBUG_FS) 669 685 mqd->debugfs_show_mqd = debugfs_show_mqd; 670 686 #endif

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

··· 120 120 } 121 121 } 122 122 123 - static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 123 + static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 124 124 struct queue_properties *q) 125 125 { 126 126 int retval; 127 + struct kfd_node *node = mm->dev; 127 128 struct kfd_mem_obj *mqd_mem_obj = NULL; 128 129 129 130 /* For V9 only, due to a HW bug, the control stack of a user mode

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c

··· 76 76 m->cp_hqd_queue_priority = q->priority; 77 77 } 78 78 79 - static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, 79 + static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 80 80 struct queue_properties *q) 81 81 { 82 + struct kfd_node *kfd = mm->dev; 82 83 struct kfd_mem_obj *mqd_mem_obj; 83 84 84 85 if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd),

+1 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 11867 11867 * check tiling flags when the FB doesn't have a modifier. 11868 11868 */ 11869 11869 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 11870 - if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { 11870 + if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { 11871 11871 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; 11872 11872 } else if (adev->family >= AMDGPU_FAMILY_AI) { 11873 11873 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;

+2 -2

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

··· 278 278 if (!dcc->enable) 279 279 return 0; 280 280 281 - if (adev->family < AMDGPU_FAMILY_GC_12_0_0 && 281 + if (adev->family != AMDGPU_FAMILY_GC_12_0_0 && 282 282 format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 283 283 return -EINVAL; 284 284 ··· 901 901 upper_32_bits(chroma_addr); 902 902 } 903 903 904 - if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { 904 + if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { 905 905 ret = amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(adev, afb, format, 906 906 rotation, plane_size, 907 907 tiling_info, dcc,

+1 -1

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 7506 7506 .stream = stream, 7507 7507 .stream_update = stream_update, 7508 7508 .update_v3 = version >= DCN_VERSION_4_01 || version == DCN_VERSION_3_2 || version == DCN_VERSION_3_21, 7509 - .do_clear_update_flags = version >= DCN_VERSION_3_2 || version == DCN_VERSION_3_01, 7509 + .do_clear_update_flags = version >= DCN_VERSION_1_0, 7510 7510 }; 7511 7511 7512 7512 return scratch;

+13

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

··· 515 515 } 516 516 } 517 517 518 + /* apply manual trigger */ 519 + int i; 520 + 521 + for (i = 0; i < dc->res_pool->pipe_count; i++) { 522 + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 523 + 524 + /* trigger event on first pipe with current stream */ 525 + if (stream == pipe_ctx->stream) { 526 + pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); 527 + break; 528 + } 529 + } 530 + 518 531 return true; 519 532 } 520 533

+2 -1

drivers/gpu/drm/amd/display/dc/dc.h

··· 63 63 struct dcn_optc_reg_state; 64 64 struct dcn_dccg_reg_state; 65 65 66 - #define DC_VER "3.2.366" 66 + #define DC_VER "3.2.367" 67 67 68 68 /** 69 69 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC ··· 1210 1210 bool disable_deferred_minimal_transitions; 1211 1211 unsigned int num_fast_flips_to_steady_state_override; 1212 1212 bool enable_dmu_recovery; 1213 + unsigned int force_vmin_threshold; 1213 1214 }; 1214 1215 1215 1216

+18

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

··· 944 944 hubbub1->debug_test_index_pstate = 0xB; 945 945 } 946 946 947 + void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv) 948 + { 949 + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); 950 + 951 + if (refdiv > 0) 952 + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, refdiv); 953 + 954 + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, enable ? 1 : 0); 955 + } 956 + 957 + void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value) 958 + { 959 + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); 960 + 961 + REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, fb_base_value); 962 + REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, fb_offset_value); 963 + } 964 +

+4

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

··· 519 519 unsigned int refclk_mhz, 520 520 bool safe_to_lower); 521 521 522 + void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv); 523 + 524 + void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value); 525 + 522 526 #endif

+2 -3

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

··· 2678 2678 uint32_t fb_base_value; 2679 2679 uint32_t fb_offset_value; 2680 2680 2681 - REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); 2682 - REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); 2681 + dcn10_hubbub_read_fb_aperture(hws->ctx->dc->res_pool->hubbub, &fb_base_value, &fb_offset_value); 2683 2682 2684 2683 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 2685 2684 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); ··· 3473 3474 triggers, params->num_frames); 3474 3475 } 3475 3476 3476 - static void dcn10_config_stereo_parameters( 3477 + void dcn10_config_stereo_parameters( 3477 3478 struct dc_stream_state *stream, struct crtc_stereo_flags *flags) 3478 3479 { 3479 3480 enum view_3d_format view_format = stream->view_format;

+2

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

··· 217 217 void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx, 218 218 struct dc_plane_state *plane_state, 219 219 bool clear_tiling); 220 + void dcn10_config_stereo_parameters( 221 + struct dc_stream_state *stream, struct crtc_stereo_flags *flags); 220 222 221 223 #endif /* __DC_HWSS_DCN10_H__ */

+12 -4

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

··· 46 46 #include "dchubbub.h" 47 47 #include "reg_helper.h" 48 48 #include "dcn10/dcn10_cm_common.h" 49 + #include "dcn10/dcn10_hubbub.h" 49 50 #include "vm_helper.h" 50 51 #include "dccg.h" 51 52 #include "dc_dmub_srv.h" ··· 3059 3058 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 3060 3059 } 3061 3060 } else { 3062 - if (dccg->funcs->enable_symclk_se) 3063 - dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, 3061 + if (dccg->funcs->enable_symclk_se && link_enc) { 3062 + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA 3063 + && link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN 3064 + && !link->link_status.link_active) { 3065 + if (dccg->funcs->disable_symclk_se) 3066 + dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, 3064 3067 link_enc->transmitter - TRANSMITTER_UNIPHY_A); 3068 + } else 3069 + dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, 3070 + link_enc->transmitter - TRANSMITTER_UNIPHY_A); 3071 + } 3065 3072 } 3066 3073 3067 3074 if (dc->res_pool->dccg->funcs->set_pixel_rate_div) ··· 3154 3145 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 3155 3146 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 3156 3147 3157 - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 3158 - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 3148 + dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); 3159 3149 if (REG(REFCLK_CNTL)) 3160 3150 REG_WRITE(REFCLK_CNTL, 0); 3161 3151 //

+1

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

··· 39 39 #include "dccg.h" 40 40 #include "clk_mgr.h" 41 41 #include "reg_helper.h" 42 + #include "dcn10/dcn10_hubbub.h" 42 43 43 44 #define CTX \ 44 45 hws->ctx

+1

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

··· 36 36 #include "dcn10/dcn10_cm_common.h" 37 37 #include "dcn30/dcn30_cm_common.h" 38 38 #include "reg_helper.h" 39 + #include "dcn10/dcn10_hubbub.h" 39 40 #include "abm.h" 40 41 #include "clk_mgr.h" 41 42 #include "hubp.h"

+1

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

··· 32 32 #include "dce/dce_hwseq.h" 33 33 #include "clk_mgr.h" 34 34 #include "reg_helper.h" 35 + #include "dcn10/dcn10_hubbub.h" 35 36 #include "abm.h" 36 37 #include "hubp.h" 37 38 #include "dchubbub.h"

+1

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

··· 32 32 #include "dce/dce_hwseq.h" 33 33 #include "clk_mgr.h" 34 34 #include "reg_helper.h" 35 + #include "dcn10/dcn10_hubbub.h" 35 36 #include "abm.h" 36 37 #include "hubp.h" 37 38 #include "dchubbub.h"

-2

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

··· 2022 2022 2023 2023 dcn20_merge_pipes_for_validate(dc, context); 2024 2024 2025 - DC_FP_START(); 2026 2025 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); 2027 - DC_FP_END(); 2028 2026 2029 2027 *pipe_cnt_out = pipe_cnt; 2030 2028

-2

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

··· 785 785 786 786 dcn20_merge_pipes_for_validate(dc, context); 787 787 788 - DC_FP_START(); 789 788 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); 790 - DC_FP_END(); 791 789 792 790 *pipe_cnt_out = pipe_cnt; 793 791

+1 -1

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

··· 1772 1772 return dpm_level; 1773 1773 } 1774 1774 1775 - static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) 1775 + unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) 1776 1776 { 1777 1777 return pipe_ctx->global_sync.dcn4x.vstartup_lines; 1778 1778 }

+2

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

··· 28 28 29 29 void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); 30 30 31 + unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx); 32 + 31 33 /* Following are definitions for run time init of reg offsets */ 32 34 33 35 /* HUBP */

+49 -6

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

··· 139 139 */ 140 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 141 142 + /** 143 + * 144 + * dirty rect cmd version legacy 145 + */ 146 + #define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0 147 + /** 148 + * dirty rect cmd version with multi edp support 149 + */ 150 + #define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1 151 + /** 152 + * dirty rect cmd version with external monitor support 153 + */ 154 + #define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2 155 + 156 + /** 157 + * 158 + * Cursor update cmd version legacy 159 + */ 160 + #define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0 161 + /** 162 + * Cursor update cmd version with multi edp support 163 + */ 164 + #define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1 165 + /** 166 + * Cursor update cmd version with external monitor support 167 + */ 168 + #define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2 142 169 143 170 /** 144 171 * ABM control version legacy ··· 3956 3929 */ 3957 3930 union dmub_psr_su_debug_flags debug_flags; 3958 3931 /** 3959 - * OTG HW instance. 3932 + * Pipe index. 3960 3933 */ 3961 3934 uint8_t pipe_idx; 3962 3935 /** ··· 3964 3937 */ 3965 3938 uint8_t dirty_rect_count; 3966 3939 /** 3967 - * PSR control version. 3940 + * dirty rects cmd version. 3968 3941 */ 3969 3942 uint8_t cmd_version; 3970 3943 /** ··· 3973 3946 * Currently the support is only for 0 or 1 3974 3947 */ 3975 3948 uint8_t panel_inst; 3949 + /** 3950 + * OTG HW instance 3951 + */ 3952 + uint8_t otg_inst; 3953 + /** 3954 + * Padding for 4 byte alignment 3955 + */ 3956 + uint8_t padding[3]; 3976 3957 }; 3977 3958 3978 3959 /** ··· 4106 4071 */ 4107 4072 uint8_t enable; 4108 4073 /** 4109 - * OTG HW instance. 4074 + * Pipe index. 4110 4075 */ 4111 4076 uint8_t pipe_idx; 4112 4077 /** 4113 - * PSR control version. 4078 + * Cursor update cmd version. 4114 4079 */ 4115 4080 uint8_t cmd_version; 4116 4081 /** ··· 4124 4089 * Registers contains Hubp & Dpp modules 4125 4090 */ 4126 4091 struct dmub_cursor_position_cfg position_cfg; 4092 + /** 4093 + * OTG HW instance 4094 + */ 4095 + uint8_t otg_inst; 4096 + /** 4097 + * Padding for 4 byte alignment 4098 + */ 4099 + uint8_t padding[3]; 4127 4100 }; 4128 4101 4129 4102 struct dmub_cmd_update_cursor_payload1 { ··· 6672 6629 */ 6673 6630 uint8_t su_y_granularity; 6674 6631 /** 6675 - * @pad: Align structure to 4 byte boundary. 6632 + * @main_link_activity_option: Indicates main link activity option selected 6676 6633 */ 6677 - uint8_t pad; 6634 + uint8_t main_link_activity_option; 6678 6635 }; 6679 6636 6680 6637 /**

+3

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

··· 419 419 boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; 420 420 boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; 421 421 boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; 422 + boot_options.bits.bootcrc_en_at_preos = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_preos; 423 + boot_options.bits.bootcrc_en_at_S0i3 = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_S0i3; 424 + boot_options.bits.bootcrc_boot_mode = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_boot_mode; 422 425 423 426 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 424 427 }

+1

drivers/gpu/drm/amd/display/include/dpcd_defs.h

··· 224 224 #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE 0x379 225 225 #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A 226 226 #define DP_SINK_EMISSION_RATE 0x37E 227 + #define DP_SINK_PR_FRAME_SKIP_COUNT 0x337 227 228 228 229 /* Remove once drm_dp_helper.h is updated upstream */ 229 230 #ifndef DP_TOTAL_LTTPR_CNT

+4 -2

drivers/gpu/drm/amd/include/mes_v12_api_def.h

··· 492 492 union MES_API_HEADER header; 493 493 /* false - suspend all gangs; true - specific gang */ 494 494 struct { 495 - uint32_t suspend_all_gangs : 1; 496 - uint32_t reserved : 31; 495 + uint32_t suspend_all_gangs : 1; // suspend all compute gangs (can be set together with suspend_all_sdma_gangs) 496 + uint32_t query_status : 1; 497 + uint32_t suspend_all_sdma_gangs : 1; // suspend all sdma gangs (can be set together with suspend_all_gangs) 498 + uint32_t reserved : 29; 497 499 }; 498 500 /* gang_context_addr is valid only if suspend_all = false */ 499 501

+4 -3

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

··· 80 80 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; 81 81 bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; 82 82 83 + mutex_lock(&adev->pm.mutex); 84 + 83 85 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && 84 86 (!is_vcn || adev->vcn.num_vcn_inst == 1)) { 85 87 dev_dbg(adev->dev, "IP block%d already in the target %s state!", 86 88 block_type, gate ? "gate" : "ungate"); 87 - return 0; 89 + goto out_unlock; 88 90 } 89 - 90 - mutex_lock(&adev->pm.mutex); 91 91 92 92 switch (block_type) { 93 93 case AMD_IP_BLOCK_TYPE_UVD: ··· 115 115 if (!ret) 116 116 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); 117 117 118 + out_unlock: 118 119 mutex_unlock(&adev->pm.mutex); 119 120 120 121 return ret;

+11 -25

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

··· 619 619 struct smu_context *smu = adev->powerplay.pp_handle; 620 620 int ret = -EOPNOTSUPP; 621 621 622 + if (!smu) 623 + return ret; 624 + 622 625 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) 623 626 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); 624 627 ··· 691 688 return ret; 692 689 } 693 690 694 - static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 691 + static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) 695 692 { 696 - struct smu_feature *feature = &smu->smu_feature; 697 - uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 698 - int ret = 0; 699 - 700 693 /* 701 694 * With SCPM enabled, the allowed featuremasks setting(via 702 695 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. ··· 701 702 * such scenario. 702 703 */ 703 704 if (smu->adev->scpm_enabled) { 704 - bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 705 + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 705 706 return 0; 706 707 } 707 708 708 - bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 709 + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 709 710 710 - ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 711 - SMU_FEATURE_MAX/32); 712 - if (ret) 713 - return ret; 714 - 715 - bitmap_or(feature->allowed, feature->allowed, 716 - (unsigned long *)allowed_feature_mask, 717 - feature->feature_num); 718 - 719 - return ret; 711 + return smu_init_allowed_features(smu); 720 712 } 721 713 722 714 static int smu_set_funcs(struct amdgpu_device *adev) ··· 1355 1365 int i, ret; 1356 1366 1357 1367 smu->pool_size = adev->pm.smu_prv_buffer_size; 1358 - smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1359 - bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1360 - bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1368 + smu_feature_init(smu, SMU_FEATURE_MAX); 1361 1369 1362 1370 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1363 1371 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); ··· 1644 1656 1645 1657 static int smu_smc_hw_setup(struct smu_context *smu) 1646 1658 { 1647 - struct smu_feature *feature = &smu->smu_feature; 1648 1659 struct amdgpu_device *adev = smu->adev; 1649 1660 uint8_t pcie_gen = 0, pcie_width = 0; 1650 1661 uint64_t features_supported; ··· 1806 1819 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1807 1820 return ret; 1808 1821 } 1809 - bitmap_copy(feature->supported, 1810 - (unsigned long *)&features_supported, 1811 - feature->feature_num); 1822 + smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, 1823 + (unsigned long *)&features_supported); 1812 1824 1813 1825 if (!smu_is_dpm_running(smu)) 1814 1826 dev_info(adev->dev, "dpm has been disabled\n"); ··· 1938 1952 if (!smu->pm_enabled) 1939 1953 return 0; 1940 1954 1941 - ret = smu_get_driver_allowed_feature_mask(smu); 1955 + ret = smu_init_driver_allowed_feature_mask(smu); 1942 1956 if (ret) 1943 1957 return ret; 1944 1958

+169 -6

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

··· 472 472 }; 473 473 474 474 #define SMU_FEATURE_MAX (64) 475 + 476 + struct smu_feature_bits { 477 + DECLARE_BITMAP(bits, SMU_FEATURE_MAX); 478 + }; 479 + 480 + enum smu_feature_list { 481 + SMU_FEATURE_LIST_SUPPORTED, 482 + SMU_FEATURE_LIST_ALLOWED, 483 + SMU_FEATURE_LIST_MAX, 484 + }; 485 + 475 486 struct smu_feature { 476 487 uint32_t feature_num; 477 - DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 478 - DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 488 + struct smu_feature_bits bits[SMU_FEATURE_LIST_MAX]; 479 489 }; 480 490 481 491 struct smu_clocks { ··· 812 802 int (*run_btc)(struct smu_context *smu); 813 803 814 804 /** 815 - * @get_allowed_feature_mask: Get allowed feature mask. 816 - * &feature_mask: Array to store feature mask. 817 - * &num: Elements in &feature_mask. 805 + * @init_allowed_features: Initialize allowed features bitmap. 806 + * Directly sets allowed features using smu_feature wrapper functions. 818 807 */ 819 - int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 808 + int (*init_allowed_features)(struct smu_context *smu); 820 809 821 810 /** 822 811 * @get_current_power_state: Get the current power state. ··· 1983 1974 1984 1975 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id); 1985 1976 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id); 1977 + 1978 + static inline bool smu_feature_bits_is_set(const struct smu_feature_bits *bits, 1979 + unsigned int bit) 1980 + { 1981 + if (bit >= SMU_FEATURE_MAX) 1982 + return false; 1983 + 1984 + return test_bit(bit, bits->bits); 1985 + } 1986 + 1987 + static inline void smu_feature_bits_set_bit(struct smu_feature_bits *bits, 1988 + unsigned int bit) 1989 + { 1990 + if (bit < SMU_FEATURE_MAX) 1991 + __set_bit(bit, bits->bits); 1992 + } 1993 + 1994 + static inline void smu_feature_bits_clear_bit(struct smu_feature_bits *bits, 1995 + unsigned int bit) 1996 + { 1997 + if (bit < SMU_FEATURE_MAX) 1998 + __clear_bit(bit, bits->bits); 1999 + } 2000 + 2001 + static inline void smu_feature_bits_clearall(struct smu_feature_bits *bits) 2002 + { 2003 + bitmap_zero(bits->bits, SMU_FEATURE_MAX); 2004 + } 2005 + 2006 + static inline void smu_feature_bits_fill(struct smu_feature_bits *bits) 2007 + { 2008 + bitmap_fill(bits->bits, SMU_FEATURE_MAX); 2009 + } 2010 + 2011 + static inline bool 2012 + smu_feature_bits_test_mask(const struct smu_feature_bits *bits, 2013 + const unsigned long *mask) 2014 + { 2015 + return bitmap_intersects(bits->bits, mask, SMU_FEATURE_MAX); 2016 + } 2017 + 2018 + static inline void smu_feature_bits_from_arr32(struct smu_feature_bits *bits, 2019 + const uint32_t *arr, 2020 + unsigned int nbits) 2021 + { 2022 + bitmap_from_arr32(bits->bits, arr, nbits); 2023 + } 2024 + 2025 + static inline void 2026 + smu_feature_bits_to_arr32(const struct smu_feature_bits *bits, uint32_t *arr, 2027 + unsigned int nbits) 2028 + { 2029 + bitmap_to_arr32(arr, bits->bits, nbits); 2030 + } 2031 + 2032 + static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits, 2033 + unsigned int nbits) 2034 + { 2035 + return bitmap_empty(bits->bits, nbits); 2036 + } 2037 + 2038 + static inline void smu_feature_bits_copy(struct smu_feature_bits *dst, 2039 + const unsigned long *src, 2040 + unsigned int nbits) 2041 + { 2042 + bitmap_copy(dst->bits, src, nbits); 2043 + } 2044 + 2045 + static inline struct smu_feature_bits * 2046 + __smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list) 2047 + { 2048 + if (unlikely(list >= SMU_FEATURE_LIST_MAX)) { 2049 + dev_warn(smu->adev->dev, "Invalid feature list: %d\n", list); 2050 + return &smu->smu_feature.bits[SMU_FEATURE_LIST_SUPPORTED]; 2051 + } 2052 + 2053 + return &smu->smu_feature.bits[list]; 2054 + } 2055 + 2056 + static inline bool smu_feature_list_is_set(struct smu_context *smu, 2057 + enum smu_feature_list list, 2058 + unsigned int bit) 2059 + { 2060 + if (bit >= smu->smu_feature.feature_num) 2061 + return false; 2062 + 2063 + return smu_feature_bits_is_set(__smu_feature_get_list(smu, list), bit); 2064 + } 2065 + 2066 + static inline void smu_feature_list_set_bit(struct smu_context *smu, 2067 + enum smu_feature_list list, 2068 + unsigned int bit) 2069 + { 2070 + if (bit >= smu->smu_feature.feature_num) 2071 + return; 2072 + 2073 + smu_feature_bits_set_bit(__smu_feature_get_list(smu, list), bit); 2074 + } 2075 + 2076 + static inline void smu_feature_list_clear_bit(struct smu_context *smu, 2077 + enum smu_feature_list list, 2078 + unsigned int bit) 2079 + { 2080 + if (bit >= smu->smu_feature.feature_num) 2081 + return; 2082 + 2083 + smu_feature_bits_clear_bit(__smu_feature_get_list(smu, list), bit); 2084 + } 2085 + 2086 + static inline void smu_feature_list_set_all(struct smu_context *smu, 2087 + enum smu_feature_list list) 2088 + { 2089 + smu_feature_bits_fill(__smu_feature_get_list(smu, list)); 2090 + } 2091 + 2092 + static inline void smu_feature_list_clear_all(struct smu_context *smu, 2093 + enum smu_feature_list list) 2094 + { 2095 + smu_feature_bits_clearall(__smu_feature_get_list(smu, list)); 2096 + } 2097 + 2098 + static inline bool smu_feature_list_is_empty(struct smu_context *smu, 2099 + enum smu_feature_list list) 2100 + { 2101 + return smu_feature_bits_empty(__smu_feature_get_list(smu, list), 2102 + smu->smu_feature.feature_num); 2103 + } 2104 + 2105 + static inline void smu_feature_list_set_bits(struct smu_context *smu, 2106 + enum smu_feature_list dst_list, 2107 + const unsigned long *src) 2108 + { 2109 + smu_feature_bits_copy(__smu_feature_get_list(smu, dst_list), src, 2110 + smu->smu_feature.feature_num); 2111 + } 2112 + 2113 + static inline void smu_feature_list_to_arr32(struct smu_context *smu, 2114 + enum smu_feature_list list, 2115 + uint32_t *arr) 2116 + { 2117 + smu_feature_bits_to_arr32(__smu_feature_get_list(smu, list), arr, 2118 + smu->smu_feature.feature_num); 2119 + } 2120 + 2121 + static inline void smu_feature_init(struct smu_context *smu, int feature_num) 2122 + { 2123 + if (!feature_num || smu->smu_feature.feature_num != 0) 2124 + return; 2125 + 2126 + smu->smu_feature.feature_num = feature_num; 2127 + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_SUPPORTED); 2128 + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 2129 + } 2130 + 1986 2131 #endif

+1

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

··· 55 55 #define SMUQ10_TO_UINT(x) ((x) >> 10) 56 56 #define SMUQ10_FRAC(x) ((x) & 0x3ff) 57 57 #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200)) 58 + #define SMU_V13_SOFT_FREQ_ROUND(x) ((x) + 1) 58 59 59 60 extern const int pmfw_decoded_link_speed[5]; 60 61 extern const int pmfw_decoded_link_width[7];

+1

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

··· 56 56 57 57 #define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx]) 58 58 #define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx]) 59 + #define SMU_V14_SOFT_FREQ_ROUND(x) ((x) + 1) 59 60 60 61 struct smu_14_0_max_sustainable_clocks { 61 62 uint32_t display_clock;

+3 -8

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

··· 345 345 } 346 346 347 347 static int 348 - arcturus_get_allowed_feature_mask(struct smu_context *smu, 349 - uint32_t *feature_mask, uint32_t num) 348 + arcturus_init_allowed_features(struct smu_context *smu) 350 349 { 351 - if (num > 2) 352 - return -EINVAL; 353 - 354 - /* pptable will handle the features to enable */ 355 - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 350 + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 356 351 357 352 return 0; 358 353 } ··· 1872 1877 1873 1878 static const struct pptable_funcs arcturus_ppt_funcs = { 1874 1879 /* init dpm */ 1875 - .get_allowed_feature_mask = arcturus_get_allowed_feature_mask, 1880 + .init_allowed_features = arcturus_init_allowed_features, 1876 1881 /* btc */ 1877 1882 .run_btc = arcturus_run_btc, 1878 1883 /* dpm/clk tables */

+42 -48

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

··· 275 275 } 276 276 277 277 static int 278 - navi10_get_allowed_feature_mask(struct smu_context *smu, 279 - uint32_t *feature_mask, uint32_t num) 278 + navi10_init_allowed_features(struct smu_context *smu) 280 279 { 281 280 struct amdgpu_device *adev = smu->adev; 282 281 283 - if (num > 2) 284 - return -EINVAL; 282 + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 285 283 286 - memset(feature_mask, 0, sizeof(uint32_t) * num); 287 - 288 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 289 - | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 290 - | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 291 - | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 292 - | FEATURE_MASK(FEATURE_PPT_BIT) 293 - | FEATURE_MASK(FEATURE_TDC_BIT) 294 - | FEATURE_MASK(FEATURE_GFX_EDC_BIT) 295 - | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) 296 - | FEATURE_MASK(FEATURE_VR0HOT_BIT) 297 - | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 298 - | FEATURE_MASK(FEATURE_THERMAL_BIT) 299 - | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) 300 - | FEATURE_MASK(FEATURE_DS_LCLK_BIT) 301 - | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 302 - | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 303 - | FEATURE_MASK(FEATURE_BACO_BIT) 304 - | FEATURE_MASK(FEATURE_GFX_SS_BIT) 305 - | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 306 - | FEATURE_MASK(FEATURE_FW_CTF_BIT) 307 - | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT) 308 - | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT); 284 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT); 285 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); 286 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT); 287 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); 288 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT); 289 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT); 290 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_EDC_BIT); 291 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_PLUS_BIT); 292 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); 293 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); 294 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT); 295 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_LED_DISPLAY_BIT); 296 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); 297 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT); 298 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); 299 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); 300 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT); 301 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT); 302 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); 303 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT); 304 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TEMP_DEPENDENT_VMIN_BIT); 309 305 310 306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 311 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 307 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); 312 308 313 309 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 314 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 310 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); 315 311 316 312 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 317 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 313 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT); 318 314 319 315 if (adev->pm.pp_feature & PP_ULV_MASK) 320 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 316 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); 321 317 322 318 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 323 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 319 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); 324 320 325 321 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 326 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 322 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); 327 323 328 324 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 329 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 325 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT); 330 326 331 327 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 332 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 328 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT); 333 329 334 330 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) 335 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); 331 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VCN_PG_BIT); 336 332 337 333 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 338 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); 334 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_JPEG_PG_BIT); 339 335 340 336 if (smu->dc_controlled_by_gpio) 341 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 337 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT); 342 338 343 339 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 344 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 340 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); 345 341 346 - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ 347 342 if (!(is_asic_secure(smu) && 348 343 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 349 344 (adev->rev_id == 0)) && 350 - (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) 351 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 352 - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 353 - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 345 + (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { 346 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); 347 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT); 348 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); 349 + } 354 350 355 - /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ 356 351 if (is_asic_secure(smu) && 357 352 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && 358 353 (adev->rev_id == 0)) 359 - *(uint64_t *)feature_mask &= 360 - ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 354 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); 361 355 362 356 return 0; 363 357 } ··· 3271 3277 } 3272 3278 3273 3279 static const struct pptable_funcs navi10_ppt_funcs = { 3274 - .get_allowed_feature_mask = navi10_get_allowed_feature_mask, 3280 + .init_allowed_features = navi10_init_allowed_features, 3275 3281 .set_default_dpm_table = navi10_set_default_dpm_table, 3276 3282 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, 3277 3283 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,

+42 -45

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

··· 276 276 }; 277 277 278 278 static int 279 - sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, 280 - uint32_t *feature_mask, uint32_t num) 279 + sienna_cichlid_init_allowed_features(struct smu_context *smu) 281 280 { 282 281 struct amdgpu_device *adev = smu->adev; 283 282 284 - if (num > 2) 285 - return -EINVAL; 283 + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 286 284 287 - memset(feature_mask, 0, sizeof(uint32_t) * num); 288 - 289 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 290 - | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) 291 - | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 292 - | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 293 - | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 294 - | FEATURE_MASK(FEATURE_DS_FCLK_BIT) 295 - | FEATURE_MASK(FEATURE_DS_UCLK_BIT) 296 - | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 297 - | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) 298 - | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 299 - | FEATURE_MASK(FEATURE_GFX_SS_BIT) 300 - | FEATURE_MASK(FEATURE_VR0HOT_BIT) 301 - | FEATURE_MASK(FEATURE_PPT_BIT) 302 - | FEATURE_MASK(FEATURE_TDC_BIT) 303 - | FEATURE_MASK(FEATURE_BACO_BIT) 304 - | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 305 - | FEATURE_MASK(FEATURE_FW_CTF_BIT) 306 - | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 307 - | FEATURE_MASK(FEATURE_THERMAL_BIT) 308 - | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 285 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT); 286 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT); 287 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); 288 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); 289 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT); 290 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT); 291 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_UCLK_BIT); 292 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); 293 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT); 294 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT); 295 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT); 296 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); 297 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT); 298 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT); 299 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); 300 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT); 301 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); 302 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); 303 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT); 304 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT); 309 305 310 306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 311 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 312 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); 307 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); 308 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_GPO_BIT); 313 309 } 314 310 315 311 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && 316 312 (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) && 317 313 !(adev->flags & AMD_IS_APU)) 318 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); 314 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_DCS_BIT); 319 315 320 - if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) 321 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 322 - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 323 - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 316 + if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { 317 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); 318 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT); 319 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); 320 + } 324 321 325 322 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 326 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 323 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); 327 324 328 325 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 329 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 326 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT); 330 327 331 328 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 332 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 329 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); 333 330 334 331 if (adev->pm.pp_feature & PP_ULV_MASK) 335 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 332 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); 336 333 337 334 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 338 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 335 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); 339 336 340 337 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 341 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 338 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); 342 339 343 340 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 344 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 341 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT); 345 342 346 343 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 347 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 344 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT); 348 345 349 346 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || 350 347 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 351 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); 348 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_PG_BIT); 352 349 353 350 if (smu->dc_controlled_by_gpio) 354 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 351 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT); 355 352 356 353 if (amdgpu_device_should_use_aspm(adev)) 357 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 354 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); 358 355 359 356 return 0; 360 357 } ··· 3082 3085 } 3083 3086 3084 3087 static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 3085 - .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, 3088 + .init_allowed_features = sienna_cichlid_init_allowed_features, 3086 3089 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, 3087 3090 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, 3088 3091 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,

+3 -2

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

··· 750 750 int ret = 0; 751 751 uint32_t feature_mask[2]; 752 752 753 - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) { 753 + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 754 + feature->feature_num < 64) { 754 755 ret = -EINVAL; 755 756 goto failed; 756 757 } 757 758 758 - bitmap_to_arr32(feature_mask, feature->allowed, 64); 759 + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); 759 760 760 761 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 761 762 feature_mask[1], NULL);

+3 -8

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

··· 329 329 return smu_v13_0_init_smc_tables(smu); 330 330 } 331 331 332 - static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, 333 - uint32_t *feature_mask, uint32_t num) 332 + static int aldebaran_init_allowed_features(struct smu_context *smu) 334 333 { 335 - if (num > 2) 336 - return -EINVAL; 337 - 338 - /* pptable will handle the features to enable */ 339 - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 334 + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 340 335 341 336 return 0; 342 337 } ··· 1962 1967 1963 1968 static const struct pptable_funcs aldebaran_ppt_funcs = { 1964 1969 /* init dpm */ 1965 - .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, 1970 + .init_allowed_features = aldebaran_init_allowed_features, 1966 1971 /* dpm/clk tables */ 1967 1972 .set_default_dpm_table = aldebaran_set_default_dpm_table, 1968 1973 .populate_umd_state_clk = aldebaran_populate_umd_state_clk,

+3 -2

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

··· 761 761 int ret = 0; 762 762 uint32_t feature_mask[2]; 763 763 764 - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || 764 + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 765 765 feature->feature_num < 64) 766 766 return -EINVAL; 767 767 768 - bitmap_to_arr32(feature_mask, feature->allowed, 64); 768 + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); 769 769 770 770 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 771 771 feature_mask[1], NULL); ··· 1554 1554 return clk_id; 1555 1555 1556 1556 if (max > 0) { 1557 + max = SMU_V13_SOFT_FREQ_ROUND(max); 1557 1558 if (automatic) 1558 1559 param = (uint32_t)((clk_id << 16) | 0xffff); 1559 1560 else

+15 -20

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

··· 287 287 }; 288 288 289 289 static int 290 - smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, 291 - uint32_t *feature_mask, uint32_t num) 290 + smu_v13_0_0_init_allowed_features(struct smu_context *smu) 292 291 { 293 292 struct amdgpu_device *adev = smu->adev; 294 293 295 - if (num > 2) 296 - return -EINVAL; 297 - 298 - memset(feature_mask, 0xff, sizeof(uint32_t) * num); 294 + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 299 295 300 296 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) { 301 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 302 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); 297 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); 298 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT); 303 299 } 304 300 305 301 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || 306 302 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 307 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 303 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT); 308 304 309 305 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) 310 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 306 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); 311 307 312 - /* PMFW 78.58 contains a critical fix for gfxoff feature */ 313 308 if ((smu->smc_fw_version < 0x004e3a00) || 314 309 !(adev->pm.pp_feature & PP_GFXOFF_MASK)) 315 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); 310 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); 316 311 317 312 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { 318 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 319 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 320 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 313 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); 314 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT); 315 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT); 321 316 } 322 317 323 318 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) 324 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 319 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); 325 320 326 321 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { 327 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); 328 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); 322 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); 323 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); 329 324 } 330 325 331 326 if (!(adev->pm.pp_feature & PP_ULV_MASK)) 332 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); 327 + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); 333 328 334 329 return 0; 335 330 } ··· 3125 3130 } 3126 3131 3127 3132 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { 3128 - .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, 3133 + .init_allowed_features = smu_v13_0_0_init_allowed_features, 3129 3134 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, 3130 3135 .i2c_init = smu_v13_0_0_i2c_control_init, 3131 3136 .i2c_fini = smu_v13_0_0_i2c_control_fini,

+3 -9

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

··· 742 742 return smu_v13_0_fini_smc_tables(smu); 743 743 } 744 744 745 - static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu, 746 - uint32_t *feature_mask, 747 - uint32_t num) 745 + static int smu_v13_0_6_init_allowed_features(struct smu_context *smu) 748 746 { 749 - if (num > 2) 750 - return -EINVAL; 751 - 752 - /* pptable will handle the features to enable */ 753 - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 747 + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 754 748 755 749 return 0; 756 750 } ··· 3830 3836 3831 3837 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { 3832 3838 /* init dpm */ 3833 - .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask, 3839 + .init_allowed_features = smu_v13_0_6_init_allowed_features, 3834 3840 /* dpm/clk tables */ 3835 3841 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table, 3836 3842 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,

+37 -41

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

··· 265 265 }; 266 266 267 267 static int 268 - smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, 269 - uint32_t *feature_mask, uint32_t num) 268 + smu_v13_0_7_init_allowed_features(struct smu_context *smu) 270 269 { 271 270 struct amdgpu_device *adev = smu->adev; 272 271 273 - if (num > 2) 274 - return -EINVAL; 272 + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 275 273 276 - memset(feature_mask, 0, sizeof(uint32_t) * num); 277 - 278 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); 274 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DATA_READ_BIT); 279 275 280 276 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 281 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 282 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); 283 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); 277 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); 278 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT); 279 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); 284 280 } 285 281 286 282 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 287 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 283 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); 288 284 289 285 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { 290 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 291 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); 292 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 293 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 286 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); 287 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT); 288 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT); 289 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT); 294 290 } 295 291 296 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 292 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); 297 293 298 294 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 299 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 295 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); 300 296 301 297 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 302 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 298 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); 303 299 304 300 if (adev->pm.pp_feature & PP_ULV_MASK) 305 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 301 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); 306 302 307 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 308 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); 309 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); 310 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); 311 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); 312 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT); 313 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT); 314 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); 315 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); 316 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT); 317 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 318 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); 319 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); 320 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); 321 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT); 322 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); 323 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT); 324 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); 325 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); 303 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); 304 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); 305 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_BIT); 306 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_VCN_BIT); 307 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT); 308 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT); 309 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THROTTLERS_BIT); 310 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); 311 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); 312 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); 313 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); 314 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); 315 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_TEMP_READ_BIT); 316 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); 317 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_MPCLK_DS_BIT); 318 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_MPCLK_DS_BIT); 319 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_PCC_DFLL_BIT); 320 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_CG_BIT); 321 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); 326 322 327 323 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 328 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); 324 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCN_BIT); 329 325 330 326 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) && 331 327 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 332 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 328 + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT); 333 329 334 330 return 0; 335 331 } ··· 2732 2736 } 2733 2737 2734 2738 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { 2735 - .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, 2739 + .init_allowed_features = smu_v13_0_7_init_allowed_features, 2736 2740 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, 2737 2741 .is_dpm_running = smu_v13_0_7_is_dpm_running, 2738 2742 .init_microcode = smu_v13_0_init_microcode,

+3 -2

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

··· 746 746 int ret = 0; 747 747 uint32_t feature_mask[2]; 748 748 749 - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || 749 + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 750 750 feature->feature_num < 64) 751 751 return -EINVAL; 752 752 753 - bitmap_to_arr32(feature_mask, feature->allowed, 64); 753 + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); 754 754 755 755 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 756 756 feature_mask[1], NULL); ··· 1177 1177 return clk_id; 1178 1178 1179 1179 if (max > 0) { 1180 + max = SMU_V14_SOFT_FREQ_ROUND(max); 1180 1181 if (automatic) 1181 1182 param = (uint32_t)((clk_id << 16) | 0xffff); 1182 1183 else

+3 -47

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

··· 264 264 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 265 265 }; 266 266 267 - static int 268 - smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu, 269 - uint32_t *feature_mask, uint32_t num) 267 + static int smu_v14_0_2_init_allowed_features(struct smu_context *smu) 270 268 { 271 - struct amdgpu_device *adev = smu->adev; 272 - /*u32 smu_version;*/ 273 - 274 - if (num > 2) 275 - return -EINVAL; 276 - 277 - memset(feature_mask, 0xff, sizeof(uint32_t) * num); 278 - 279 - if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 280 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 281 - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); 282 - } 283 - #if 0 284 - if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || 285 - !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 286 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 287 - 288 - if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) 289 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 290 - 291 - /* PMFW 78.58 contains a critical fix for gfxoff feature */ 292 - smu_cmn_get_smc_version(smu, NULL, &smu_version); 293 - if ((smu_version < 0x004e3a00) || 294 - !(adev->pm.pp_feature & PP_GFXOFF_MASK)) 295 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); 296 - 297 - if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { 298 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 299 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 300 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 301 - } 302 - 303 - if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) 304 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 305 - 306 - if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { 307 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); 308 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); 309 - } 310 - 311 - if (!(adev->pm.pp_feature & PP_ULV_MASK)) 312 - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); 313 - #endif 269 + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 314 270 315 271 return 0; 316 272 } ··· 2752 2796 } 2753 2797 2754 2798 static const struct pptable_funcs smu_v14_0_2_ppt_funcs = { 2755 - .get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask, 2799 + .init_allowed_features = smu_v14_0_2_init_allowed_features, 2756 2800 .set_default_dpm_table = smu_v14_0_2_set_default_dpm_table, 2757 2801 .i2c_init = smu_v14_0_2_i2c_control_init, 2758 2802 .i2c_fini = smu_v14_0_2_i2c_control_fini,

+2 -2

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

··· 715 715 int ret = 0; 716 716 uint32_t feature_mask[2]; 717 717 718 - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || 718 + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 719 719 feature->feature_num < 64) 720 720 return -EINVAL; 721 721 722 - bitmap_to_arr32(feature_mask, feature->allowed, 64); 722 + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); 723 723 724 724 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 725 725 feature_mask[1], NULL);

+2 -4

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

··· 677 677 int smu_cmn_feature_is_supported(struct smu_context *smu, 678 678 enum smu_feature_mask mask) 679 679 { 680 - struct smu_feature *feature = &smu->smu_feature; 681 680 int feature_id; 682 681 683 682 feature_id = smu_cmn_to_asic_specific_index(smu, ··· 685 686 if (feature_id < 0) 686 687 return 0; 687 688 688 - WARN_ON(feature_id > feature->feature_num); 689 - 690 - return test_bit(feature_id, feature->supported); 689 + return smu_feature_list_is_set(smu, SMU_FEATURE_LIST_SUPPORTED, 690 + feature_id); 691 691 } 692 692 693 693 static int __smu_get_enabled_features(struct smu_context *smu,

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu_internal.h

··· 70 70 #define smu_apply_clocks_adjust_rules(smu) smu_ppt_funcs(apply_clocks_adjust_rules, 0, smu) 71 71 #define smu_notify_smc_display_config(smu) smu_ppt_funcs(notify_smc_display_config, 0, smu) 72 72 #define smu_run_btc(smu) smu_ppt_funcs(run_btc, 0, smu) 73 - #define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num) 73 + #define smu_init_allowed_features(smu) smu_ppt_funcs(init_allowed_features, 0, smu) 74 74 #define smu_set_watermarks_table(smu, clock_ranges) smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges) 75 75 #define smu_thermal_temperature_range_update(smu, range, rw) smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw) 76 76 #define smu_register_irq_handler(smu) smu_ppt_funcs(register_irq_handler, 0, smu)

+2

include/uapi/linux/kfd_ioctl.h

··· 149 149 __u32 num_xcc; 150 150 __u32 capability; 151 151 __u32 debug_prop; 152 + __u32 capability2; 153 + __u32 pad; 152 154 }; 153 155 154 156 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */

Configure Feed

Configure Feed