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drm/amd/pm: move those code piece used by Stoney only to smu8_hwmgr.c

Instead of putting them in amdgpu_dpm.c.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Evan Quan and committed by
Alex Deucher
a627967e 6ddbd37f

+9 -18
-14
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
··· 32 32 #include "hwmgr.h" 33 33 #include <linux/power_supply.h> 34 34 35 - #define WIDTH_4K 3840 36 - 37 35 #define amdgpu_dpm_enable_bapm(adev, e) \ 38 36 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 39 37 ··· 384 386 if (ret) 385 387 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", 386 388 enable ? "enable" : "disable", ret); 387 - 388 - /* enable/disable Low Memory PState for UVD (4k videos) */ 389 - if (adev->asic_type == CHIP_STONEY && 390 - adev->uvd.decode_image_width >= WIDTH_4K) { 391 - struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 392 - 393 - if (hwmgr && hwmgr->hwmgr_func && 394 - hwmgr->hwmgr_func->update_nbdpm_pstate) 395 - hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr, 396 - !enable, 397 - true); 398 - } 399 389 } 400 390 401 391 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
-3
drivers/gpu/drm/amd/pm/inc/hwmgr.h
··· 331 331 uint32_t mc_addr_low, 332 332 uint32_t mc_addr_hi, 333 333 uint32_t size); 334 - int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr, 335 - bool enable, 336 - bool lock); 337 334 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr, 338 335 struct PP_TemperatureRange *range); 339 336 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
+9 -1
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
··· 1950 1950 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerON, NULL); 1951 1951 } 1952 1952 1953 + #define WIDTH_4K 3840 1954 + 1953 1955 static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 1954 1956 { 1955 1957 struct smu8_hwmgr *data = hwmgr->backend; 1958 + struct amdgpu_device *adev = hwmgr->adev; 1956 1959 1957 1960 data->uvd_power_gated = bgate; 1958 1961 ··· 1979 1976 smu8_dpm_update_uvd_dpm(hwmgr, false); 1980 1977 } 1981 1978 1979 + /* enable/disable Low Memory PState for UVD (4k videos) */ 1980 + if (adev->asic_type == CHIP_STONEY && 1981 + adev->uvd.decode_image_width >= WIDTH_4K) 1982 + smu8_nbdpm_pstate_enable_disable(hwmgr, 1983 + bgate, 1984 + true); 1982 1985 } 1983 1986 1984 1987 static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) ··· 2046 2037 .power_state_set = smu8_set_power_state_tasks, 2047 2038 .dynamic_state_management_disable = smu8_disable_dpm_tasks, 2048 2039 .notify_cac_buffer_info = smu8_notify_cac_buffer_info, 2049 - .update_nbdpm_pstate = smu8_nbdpm_pstate_enable_disable, 2050 2040 .get_thermal_temperature_range = smu8_get_thermal_temperature_range, 2051 2041 }; 2052 2042