Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86_cpu_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpuid updates from Borislav Petkov:
- Make UMIP instruction detection more robust
- Correct and cleanup AMD CPU topology detection; document the relevant
CPUID leaves topology parsing precedence on AMD
- Add support for running the kernel as guest on FreeBSD's Bhyve
hypervisor
- Cleanups and improvements
* tag 'x86_cpu_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/umip: Fix decoding of register forms of 0F 01 (SGDT and SIDT aliases)
x86/umip: Check that the instruction opcode is at least two bytes
Documentation/x86/topology: Detail CPUID leaves used for topology enumeration
x86/cpu/topology: Define AMD64_CPUID_EXT_FEAT MSR
x86/cpu/topology: Check for X86_FEATURE_XTOPOLOGY instead of passing has_xtopology
x86/cpu/cacheinfo: Simplify cacheinfo_amd_init_llc_id() using _cpuid4_info
x86/cpu: Rename and move CPU model entry for Diamond Rapids
x86/cpu: Detect FreeBSD Bhyve hypervisor
+329
-50
+191
Documentation/arch/x86/topology.rst
+191
Documentation/arch/x86/topology.rst
···
141
141
142
142
143
143
144
+
System topology enumeration
145
+
===========================
146
+
147
+
The topology on x86 systems can be discovered using a combination of vendor
148
+
specific CPUID leaves which enumerate the processor topology and the cache
149
+
hierarchy.
150
+
151
+
The CPUID leaves in their preferred order of parsing for each x86 vendor is as
152
+
follows:
153
+
154
+
1) AMD
155
+
156
+
1) CPUID leaf 0x80000026 [Extended CPU Topology] (Core::X86::Cpuid::ExCpuTopology)
157
+
158
+
The extended CPUID leaf 0x80000026 is the extension of the CPUID leaf 0xB
159
+
and provides the topology information of Core, Complex, CCD (Die), and
160
+
Socket in each level.
161
+
162
+
Support for the leaf is discovered by checking if the maximum extended
163
+
CPUID level is >= 0x80000026 and then checking if `LogProcAtThisLevel`
164
+
in `EBX[15:0]` at a particular level (starting from 0) is non-zero.
165
+
166
+
The `LevelType` in `ECX[15:8]` at the level provides the topology domain
167
+
the level describes - Core, Complex, CCD(Die), or the Socket.
168
+
169
+
The kernel uses the `CoreMaskWidth` from `EAX[4:0]` to discover the
170
+
number of bits that need to be right-shifted from `ExtendedLocalApicId`
171
+
in `EDX[31:0]` in order to get a unique Topology ID for the topology
172
+
level. CPUs with the same Topology ID share the resources at that level.
173
+
174
+
CPUID leaf 0x80000026 also provides more information regarding the power
175
+
and efficiency rankings, and about the core type on AMD processors with
176
+
heterogeneous characteristics.
177
+
178
+
If CPUID leaf 0x80000026 is supported, further parsing is not required.
179
+
180
+
2) CPUID leaf 0x0000000B [Extended Topology Enumeration] (Core::X86::Cpuid::ExtTopEnum)
181
+
182
+
The extended CPUID leaf 0x0000000B is the predecessor on the extended
183
+
CPUID leaf 0x80000026 and only describes the core, and the socket domains
184
+
of the processor topology.
185
+
186
+
The support for the leaf is discovered by checking if the maximum supported
187
+
CPUID level is >= 0xB and then if `EBX[31:0]` at a particular level
188
+
(starting from 0) is non-zero.
189
+
190
+
The `LevelType` in `ECX[15:8]` at the level provides the topology domain
191
+
that the level describes - Thread, or Processor (Socket).
192
+
193
+
The kernel uses the `CoreMaskWidth` from `EAX[4:0]` to discover the
194
+
number of bits that need to be right-shifted from the `ExtendedLocalApicId`
195
+
in `EDX[31:0]` to get a unique Topology ID for that topology level. CPUs
196
+
sharing the Topology ID share the resources at that level.
197
+
198
+
If CPUID leaf 0xB is supported, further parsing is not required.
199
+
200
+
201
+
3) CPUID leaf 0x80000008 ECX [Size Identifiers] (Core::X86::Cpuid::SizeId)
202
+
203
+
If neither the CPUID leaf 0x80000026 nor 0xB is supported, the number of
204
+
CPUs on the package is detected using the Size Identifier leaf
205
+
0x80000008 ECX.
206
+
207
+
The support for the leaf is discovered by checking if the supported
208
+
extended CPUID level is >= 0x80000008.
209
+
210
+
The shifts from the APIC ID for the Socket ID is calculated from the
211
+
`ApicIdSize` field in `ECX[15:12]` if it is non-zero.
212
+
213
+
If `ApicIdSize` is reported to be zero, the shift is calculated as the
214
+
order of the `number of threads` calculated from `NC` field in
215
+
`ECX[7:0]` which describes the `number of threads - 1` on the package.
216
+
217
+
Unless Extended APIC ID is supported, the APIC ID used to find the
218
+
Socket ID is from the `LocalApicId` field of CPUID leaf 0x00000001
219
+
`EBX[31:24]`.
220
+
221
+
The topology parsing continues to detect if Extended APIC ID is
222
+
supported or not.
223
+
224
+
225
+
4) CPUID leaf 0x8000001E [Extended APIC ID, Core Identifiers, Node Identifiers]
226
+
(Core::X86::Cpuid::{ExtApicId,CoreId,NodeId})
227
+
228
+
The support for Extended APIC ID can be detected by checking for the
229
+
presence of `TopologyExtensions` in `ECX[22]` of CPUID leaf 0x80000001
230
+
[Feature Identifiers] (Core::X86::Cpuid::FeatureExtIdEcx).
231
+
232
+
If Topology Extensions is supported, the APIC ID from `ExtendedApicId`
233
+
from CPUID leaf 0x8000001E `EAX[31:0]` should be preferred over that from
234
+
`LocalApicId` field of CPUID leaf 0x00000001 `EBX[31:24]` for topology
235
+
enumeration.
236
+
237
+
On processors of Family 0x17 and above that do not support CPUID leaf
238
+
0x80000026 or CPUID leaf 0xB, the shifts from the APIC ID for the Core
239
+
ID is calculated using the order of `number of threads per core`
240
+
calculated using the `ThreadsPerCore` field in `EBX[15:8]` which
241
+
describes `number of threads per core - 1`.
242
+
243
+
On Processors of Family 0x15, the Core ID from `EBX[7:0]` is used as the
244
+
`cu_id` (Compute Unit ID) to detect CPUs that share the compute units.
245
+
246
+
247
+
All AMD processors that support the `TopologyExtensions` feature store the
248
+
`NodeId` from the `ECX[7:0]` of CPUID leaf 0x8000001E
249
+
(Core::X86::Cpuid::NodeId) as the per-CPU `node_id`. On older processors,
250
+
the `node_id` was discovered using MSR_FAM10H_NODE_ID MSR (MSR
251
+
0x0xc001_100c). The presence of the NODE_ID MSR was detected by checking
252
+
`ECX[19]` of CPUID leaf 0x80000001 [Feature Identifiers]
253
+
(Core::X86::Cpuid::FeatureExtIdEcx).
254
+
255
+
256
+
2) Intel
257
+
258
+
On Intel platforms, the CPUID leaves that enumerate the processor
259
+
topology are as follows:
260
+
261
+
1) CPUID leaf 0x1F (V2 Extended Topology Enumeration Leaf)
262
+
263
+
The CPUID leaf 0x1F is the extension of the CPUID leaf 0xB and provides
264
+
the topology information of Core, Module, Tile, Die, DieGrp, and Socket
265
+
in each level.
266
+
267
+
The support for the leaf is discovered by checking if the supported
268
+
CPUID level is >= 0x1F and then `EBX[31:0]` at a particular level
269
+
(starting from 0) is non-zero.
270
+
271
+
The `Domain Type` in `ECX[15:8]` of the sub-leaf provides the topology
272
+
domain that the level describes - Core, Module, Tile, Die, DieGrp, and
273
+
Socket.
274
+
275
+
The kernel uses the value from `EAX[4:0]` to discover the number of
276
+
bits that need to be right shifted from the `x2APIC ID` in `EDX[31:0]`
277
+
to get a unique Topology ID for the topology level. CPUs with the same
278
+
Topology ID share the resources at that level.
279
+
280
+
If CPUID leaf 0x1F is supported, further parsing is not required.
281
+
282
+
283
+
2) CPUID leaf 0x0000000B (Extended Topology Enumeration Leaf)
284
+
285
+
The extended CPUID leaf 0x0000000B is the predecessor of the V2 Extended
286
+
Topology Enumeration Leaf 0x1F and only describes the core, and the
287
+
socket domains of the processor topology.
288
+
289
+
The support for the leaf is iscovered by checking if the supported CPUID
290
+
level is >= 0xB and then checking if `EBX[31:0]` at a particular level
291
+
(starting from 0) is non-zero.
292
+
293
+
CPUID leaf 0x0000000B shares the same layout as CPUID leaf 0x1F and
294
+
should be enumerated in a similar manner.
295
+
296
+
If CPUID leaf 0xB is supported, further parsing is not required.
297
+
298
+
299
+
3) CPUID leaf 0x00000004 (Deterministic Cache Parameters Leaf)
300
+
301
+
On Intel processors that support neither CPUID leaf 0x1F, nor CPUID leaf
302
+
0xB, the shifts for the SMT domains is calculated using the number of
303
+
CPUs sharing the L1 cache.
304
+
305
+
Processors that feature Hyper-Threading is detected using `EDX[28]` of
306
+
CPUID leaf 0x1 (Basic CPUID Information).
307
+
308
+
The order of `Maximum number of addressable IDs for logical processors
309
+
sharing this cache` from `EAX[25:14]` of level-0 of CPUID 0x4 provides
310
+
the shifts from the APIC ID required to compute the Core ID.
311
+
312
+
The APIC ID and Package information is computed using the data from
313
+
CPUID leaf 0x1.
314
+
315
+
316
+
4) CPUID leaf 0x00000001 (Basic CPUID Information)
317
+
318
+
The mask and shifts to derive the Physical Package (socket) ID is
319
+
computed using the `Maximum number of addressable IDs for logical
320
+
processors in this physical package` from `EBX[23:16]` of CPUID leaf
321
+
0x1.
322
+
323
+
The APIC ID on the legacy platforms is derived from the `Initial APIC
324
+
ID` field from `EBX[31:24]` of CPUID leaf 0x1.
325
+
326
+
327
+
3) Centaur and Zhaoxin
328
+
329
+
Similar to Intel, Centaur and Zhaoxin use a combination of CPUID leaf
330
+
0x00000004 (Deterministic Cache Parameters Leaf) and CPUID leaf 0x00000001
331
+
(Basic CPUID Information) to derive the topology information.
332
+
333
+
334
+
144
335
System topology examples
145
336
========================
146
337
+9
arch/x86/Kconfig
+9
arch/x86/Kconfig
···
883
883
IOT with small footprint and real-time features. More details can be
884
884
found in https://projectacrn.org/.
885
885
886
+
config BHYVE_GUEST
887
+
bool "Bhyve (BSD Hypervisor) Guest support"
888
+
depends on X86_64
889
+
help
890
+
This option allows to run Linux to recognise when it is running as a
891
+
guest in the Bhyve hypervisor, and to support more than 255 vCPUs when
892
+
when doing so. More details about Bhyve can be found at https://bhyve.org
893
+
and https://wiki.freebsd.org/bhyve/.
894
+
886
895
config INTEL_TDX_GUEST
887
896
bool "Intel TDX (Trust Domain Extensions) - Guest Support"
888
897
depends on X86_64 && CPU_SUP_INTEL
+2
arch/x86/include/asm/hypervisor.h
+2
arch/x86/include/asm/hypervisor.h
···
30
30
X86_HYPER_KVM,
31
31
X86_HYPER_JAILHOUSE,
32
32
X86_HYPER_ACRN,
33
+
X86_HYPER_BHYVE,
33
34
};
34
35
35
36
#ifdef CONFIG_HYPERVISOR_GUEST
···
65
64
extern const struct hypervisor_x86 x86_hyper_kvm;
66
65
extern const struct hypervisor_x86 x86_hyper_jailhouse;
67
66
extern const struct hypervisor_x86 x86_hyper_acrn;
67
+
extern const struct hypervisor_x86 x86_hyper_bhyve;
68
68
extern struct hypervisor_x86 x86_hyper_xen_hvm;
69
69
70
70
extern bool nopv;
+3
-4
arch/x86/include/asm/intel-family.h
+3
-4
arch/x86/include/asm/intel-family.h
···
51
51
#define INTEL_PENTIUM_MMX IFM(5, 0x04) /* P55C */
52
52
#define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */
53
53
54
-
/* Family 6 */
54
+
/* Family 6, 18, 19 */
55
55
#define INTEL_PENTIUM_PRO IFM(6, 0x01)
56
56
#define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03)
57
57
#define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05)
···
125
125
126
126
#define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */
127
127
#define INTEL_GRANITERAPIDS_D IFM(6, 0xAE)
128
+
129
+
#define INTEL_DIAMONDRAPIDS_X IFM(19, 0x01) /* Panther Cove */
128
130
129
131
#define INTEL_BARTLETTLAKE IFM(6, 0xD7) /* Raptor Cove */
130
132
···
204
202
#define INTEL_P4_PRESCOTT IFM(15, 0x03)
205
203
#define INTEL_P4_PRESCOTT_2M IFM(15, 0x04)
206
204
#define INTEL_P4_CEDARMILL IFM(15, 0x06) /* Also Xeon Dempsey */
207
-
208
-
/* Family 19 */
209
-
#define INTEL_PANTHERCOVE_X IFM(19, 0x01) /* Diamond Rapids */
210
205
211
206
/*
212
207
* Intel CPU core types
+5
arch/x86/include/asm/msr-index.h
+5
arch/x86/include/asm/msr-index.h
···
633
633
#define MSR_AMD_PPIN 0xc00102f1
634
634
#define MSR_AMD64_CPUID_FN_7 0xc0011002
635
635
#define MSR_AMD64_CPUID_FN_1 0xc0011004
636
+
637
+
#define MSR_AMD64_CPUID_EXT_FEAT 0xc0011005
638
+
#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT 54
639
+
#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT BIT_ULL(MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT)
640
+
636
641
#define MSR_AMD64_LS_CFG 0xc0011020
637
642
#define MSR_AMD64_DC_CFG 0xc0011022
638
643
#define MSR_AMD64_TW_CFG 0xc0011023
+1
arch/x86/kernel/cpu/Makefile
+1
arch/x86/kernel/cpu/Makefile
+66
arch/x86/kernel/cpu/bhyve.c
+66
arch/x86/kernel/cpu/bhyve.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* FreeBSD Bhyve guest enlightenments
4
+
*
5
+
* Copyright © 2025 Amazon.com, Inc. or its affiliates.
6
+
*
7
+
* Author: David Woodhouse <dwmw2@infradead.org>
8
+
*/
9
+
10
+
#include <linux/init.h>
11
+
#include <linux/export.h>
12
+
#include <asm/processor.h>
13
+
#include <asm/hypervisor.h>
14
+
15
+
static uint32_t bhyve_cpuid_base;
16
+
static uint32_t bhyve_cpuid_max;
17
+
18
+
#define BHYVE_SIGNATURE "bhyve bhyve "
19
+
20
+
#define CPUID_BHYVE_FEATURES 0x40000001
21
+
22
+
/* Features advertised in CPUID_BHYVE_FEATURES %eax */
23
+
24
+
/* MSI Extended Dest ID */
25
+
#define CPUID_BHYVE_FEAT_EXT_DEST_ID (1UL << 0)
26
+
27
+
static uint32_t __init bhyve_detect(void)
28
+
{
29
+
if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
30
+
return 0;
31
+
32
+
bhyve_cpuid_base = cpuid_base_hypervisor(BHYVE_SIGNATURE, 0);
33
+
if (!bhyve_cpuid_base)
34
+
return 0;
35
+
36
+
bhyve_cpuid_max = cpuid_eax(bhyve_cpuid_base);
37
+
return bhyve_cpuid_max;
38
+
}
39
+
40
+
static uint32_t bhyve_features(void)
41
+
{
42
+
unsigned int cpuid_leaf = bhyve_cpuid_base | CPUID_BHYVE_FEATURES;
43
+
44
+
if (bhyve_cpuid_max < cpuid_leaf)
45
+
return 0;
46
+
47
+
return cpuid_eax(cpuid_leaf);
48
+
}
49
+
50
+
static bool __init bhyve_ext_dest_id(void)
51
+
{
52
+
return !!(bhyve_features() & CPUID_BHYVE_FEAT_EXT_DEST_ID);
53
+
}
54
+
55
+
static bool __init bhyve_x2apic_available(void)
56
+
{
57
+
return true;
58
+
}
59
+
60
+
const struct hypervisor_x86 x86_hyper_bhyve __refconst = {
61
+
.name = "Bhyve",
62
+
.detect = bhyve_detect,
63
+
.init.init_platform = x86_init_noop,
64
+
.init.x2apic_available = bhyve_x2apic_available,
65
+
.init.msi_ext_dest_id = bhyve_ext_dest_id,
66
+
};
+21
-27
arch/x86/kernel/cpu/cacheinfo.c
+21
-27
arch/x86/kernel/cpu/cacheinfo.c
···
290
290
}
291
291
292
292
/*
293
+
* The max shared threads number comes from CPUID(0x4) EAX[25-14] with input
294
+
* ECX as cache index. Then right shift apicid by the number's order to get
295
+
* cache id for this cache node.
296
+
*/
297
+
static unsigned int get_cache_id(u32 apicid, const struct _cpuid4_info *id4)
298
+
{
299
+
unsigned long num_threads_sharing;
300
+
int index_msb;
301
+
302
+
num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
303
+
index_msb = get_count_order(num_threads_sharing);
304
+
305
+
return apicid >> index_msb;
306
+
}
307
+
308
+
/*
293
309
* AMD/Hygon CPUs may have multiple LLCs if L3 caches exist.
294
310
*/
295
311
···
328
312
* Newer families: LLC ID is calculated from the number
329
313
* of threads sharing the L3 cache.
330
314
*/
331
-
u32 eax, ebx, ecx, edx, num_sharing_cache = 0;
332
315
u32 llc_index = find_num_cache_leaves(c) - 1;
316
+
struct _cpuid4_info id4 = {};
333
317
334
-
cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx);
335
-
if (eax)
336
-
num_sharing_cache = ((eax >> 14) & 0xfff) + 1;
337
-
338
-
if (num_sharing_cache) {
339
-
int index_msb = get_count_order(num_sharing_cache);
340
-
341
-
c->topo.llc_id = c->topo.apicid >> index_msb;
342
-
}
318
+
if (!amd_fill_cpuid4_info(llc_index, &id4))
319
+
c->topo.llc_id = get_cache_id(c->topo.apicid, &id4);
343
320
}
344
321
}
345
322
···
607
598
return 0;
608
599
}
609
600
610
-
/*
611
-
* The max shared threads number comes from CPUID(0x4) EAX[25-14] with input
612
-
* ECX as cache index. Then right shift apicid by the number's order to get
613
-
* cache id for this cache node.
614
-
*/
615
-
static void get_cache_id(int cpu, struct _cpuid4_info *id4)
616
-
{
617
-
struct cpuinfo_x86 *c = &cpu_data(cpu);
618
-
unsigned long num_threads_sharing;
619
-
int index_msb;
620
-
621
-
num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
622
-
index_msb = get_count_order(num_threads_sharing);
623
-
id4->id = c->topo.apicid >> index_msb;
624
-
}
625
-
626
601
int populate_cache_leaves(unsigned int cpu)
627
602
{
628
603
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
629
604
struct cacheinfo *ci = this_cpu_ci->info_list;
630
605
u8 cpu_vendor = boot_cpu_data.x86_vendor;
606
+
u32 apicid = cpu_data(cpu).topo.apicid;
631
607
struct amd_northbridge *nb = NULL;
632
608
struct _cpuid4_info id4 = {};
633
609
int idx, ret;
···
622
628
if (ret)
623
629
return ret;
624
630
625
-
get_cache_id(cpu, &id4);
631
+
id4.id = get_cache_id(apicid, &id4);
626
632
627
633
if (cpu_vendor == X86_VENDOR_AMD || cpu_vendor == X86_VENDOR_HYGON)
628
634
nb = amd_init_l3_cache(idx);
+3
arch/x86/kernel/cpu/hypervisor.c
+3
arch/x86/kernel/cpu/hypervisor.c
+12
-14
arch/x86/kernel/cpu/topology_amd.c
+12
-14
arch/x86/kernel/cpu/topology_amd.c
···
59
59
tscan->amd_node_id = node_id;
60
60
}
61
61
62
-
static bool parse_8000_001e(struct topo_scan *tscan, bool has_topoext)
62
+
static bool parse_8000_001e(struct topo_scan *tscan)
63
63
{
64
64
struct {
65
65
// eax
···
85
85
* If leaf 0xb/0x26 is available, then the APIC ID and the domain
86
86
* shifts are set already.
87
87
*/
88
-
if (!has_topoext) {
88
+
if (!cpu_feature_enabled(X86_FEATURE_XTOPOLOGY)) {
89
89
tscan->c->topo.initial_apicid = leaf.ext_apic_id;
90
90
91
91
/*
···
163
163
c->x86 != 0x15 || c->x86_model < 0x10 || c->x86_model > 0x6f)
164
164
return;
165
165
166
-
if (msr_set_bit(0xc0011005, 54) <= 0)
166
+
if (msr_set_bit(MSR_AMD64_CPUID_EXT_FEAT,
167
+
MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT) <= 0)
167
168
return;
168
169
169
-
rdmsrq(0xc0011005, msrval);
170
-
if (msrval & BIT_64(54)) {
170
+
rdmsrq(MSR_AMD64_CPUID_EXT_FEAT, msrval);
171
+
if (msrval & MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT) {
171
172
set_cpu_cap(c, X86_FEATURE_TOPOEXT);
172
173
pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
173
174
}
···
176
175
177
176
static void parse_topology_amd(struct topo_scan *tscan)
178
177
{
178
+
if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES))
179
+
tscan->c->topo.cpu_type = cpuid_ebx(0x80000026);
180
+
179
181
/*
180
182
* Try to get SMT, CORE, TILE, and DIE shifts from extended
181
183
* CPUID leaf 0x8000_0026 on supported processors first. If
182
184
* extended CPUID leaf 0x8000_0026 is not supported, try to
183
185
* get SMT and CORE shift from leaf 0xb. If either leaf is
184
186
* available, cpu_parse_topology_ext() will return true.
185
-
*/
186
-
bool has_xtopology = cpu_parse_topology_ext(tscan);
187
-
188
-
if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES))
189
-
tscan->c->topo.cpu_type = cpuid_ebx(0x80000026);
190
-
191
-
/*
187
+
*
192
188
* If XTOPOLOGY leaves (0x26/0xb) are not available, try to
193
189
* get the CORE shift from leaf 0x8000_0008 first.
194
190
*/
195
-
if (!has_xtopology && !parse_8000_0008(tscan))
191
+
if (!cpu_parse_topology_ext(tscan) && !parse_8000_0008(tscan))
196
192
return;
197
193
198
194
/*
199
195
* Prefer leaf 0x8000001e if available to get the SMT shift and
200
196
* the initial APIC ID if XTOPOLOGY leaves are not available.
201
197
*/
202
-
if (parse_8000_001e(tscan, has_xtopology))
198
+
if (parse_8000_001e(tscan))
203
199
return;
204
200
205
201
/* Try the NODEID MSR */
+13
-2
arch/x86/kernel/umip.c
+13
-2
arch/x86/kernel/umip.c
···
156
156
if (!insn->modrm.nbytes)
157
157
return -EINVAL;
158
158
159
-
/* All the instructions of interest start with 0x0f. */
160
-
if (insn->opcode.bytes[0] != 0xf)
159
+
/* The instructions of interest have 2-byte opcodes: 0F 00 or 0F 01. */
160
+
if (insn->opcode.nbytes < 2 || insn->opcode.bytes[0] != 0xf)
161
161
return -EINVAL;
162
162
163
163
if (insn->opcode.bytes[1] == 0x1) {
164
164
switch (X86_MODRM_REG(insn->modrm.value)) {
165
165
case 0:
166
+
/* The reg form of 0F 01 /0 encodes VMX instructions. */
167
+
if (X86_MODRM_MOD(insn->modrm.value) == 3)
168
+
return -EINVAL;
169
+
166
170
return UMIP_INST_SGDT;
167
171
case 1:
172
+
/*
173
+
* The reg form of 0F 01 /1 encodes MONITOR/MWAIT,
174
+
* STAC/CLAC, and ENCLS.
175
+
*/
176
+
if (X86_MODRM_MOD(insn->modrm.value) == 3)
177
+
return -EINVAL;
178
+
168
179
return UMIP_INST_SIDT;
169
180
case 4:
170
181
return UMIP_INST_SMSW;
+1
-1
drivers/platform/x86/intel/speed_select_if/isst_if_common.c
+1
-1
drivers/platform/x86/intel/speed_select_if/isst_if_common.c
···
790
790
X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, SST_HPM_SUPPORTED),
791
791
X86_MATCH_VFM(INTEL_ICELAKE_D, 0),
792
792
X86_MATCH_VFM(INTEL_ICELAKE_X, 0),
793
-
X86_MATCH_VFM(INTEL_PANTHERCOVE_X, SST_HPM_SUPPORTED),
793
+
X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, SST_HPM_SUPPORTED),
794
794
X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, 0),
795
795
X86_MATCH_VFM(INTEL_SKYLAKE_X, SST_MBOX_SUPPORTED),
796
796
{}
+1
-1
drivers/platform/x86/intel/tpmi_power_domains.c
+1
-1
drivers/platform/x86/intel/tpmi_power_domains.c
···
85
85
X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, NULL),
86
86
X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, NULL),
87
87
X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, NULL),
88
-
X86_MATCH_VFM(INTEL_PANTHERCOVE_X, NULL),
88
+
X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, NULL),
89
89
{}
90
90
};
91
91
MODULE_DEVICE_TABLE(x86cpu, tpmi_cpu_ids);
+1
-1
tools/power/x86/turbostat/turbostat.c
+1
-1
tools/power/x86/turbostat/turbostat.c
···
1195
1195
{ INTEL_EMERALDRAPIDS_X, &spr_features },
1196
1196
{ INTEL_GRANITERAPIDS_X, &spr_features },
1197
1197
{ INTEL_GRANITERAPIDS_D, &spr_features },
1198
-
{ INTEL_PANTHERCOVE_X, &dmr_features },
1198
+
{ INTEL_DIAMONDRAPIDS_X, &dmr_features },
1199
1199
{ INTEL_LAKEFIELD, &cnl_features },
1200
1200
{ INTEL_ALDERLAKE, &adl_features },
1201
1201
{ INTEL_ALDERLAKE_L, &adl_features },