Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus' of https://github.com/openrisc/linux
Pull OpenRISC updates from Stafford Horne:
"The main focus for this series has been to improve OpenRISC kernel
out-of-the-box support for FPGA dev boards.
- Add device tree configurations for De0 Nano single and multicore
configurations
- Fix bug in OpenRISC SMP preventing the kernel from running on FPGA
boards, due to IPIs not being unmasked on secondary CPUs in some
configurations
- Pick up a fix from Brian Masney defining the nop() macro to fix
build failures on OpenRISC for drivers using it"
* tag 'for-linus' of https://github.com/openrisc/linux:
openrisc: define arch-specific version of nop()
openrisc: dts: Add de0 nano multicore config and devicetree
openrisc: dts: Split simple smp dts to dts and dtsi
openrisc: Fix IPIs on simple multicore systems
openrisc: dts: Add de0 nano config and devicetree
+386
-15
+42
arch/openrisc/boot/dts/de0-nano-common.dtsi
+42
arch/openrisc/boot/dts/de0-nano-common.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
3
+
#include <dt-bindings/gpio/gpio.h>
4
+
#include <dt-bindings/leds/common.h>
5
+
6
+
/ {
7
+
leds0: leds {
8
+
compatible = "gpio-leds";
9
+
10
+
led-heartbeat {
11
+
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
12
+
color = <LED_COLOR_ID_GREEN>;
13
+
function = LED_FUNCTION_HEARTBEAT;
14
+
linux,default-trigger = "heartbeat";
15
+
label = "heartbeat";
16
+
};
17
+
};
18
+
19
+
memory@0 {
20
+
device_type = "memory";
21
+
reg = <0x00000000 0x02000000>;
22
+
};
23
+
24
+
/* 8 Green LEDs */
25
+
gpio0: gpio@91000000 {
26
+
compatible = "opencores,gpio";
27
+
reg = <0x91000000 0x1>, <0x91000001 0x1>;
28
+
reg-names = "dat", "dirout";
29
+
gpio-controller;
30
+
#gpio-cells = <2>;
31
+
};
32
+
33
+
/* 4 DIP Switches */
34
+
gpio1: gpio@92000000 {
35
+
compatible = "opencores,gpio";
36
+
reg = <0x92000000 0x1>, <0x92000001 0x1>;
37
+
reg-names = "dat", "dirout";
38
+
gpio-controller;
39
+
#gpio-cells = <2>;
40
+
status = "disabled";
41
+
};
42
+
};
+25
arch/openrisc/boot/dts/de0-nano-multicore.dts
+25
arch/openrisc/boot/dts/de0-nano-multicore.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
3
+
#include <dt-bindings/gpio/gpio.h>
4
+
#include <dt-bindings/leds/common.h>
5
+
6
+
/dts-v1/;
7
+
8
+
#include "simple-smp.dtsi"
9
+
#include "de0-nano-common.dtsi"
10
+
11
+
/ {
12
+
model = "Terasic DE0 Nano - Multicore";
13
+
};
14
+
15
+
&cpu0 {
16
+
clock-frequency = <50000000>;
17
+
};
18
+
19
+
&cpu1 {
20
+
clock-frequency = <50000000>;
21
+
};
22
+
23
+
&serial0 {
24
+
clock-frequency = <50000000>;
25
+
};
+54
arch/openrisc/boot/dts/de0-nano.dts
+54
arch/openrisc/boot/dts/de0-nano.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
3
+
/dts-v1/;
4
+
5
+
#include "de0-nano-common.dtsi"
6
+
7
+
/ {
8
+
model = "Terasic DE0 Nano";
9
+
compatible = "opencores,or1ksim";
10
+
#address-cells = <1>;
11
+
#size-cells = <1>;
12
+
interrupt-parent = <&pic>;
13
+
14
+
aliases {
15
+
uart0 = &serial0;
16
+
};
17
+
18
+
chosen {
19
+
stdout-path = "uart0:115200";
20
+
};
21
+
22
+
cpus {
23
+
#address-cells = <1>;
24
+
#size-cells = <0>;
25
+
26
+
cpu@0 {
27
+
compatible = "opencores,or1200-rtlsvn481";
28
+
reg = <0>;
29
+
clock-frequency = <50000000>;
30
+
};
31
+
};
32
+
33
+
/*
34
+
* OR1K PIC is built into CPU and accessed via special purpose
35
+
* registers. It is not addressable and, hence, has no 'reg'
36
+
* property.
37
+
*/
38
+
pic: pic {
39
+
compatible = "opencores,or1k-pic";
40
+
#interrupt-cells = <1>;
41
+
interrupt-controller;
42
+
};
43
+
44
+
serial0: serial@90000000 {
45
+
compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
46
+
reg = <0x90000000 0x100>;
47
+
interrupts = <2>;
48
+
clock-frequency = <50000000>;
49
+
};
50
+
};
51
+
52
+
&gpio1 {
53
+
status = "okay";
54
+
};
+25
arch/openrisc/boot/dts/simple-smp.dts
+25
arch/openrisc/boot/dts/simple-smp.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
3
+
/dts-v1/;
4
+
5
+
#include "simple-smp.dtsi"
6
+
7
+
/ {
8
+
model = "Simple SMP Board";
9
+
};
10
+
11
+
&cpu0 {
12
+
clock-frequency = <20000000>;
13
+
};
14
+
15
+
&cpu1 {
16
+
clock-frequency = <20000000>;
17
+
};
18
+
19
+
&enet0 {
20
+
status = "okay";
21
+
};
22
+
23
+
&serial0 {
24
+
clock-frequency = <20000000>;
25
+
};
+5
-6
arch/openrisc/boot/dts/simple_smp.dts
arch/openrisc/boot/dts/simple-smp.dtsi
+5
-6
arch/openrisc/boot/dts/simple_smp.dts
arch/openrisc/boot/dts/simple-smp.dtsi
···
1
-
/dts-v1/;
2
1
/ {
3
2
compatible = "opencores,or1ksim";
4
3
#address-cells = <1>;
···
21
22
cpus {
22
23
#address-cells = <1>;
23
24
#size-cells = <0>;
24
-
cpu@0 {
25
+
26
+
cpu0: cpu@0 {
25
27
compatible = "opencores,or1200-rtlsvn481";
26
28
reg = <0>;
27
-
clock-frequency = <20000000>;
28
29
};
29
-
cpu@1 {
30
+
31
+
cpu1: cpu@1 {
30
32
compatible = "opencores,or1200-rtlsvn481";
31
33
reg = <1>;
32
-
clock-frequency = <20000000>;
33
34
};
34
35
};
35
36
···
56
57
compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
57
58
reg = <0x90000000 0x100>;
58
59
interrupts = <2>;
59
-
clock-frequency = <20000000>;
60
60
};
61
61
62
62
enet0: ethoc@92000000 {
···
63
65
reg = <0x92000000 0x800>;
64
66
interrupts = <4>;
65
67
big-endian;
68
+
status = "disabled";
66
69
};
67
70
};
+79
arch/openrisc/configs/de0_nano_defconfig
+79
arch/openrisc/configs/de0_nano_defconfig
···
1
+
CONFIG_SYSVIPC=y
2
+
CONFIG_NO_HZ=y
3
+
CONFIG_LOG_BUF_SHIFT=14
4
+
CONFIG_BLK_DEV_INITRD=y
5
+
# CONFIG_RD_GZIP is not set
6
+
# CONFIG_RD_LZMA is not set
7
+
# CONFIG_RD_LZO is not set
8
+
# CONFIG_RD_LZ4 is not set
9
+
# CONFIG_RD_ZSTD is not set
10
+
CONFIG_EXPERT=y
11
+
# CONFIG_EPOLL is not set
12
+
# CONFIG_TIMERFD is not set
13
+
# CONFIG_EVENTFD is not set
14
+
# CONFIG_AIO is not set
15
+
CONFIG_BUILTIN_DTB_NAME="de0-nano"
16
+
# CONFIG_FPU is not set
17
+
CONFIG_HZ_100=y
18
+
# CONFIG_BLOCK is not set
19
+
CONFIG_SLUB_TINY=y
20
+
# CONFIG_COMPAT_BRK is not set
21
+
# CONFIG_VM_EVENT_COUNTERS is not set
22
+
CONFIG_NET=y
23
+
CONFIG_UNIX=y
24
+
CONFIG_UNIX_DIAG=y
25
+
CONFIG_INET=y
26
+
CONFIG_IP_MULTICAST=y
27
+
CONFIG_INET_UDP_DIAG=y
28
+
CONFIG_INET_RAW_DIAG=y
29
+
CONFIG_INET_DIAG_DESTROY=y
30
+
# CONFIG_IPV6 is not set
31
+
CONFIG_DEVTMPFS=y
32
+
CONFIG_DEVTMPFS_MOUNT=y
33
+
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
34
+
# CONFIG_FW_LOADER is not set
35
+
# CONFIG_INPUT is not set
36
+
# CONFIG_SERIO is not set
37
+
# CONFIG_VT is not set
38
+
# CONFIG_LEGACY_PTYS is not set
39
+
CONFIG_SERIAL_8250=y
40
+
CONFIG_SERIAL_8250_CONSOLE=y
41
+
CONFIG_SERIAL_OF_PLATFORM=y
42
+
# CONFIG_HW_RANDOM is not set
43
+
CONFIG_PPS=y
44
+
CONFIG_GPIO_SYSFS=y
45
+
# CONFIG_GPIO_SYSFS_LEGACY is not set
46
+
CONFIG_GPIO_GENERIC_PLATFORM=y
47
+
# CONFIG_HWMON is not set
48
+
# CONFIG_USB_SUPPORT is not set
49
+
CONFIG_NEW_LEDS=y
50
+
CONFIG_LEDS_CLASS=y
51
+
CONFIG_LEDS_GPIO=y
52
+
CONFIG_LEDS_TRIGGERS=y
53
+
CONFIG_LEDS_TRIGGER_TIMER=y
54
+
CONFIG_LEDS_TRIGGER_ONESHOT=y
55
+
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
56
+
CONFIG_LEDS_TRIGGER_CPU=y
57
+
CONFIG_LEDS_TRIGGER_ACTIVITY=y
58
+
CONFIG_LEDS_TRIGGER_GPIO=y
59
+
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
60
+
CONFIG_LEDS_TRIGGER_TRANSIENT=y
61
+
CONFIG_LEDS_TRIGGER_PANIC=y
62
+
CONFIG_LEDS_TRIGGER_NETDEV=y
63
+
CONFIG_LEDS_TRIGGER_PATTERN=y
64
+
CONFIG_LEDS_TRIGGER_TTY=y
65
+
# CONFIG_VIRTIO_MENU is not set
66
+
# CONFIG_VHOST_MENU is not set
67
+
# CONFIG_DNOTIFY is not set
68
+
CONFIG_TMPFS=y
69
+
# CONFIG_XZ_DEC_X86 is not set
70
+
# CONFIG_XZ_DEC_POWERPC is not set
71
+
# CONFIG_XZ_DEC_ARM is not set
72
+
# CONFIG_XZ_DEC_ARMTHUMB is not set
73
+
# CONFIG_XZ_DEC_ARM64 is not set
74
+
# CONFIG_XZ_DEC_SPARC is not set
75
+
# CONFIG_XZ_DEC_RISCV is not set
76
+
CONFIG_PRINTK_TIME=y
77
+
# CONFIG_DEBUG_MISC is not set
78
+
# CONFIG_FTRACE is not set
79
+
# CONFIG_RUNTIME_TESTING_MENU is not set
+92
arch/openrisc/configs/de0_nano_multicore_defconfig
+92
arch/openrisc/configs/de0_nano_multicore_defconfig
···
1
+
CONFIG_LOCALVERSION="-de0nano-smp"
2
+
CONFIG_SYSVIPC=y
3
+
CONFIG_POSIX_MQUEUE=y
4
+
CONFIG_NO_HZ=y
5
+
CONFIG_LOG_BUF_SHIFT=14
6
+
CONFIG_BLK_DEV_INITRD=y
7
+
# CONFIG_RD_GZIP is not set
8
+
# CONFIG_RD_BZIP2 is not set
9
+
# CONFIG_RD_LZMA is not set
10
+
# CONFIG_RD_XZ is not set
11
+
# CONFIG_RD_LZO is not set
12
+
# CONFIG_RD_LZ4 is not set
13
+
CONFIG_EXPERT=y
14
+
# CONFIG_EPOLL is not set
15
+
# CONFIG_TIMERFD is not set
16
+
# CONFIG_EVENTFD is not set
17
+
# CONFIG_AIO is not set
18
+
CONFIG_KALLSYMS_ALL=y
19
+
CONFIG_DCACHE_WRITETHROUGH=y
20
+
CONFIG_BUILTIN_DTB_NAME="de0-nano-multicore"
21
+
CONFIG_OPENRISC_HAVE_INST_CMOV=y
22
+
CONFIG_SMP=y
23
+
CONFIG_HZ_100=y
24
+
CONFIG_JUMP_LABEL=y
25
+
# CONFIG_BLOCK is not set
26
+
CONFIG_SLUB_TINY=y
27
+
# CONFIG_COMPAT_BRK is not set
28
+
# CONFIG_VM_EVENT_COUNTERS is not set
29
+
CONFIG_NET=y
30
+
CONFIG_PACKET=y
31
+
CONFIG_UNIX=y
32
+
CONFIG_UNIX_DIAG=y
33
+
CONFIG_INET=y
34
+
CONFIG_IP_MULTICAST=y
35
+
CONFIG_TCP_CONG_ADVANCED=y
36
+
# CONFIG_TCP_CONG_BIC is not set
37
+
# CONFIG_TCP_CONG_CUBIC is not set
38
+
# CONFIG_TCP_CONG_WESTWOOD is not set
39
+
# CONFIG_TCP_CONG_HTCP is not set
40
+
# CONFIG_IPV6 is not set
41
+
# CONFIG_WIRELESS is not set
42
+
CONFIG_DEVTMPFS=y
43
+
CONFIG_DEVTMPFS_MOUNT=y
44
+
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
45
+
# CONFIG_FW_LOADER is not set
46
+
CONFIG_NETDEVICES=y
47
+
CONFIG_ETHOC=y
48
+
CONFIG_MICREL_PHY=y
49
+
# CONFIG_WLAN is not set
50
+
# CONFIG_INPUT is not set
51
+
# CONFIG_SERIO is not set
52
+
# CONFIG_VT is not set
53
+
# CONFIG_LEGACY_PTYS is not set
54
+
CONFIG_SERIAL_8250=y
55
+
CONFIG_SERIAL_8250_CONSOLE=y
56
+
CONFIG_SERIAL_OF_PLATFORM=y
57
+
# CONFIG_HW_RANDOM is not set
58
+
CONFIG_GPIO_SYSFS=y
59
+
# CONFIG_GPIO_CDEV_V1 is not set
60
+
CONFIG_GPIO_GENERIC_PLATFORM=y
61
+
# CONFIG_HWMON is not set
62
+
# CONFIG_USB_SUPPORT is not set
63
+
CONFIG_NEW_LEDS=y
64
+
CONFIG_LEDS_CLASS=y
65
+
CONFIG_LEDS_GPIO=y
66
+
CONFIG_LEDS_TRIGGERS=y
67
+
CONFIG_LEDS_TRIGGER_TIMER=y
68
+
CONFIG_LEDS_TRIGGER_ONESHOT=y
69
+
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
70
+
CONFIG_LEDS_TRIGGER_CPU=y
71
+
CONFIG_LEDS_TRIGGER_ACTIVITY=y
72
+
CONFIG_LEDS_TRIGGER_GPIO=y
73
+
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
74
+
CONFIG_LEDS_TRIGGER_TRANSIENT=y
75
+
CONFIG_LEDS_TRIGGER_PANIC=y
76
+
CONFIG_LEDS_TRIGGER_NETDEV=y
77
+
CONFIG_LEDS_TRIGGER_PATTERN=y
78
+
CONFIG_LEDS_TRIGGER_TTY=y
79
+
# CONFIG_DNOTIFY is not set
80
+
CONFIG_TMPFS=y
81
+
CONFIG_NFS_FS=y
82
+
CONFIG_XZ_DEC=y
83
+
CONFIG_PRINTK_TIME=y
84
+
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
85
+
CONFIG_GDB_SCRIPTS=y
86
+
CONFIG_VMLINUX_MAP=y
87
+
CONFIG_HARDLOCKUP_DETECTOR=y
88
+
CONFIG_WQ_WATCHDOG=y
89
+
CONFIG_WQ_CPU_INTENSIVE_REPORT=y
90
+
CONFIG_STACKTRACE=y
91
+
CONFIG_RCU_CPU_STALL_CPUTIME=y
92
+
# CONFIG_RCU_TRACE is not set
+1
-1
arch/openrisc/configs/simple_smp_defconfig
+1
-1
arch/openrisc/configs/simple_smp_defconfig
+2
arch/openrisc/include/asm/barrier.h
+2
arch/openrisc/include/asm/barrier.h
+2
-1
arch/openrisc/include/asm/smp.h
+2
-1
arch/openrisc/include/asm/smp.h
···
20
20
extern void arch_send_call_function_single_ipi(int cpu);
21
21
extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
22
22
23
-
extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
23
+
extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int),
24
+
unsigned int irq);
24
25
extern void handle_IPI(unsigned int ipi_msg);
25
26
26
27
#endif /* __ASM_OPENRISC_SMP_H */
+21
-1
arch/openrisc/kernel/smp.c
+21
-1
arch/openrisc/kernel/smp.c
···
13
13
14
14
#include <linux/smp.h>
15
15
#include <linux/cpu.h>
16
+
#include <linux/interrupt.h>
16
17
#include <linux/sched.h>
17
18
#include <linux/sched/mm.h>
18
19
#include <linux/irq.h>
···
26
25
27
26
asmlinkage __init void secondary_start_kernel(void);
28
27
28
+
static unsigned int ipi_irq __ro_after_init;
29
29
static void (*smp_cross_call)(const struct cpumask *, unsigned int);
30
30
31
31
unsigned long secondary_release = -1;
···
40
38
};
41
39
42
40
static DEFINE_SPINLOCK(boot_lock);
41
+
42
+
static void or1k_ipi_enable(void)
43
+
{
44
+
if (WARN_ON_ONCE(!ipi_irq))
45
+
return;
46
+
47
+
enable_percpu_irq(ipi_irq, 0);
48
+
}
43
49
44
50
static void boot_secondary(unsigned int cpu, struct task_struct *idle)
45
51
{
···
146
136
complete(&cpu_running);
147
137
148
138
synchronise_count_slave(cpu);
139
+
or1k_ipi_enable();
149
140
set_cpu_online(cpu, true);
150
141
151
142
local_irq_enable();
···
206
195
smp_call_function(stop_this_cpu, NULL, 0);
207
196
}
208
197
209
-
void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
198
+
void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int),
199
+
unsigned int irq)
210
200
{
201
+
if (WARN_ON(ipi_irq))
202
+
return;
203
+
211
204
smp_cross_call = fn;
205
+
206
+
ipi_irq = irq;
207
+
208
+
/* Enabled IPIs for boot CPU immediately */
209
+
or1k_ipi_enable();
212
210
}
213
211
214
212
void arch_send_call_function_single_ipi(int cpu)
+12
-5
drivers/irqchip/irq-ompic.c
+12
-5
drivers/irqchip/irq-ompic.c
···
84
84
85
85
static void __iomem *ompic_base;
86
86
87
+
static DEFINE_PER_CPU_READ_MOSTLY(int, ipi_dummy_dev);
88
+
87
89
static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
88
90
{
89
91
return ioread32be(base + offset);
···
185
183
goto out_unmap;
186
184
}
187
185
188
-
ret = request_irq(irq, ompic_ipi_handler, IRQF_PERCPU,
189
-
"ompic_ipi", NULL);
190
-
if (ret)
191
-
goto out_irq_disp;
186
+
irq_set_percpu_devid(irq);
187
+
ret = request_percpu_irq(irq, ompic_ipi_handler, "ompic_ipi",
188
+
&ipi_dummy_dev);
192
189
193
-
set_smp_cross_call(ompic_raise_softirq);
190
+
if (ret) {
191
+
pr_err("ompic: failed to request irq %d, error: %d",
192
+
irq, ret);
193
+
goto out_irq_disp;
194
+
}
195
+
196
+
set_smp_cross_call(ompic_raise_softirq, irq);
194
197
195
198
return 0;
196
199
+26
-1
drivers/irqchip/irq-or1k-pic.c
+26
-1
drivers/irqchip/irq-or1k-pic.c
···
118
118
generic_handle_domain_irq(root_domain, irq);
119
119
}
120
120
121
+
/*
122
+
* The OR1K PIC is a cpu-local interrupt controller and does not distinguish or
123
+
* use distinct irq number ranges for per-cpu event interrupts (IPI). Since
124
+
* information to determine whether a particular irq number should be treated as
125
+
* per-cpu is not available at mapping time, we use a wrapper handler function
126
+
* which chooses the right handler at runtime based on whether IRQF_PERCPU was
127
+
* used when requesting the irq. Borrowed from J-Core AIC.
128
+
*/
129
+
static void or1k_irq_flow_handler(struct irq_desc *desc)
130
+
{
131
+
#ifdef CONFIG_SMP
132
+
struct irq_data *data = irq_desc_get_irq_data(desc);
133
+
struct or1k_pic_dev *pic = data->domain->host_data;
134
+
135
+
if (irqd_is_per_cpu(data))
136
+
handle_percpu_devid_irq(desc);
137
+
else
138
+
pic->handle(desc);
139
+
#endif
140
+
}
141
+
121
142
static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
122
143
{
123
144
struct or1k_pic_dev *pic = d->host_data;
124
145
125
-
irq_set_chip_and_handler(irq, &pic->chip, pic->handle);
146
+
if (IS_ENABLED(CONFIG_SMP))
147
+
irq_set_chip_and_handler(irq, &pic->chip, or1k_irq_flow_handler);
148
+
else
149
+
irq_set_chip_and_handler(irq, &pic->chip, pic->handle);
150
+
126
151
irq_set_status_flags(irq, pic->flags);
127
152
128
153
return 0;