Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"I've been a bit slow gathering these:
- drm/mst: one mutex leak in a fail path
- radeon: two oops fixes, one dpm fix
- i915: one messy set of fixes, where we revert the original fix, and
pull back the proper set of fixes from -next on top.
- nouveau: one fix for an illegal buffer placement.
Doesn't look too bad, hopefully shouldn't be too much more"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/nouveau/gem: return only valid domain when there's only one
drm: fix mutex leak in drm_dp_get_mst_branch_device
drm/amdgpu: add missing dpm check for KV dpm late init
drm/amdgpu/dpm: don't add pwm attributes if DPM is disabled
drm/radeon/dpm: don't add pwm attributes if DPM is disabled
drm/i915: Add primary plane to mask if it's visible
drm/i915: Move sprite/cursor plane disable to intel_sanitize_crtc()
drm/i915: Assign hwmode after encoder state readout
Revert "drm/i915: Add primary plane to mask if it's visible"
drm/i915: Deny wrapping an userptr into a framebuffer
drm/i915: Enable DPLL VGA mode before P1/P2 divider write
drm/i915: Restore lost DPLL register write on gen2-4
drm/i915: Flush pipecontrol post-sync writes
drm/i915: Fix kerneldoc for i915_gem_shrink_all
+97
-64
+6
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+6
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
···
294
294
struct amdgpu_device *adev = dev_get_drvdata(dev);
295
295
umode_t effective_mode = attr->mode;
296
296
297
-
/* Skip limit attributes if DPM is not enabled */
297
+
/* Skip attributes if DPM is not enabled */
298
298
if (!adev->pm.dpm_enabled &&
299
299
(attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
300
-
attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
300
+
attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
301
+
attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
302
+
attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
303
+
attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
304
+
attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
301
305
return 0;
302
306
303
307
/* Skip fan attributes if fan is not present */
+3
drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+3
drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+4
-3
drivers/gpu/drm/drm_dp_mst_topology.c
+4
-3
drivers/gpu/drm/drm_dp_mst_topology.c
···
1194
1194
1195
1195
list_for_each_entry(port, &mstb->ports, next) {
1196
1196
if (port->port_num == port_num) {
1197
-
if (!port->mstb) {
1197
+
mstb = port->mstb;
1198
+
if (!mstb) {
1198
1199
DRM_ERROR("failed to lookup MSTB with lct %d, rad %02x\n", lct, rad[0]);
1199
-
return NULL;
1200
+
goto out;
1200
1201
}
1201
1202
1202
-
mstb = port->mstb;
1203
1203
break;
1204
1204
}
1205
1205
}
1206
1206
}
1207
1207
kref_get(&mstb->kref);
1208
+
out:
1208
1209
mutex_unlock(&mgr->lock);
1209
1210
return mstb;
1210
1211
}
+1
-1
drivers/gpu/drm/i915/i915_gem_shrinker.c
+1
-1
drivers/gpu/drm/i915/i915_gem_shrinker.c
+4
-1
drivers/gpu/drm/i915/i915_gem_userptr.c
+4
-1
drivers/gpu/drm/i915/i915_gem_userptr.c
···
804
804
* Also note, that the object created here is not currently a "first class"
805
805
* object, in that several ioctls are banned. These are the CPU access
806
806
* ioctls: mmap(), pwrite and pread. In practice, you are expected to use
807
-
* direct access via your pointer rather than use those ioctls.
807
+
* direct access via your pointer rather than use those ioctls. Another
808
+
* restriction is that we do not allow userptr surfaces to be pinned to the
809
+
* hardware and so we reject any attempt to create a framebuffer out of a
810
+
* userptr.
808
811
*
809
812
* If you think this is a good interface to use to pass GPU memory between
810
813
* drivers, please use dma-buf instead. In fact, wherever possible use
+67
-53
drivers/gpu/drm/i915/intel_display.c
+67
-53
drivers/gpu/drm/i915/intel_display.c
···
1724
1724
I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725
1725
}
1726
1726
1727
+
/*
1728
+
* Apparently we need to have VGA mode enabled prior to changing
1729
+
* the P1/P2 dividers. Otherwise the DPLL will keep using the old
1730
+
* dividers, even though the register value does change.
1731
+
*/
1732
+
I915_WRITE(reg, 0);
1733
+
1734
+
I915_WRITE(reg, dpll);
1735
+
1727
1736
/* Wait for the clocks to stabilize. */
1728
1737
POSTING_READ(reg);
1729
1738
udelay(150);
···
14116
14107
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14117
14108
struct drm_i915_gem_object *obj = intel_fb->obj;
14118
14109
14110
+
if (obj->userptr.mm) {
14111
+
DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14112
+
return -EINVAL;
14113
+
}
14114
+
14119
14115
return drm_gem_handle_create(file, &obj->base, handle);
14120
14116
}
14121
14117
···
14911
14897
/* restore vblank interrupts to correct state */
14912
14898
drm_crtc_vblank_reset(&crtc->base);
14913
14899
if (crtc->active) {
14900
+
struct intel_plane *plane;
14901
+
14914
14902
drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
14915
14903
update_scanline_offset(crtc);
14916
14904
drm_crtc_vblank_on(&crtc->base);
14905
+
14906
+
/* Disable everything but the primary plane */
14907
+
for_each_intel_plane_on_crtc(dev, crtc, plane) {
14908
+
if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14909
+
continue;
14910
+
14911
+
plane->disable_plane(&plane->base, &crtc->base);
14912
+
}
14917
14913
}
14918
14914
14919
14915
/* We need to sanitize the plane -> pipe mapping first because this will
···
15091
15067
i915_redisable_vga_power_on(dev);
15092
15068
}
15093
15069
15094
-
static bool primary_get_hw_state(struct intel_crtc *crtc)
15070
+
static bool primary_get_hw_state(struct intel_plane *plane)
15095
15071
{
15096
-
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15072
+
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15097
15073
15098
-
return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15074
+
return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15099
15075
}
15100
15076
15101
-
static void readout_plane_state(struct intel_crtc *crtc,
15102
-
struct intel_crtc_state *crtc_state)
15077
+
/* FIXME read out full plane state for all planes */
15078
+
static void readout_plane_state(struct intel_crtc *crtc)
15103
15079
{
15104
-
struct intel_plane *p;
15105
-
struct intel_plane_state *plane_state;
15106
-
bool active = crtc_state->base.active;
15080
+
struct drm_plane *primary = crtc->base.primary;
15081
+
struct intel_plane_state *plane_state =
15082
+
to_intel_plane_state(primary->state);
15107
15083
15108
-
for_each_intel_plane(crtc->base.dev, p) {
15109
-
if (crtc->pipe != p->pipe)
15110
-
continue;
15084
+
plane_state->visible =
15085
+
primary_get_hw_state(to_intel_plane(primary));
15111
15086
15112
-
plane_state = to_intel_plane_state(p->base.state);
15113
-
15114
-
if (p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15115
-
plane_state->visible = primary_get_hw_state(crtc);
15116
-
if (plane_state->visible)
15117
-
crtc->base.state->plane_mask |=
15118
-
1 << drm_plane_index(&p->base);
15119
-
} else {
15120
-
if (active)
15121
-
p->disable_plane(&p->base, &crtc->base);
15122
-
15123
-
plane_state->visible = false;
15124
-
}
15125
-
}
15087
+
if (plane_state->visible)
15088
+
crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15126
15089
}
15127
15090
15128
15091
static void intel_modeset_readout_hw_state(struct drm_device *dev)
···
15132
15121
crtc->base.state->active = crtc->active;
15133
15122
crtc->base.enabled = crtc->active;
15134
15123
15135
-
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15136
-
if (crtc->base.state->active) {
15137
-
intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15138
-
intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15139
-
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15140
-
15141
-
/*
15142
-
* The initial mode needs to be set in order to keep
15143
-
* the atomic core happy. It wants a valid mode if the
15144
-
* crtc's enabled, so we do the above call.
15145
-
*
15146
-
* At this point some state updated by the connectors
15147
-
* in their ->detect() callback has not run yet, so
15148
-
* no recalculation can be done yet.
15149
-
*
15150
-
* Even if we could do a recalculation and modeset
15151
-
* right now it would cause a double modeset if
15152
-
* fbdev or userspace chooses a different initial mode.
15153
-
*
15154
-
* If that happens, someone indicated they wanted a
15155
-
* mode change, which means it's safe to do a full
15156
-
* recalculation.
15157
-
*/
15158
-
crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15159
-
}
15160
-
15161
-
crtc->base.hwmode = crtc->config->base.adjusted_mode;
15162
-
readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15124
+
readout_plane_state(crtc);
15163
15125
15164
15126
DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15165
15127
crtc->base.base.id,
···
15190
15206
connector->base.base.id,
15191
15207
connector->base.name,
15192
15208
connector->base.encoder ? "enabled" : "disabled");
15209
+
}
15210
+
15211
+
for_each_intel_crtc(dev, crtc) {
15212
+
crtc->base.hwmode = crtc->config->base.adjusted_mode;
15213
+
15214
+
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15215
+
if (crtc->base.state->active) {
15216
+
intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15217
+
intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15218
+
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15219
+
15220
+
/*
15221
+
* The initial mode needs to be set in order to keep
15222
+
* the atomic core happy. It wants a valid mode if the
15223
+
* crtc's enabled, so we do the above call.
15224
+
*
15225
+
* At this point some state updated by the connectors
15226
+
* in their ->detect() callback has not run yet, so
15227
+
* no recalculation can be done yet.
15228
+
*
15229
+
* Even if we could do a recalculation and modeset
15230
+
* right now it would cause a double modeset if
15231
+
* fbdev or userspace chooses a different initial mode.
15232
+
*
15233
+
* If that happens, someone indicated they wanted a
15234
+
* mode change, which means it's safe to do a full
15235
+
* recalculation.
15236
+
*/
15237
+
crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15238
+
}
15193
15239
}
15194
15240
}
15195
15241
+1
drivers/gpu/drm/i915/intel_lrc.c
+1
drivers/gpu/drm/i915/intel_lrc.c
+2
drivers/gpu/drm/i915/intel_ringbuffer.c
+2
drivers/gpu/drm/i915/intel_ringbuffer.c
···
347
347
if (flush_domains) {
348
348
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349
349
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
350
+
flags |= PIPE_CONTROL_FLUSH_ENABLE;
350
351
}
351
352
if (invalidate_domains) {
352
353
flags |= PIPE_CONTROL_TLB_INVALIDATE;
···
419
418
if (flush_domains) {
420
419
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
421
420
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
421
+
flags |= PIPE_CONTROL_FLUSH_ENABLE;
422
422
}
423
423
if (invalidate_domains) {
424
424
flags |= PIPE_CONTROL_TLB_INVALIDATE;
+3
-2
drivers/gpu/drm/nouveau/nouveau_gem.c
+3
-2
drivers/gpu/drm/nouveau/nouveau_gem.c
···
227
227
struct nouveau_bo *nvbo = nouveau_gem_object(gem);
228
228
struct nvkm_vma *vma;
229
229
230
-
if (nvbo->bo.mem.mem_type == TTM_PL_TT)
230
+
if (is_power_of_2(nvbo->valid_domains))
231
+
rep->domain = nvbo->valid_domains;
232
+
else if (nvbo->bo.mem.mem_type == TTM_PL_TT)
231
233
rep->domain = NOUVEAU_GEM_DOMAIN_GART;
232
234
else
233
235
rep->domain = NOUVEAU_GEM_DOMAIN_VRAM;
234
-
235
236
rep->offset = nvbo->bo.offset;
236
237
if (cli->vm) {
237
238
vma = nouveau_bo_vma_find(nvbo, cli->vm);
+6
-2
drivers/gpu/drm/radeon/radeon_pm.c
+6
-2
drivers/gpu/drm/radeon/radeon_pm.c
···
717
717
struct radeon_device *rdev = dev_get_drvdata(dev);
718
718
umode_t effective_mode = attr->mode;
719
719
720
-
/* Skip limit attributes if DPM is not enabled */
720
+
/* Skip attributes if DPM is not enabled */
721
721
if (rdev->pm.pm_method != PM_METHOD_DPM &&
722
722
(attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
723
-
attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
723
+
attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
724
+
attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
725
+
attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
726
+
attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
727
+
attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
724
728
return 0;
725
729
726
730
/* Skip fan attributes if fan is not present */