Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20240731062916.2680823-7-quic_skakitap@quicinc.com' into clk-for-6.12
Merge SM8150 camera clock controller binding through topic branch, to
allow this to be shared with DeviceTree source branches as well.
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Documentation/devicetree/bindings/clock/qcom,sm8150-camcc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm8150-camcc.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Camera Clock & Reset Controller on SM8150
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maintainers:
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- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
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description: |
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Qualcomm camera clock control module provides the clocks, resets and
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power domains on SM8150.
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See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
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properties:
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compatible:
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const: qcom,sm8150-camcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Camera AHB clock from GCC
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power-domains:
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maxItems: 1
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description:
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A phandle and PM domain specifier for the MMCX power domain.
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required-opps:
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maxItems: 1
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description:
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A phandle to an OPP node describing required MMCX performance point.
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- power-domains
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- required-opps
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8150.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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clock-controller@ad00000 {
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compatible = "qcom,sm8150-camcc";
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reg = <0x0ad00000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_CAMERA_AHB_CLK>;
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power-domains = <&rpmhpd SM8150_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
+135
include/dt-bindings/clock/qcom,sm8150-camcc.h
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include/dt-bindings/clock/qcom,sm8150-camcc.h
···
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
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#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
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/* CAM_CC clocks */
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#define CAM_CC_PLL0 0
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#define CAM_CC_PLL0_OUT_EVEN 1
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#define CAM_CC_PLL0_OUT_ODD 2
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#define CAM_CC_PLL1 3
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#define CAM_CC_PLL1_OUT_EVEN 4
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#define CAM_CC_PLL2 5
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#define CAM_CC_PLL2_OUT_MAIN 6
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#define CAM_CC_PLL3 7
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#define CAM_CC_PLL3_OUT_EVEN 8
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#define CAM_CC_PLL4 9
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#define CAM_CC_PLL4_OUT_EVEN 10
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#define CAM_CC_BPS_AHB_CLK 11
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#define CAM_CC_BPS_AREG_CLK 12
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#define CAM_CC_BPS_AXI_CLK 13
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#define CAM_CC_BPS_CLK 14
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#define CAM_CC_BPS_CLK_SRC 15
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#define CAM_CC_CAMNOC_AXI_CLK 16
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#define CAM_CC_CAMNOC_AXI_CLK_SRC 17
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#define CAM_CC_CAMNOC_DCD_XO_CLK 18
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#define CAM_CC_CCI_0_CLK 19
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#define CAM_CC_CCI_0_CLK_SRC 20
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#define CAM_CC_CCI_1_CLK 21
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#define CAM_CC_CCI_1_CLK_SRC 22
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#define CAM_CC_CORE_AHB_CLK 23
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#define CAM_CC_CPAS_AHB_CLK 24
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#define CAM_CC_CPHY_RX_CLK_SRC 25
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#define CAM_CC_CSI0PHYTIMER_CLK 26
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#define CAM_CC_CSI0PHYTIMER_CLK_SRC 27
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#define CAM_CC_CSI1PHYTIMER_CLK 28
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#define CAM_CC_CSI1PHYTIMER_CLK_SRC 29
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#define CAM_CC_CSI2PHYTIMER_CLK 30
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#define CAM_CC_CSI2PHYTIMER_CLK_SRC 31
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#define CAM_CC_CSI3PHYTIMER_CLK 32
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#define CAM_CC_CSI3PHYTIMER_CLK_SRC 33
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#define CAM_CC_CSIPHY0_CLK 34
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#define CAM_CC_CSIPHY1_CLK 35
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#define CAM_CC_CSIPHY2_CLK 36
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#define CAM_CC_CSIPHY3_CLK 37
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#define CAM_CC_FAST_AHB_CLK_SRC 38
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#define CAM_CC_FD_CORE_CLK 39
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#define CAM_CC_FD_CORE_CLK_SRC 40
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#define CAM_CC_FD_CORE_UAR_CLK 41
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#define CAM_CC_GDSC_CLK 42
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#define CAM_CC_ICP_AHB_CLK 43
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#define CAM_CC_ICP_CLK 44
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#define CAM_CC_ICP_CLK_SRC 45
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#define CAM_CC_IFE_0_AXI_CLK 46
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#define CAM_CC_IFE_0_CLK 47
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#define CAM_CC_IFE_0_CLK_SRC 48
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#define CAM_CC_IFE_0_CPHY_RX_CLK 49
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#define CAM_CC_IFE_0_CSID_CLK 50
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#define CAM_CC_IFE_0_CSID_CLK_SRC 51
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#define CAM_CC_IFE_0_DSP_CLK 52
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#define CAM_CC_IFE_1_AXI_CLK 53
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#define CAM_CC_IFE_1_CLK 54
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#define CAM_CC_IFE_1_CLK_SRC 55
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#define CAM_CC_IFE_1_CPHY_RX_CLK 56
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#define CAM_CC_IFE_1_CSID_CLK 57
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#define CAM_CC_IFE_1_CSID_CLK_SRC 58
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#define CAM_CC_IFE_1_DSP_CLK 59
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#define CAM_CC_IFE_LITE_0_CLK 60
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#define CAM_CC_IFE_LITE_0_CLK_SRC 61
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#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 62
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#define CAM_CC_IFE_LITE_0_CSID_CLK 63
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#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 64
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#define CAM_CC_IFE_LITE_1_CLK 65
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#define CAM_CC_IFE_LITE_1_CLK_SRC 66
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#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 67
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#define CAM_CC_IFE_LITE_1_CSID_CLK 68
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#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 69
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#define CAM_CC_IPE_0_AHB_CLK 70
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#define CAM_CC_IPE_0_AREG_CLK 71
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#define CAM_CC_IPE_0_AXI_CLK 72
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#define CAM_CC_IPE_0_CLK 73
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#define CAM_CC_IPE_0_CLK_SRC 74
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#define CAM_CC_IPE_1_AHB_CLK 75
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#define CAM_CC_IPE_1_AREG_CLK 76
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#define CAM_CC_IPE_1_AXI_CLK 77
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#define CAM_CC_IPE_1_CLK 78
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#define CAM_CC_JPEG_CLK 79
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#define CAM_CC_JPEG_CLK_SRC 80
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#define CAM_CC_LRME_CLK 81
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#define CAM_CC_LRME_CLK_SRC 82
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#define CAM_CC_MCLK0_CLK 83
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#define CAM_CC_MCLK0_CLK_SRC 84
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#define CAM_CC_MCLK1_CLK 85
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#define CAM_CC_MCLK1_CLK_SRC 86
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#define CAM_CC_MCLK2_CLK 87
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#define CAM_CC_MCLK2_CLK_SRC 88
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#define CAM_CC_MCLK3_CLK 89
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#define CAM_CC_MCLK3_CLK_SRC 90
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#define CAM_CC_SLOW_AHB_CLK_SRC 91
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/* CAM_CC power domains */
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#define TITAN_TOP_GDSC 0
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#define BPS_GDSC 1
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#define IFE_0_GDSC 2
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#define IFE_1_GDSC 3
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#define IPE_0_GDSC 4
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#define IPE_1_GDSC 5
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/* CAM_CC resets */
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#define CAM_CC_BPS_BCR 0
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#define CAM_CC_CAMNOC_BCR 1
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#define CAM_CC_CCI_BCR 2
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#define CAM_CC_CPAS_BCR 3
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#define CAM_CC_CSI0PHY_BCR 4
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#define CAM_CC_CSI1PHY_BCR 5
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#define CAM_CC_CSI2PHY_BCR 6
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#define CAM_CC_CSI3PHY_BCR 7
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#define CAM_CC_FD_BCR 8
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#define CAM_CC_ICP_BCR 9
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#define CAM_CC_IFE_0_BCR 10
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#define CAM_CC_IFE_1_BCR 11
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#define CAM_CC_IFE_LITE_0_BCR 12
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#define CAM_CC_IFE_LITE_1_BCR 13
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#define CAM_CC_IPE_0_BCR 14
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#define CAM_CC_IPE_1_BCR 15
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#define CAM_CC_JPEG_BCR 16
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#define CAM_CC_LRME_BCR 17
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#define CAM_CC_MCLK0_BCR 18
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#define CAM_CC_MCLK1_BCR 19
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#define CAM_CC_MCLK2_BCR 20
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#define CAM_CC_MCLK3_BCR 21
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#endif