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MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers

Add both MACB/GEM instances found in the Mobileye EyeQ5 SoC.

Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

authored by

Théo Lebrun and committed by
Thomas Bogendoerfer
a692761a 7d1b6b70

+45
+45
arch/mips/boot/dts/mobileye/eyeq5.dtsi
··· 77 77 serial0 = &uart0; 78 78 serial1 = &uart1; 79 79 serial2 = &uart2; 80 + ethernet0 = &macb0; 81 + ethernet1 = &macb1; 80 82 }; 81 83 82 84 cpu_intc: interrupt-controller { ··· 233 231 #clock-cells = <1>; 234 232 clocks = <&xtal>; 235 233 clock-names = "ref"; 234 + #phy-cells = <1>; 236 235 }; 237 236 238 237 gic: interrupt-controller@140000 { ··· 308 305 #interrupt-cells = <2>; 309 306 resets = <&olb 0 26>; 310 307 }; 308 + 309 + iocu-bus { 310 + compatible = "simple-bus"; 311 + #address-cells = <2>; 312 + #size-cells = <2>; 313 + ranges; 314 + dma-coherent; 315 + dma-ranges = <0x10 0x00000000 0x0 0x0 0x10 0>; 316 + 317 + macb0: ethernet@2a00000 { 318 + compatible = "mobileye,eyeq5-gem"; 319 + reg = <0x0 0x02a00000 0x0 0x4000>; 320 + interrupt-parent = <&gic>; 321 + /* One interrupt per queue */ 322 + interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>, 323 + <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>, 324 + <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>, 325 + <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 326 + clock-names = "pclk", "hclk", "tsu_clk"; 327 + clocks = <&pclk>, <&pclk>, <&tsu_clk>; 328 + nvmem-cells = <&eth0_mac>; 329 + nvmem-cell-names = "mac-address"; 330 + phys = <&olb 0>; 331 + }; 332 + 333 + macb1: ethernet@2b00000 { 334 + compatible = "mobileye,eyeq5-gem"; 335 + reg = <0x0 0x02b00000 0x0 0x4000>; 336 + interrupt-parent = <&gic>; 337 + /* One interrupt per queue */ 338 + interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 339 + <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 340 + <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 341 + <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; 342 + clock-names = "pclk", "hclk", "tsu_clk"; 343 + clocks = <&pclk>, <&pclk>, <&tsu_clk>; 344 + nvmem-cells = <&eth1_mac>; 345 + nvmem-cell-names = "mac-address"; 346 + phys = <&olb 1>; 347 + }; 348 + }; 349 + 311 350 }; 312 351 }; 313 352