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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add GPU clock controller driver for SM6125
Add support for the GPU clock controller found on SM6125.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208091340.124641-7-konrad.dybcio@linaro.org
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
a6b18286
b96fbb03
+434
+9
drivers/clk/qcom/Kconfig
+9
drivers/clk/qcom/Kconfig
···
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Say Y if you want to use peripheral devices such as UART,
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SPI, I2C, USB, SD/UFS, PCIe etc.
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config SM_GPUCC_6125
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tristate "SM6125 Graphics Clock Controller"
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select SM_GCC_6125
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depends on ARM64 || COMPILE_TEST
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help
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Support for the graphics clock controller on SM6125 devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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config SM_GPUCC_6350
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tristate "SM6350 Graphics Clock Controller"
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select SM_GCC_6350
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
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obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
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obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
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obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o
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obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
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obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
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obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
+424
drivers/clk/qcom/gpucc-sm6125.c
+424
drivers/clk/qcom/gpucc-sm6125.c
···
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+
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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+
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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+
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#include <dt-bindings/clock/qcom,sm6125-gpucc.h>
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+
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "clk-regmap-phy-mux.h"
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#include "gdsc.h"
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#include "reset.h"
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+
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enum {
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DT_BI_TCXO,
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DT_GCC_GPU_GPLL0_CLK_SRC,
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};
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enum {
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P_BI_TCXO,
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P_GPLL0_OUT_MAIN,
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P_GPU_CC_PLL0_2X_CLK,
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P_GPU_CC_PLL0_OUT_AUX2,
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P_GPU_CC_PLL1_OUT_AUX,
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P_GPU_CC_PLL1_OUT_AUX2,
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};
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+
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static struct pll_vco gpu_cc_pll_vco[] = {
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{ 1000000000, 2000000000, 0 },
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{ 500000000, 1000000000, 2 },
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};
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+
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/* 1020MHz configuration */
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static const struct alpha_pll_config gpu_pll0_config = {
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.l = 0x35,
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.config_ctl_val = 0x4001055b,
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.alpha_hi = 0x20,
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.alpha = 0x00,
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.alpha_en_mask = BIT(24),
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.vco_val = 0x0 << 20,
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.vco_mask = 0x3 << 20,
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.aux2_output_mask = BIT(2),
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};
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+
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/* 930MHz configuration */
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static const struct alpha_pll_config gpu_pll1_config = {
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.l = 0x30,
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.config_ctl_val = 0x4001055b,
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.alpha_hi = 0x70,
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.alpha = 0x00,
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.alpha_en_mask = BIT(24),
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.vco_val = 0x2 << 20,
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.vco_mask = 0x3 << 20,
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.aux2_output_mask = BIT(2),
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};
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+
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static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = {
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.offset = 0x0,
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.vco_table = gpu_cc_pll_vco,
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.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0_out_aux2",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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},
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};
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+
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static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = {
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.offset = 0x100,
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.vco_table = gpu_cc_pll_vco,
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.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1_out_aux2",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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},
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};
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+
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPLL0_OUT_MAIN, 5 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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};
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+
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
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{ P_GPU_CC_PLL1_OUT_AUX2, 4 },
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};
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+
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static const struct clk_parent_data gpu_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &gpu_cc_pll0_out_aux2.clkr.hw },
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{ .hw = &gpu_cc_pll1_out_aux2.clkr.hw },
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};
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+
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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{ }
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};
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+
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
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F(320000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
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F(465000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
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F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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{ }
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};
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+
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static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
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.cmd_rcgr = 0x101c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_1,
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.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk_src",
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_rcg2_ops,
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},
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};
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+
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_apb_clk = {
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.halt_reg = 0x1088,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1088,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_apb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_gx_gfx3d_clk = {
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.halt_reg = 0x1054,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x1054,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gfx3d_clk = {
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.halt_reg = 0x10a4,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x10a4,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gfx3d_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_gx_gfx3d_clk.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_snoc_dvm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
269
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
275
+
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static struct clk_branch gpu_cc_cxo_clk = {
277
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
280
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
283
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.name = "gpu_cc_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
288
+
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static struct clk_branch gpu_cc_sleep_clk = {
290
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.halt_reg = 0x1090,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
293
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.enable_reg = 0x1090,
294
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.enable_mask = BIT(0),
295
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_sleep_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
301
+
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static struct clk_branch gpu_cc_ahb_clk = {
303
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
306
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
308
+
.hw.init = &(struct clk_init_data){
309
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.name = "gpu_cc_ahb_clk",
310
+
.flags = CLK_IS_CRITICAL,
311
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.ops = &clk_branch2_ops,
312
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},
313
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},
314
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};
315
+
316
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static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
317
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.halt_reg = 0x5000,
318
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.halt_check = BRANCH_VOTED,
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.clkr = {
320
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.enable_reg = 0x5000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
323
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.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
328
+
329
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static struct gdsc gpu_cx_gdsc = {
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.gdscr = 0x106c,
331
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.gds_hw_ctrl = 0x1540,
332
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.pd = {
333
+
.name = "gpu_cx_gdsc",
334
+
},
335
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.pwrsts = PWRSTS_OFF_ON,
336
+
.flags = VOTABLE,
337
+
};
338
+
339
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static struct gdsc gpu_gx_gdsc = {
340
+
.gdscr = 0x100c,
341
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.pd = {
342
+
.name = "gpu_gx_gdsc",
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+
},
344
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.pwrsts = PWRSTS_OFF_ON,
345
+
.flags = VOTABLE,
346
+
};
347
+
348
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static struct clk_regmap *gpu_cc_sm6125_clocks[] = {
349
+
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
350
+
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
351
+
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
352
+
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
353
+
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
354
+
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
355
+
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
356
+
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
357
+
[GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
358
+
[GPU_CC_PLL1_OUT_AUX2] = &gpu_cc_pll1_out_aux2.clkr,
359
+
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
360
+
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
361
+
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
362
+
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
363
+
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
364
+
};
365
+
366
+
static struct gdsc *gpucc_sm6125_gdscs[] = {
367
+
[GPU_CX_GDSC] = &gpu_cx_gdsc,
368
+
[GPU_GX_GDSC] = &gpu_gx_gdsc,
369
+
};
370
+
371
+
static const struct regmap_config gpu_cc_sm6125_regmap_config = {
372
+
.reg_bits = 32,
373
+
.reg_stride = 4,
374
+
.val_bits = 32,
375
+
.max_register = 0x9000,
376
+
.fast_io = true,
377
+
};
378
+
379
+
static const struct qcom_cc_desc gpu_cc_sm6125_desc = {
380
+
.config = &gpu_cc_sm6125_regmap_config,
381
+
.clks = gpu_cc_sm6125_clocks,
382
+
.num_clks = ARRAY_SIZE(gpu_cc_sm6125_clocks),
383
+
.gdscs = gpucc_sm6125_gdscs,
384
+
.num_gdscs = ARRAY_SIZE(gpucc_sm6125_gdscs),
385
+
};
386
+
387
+
static const struct of_device_id gpu_cc_sm6125_match_table[] = {
388
+
{ .compatible = "qcom,sm6125-gpucc" },
389
+
{ }
390
+
};
391
+
MODULE_DEVICE_TABLE(of, gpu_cc_sm6125_match_table);
392
+
393
+
static int gpu_cc_sm6125_probe(struct platform_device *pdev)
394
+
{
395
+
struct regmap *regmap;
396
+
397
+
regmap = qcom_cc_map(pdev, &gpu_cc_sm6125_desc);
398
+
if (IS_ERR(regmap))
399
+
return PTR_ERR(regmap);
400
+
401
+
clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap, &gpu_pll0_config);
402
+
clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap, &gpu_pll1_config);
403
+
404
+
/* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
405
+
qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf);
406
+
qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf);
407
+
408
+
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
409
+
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
410
+
411
+
return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap);
412
+
}
413
+
414
+
static struct platform_driver gpu_cc_sm6125_driver = {
415
+
.probe = gpu_cc_sm6125_probe,
416
+
.driver = {
417
+
.name = "gpucc-sm6125",
418
+
.of_match_table = gpu_cc_sm6125_match_table,
419
+
},
420
+
};
421
+
module_platform_driver(gpu_cc_sm6125_driver);
422
+
423
+
MODULE_DESCRIPTION("QTI GPUCC SM6125 Driver");
424
+
MODULE_LICENSE("GPL");