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drm/msm/mdp5: Remove MSM8974v1

To the best of my knowledge, the v1 version of this SoC had been
superseded before any device was released on the market. Everywhere
else in the kernel, there are assumptions about the SoC being revision
2 or the later MSM8974PRO.

Remove the config for that flavor of MDP. To bring the naming in line
with the rest of the kernel, remove the v2 suffix from the remaining
config.

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/708112/
Link: https://lore.kernel.org/r/20260302-topic-goodnight_8974v1-v1-1-e0006f7a0526@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Konrad Dybcio and committed by
Dmitry Baryshkov
a6f081ec b21e8540

+2 -92
+2 -92
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
··· 14 14 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */ 15 15 const struct mdp5_cfg_hw *mdp5_cfg = NULL; 16 16 17 - static const struct mdp5_cfg_hw msm8x74v1_config = { 18 - .name = "msm8x74v1", 19 - .mdp = { 20 - .count = 1, 21 - .caps = MDP_CAP_SMP | 22 - 0, 23 - }, 24 - .smp = { 25 - .mmb_count = 22, 26 - .mmb_size = 4096, 27 - .clients = { 28 - [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7, 29 - [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, 30 - [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18, 31 - }, 32 - }, 33 - .ctl = { 34 - .count = 5, 35 - .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, 36 - .flush_hw_mask = 0x0003ffff, 37 - }, 38 - .pipe_vig = { 39 - .count = 3, 40 - .base = { 0x01100, 0x01500, 0x01900 }, 41 - .caps = MDP_PIPE_CAP_HFLIP | 42 - MDP_PIPE_CAP_VFLIP | 43 - MDP_PIPE_CAP_SCALE | 44 - MDP_PIPE_CAP_CSC | 45 - 0, 46 - }, 47 - .pipe_rgb = { 48 - .count = 3, 49 - .base = { 0x01d00, 0x02100, 0x02500 }, 50 - .caps = MDP_PIPE_CAP_HFLIP | 51 - MDP_PIPE_CAP_VFLIP | 52 - MDP_PIPE_CAP_SCALE | 53 - 0, 54 - }, 55 - .pipe_dma = { 56 - .count = 2, 57 - .base = { 0x02900, 0x02d00 }, 58 - .caps = MDP_PIPE_CAP_HFLIP | 59 - MDP_PIPE_CAP_VFLIP | 60 - 0, 61 - }, 62 - .lm = { 63 - .count = 5, 64 - .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 }, 65 - .instances = { 66 - { .id = 0, .pp = 0, .dspp = 0, 67 - .caps = MDP_LM_CAP_DISPLAY, }, 68 - { .id = 1, .pp = 1, .dspp = 1, 69 - .caps = MDP_LM_CAP_DISPLAY, }, 70 - { .id = 2, .pp = 2, .dspp = 2, 71 - .caps = MDP_LM_CAP_DISPLAY, }, 72 - { .id = 3, .pp = -1, .dspp = -1, 73 - .caps = MDP_LM_CAP_WB }, 74 - { .id = 4, .pp = -1, .dspp = -1, 75 - .caps = MDP_LM_CAP_WB }, 76 - }, 77 - .nb_stages = 5, 78 - .max_width = 2048, 79 - .max_height = 0xFFFF, 80 - }, 81 - .dspp = { 82 - .count = 3, 83 - .base = { 0x04500, 0x04900, 0x04d00 }, 84 - }, 85 - .pp = { 86 - .count = 3, 87 - .base = { 0x21a00, 0x21b00, 0x21c00 }, 88 - }, 89 - .intf = { 90 - .base = { 0x21000, 0x21200, 0x21400, 0x21600 }, 91 - .connect = { 92 - [0] = INTF_eDP, 93 - [1] = INTF_DSI, 94 - [2] = INTF_DSI, 95 - [3] = INTF_HDMI, 96 - }, 97 - }, 98 - .perf = { 99 - .ab_inefficiency = 200, 100 - .ib_inefficiency = 120, 101 - .clk_inefficiency = 125 102 - }, 103 - .max_clk = 200000000, 104 - }; 105 - 106 17 static const struct mdp5_cfg_hw msm8x26_config = { 107 18 .name = "msm8x26", 108 19 .mdp = { ··· 95 184 .max_clk = 200000000, 96 185 }; 97 186 98 - static const struct mdp5_cfg_hw msm8x74v2_config = { 187 + static const struct mdp5_cfg_hw msm8x74_config = { 99 188 .name = "msm8x74", 100 189 .mdp = { 101 190 .count = 1, ··· 1009 1098 }; 1010 1099 1011 1100 static const struct mdp5_cfg_handler cfg_handlers_v1[] = { 1012 - { .revision = 0, .config = { .hw = &msm8x74v1_config } }, 1013 1101 { .revision = 1, .config = { .hw = &msm8x26_config } }, 1014 - { .revision = 2, .config = { .hw = &msm8x74v2_config } }, 1102 + { .revision = 2, .config = { .hw = &msm8x74_config } }, 1015 1103 { .revision = 3, .config = { .hw = &apq8084_config } }, 1016 1104 { .revision = 6, .config = { .hw = &msm8x16_config } }, 1017 1105 { .revision = 8, .config = { .hw = &msm8x36_config } },