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dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers

Add device tree bindings for syscon clock and reset controllers (IMGSYS,
MFGCFG, VDECSYS and VENCSYS).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241106111402.200940-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Yassine Oudjana and committed by
Stephen Boyd a7479860 be530c3f

+71
+4
Documentation/devicetree/bindings/clock/mediatek,syscon.yaml
··· 28 28 - mediatek,mt2712-mfgcfg 29 29 - mediatek,mt2712-vdecsys 30 30 - mediatek,mt2712-vencsys 31 + - mediatek,mt6735-imgsys 32 + - mediatek,mt6735-mfgcfg 33 + - mediatek,mt6735-vdecsys 34 + - mediatek,mt6735-vencsys 31 35 - mediatek,mt6765-camsys 32 36 - mediatek,mt6765-imgsys 33 37 - mediatek,mt6765-mipi0a
+6
MAINTAINERS
··· 14538 14538 F: drivers/clk/mediatek/clk-mt6735-pericfg.c 14539 14539 F: drivers/clk/mediatek/clk-mt6735-topckgen.c 14540 14540 F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h 14541 + F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h 14541 14542 F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h 14543 + F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h 14542 14544 F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h 14543 14545 F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h 14546 + F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h 14547 + F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h 14544 14548 F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h 14549 + F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h 14545 14550 F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h 14551 + F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h 14546 14552 14547 14553 MEDIATEK MT76 WIRELESS LAN DRIVER 14548 14554 M: Felix Fietkau <nbd@nbd.name>
+15
include/dt-bindings/clock/mediatek,mt6735-imgsys.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + 3 + #ifndef _DT_BINDINGS_CLK_MT6735_IMGSYS_H 4 + #define _DT_BINDINGS_CLK_MT6735_IMGSYS_H 5 + 6 + #define CLK_IMG_SMI_LARB2 0 7 + #define CLK_IMG_CAM_SMI 1 8 + #define CLK_IMG_CAM_CAM 2 9 + #define CLK_IMG_SEN_TG 3 10 + #define CLK_IMG_SEN_CAM 4 11 + #define CLK_IMG_CAM_SV 5 12 + #define CLK_IMG_SUFOD 6 13 + #define CLK_IMG_FD 7 14 + 15 + #endif /* _DT_BINDINGS_CLK_MT6735_IMGSYS_H */
+8
include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + 3 + #ifndef _DT_BINDINGS_CLK_MT6735_MFGCFG_H 4 + #define _DT_BINDINGS_CLK_MT6735_MFGCFG_H 5 + 6 + #define CLK_MFG_BG3D 0 7 + 8 + #endif /* _DT_BINDINGS_CLK_MT6735_MFGCFG_H */
+9
include/dt-bindings/clock/mediatek,mt6735-vdecsys.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + 3 + #ifndef _DT_BINDINGS_CLK_MT6735_VDECSYS_H 4 + #define _DT_BINDINGS_CLK_MT6735_VDECSYS_H 5 + 6 + #define CLK_VDEC_VDEC 0 7 + #define CLK_VDEC_SMI_LARB1 1 8 + 9 + #endif /* _DT_BINDINGS_CLK_MT6735_VDECSYS_H */
+11
include/dt-bindings/clock/mediatek,mt6735-vencsys.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + 3 + #ifndef _DT_BINDINGS_CLK_MT6735_VENCSYS_H 4 + #define _DT_BINDINGS_CLK_MT6735_VENCSYS_H 5 + 6 + #define CLK_VENC_SMI_LARB3 0 7 + #define CLK_VENC_VENC 1 8 + #define CLK_VENC_JPGENC 2 9 + #define CLK_VENC_JPGDEC 3 10 + 11 + #endif /* _DT_BINDINGS_CLK_MT6735_VENCSYS_H */
+9
include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + 3 + #ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H 4 + #define _DT_BINDINGS_RESET_MT6735_MFGCFG_H 5 + 6 + #define MT6735_MFG_RST0_AXI 0 7 + #define MT6735_MFG_RST0_G3D 1 8 + 9 + #endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */
+9
include/dt-bindings/reset/mediatek,mt6735-vdecsys.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + 3 + #ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H 4 + #define _DT_BINDINGS_RESET_MT6735_VDECSYS_H 5 + 6 + #define MT6735_VDEC_RST0_VDEC 0 7 + #define MT6735_VDEC_RST1_SMI_LARB1 1 8 + 9 + #endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */