Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: mediatek: Add MT8196 ufssys clock support
Add support for the MT8196 ufssys clock controller, which provides clock
gate control for UFS.
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Laura Nao
and committed by
Stephen Boyd
a74d5e83
21277990
+116
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drivers/clk/mediatek/Kconfig
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drivers/clk/mediatek/Kconfig
···
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help
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This driver supports MediaTek MT8196 basic clocks.
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config COMMON_CLK_MT8196_UFSSYS
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tristate "Clock driver for MediaTek MT8196 ufssys"
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depends on COMMON_CLK_MT8196
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default COMMON_CLK_MT8196
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help
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This driver supports MediaTek MT8196 ufssys clocks.
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config COMMON_CLK_MT8365
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tristate "Clock driver for MediaTek MT8365"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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drivers/clk/mediatek/Makefile
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drivers/clk/mediatek/Makefile
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obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
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clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
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clk-mt8196-peri_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
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obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
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obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
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drivers/clk/mediatek/clk-mt8196-ufs_ao.c
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drivers/clk/mediatek/clk-mt8196-ufs_ao.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <dt-bindings/reset/mediatek,mt8196-resets.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#define MT8196_UFSAO_RST0_SET_OFFSET 0x48
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#define MT8196_UFSAO_RST1_SET_OFFSET 0x148
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static const struct mtk_gate_regs ufsao0_cg_regs = {
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.set_ofs = 0x108,
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.clr_ofs = 0x10c,
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.sta_ofs = 0x104,
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};
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static const struct mtk_gate_regs ufsao1_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0xc,
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.sta_ofs = 0x4,
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};
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#define GATE_UFSAO0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ufsao0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_UFSAO1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ufsao1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate ufsao_clks[] = {
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/* UFSAO0 */
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GATE_UFSAO0(CLK_UFSAO_UFSHCI_UFS, "ufsao_ufshci_ufs", "ufs", 0),
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GATE_UFSAO0(CLK_UFSAO_UFSHCI_AES, "ufsao_ufshci_aes", "aes_ufsfde", 1),
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/* UFSAO1 */
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GATE_UFSAO1(CLK_UFSAO_UNIPRO_TX_SYM, "ufsao_unipro_tx_sym", "clk26m", 0),
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GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM0, "ufsao_unipro_rx_sym0", "clk26m", 1),
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GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM1, "ufsao_unipro_rx_sym1", "clk26m", 2),
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GATE_UFSAO1(CLK_UFSAO_UNIPRO_SYS, "ufsao_unipro_sys", "ufs", 3),
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GATE_UFSAO1(CLK_UFSAO_UNIPRO_SAP, "ufsao_unipro_sap", "clk26m", 4),
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GATE_UFSAO1(CLK_UFSAO_PHY_SAP, "ufsao_phy_sap", "clk26m", 8),
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};
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static u16 ufsao_rst_ofs[] = {
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MT8196_UFSAO_RST0_SET_OFFSET,
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MT8196_UFSAO_RST1_SET_OFFSET
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};
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static u16 ufsao_rst_idx_map[] = {
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[MT8196_UFSAO_RST0_UFS_MPHY] = 8,
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[MT8196_UFSAO_RST1_UFS_UNIPRO] = 1 * RST_NR_PER_BANK + 0,
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[MT8196_UFSAO_RST1_UFS_CRYPTO] = 1 * RST_NR_PER_BANK + 1,
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[MT8196_UFSAO_RST1_UFSHCI] = 1 * RST_NR_PER_BANK + 2,
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};
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static const struct mtk_clk_rst_desc ufsao_rst_desc = {
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.version = MTK_RST_SET_CLR,
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.rst_bank_ofs = ufsao_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(ufsao_rst_ofs),
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.rst_idx_map = ufsao_rst_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(ufsao_rst_idx_map),
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};
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static const struct mtk_clk_desc ufsao_mcd = {
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.clks = ufsao_clks,
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.num_clks = ARRAY_SIZE(ufsao_clks),
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.rst_desc = &ufsao_rst_desc,
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};
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static const struct of_device_id of_match_clk_mt8196_ufs_ao[] = {
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{ .compatible = "mediatek,mt8196-ufscfg-ao", .data = &ufsao_mcd },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ufs_ao);
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static struct platform_driver clk_mt8196_ufs_ao_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8196-ufs-ao",
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.of_match_table = of_match_clk_mt8196_ufs_ao,
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},
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};
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module_platform_driver(clk_mt8196_ufs_ao_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 ufs_ao clocks driver");
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MODULE_LICENSE("GPL");