tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch '20241022-qcs615-clock-driver-v4-0-3d716ad0d987@quicinc.com' into clk-for-6.14

Merge QCS615 global clock controller binding through topic branch to
allow constant to be merged into DeviceTree branch as well.

Bjorn Andersson a751a65e 40384c84

+270
+59
Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global Clock & Reset Controller on QCS615 8 + 9 + maintainers: 10 + - Taniya Das <quic_tdas@quicinc.com> 11 + 12 + description: | 13 + Qualcomm global clock control module provides the clocks, resets and power 14 + domains on QCS615. 15 + 16 + See also: include/dt-bindings/clock/qcom,qcs615-gcc.h 17 + 18 + properties: 19 + compatible: 20 + const: qcom,qcs615-gcc 21 + 22 + clocks: 23 + items: 24 + - description: Board XO source 25 + - description: Board active XO source 26 + - description: Sleep clock source 27 + 28 + clock-names: 29 + items: 30 + - const: bi_tcxo 31 + - const: bi_tcxo_ao 32 + - const: sleep_clk 33 + 34 + required: 35 + - compatible 36 + - clocks 37 + - clock-names 38 + - '#power-domain-cells' 39 + 40 + allOf: 41 + - $ref: qcom,gcc.yaml# 42 + 43 + unevaluatedProperties: false 44 + 45 + examples: 46 + - | 47 + #include <dt-bindings/clock/qcom,rpmh.h> 48 + clock-controller@100000 { 49 + compatible = "qcom,qcs615-gcc"; 50 + reg = <0x00100000 0x1f0000>; 51 + clocks = <&rpmhcc RPMH_CXO_CLK>, 52 + <&rpmhcc RPMH_CXO_CLK_A>, 53 + <&sleep_clk>; 54 + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 55 + #clock-cells = <1>; 56 + #reset-cells = <1>; 57 + #power-domain-cells = <1>; 58 + }; 59 + ...
+211
include/dt-bindings/clock/qcom,qcs615-gcc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H 7 + #define _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H 8 + 9 + /* GCC clocks */ 10 + #define GPLL0_OUT_AUX2_DIV 0 11 + #define GPLL3_OUT_AUX2_DIV 1 12 + #define GPLL0 2 13 + #define GPLL3 3 14 + #define GPLL4 4 15 + #define GPLL6 5 16 + #define GPLL6_OUT_MAIN 6 17 + #define GPLL7 7 18 + #define GPLL8 8 19 + #define GPLL8_OUT_MAIN 9 20 + #define GCC_AGGRE_UFS_PHY_AXI_CLK 10 21 + #define GCC_AGGRE_USB2_SEC_AXI_CLK 11 22 + #define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 23 + #define GCC_AHB2PHY_EAST_CLK 13 24 + #define GCC_AHB2PHY_WEST_CLK 14 25 + #define GCC_BOOT_ROM_AHB_CLK 15 26 + #define GCC_CAMERA_AHB_CLK 16 27 + #define GCC_CAMERA_HF_AXI_CLK 17 28 + #define GCC_CAMERA_XO_CLK 18 29 + #define GCC_CE1_AHB_CLK 19 30 + #define GCC_CE1_AXI_CLK 20 31 + #define GCC_CE1_CLK 21 32 + #define GCC_CFG_NOC_USB2_SEC_AXI_CLK 22 33 + #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 34 + #define GCC_CPUSS_AHB_CLK 24 35 + #define GCC_CPUSS_AHB_CLK_SRC 25 36 + #define GCC_CPUSS_GNOC_CLK 26 37 + #define GCC_DDRSS_GPU_AXI_CLK 27 38 + #define GCC_DISP_AHB_CLK 28 39 + #define GCC_DISP_GPLL0_DIV_CLK_SRC 29 40 + #define GCC_DISP_HF_AXI_CLK 30 41 + #define GCC_DISP_XO_CLK 31 42 + #define GCC_EMAC_AXI_CLK 32 43 + #define GCC_EMAC_PTP_CLK 33 44 + #define GCC_EMAC_PTP_CLK_SRC 34 45 + #define GCC_EMAC_RGMII_CLK 35 46 + #define GCC_EMAC_RGMII_CLK_SRC 36 47 + #define GCC_EMAC_SLV_AHB_CLK 37 48 + #define GCC_GP1_CLK 38 49 + #define GCC_GP1_CLK_SRC 39 50 + #define GCC_GP2_CLK 40 51 + #define GCC_GP2_CLK_SRC 41 52 + #define GCC_GP3_CLK 42 53 + #define GCC_GP3_CLK_SRC 43 54 + #define GCC_GPU_CFG_AHB_CLK 44 55 + #define GCC_GPU_GPLL0_CLK_SRC 45 56 + #define GCC_GPU_GPLL0_DIV_CLK_SRC 46 57 + #define GCC_GPU_IREF_CLK 47 58 + #define GCC_GPU_MEMNOC_GFX_CLK 48 59 + #define GCC_GPU_SNOC_DVM_GFX_CLK 49 60 + #define GCC_PCIE0_PHY_REFGEN_CLK 50 61 + #define GCC_PCIE_0_AUX_CLK 51 62 + #define GCC_PCIE_0_AUX_CLK_SRC 52 63 + #define GCC_PCIE_0_CFG_AHB_CLK 53 64 + #define GCC_PCIE_0_CLKREF_CLK 54 65 + #define GCC_PCIE_0_MSTR_AXI_CLK 55 66 + #define GCC_PCIE_0_PIPE_CLK 56 67 + #define GCC_PCIE_0_SLV_AXI_CLK 57 68 + #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 58 69 + #define GCC_PCIE_PHY_AUX_CLK 59 70 + #define GCC_PCIE_PHY_REFGEN_CLK_SRC 60 71 + #define GCC_PDM2_CLK 61 72 + #define GCC_PDM2_CLK_SRC 62 73 + #define GCC_PDM_AHB_CLK 63 74 + #define GCC_PDM_XO4_CLK 64 75 + #define GCC_PRNG_AHB_CLK 65 76 + #define GCC_QMIP_CAMERA_NRT_AHB_CLK 66 77 + #define GCC_QMIP_DISP_AHB_CLK 67 78 + #define GCC_QMIP_PCIE_AHB_CLK 68 79 + #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 69 80 + #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 70 81 + #define GCC_QSPI_CORE_CLK 71 82 + #define GCC_QSPI_CORE_CLK_SRC 72 83 + #define GCC_QUPV3_WRAP0_CORE_2X_CLK 73 84 + #define GCC_QUPV3_WRAP0_CORE_CLK 74 85 + #define GCC_QUPV3_WRAP0_S0_CLK 75 86 + #define GCC_QUPV3_WRAP0_S0_CLK_SRC 76 87 + #define GCC_QUPV3_WRAP0_S1_CLK 77 88 + #define GCC_QUPV3_WRAP0_S1_CLK_SRC 78 89 + #define GCC_QUPV3_WRAP0_S2_CLK 79 90 + #define GCC_QUPV3_WRAP0_S2_CLK_SRC 80 91 + #define GCC_QUPV3_WRAP0_S3_CLK 81 92 + #define GCC_QUPV3_WRAP0_S3_CLK_SRC 82 93 + #define GCC_QUPV3_WRAP0_S4_CLK 83 94 + #define GCC_QUPV3_WRAP0_S4_CLK_SRC 84 95 + #define GCC_QUPV3_WRAP0_S5_CLK 85 96 + #define GCC_QUPV3_WRAP0_S5_CLK_SRC 86 97 + #define GCC_QUPV3_WRAP1_CORE_2X_CLK 87 98 + #define GCC_QUPV3_WRAP1_CORE_CLK 88 99 + #define GCC_QUPV3_WRAP1_S0_CLK 89 100 + #define GCC_QUPV3_WRAP1_S0_CLK_SRC 90 101 + #define GCC_QUPV3_WRAP1_S1_CLK 91 102 + #define GCC_QUPV3_WRAP1_S1_CLK_SRC 92 103 + #define GCC_QUPV3_WRAP1_S2_CLK 93 104 + #define GCC_QUPV3_WRAP1_S2_CLK_SRC 94 105 + #define GCC_QUPV3_WRAP1_S3_CLK 95 106 + #define GCC_QUPV3_WRAP1_S3_CLK_SRC 96 107 + #define GCC_QUPV3_WRAP1_S4_CLK 97 108 + #define GCC_QUPV3_WRAP1_S4_CLK_SRC 98 109 + #define GCC_QUPV3_WRAP1_S5_CLK 99 110 + #define GCC_QUPV3_WRAP1_S5_CLK_SRC 100 111 + #define GCC_QUPV3_WRAP_0_M_AHB_CLK 101 112 + #define GCC_QUPV3_WRAP_0_S_AHB_CLK 102 113 + #define GCC_QUPV3_WRAP_1_M_AHB_CLK 103 114 + #define GCC_QUPV3_WRAP_1_S_AHB_CLK 104 115 + #define GCC_RX1_USB2_CLKREF_CLK 105 116 + #define GCC_RX3_USB2_CLKREF_CLK 106 117 + #define GCC_SDCC1_AHB_CLK 107 118 + #define GCC_SDCC1_APPS_CLK 108 119 + #define GCC_SDCC1_APPS_CLK_SRC 109 120 + #define GCC_SDCC1_ICE_CORE_CLK 110 121 + #define GCC_SDCC1_ICE_CORE_CLK_SRC 111 122 + #define GCC_SDCC2_AHB_CLK 112 123 + #define GCC_SDCC2_APPS_CLK 113 124 + #define GCC_SDCC2_APPS_CLK_SRC 114 125 + #define GCC_SDR_CORE_CLK 115 126 + #define GCC_SDR_CSR_HCLK 116 127 + #define GCC_SDR_PRI_MI2S_CLK 117 128 + #define GCC_SDR_SEC_MI2S_CLK 118 129 + #define GCC_SDR_WR0_MEM_CLK 119 130 + #define GCC_SDR_WR1_MEM_CLK 120 131 + #define GCC_SDR_WR2_MEM_CLK 121 132 + #define GCC_SYS_NOC_CPUSS_AHB_CLK 122 133 + #define GCC_UFS_CARD_CLKREF_CLK 123 134 + #define GCC_UFS_MEM_CLKREF_CLK 124 135 + #define GCC_UFS_PHY_AHB_CLK 125 136 + #define GCC_UFS_PHY_AXI_CLK 126 137 + #define GCC_UFS_PHY_AXI_CLK_SRC 127 138 + #define GCC_UFS_PHY_ICE_CORE_CLK 128 139 + #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 129 140 + #define GCC_UFS_PHY_PHY_AUX_CLK 130 141 + #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 131 142 + #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 132 143 + #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 133 144 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK 134 145 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 135 146 + #define GCC_USB20_SEC_MASTER_CLK 136 147 + #define GCC_USB20_SEC_MASTER_CLK_SRC 137 148 + #define GCC_USB20_SEC_MOCK_UTMI_CLK 138 149 + #define GCC_USB20_SEC_MOCK_UTMI_CLK_SRC 139 150 + #define GCC_USB20_SEC_SLEEP_CLK 140 151 + #define GCC_USB2_PRIM_CLKREF_CLK 141 152 + #define GCC_USB2_SEC_CLKREF_CLK 142 153 + #define GCC_USB2_SEC_PHY_AUX_CLK 143 154 + #define GCC_USB2_SEC_PHY_AUX_CLK_SRC 144 155 + #define GCC_USB2_SEC_PHY_COM_AUX_CLK 145 156 + #define GCC_USB2_SEC_PHY_PIPE_CLK 146 157 + #define GCC_USB30_PRIM_MASTER_CLK 147 158 + #define GCC_USB30_PRIM_MASTER_CLK_SRC 148 159 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK 149 160 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 150 161 + #define GCC_USB30_PRIM_SLEEP_CLK 151 162 + #define GCC_USB3_PRIM_CLKREF_CLK 152 163 + #define GCC_USB3_PRIM_PHY_AUX_CLK 153 164 + #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 154 165 + #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 155 166 + #define GCC_USB3_PRIM_PHY_PIPE_CLK 156 167 + #define GCC_USB3_SEC_CLKREF_CLK 157 168 + #define GCC_VIDEO_AHB_CLK 158 169 + #define GCC_VIDEO_AXI0_CLK 159 170 + #define GCC_VIDEO_XO_CLK 160 171 + #define GCC_VSENSOR_CLK_SRC 161 172 + #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 162 173 + #define GCC_UFS_PHY_AXI_HW_CTL_CLK 163 174 + #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 164 175 + #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165 176 + #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 166 177 + 178 + /* GCC Resets */ 179 + #define GCC_EMAC_BCR 0 180 + #define GCC_QUSB2PHY_PRIM_BCR 1 181 + #define GCC_QUSB2PHY_SEC_BCR 2 182 + #define GCC_USB30_PRIM_BCR 3 183 + #define GCC_USB2_PHY_SEC_BCR 4 184 + #define GCC_USB3_DP_PHY_SEC_BCR 5 185 + #define GCC_USB3PHY_PHY_SEC_BCR 6 186 + #define GCC_PCIE_0_BCR 7 187 + #define GCC_PCIE_0_PHY_BCR 8 188 + #define GCC_PCIE_PHY_BCR 9 189 + #define GCC_PCIE_PHY_COM_BCR 10 190 + #define GCC_UFS_PHY_BCR 11 191 + #define GCC_USB20_SEC_BCR 12 192 + #define GCC_USB3_PHY_PRIM_SP0_BCR 13 193 + #define GCC_USB3PHY_PHY_PRIM_SP0_BCR 14 194 + #define GCC_SDCC1_BCR 15 195 + #define GCC_SDCC2_BCR 16 196 + 197 + /* GCC power domains */ 198 + #define EMAC_GDSC 0 199 + #define PCIE_0_GDSC 1 200 + #define UFS_PHY_GDSC 2 201 + #define USB20_SEC_GDSC 3 202 + #define USB30_PRIM_GDSC 4 203 + #define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 5 204 + #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 6 205 + #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 7 206 + #define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 8 207 + #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 9 208 + #define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 10 209 + #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 210 + 211 + #endif