Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'phy-fixes-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy fixes from Vinod Koul:
- rockchip phy kconfig dependency fix with USB_COMMON and regression
fix for old DT
- stm32 phy overflow assertion fix
- exonysfs phy refclk masks fix and power gate on exit fix
- freescale fix for clock dividor valid range
- TI regmap syscon register fix
- tegra reset registers on init fix
* tag 'phy-fixes-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
phy: tegra: xusb: reset VBUS & ID OVERRIDE
phy: ti: gmii-sel: Do not use syscon helper to build regmap
phy: exynos5-usbdrd: gs101: ensure power is gated to SS phy in phy_exit()
phy: freescale: fsl-samsung-hdmi: Limit PLL lock detection clock divider to valid range
phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclk
phy: stm32: Fix constant-value overflow assertion
phy: rockchip: naneng-combphy: compatible reset with old DT
phy: rockchip: fix Kconfig dependency more
+73
-35
+11
-2
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
+11
-2
drivers/phy/freescale/phy-fsl-samsung-hdmi.c
···
325
325
return container_of(hw, struct fsl_samsung_hdmi_phy, hw);
326
326
}
327
327
328
-
static void
328
+
static int
329
329
fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
330
330
const struct phy_config *cfg)
331
331
{
···
340
340
if (int_pllclk < (50 * MHZ))
341
341
break;
342
342
}
343
+
344
+
if (unlikely(div == 4))
345
+
return -EINVAL;
343
346
344
347
writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12));
345
348
···
367
364
FIELD_PREP(REG14_RP_CODE_MASK, 2) |
368
365
FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8),
369
366
phy->regs + PHY_REG(14));
367
+
368
+
return 0;
370
369
}
371
370
372
371
static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s)
···
471
466
writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK,
472
467
cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21));
473
468
474
-
fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);
469
+
ret = fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);
470
+
if (ret) {
471
+
dev_err(phy->dev, "pixclock too large\n");
472
+
return ret;
473
+
}
475
474
476
475
writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));
477
476
+1
drivers/phy/rockchip/Kconfig
+1
drivers/phy/rockchip/Kconfig
+4
-1
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+4
-1
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
···
324
324
325
325
priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
326
326
327
-
priv->phy_rst = devm_reset_control_get(dev, "phy");
327
+
priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy");
328
+
/* fallback to old behaviour */
329
+
if (PTR_ERR(priv->phy_rst) == -ENOENT)
330
+
priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
328
331
if (IS_ERR(priv->phy_rst))
329
332
return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
330
333
+14
-11
drivers/phy/samsung/phy-exynos5-usbdrd.c
+14
-11
drivers/phy/samsung/phy-exynos5-usbdrd.c
···
488
488
reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
489
489
490
490
/* FSEL settings corresponding to reference clock */
491
-
reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
492
-
PHYCLKRST_MPLL_MULTIPLIER_MASK |
493
-
PHYCLKRST_SSC_REFCLKSEL_MASK;
491
+
reg &= ~(PHYCLKRST_FSEL_PIPE_MASK |
492
+
PHYCLKRST_MPLL_MULTIPLIER_MASK |
493
+
PHYCLKRST_SSC_REFCLKSEL_MASK);
494
494
switch (phy_drd->extrefclk) {
495
495
case EXYNOS5_FSEL_50MHZ:
496
496
reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
···
532
532
reg &= ~PHYCLKRST_REFCLKSEL_MASK;
533
533
reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
534
534
535
-
reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
536
-
PHYCLKRST_MPLL_MULTIPLIER_MASK |
537
-
PHYCLKRST_SSC_REFCLKSEL_MASK;
535
+
reg &= ~(PHYCLKRST_FSEL_UTMI_MASK |
536
+
PHYCLKRST_MPLL_MULTIPLIER_MASK |
537
+
PHYCLKRST_SSC_REFCLKSEL_MASK);
538
538
reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
539
539
540
540
return reg;
···
1296
1296
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
1297
1297
int ret;
1298
1298
1299
+
if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
1300
+
ret = exynos850_usbdrd_phy_exit(phy);
1301
+
if (ret)
1302
+
return ret;
1303
+
}
1304
+
1305
+
exynos5_usbdrd_phy_isol(inst, true);
1306
+
1299
1307
if (inst->phy_cfg->id != EXYNOS5_DRDPHY_UTMI)
1300
1308
return 0;
1301
1309
1302
-
ret = exynos850_usbdrd_phy_exit(phy);
1303
-
if (ret)
1304
-
return ret;
1305
-
1306
-
exynos5_usbdrd_phy_isol(inst, true);
1307
1310
return regulator_bulk_disable(phy_drd->drv_data->n_regulators,
1308
1311
phy_drd->regulators);
1309
1312
}
+18
-20
drivers/phy/st/phy-stm32-combophy.c
+18
-20
drivers/phy/st/phy-stm32-combophy.c
···
111
111
{ 4204000, { 511000, 609000, 706000, 802000 } },
112
112
{ 3999000, { 571000, 648000, 726000, 803000 } }
113
113
};
114
+
#define DEFAULT_IMP_INDEX 3 /* Default impedance is 50 Ohm */
114
115
115
116
static int stm32_impedance_tune(struct stm32_combophy *combophy)
116
117
{
···
120
119
u8 imp_of, vswing_of;
121
120
u32 max_imp = imp_lookup[0].microohm;
122
121
u32 min_imp = imp_lookup[imp_size - 1].microohm;
123
-
u32 max_vswing = imp_lookup[imp_size - 1].vswing[vswing_size - 1];
122
+
u32 max_vswing;
124
123
u32 min_vswing = imp_lookup[0].vswing[0];
125
124
u32 val;
126
-
u32 regval;
127
125
128
126
if (!of_property_read_u32(combophy->dev->of_node, "st,output-micro-ohms", &val)) {
129
127
if (val < min_imp || val > max_imp) {
···
130
130
return -EINVAL;
131
131
}
132
132
133
-
regval = 0;
134
-
for (imp_of = 0; imp_of < ARRAY_SIZE(imp_lookup); imp_of++) {
135
-
if (imp_lookup[imp_of].microohm <= val) {
136
-
regval = FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_OHM, imp_of);
133
+
for (imp_of = 0; imp_of < ARRAY_SIZE(imp_lookup); imp_of++)
134
+
if (imp_lookup[imp_of].microohm <= val)
137
135
break;
138
-
}
139
-
}
136
+
137
+
if (WARN_ON(imp_of == ARRAY_SIZE(imp_lookup)))
138
+
return -EINVAL;
140
139
141
140
dev_dbg(combophy->dev, "Set %u micro-ohms output impedance\n",
142
141
imp_lookup[imp_of].microohm);
143
142
144
143
regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR,
145
144
STM32MP25_PCIEPRG_IMPCTRL_OHM,
146
-
regval);
147
-
} else {
148
-
regmap_read(combophy->regmap, SYSCFG_PCIEPRGCR, &val);
149
-
imp_of = FIELD_GET(STM32MP25_PCIEPRG_IMPCTRL_OHM, val);
150
-
}
145
+
FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_OHM, imp_of));
146
+
} else
147
+
imp_of = DEFAULT_IMP_INDEX;
151
148
152
149
if (!of_property_read_u32(combophy->dev->of_node, "st,output-vswing-microvolt", &val)) {
150
+
max_vswing = imp_lookup[imp_of].vswing[vswing_size - 1];
151
+
153
152
if (val < min_vswing || val > max_vswing) {
154
153
dev_err(combophy->dev, "Invalid value %u for output vswing\n", val);
155
154
return -EINVAL;
156
155
}
157
156
158
-
regval = 0;
159
-
for (vswing_of = 0; vswing_of < ARRAY_SIZE(imp_lookup[imp_of].vswing); vswing_of++) {
160
-
if (imp_lookup[imp_of].vswing[vswing_of] >= val) {
161
-
regval = FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_VSWING, vswing_of);
157
+
for (vswing_of = 0; vswing_of < ARRAY_SIZE(imp_lookup[imp_of].vswing); vswing_of++)
158
+
if (imp_lookup[imp_of].vswing[vswing_of] >= val)
162
159
break;
163
-
}
164
-
}
160
+
161
+
if (WARN_ON(vswing_of == ARRAY_SIZE(imp_lookup[imp_of].vswing)))
162
+
return -EINVAL;
165
163
166
164
dev_dbg(combophy->dev, "Set %u microvolt swing\n",
167
165
imp_lookup[imp_of].vswing[vswing_of]);
168
166
169
167
regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR,
170
168
STM32MP25_PCIEPRG_IMPCTRL_VSWING,
171
-
regval);
169
+
FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_VSWING, vswing_of));
172
170
}
173
171
174
172
return 0;
+11
drivers/phy/tegra/xusb-tegra186.c
+11
drivers/phy/tegra/xusb-tegra186.c
···
928
928
unsigned int index = lane->index;
929
929
struct device *dev = padctl->dev;
930
930
int err;
931
+
u32 reg;
931
932
932
933
port = tegra_xusb_find_usb2_port(padctl, index);
933
934
if (!port) {
934
935
dev_err(dev, "no port found for USB2 lane %u\n", index);
935
936
return -ENODEV;
937
+
}
938
+
939
+
if (port->mode == USB_DR_MODE_OTG ||
940
+
port->mode == USB_DR_MODE_PERIPHERAL) {
941
+
/* reset VBUS&ID OVERRIDE */
942
+
reg = padctl_readl(padctl, USB2_VBUS_ID);
943
+
reg &= ~VBUS_OVERRIDE;
944
+
reg &= ~ID_OVERRIDE(~0);
945
+
reg |= ID_OVERRIDE_FLOATING;
946
+
padctl_writel(padctl, reg, USB2_VBUS_ID);
936
947
}
937
948
938
949
if (port->supply && port->mode == USB_DR_MODE_HOST) {
+14
-1
drivers/phy/ti/phy-gmii-sel.c
+14
-1
drivers/phy/ti/phy-gmii-sel.c
···
424
424
return 0;
425
425
}
426
426
427
+
static const struct regmap_config phy_gmii_sel_regmap_cfg = {
428
+
.reg_bits = 32,
429
+
.val_bits = 32,
430
+
.reg_stride = 4,
431
+
};
432
+
427
433
static int phy_gmii_sel_probe(struct platform_device *pdev)
428
434
{
429
435
struct device *dev = &pdev->dev;
···
474
468
475
469
priv->regmap = syscon_node_to_regmap(node->parent);
476
470
if (IS_ERR(priv->regmap)) {
477
-
priv->regmap = device_node_to_regmap(node);
471
+
void __iomem *base;
472
+
473
+
base = devm_platform_ioremap_resource(pdev, 0);
474
+
if (IS_ERR(base))
475
+
return dev_err_probe(dev, PTR_ERR(base),
476
+
"failed to get base memory resource\n");
477
+
478
+
priv->regmap = regmap_init_mmio(dev, base, &phy_gmii_sel_regmap_cfg);
478
479
if (IS_ERR(priv->regmap))
479
480
return dev_err_probe(dev, PTR_ERR(priv->regmap),
480
481
"Failed to get syscon\n");