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cxl: update documentation structure in prep for new docs

Restructure the cxl folder to make adding docs per-page cleaner.

Signed-off-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250512162134.3596150-2-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

authored by

Gregory Price and committed by
Dave Jiang
a7706472 b4432656

+18 -8
Documentation/driver-api/cxl/access-coordinates.rst Documentation/driver-api/cxl/linux/access-coordinates.rst
+13 -3
Documentation/driver-api/cxl/index.rst
··· 4 4 Compute Express Link 5 5 ==================== 6 6 7 + CXL device configuration has a complex handoff between platform (Hardware, 8 + BIOS, EFI), OS (early boot, core kernel, driver), and user policy decisions 9 + that have impacts on each other. The docs here break up configurations steps. 10 + 11 + .. toctree:: 12 + :maxdepth: 2 13 + :caption: Overview 14 + 15 + theory-of-operation 16 + maturity-map 17 + 7 18 .. toctree:: 8 19 :maxdepth: 1 20 + :caption: Linux Kernel Configuration 9 21 10 - memory-devices 11 - access-coordinates 22 + linux/access-coordinates 12 23 13 - maturity-map 14 24 15 25 .. only:: subproject and html
+5 -5
Documentation/driver-api/cxl/memory-devices.rst Documentation/driver-api/cxl/theory-of-operation.rst
··· 1 1 .. SPDX-License-Identifier: GPL-2.0 2 2 .. include:: <isonum.txt> 3 3 4 - =================================== 5 - Compute Express Link Memory Devices 6 - =================================== 4 + =============================================== 5 + Compute Express Link Driver Theory of Operation 6 + =============================================== 7 7 8 8 A Compute Express Link Memory Device is a CXL component that implements the 9 9 CXL.mem protocol. It contains some amount of volatile memory, persistent memory, ··· 14 14 range across multiple devices underneath a host-bridge or interleaved 15 15 across host-bridges. 16 16 17 - CXL Bus: Theory of Operation 18 - ============================ 17 + The CXL Bus 18 + =========== 19 19 Similar to how a RAID driver takes disk objects and assembles them into a new 20 20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and 21 21 assemble them into a CXL.mem decode topology. The need for runtime configuration