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Merge tag 'asoc-fix-v7.1-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

ASoC: Fixes for v7.1

We've had quite a lot of fixes come in this past week, all driver stuff
rather than any broad systematic issue. All quite routine stuff.

+101 -38
+1 -1
sound/soc/amd/acp/acp-legacy-mach.c
··· 174 174 acp_card_drvdata->acp_rev = mach->mach_params.subsystem_rev; 175 175 176 176 dmi_id = dmi_first_match(acp_quirk_table); 177 - if (dmi_id && dmi_id->driver_data) 177 + if (dmi_id && dmi_id->driver_data == (void *)QUIRK_TDM_MODE_ENABLE) 178 178 acp_card_drvdata->tdm_mode = dmi_id->driver_data; 179 179 180 180 ret = acp_legacy_dai_links_create(card);
+19 -3
sound/soc/amd/acp/acp-mach-common.c
··· 20 20 #include <sound/soc.h> 21 21 #include <linux/input.h> 22 22 #include <linux/module.h> 23 + #include <linux/dmi.h> 23 24 24 25 #include "../../codecs/rt5682.h" 25 26 #include "../../codecs/rt1019.h" ··· 38 37 #define NAU8821_FREQ_OUT 12288000 39 38 #define MAX98388_CODEC_DAI "max98388-aif1" 40 39 41 - #define TDM_MODE_ENABLE 1 42 - 43 40 const struct dmi_system_id acp_quirk_table[] = { 44 41 { 45 42 /* Google skyrim proto-0 */ 46 43 .matches = { 47 44 DMI_EXACT_MATCH(DMI_PRODUCT_FAMILY, "Google_Skyrim"), 48 45 }, 49 - .driver_data = (void *)TDM_MODE_ENABLE, 46 + .driver_data = (void *)QUIRK_TDM_MODE_ENABLE, 47 + }, 48 + { 49 + /* Valve Steam Deck OLED */ 50 + .matches = { 51 + DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 52 + DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 53 + }, 54 + .driver_data = (void *)QUIRK_REMAP_DMIC_BT, 50 55 }, 51 56 {} 52 57 }; ··· 1408 1401 struct snd_soc_dai_link *links; 1409 1402 struct device *dev = card->dev; 1410 1403 struct acp_card_drvdata *drv_data = card->drvdata; 1404 + const struct dmi_system_id *dmi_id = dmi_first_match(acp_quirk_table); 1411 1405 int i = 0, num_links = 0; 1412 1406 1413 1407 if (drv_data->hs_cpu_id) ··· 1580 1572 links[i].codecs = &snd_soc_dummy_dlc; 1581 1573 links[i].num_codecs = 1; 1582 1574 } 1575 + 1576 + if (dmi_id && dmi_id->driver_data == (void *)QUIRK_REMAP_DMIC_BT) 1577 + links[i].id = DMIC_BE_ID; 1583 1578 i++; 1584 1579 } 1585 1580 ··· 1598 1587 links[i].capture_only = 1; 1599 1588 links[i].nonatomic = true; 1600 1589 links[i].no_pcm = 1; 1590 + 1591 + if (dmi_id && dmi_id->driver_data == (void *)QUIRK_REMAP_DMIC_BT) { 1592 + links[i].id = BT_BE_ID; 1593 + dev_dbg(dev, "quirk REMAP_DMIC_BT enabled\n"); 1594 + } 1601 1595 } 1602 1596 1603 1597 card->dai_link = links;
+4
sound/soc/amd/acp/acp-mach.h
··· 26 26 27 27 #define acp_get_drvdata(card) ((struct acp_card_drvdata *)(card)->drvdata) 28 28 29 + /* List of DMI quirks - check acp-mach-common.c for usage. */ 30 + #define QUIRK_TDM_MODE_ENABLE 1 31 + #define QUIRK_REMAP_DMIC_BT 2 32 + 29 33 enum be_id { 30 34 HEADSET_BE_ID = 0, 31 35 AMP_BE_ID,
+1 -1
sound/soc/amd/acp/acp-sof-mach.c
··· 110 110 111 111 acp_card_drvdata = card->drvdata; 112 112 dmi_id = dmi_first_match(acp_quirk_table); 113 - if (dmi_id && dmi_id->driver_data) 113 + if (dmi_id && dmi_id->driver_data == (void *)QUIRK_TDM_MODE_ENABLE) 114 114 acp_card_drvdata->tdm_mode = dmi_id->driver_data; 115 115 116 116 acp_card_drvdata->acp_rev = mach->mach_params.subsystem_rev;
+3 -3
sound/soc/codecs/ab8500-codec.c
··· 2496 2496 return status; 2497 2497 } 2498 2498 fc = (struct filter_control *) 2499 - &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value; 2499 + ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value; 2500 2500 drvdata->anc_fir_values = (long *)fc->value; 2501 2501 fc = (struct filter_control *) 2502 - &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value; 2502 + ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value; 2503 2503 drvdata->anc_iir_values = (long *)fc->value; 2504 2504 fc = (struct filter_control *) 2505 - &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value; 2505 + ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value; 2506 2506 drvdata->sid_fir_values = (long *)fc->value; 2507 2507 2508 2508 snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
+4 -5
sound/soc/codecs/aw88395/aw88395.c
··· 456 456 usleep_range(AW88395_1000_US, AW88395_1000_US + 10); 457 457 gpiod_set_value_cansleep(aw88395->reset_gpio, 1); 458 458 usleep_range(AW88395_1000_US, AW88395_1000_US + 10); 459 - } else { 460 - dev_err(aw88395->aw_pa->dev, "%s failed", __func__); 461 459 } 462 460 } 463 461 ··· 520 522 i2c_set_clientdata(i2c, aw88395); 521 523 522 524 aw88395->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_LOW); 523 - if (IS_ERR(aw88395->reset_gpio)) 524 - dev_info(&i2c->dev, "reset gpio not defined\n"); 525 - 525 + if (IS_ERR(aw88395->reset_gpio)) { 526 + return dev_err_probe(&i2c->dev, PTR_ERR(aw88395->reset_gpio), 527 + "failed to get reset gpio\n"); 528 + } 526 529 /* hardware reset */ 527 530 aw88395_hw_reset(aw88395); 528 531
+3 -4
sound/soc/codecs/cs35l56-shared.c
··· 108 108 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); 109 109 110 110 static const struct reg_default cs35l56_reg_defaults[] = { 111 - /* no defaults for OTP_MEM - first read populates cache */ 112 - 113 111 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 114 112 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 115 113 { CS35L56_ASP1_CONTROL2, 0x18180200 }, ··· 136 138 }; 137 139 138 140 static const struct reg_default cs35l63_reg_defaults[] = { 139 - /* no defaults for OTP_MEM - first read populates cache */ 140 - 141 141 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 142 142 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 143 143 { CS35L56_ASP1_CONTROL2, 0x18180200 }, ··· 278 282 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 279 283 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 280 284 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 285 + case CS35L56_OTP_MEM_53: 286 + case CS35L56_OTP_MEM_54: 287 + case CS35L56_OTP_MEM_55: 281 288 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 282 289 case CS35L56_UPDATE_REGS: 283 290 case CS35L56_REFCLK_INPUT: /* owned by firmware */
+1 -1
sound/soc/codecs/es8389.c
··· 892 892 return ret; 893 893 } 894 894 895 - es8389->mclk = devm_clk_get(component->dev, "mclk"); 895 + es8389->mclk = devm_clk_get_optional(component->dev, "mclk"); 896 896 if (IS_ERR(es8389->mclk)) 897 897 return dev_err_probe(component->dev, PTR_ERR(es8389->mclk), 898 898 "ES8389 is unable to get mclk\n");
+1
sound/soc/codecs/tas2764.c
··· 904 904 { 905 905 switch (reg) { 906 906 case TAS2764_SW_RST: 907 + case TAS2764_TEMP: 907 908 case TAS2764_INT_LTCH0 ... TAS2764_INT_LTCH4: 908 909 case TAS2764_INT_CLK_CFG: 909 910 return true;
+2 -2
sound/soc/codecs/tas2770.c
··· 624 624 /* 625 625 * As per datasheet: divide register by 16 and subtract 93 to get 626 626 * degrees Celsius. hwmon requires millidegrees. Let's avoid rounding 627 - * errors by subtracting 93 * 16 then multiplying by 1000 / 16. 627 + * errors by subtracting 93 * 16 and scaling before dividing. 628 628 * 629 629 * NOTE: The ADC registers are initialised to 0 on reset. This means 630 630 * that the temperature will read -93 *C until the chip is brought out ··· 633 633 * value read back from its registers will be the last value sampled 634 634 * before entering software shutdown. 635 635 */ 636 - *result = (reading - (93 * 16)) * (1000 / 16); 636 + *result = (reading - (93 * 16)) * 1000 / 16; 637 637 return 0; 638 638 } 639 639
+25 -1
sound/soc/codecs/wcd937x.c
··· 547 547 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 548 548 BIT(2), BIT(2)); 549 549 snd_soc_component_update_bits(component, 550 + WCD937X_AUX_AUXPA, 551 + BIT(4), BIT(4)); 552 + snd_soc_component_update_bits(component, 550 553 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 551 554 BIT(2), BIT(2)); 552 555 snd_soc_component_update_bits(component, ··· 565 562 snd_soc_component_update_bits(component, 566 563 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 567 564 BIT(2), 0x00); 565 + snd_soc_component_update_bits(component, 566 + WCD937X_AUX_AUXPA, 567 + BIT(4), 0x00); 568 568 break; 569 569 } 570 570 ··· 736 730 snd_soc_component_update_bits(component, 737 731 WCD937X_ANA_RX_SUPPLIES, 738 732 BIT(1), BIT(1)); 733 + /* Enable AUX PA related RX supplies */ 734 + snd_soc_component_update_bits(component, 735 + WCD937X_ANA_RX_SUPPLIES, 736 + BIT(6), BIT(6)); 737 + snd_soc_component_update_bits(component, 738 + WCD937X_ANA_RX_SUPPLIES, 739 + BIT(7), BIT(7)); 739 740 enable_irq(wcd937x->aux_pdm_wd_int); 740 741 break; 741 742 case SND_SOC_DAPM_PRE_PMD: 742 743 disable_irq_nosync(wcd937x->aux_pdm_wd_int); 744 + snd_soc_component_update_bits(component, 745 + WCD937X_ANA_RX_SUPPLIES, 746 + BIT(6), 0x00); 747 + snd_soc_component_update_bits(component, 748 + WCD937X_ANA_RX_SUPPLIES, 749 + BIT(7), 0x00); 743 750 break; 744 751 case SND_SOC_DAPM_POST_PMD: 745 752 usleep_range(2000, 2010); ··· 2070 2051 wcd937x_get_swr_port, wcd937x_set_swr_port), 2071 2052 SOC_SINGLE_EXT("LO Switch", WCD937X_LO, 0, 1, 0, 2072 2053 wcd937x_get_swr_port, wcd937x_set_swr_port), 2073 - 2054 + SOC_SINGLE_EXT("CLSH PA Switch", WCD937X_CLSH, 0, 1, 0, 2055 + wcd937x_get_swr_port, wcd937x_set_swr_port), 2056 + SOC_SINGLE_EXT("DSD_L Switch", WCD937X_DSD_L, 0, 1, 0, 2057 + wcd937x_get_swr_port, wcd937x_set_swr_port), 2058 + SOC_SINGLE_EXT("DSD_R Switch", WCD937X_DSD_R, 0, 1, 0, 2059 + wcd937x_get_swr_port, wcd937x_set_swr_port), 2074 2060 SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0, 2075 2061 wcd937x_get_swr_port, wcd937x_set_swr_port), 2076 2062 SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0,
+1
sound/soc/intel/boards/bytcr_wm5102.c
··· 170 170 ret = byt_wm5102_prepare_and_enable_pll1(codec_dai, 48000); 171 171 if (ret) { 172 172 dev_err(card->dev, "Error setting codec sysclk: %d\n", ret); 173 + clk_disable_unprepare(priv->mclk); 173 174 return ret; 174 175 } 175 176 } else {
+2 -1
sound/soc/sof/intel/hda.c
··· 1412 1412 link_mask |= BIT(peripherals->array[i]->bus->link_id); 1413 1413 1414 1414 link_num = hweight32(link_mask); 1415 - links = devm_kcalloc(sdev->dev, link_num, sizeof(*links), GFP_KERNEL); 1415 + /* An empty adr_link is needed to terminate the adr_link loop */ 1416 + links = devm_kcalloc(sdev->dev, link_num + 1, sizeof(*links), GFP_KERNEL); 1416 1417 if (!links) 1417 1418 return NULL; 1418 1419
+34 -15
sound/soc/spacemit/k1_i2s.c
··· 93 93 u32 sscr_val, sspsp_val, ssfcr_val, ssrwt_val; 94 94 95 95 sscr_val = SSCR_TRAIL | SSCR_FRF_PSP; 96 - ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 5) | 97 - FIELD_PREP(SSFCR_FIELD_RFT, 5) | 96 + ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 0xF) | 97 + FIELD_PREP(SSFCR_FIELD_RFT, 0xF) | 98 98 SSFCR_RSRE | SSFCR_TSRE; 99 99 ssrwt_val = SSRWT_RWOT; 100 100 sspsp_val = SSPSP_SFRMP; ··· 104 104 writel(sspsp_val, i2s->base + SSPSP); 105 105 writel(ssrwt_val, i2s->base + SSRWT); 106 106 writel(0, i2s->base + SSINTEN); 107 + } 108 + 109 + static int spacemit_i2s_startup(struct snd_pcm_substream *substream, 110 + struct snd_soc_dai *dai) 111 + { 112 + struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); 113 + 114 + switch (i2s->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 115 + case SND_SOC_DAIFMT_I2S: 116 + snd_pcm_hw_constraint_minmax(substream->runtime, 117 + SNDRV_PCM_HW_PARAM_CHANNELS, 118 + 2, 2); 119 + snd_pcm_hw_constraint_mask64(substream->runtime, 120 + SNDRV_PCM_HW_PARAM_FORMAT, 121 + SNDRV_PCM_FMTBIT_S16_LE); 122 + break; 123 + case SND_SOC_DAIFMT_DSP_A: 124 + case SND_SOC_DAIFMT_DSP_B: 125 + snd_pcm_hw_constraint_minmax(substream->runtime, 126 + SNDRV_PCM_HW_PARAM_CHANNELS, 127 + 1, 1); 128 + snd_pcm_hw_constraint_mask64(substream->runtime, 129 + SNDRV_PCM_HW_PARAM_FORMAT, 130 + SNDRV_PCM_FMTBIT_S32_LE); 131 + break; 132 + default: 133 + dev_dbg(i2s->dev, "unexpected format type"); 134 + return -EINVAL; 135 + } 136 + 137 + return 0; 107 138 } 108 139 109 140 static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, ··· 188 157 dma_data->maxburst = 32; 189 158 dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 190 159 } 191 - 192 - snd_pcm_hw_constraint_minmax(substream->runtime, 193 - SNDRV_PCM_HW_PARAM_CHANNELS, 194 - 1, 2); 195 - snd_pcm_hw_constraint_mask64(substream->runtime, 196 - SNDRV_PCM_HW_PARAM_FORMAT, 197 - SNDRV_PCM_FMTBIT_S16_LE); 198 160 break; 199 161 case SND_SOC_DAIFMT_DSP_A: 200 162 case SND_SOC_DAIFMT_DSP_B: 201 - snd_pcm_hw_constraint_minmax(substream->runtime, 202 - SNDRV_PCM_HW_PARAM_CHANNELS, 203 - 1, 1); 204 - snd_pcm_hw_constraint_mask64(substream->runtime, 205 - SNDRV_PCM_HW_PARAM_FORMAT, 206 - SNDRV_PCM_FMTBIT_S32_LE); 207 163 break; 208 164 default: 209 165 dev_dbg(i2s->dev, "unexpected format type"); ··· 321 303 static const struct snd_soc_dai_ops spacemit_i2s_dai_ops = { 322 304 .probe = spacemit_i2s_dai_probe, 323 305 .remove = spacemit_i2s_dai_remove, 306 + .startup = spacemit_i2s_startup, 324 307 .hw_params = spacemit_i2s_hw_params, 325 308 .set_sysclk = spacemit_i2s_set_sysclk, 326 309 .set_fmt = spacemit_i2s_set_fmt,
-1
sound/soc/tegra/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 # Tegra platform Support 3 3 snd-soc-tegra-pcm-y := tegra_pcm.o 4 - snd-soc-tegra-utils-y += tegra_asoc_utils.o 5 4 snd-soc-tegra20-ac97-y := tegra20_ac97.o 6 5 snd-soc-tegra20-das-y := tegra20_das.o 7 6 snd-soc-tegra20-i2s-y := tegra20_i2s.o