Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-6.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- A handful of build fixes for the T-Head errata, including some
functional issues the compilers found
- A fix for a nasty sigreturn bug
* tag 'riscv-for-linus-6.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
RISC-V: Avoid coupling the T-Head CMOs and Zicbom
riscv: fix a nasty sigreturn bug...
riscv: make t-head erratas depend on MMU
riscv: fix RISCV_ISA_SVPBMT kconfig dependency warning
RISC-V: Clean up the Zicbom block size probing
+25
-13
+1
arch/riscv/Kconfig
+1
arch/riscv/Kconfig
+2
-2
arch/riscv/Kconfig.erratas
+2
-2
arch/riscv/Kconfig.erratas
···
46
46
47
47
config ERRATA_THEAD_PBMT
48
48
bool "Apply T-Head memory type errata"
49
-
depends on ERRATA_THEAD && 64BIT
49
+
depends on ERRATA_THEAD && 64BIT && MMU
50
50
select RISCV_ALTERNATIVE_EARLY
51
51
default y
52
52
help
···
57
57
58
58
config ERRATA_THEAD_CMO
59
59
bool "Apply T-Head cache management errata"
60
-
depends on ERRATA_THEAD
60
+
depends on ERRATA_THEAD && MMU
61
61
select RISCV_DMA_NONCOHERENT
62
62
default y
63
63
help
+1
arch/riscv/errata/thead/errata.c
+1
arch/riscv/errata/thead/errata.c
+5
arch/riscv/include/asm/cacheflush.h
+5
arch/riscv/include/asm/cacheflush.h
···
42
42
43
43
#endif /* CONFIG_SMP */
44
44
45
+
/*
46
+
* The T-Head CMO errata internally probe the CBOM block size, but otherwise
47
+
* don't depend on Zicbom.
48
+
*/
49
+
extern unsigned int riscv_cbom_block_size;
45
50
#ifdef CONFIG_RISCV_ISA_ZICBOM
46
51
void riscv_init_cbom_blocksize(void);
47
52
#else
+1
-1
arch/riscv/kernel/setup.c
+1
-1
arch/riscv/kernel/setup.c
+2
arch/riscv/kernel/signal.c
+2
arch/riscv/kernel/signal.c
+13
-10
arch/riscv/mm/dma-noncoherent.c
+13
-10
arch/riscv/mm/dma-noncoherent.c
···
12
12
#include <linux/of_device.h>
13
13
#include <asm/cacheflush.h>
14
14
15
-
static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
15
+
unsigned int riscv_cbom_block_size;
16
16
static bool noncoherent_supported;
17
17
18
18
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
···
79
79
void riscv_init_cbom_blocksize(void)
80
80
{
81
81
struct device_node *node;
82
+
unsigned long cbom_hartid;
83
+
u32 val, probed_block_size;
82
84
int ret;
83
-
u32 val;
84
85
86
+
probed_block_size = 0;
85
87
for_each_of_cpu_node(node) {
86
88
unsigned long hartid;
87
-
int cbom_hartid;
88
89
89
90
ret = riscv_of_processor_hartid(node, &hartid);
90
91
if (ret)
91
-
continue;
92
-
93
-
if (hartid < 0)
94
92
continue;
95
93
96
94
/* set block-size for cbom extension if available */
···
96
98
if (ret)
97
99
continue;
98
100
99
-
if (!riscv_cbom_block_size) {
100
-
riscv_cbom_block_size = val;
101
+
if (!probed_block_size) {
102
+
probed_block_size = val;
101
103
cbom_hartid = hartid;
102
104
} else {
103
-
if (riscv_cbom_block_size != val)
104
-
pr_warn("cbom-block-size mismatched between harts %d and %lu\n",
105
+
if (probed_block_size != val)
106
+
pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
105
107
cbom_hartid, hartid);
106
108
}
107
109
}
110
+
111
+
if (probed_block_size)
112
+
riscv_cbom_block_size = probed_block_size;
108
113
}
109
114
#endif
110
115
111
116
void riscv_noncoherent_supported(void)
112
117
{
118
+
WARN(!riscv_cbom_block_size,
119
+
"Non-coherent DMA support enabled without a block size\n");
113
120
noncoherent_supported = true;
114
121
}