Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2019-12-21' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Probably the last one before Christmas, I'll see if there is much
demand over next few weeks for more fixes, I expect it'll be quiet
enough.
This has one exynos fix, and a bunch of i915 core and i915 GVT fixes.
Summary:
exynos:
- component delete fix
i915:
- Fix to drop an unused and harmful display W/A
- Fix to define EHL power wells independent of ICL
- Fix for priority inversion on bonded requests
- Fix in mmio offset calculation of DSB instance
- Fix memory leak from get_task_pid when banning clients
- Fixes to avoid dereference of uninitialized ops in dma_fence
tracing and keep reference to execbuf object until submitted.
- vGPU state setting locking fix (Zhenyu)
- Fix vGPU display dmabuf as read-only (Zhenyu)
- Properly handle vGPU display dmabuf page pin when rendering (Tina)
- Fix one guest boot warning to handle guc reset state (Fred)"
* tag 'drm-fixes-2019-12-21' of git://anongit.freedesktop.org/drm/drm:
drm/exynos: gsc: add missed component_del
drm/i915: Fix pid leak with banned clients
drm/i915/gem: Keep request alive while attaching fences
drm/i915: Fix WARN_ON condition for cursor plane ddb allocation
drm/i915/gvt: Fix guest boot warning
drm/i915/tgl: Drop Wa#1178
drm/i915/ehl: Define EHL powerwells independently of ICL
drm/i915: Set fence_work.ops before dma_fence_init
drm/i915: Copy across scheduler behaviour flags across submit fences
drm/i915/dsb: Fix in mmio offset calculation of DSB instance
drm/i915/gvt: Pin vgpu dma address before using
drm/i915/gvt: set guest display buffer as readonly
drm/i915/gvt: use vgpu lock for active state setting
+366
-45
+1
drivers/gpu/drm/exynos/exynos_drm_gsc.c
+1
drivers/gpu/drm/exynos/exynos_drm_gsc.c
+150
-3
drivers/gpu/drm/i915/display/intel_display_power.c
+150
-3
drivers/gpu/drm/i915/display/intel_display_power.c
···
3688
3688
},
3689
3689
};
3690
3690
3691
+
static const struct i915_power_well_desc ehl_power_wells[] = {
3692
+
{
3693
+
.name = "always-on",
3694
+
.always_on = true,
3695
+
.domains = POWER_DOMAIN_MASK,
3696
+
.ops = &i9xx_always_on_power_well_ops,
3697
+
.id = DISP_PW_ID_NONE,
3698
+
},
3699
+
{
3700
+
.name = "power well 1",
3701
+
/* Handled by the DMC firmware */
3702
+
.always_on = true,
3703
+
.domains = 0,
3704
+
.ops = &hsw_power_well_ops,
3705
+
.id = SKL_DISP_PW_1,
3706
+
{
3707
+
.hsw.regs = &hsw_power_well_regs,
3708
+
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
3709
+
.hsw.has_fuses = true,
3710
+
},
3711
+
},
3712
+
{
3713
+
.name = "DC off",
3714
+
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
3715
+
.ops = &gen9_dc_off_power_well_ops,
3716
+
.id = SKL_DISP_DC_OFF,
3717
+
},
3718
+
{
3719
+
.name = "power well 2",
3720
+
.domains = ICL_PW_2_POWER_DOMAINS,
3721
+
.ops = &hsw_power_well_ops,
3722
+
.id = SKL_DISP_PW_2,
3723
+
{
3724
+
.hsw.regs = &hsw_power_well_regs,
3725
+
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
3726
+
.hsw.has_fuses = true,
3727
+
},
3728
+
},
3729
+
{
3730
+
.name = "power well 3",
3731
+
.domains = ICL_PW_3_POWER_DOMAINS,
3732
+
.ops = &hsw_power_well_ops,
3733
+
.id = DISP_PW_ID_NONE,
3734
+
{
3735
+
.hsw.regs = &hsw_power_well_regs,
3736
+
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
3737
+
.hsw.irq_pipe_mask = BIT(PIPE_B),
3738
+
.hsw.has_vga = true,
3739
+
.hsw.has_fuses = true,
3740
+
},
3741
+
},
3742
+
{
3743
+
.name = "DDI A IO",
3744
+
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
3745
+
.ops = &hsw_power_well_ops,
3746
+
.id = DISP_PW_ID_NONE,
3747
+
{
3748
+
.hsw.regs = &icl_ddi_power_well_regs,
3749
+
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
3750
+
},
3751
+
},
3752
+
{
3753
+
.name = "DDI B IO",
3754
+
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
3755
+
.ops = &hsw_power_well_ops,
3756
+
.id = DISP_PW_ID_NONE,
3757
+
{
3758
+
.hsw.regs = &icl_ddi_power_well_regs,
3759
+
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
3760
+
},
3761
+
},
3762
+
{
3763
+
.name = "DDI C IO",
3764
+
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
3765
+
.ops = &hsw_power_well_ops,
3766
+
.id = DISP_PW_ID_NONE,
3767
+
{
3768
+
.hsw.regs = &icl_ddi_power_well_regs,
3769
+
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
3770
+
},
3771
+
},
3772
+
{
3773
+
.name = "DDI D IO",
3774
+
.domains = ICL_DDI_IO_D_POWER_DOMAINS,
3775
+
.ops = &hsw_power_well_ops,
3776
+
.id = DISP_PW_ID_NONE,
3777
+
{
3778
+
.hsw.regs = &icl_ddi_power_well_regs,
3779
+
.hsw.idx = ICL_PW_CTL_IDX_DDI_D,
3780
+
},
3781
+
},
3782
+
{
3783
+
.name = "AUX A",
3784
+
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
3785
+
.ops = &hsw_power_well_ops,
3786
+
.id = DISP_PW_ID_NONE,
3787
+
{
3788
+
.hsw.regs = &icl_aux_power_well_regs,
3789
+
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
3790
+
},
3791
+
},
3792
+
{
3793
+
.name = "AUX B",
3794
+
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
3795
+
.ops = &hsw_power_well_ops,
3796
+
.id = DISP_PW_ID_NONE,
3797
+
{
3798
+
.hsw.regs = &icl_aux_power_well_regs,
3799
+
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
3800
+
},
3801
+
},
3802
+
{
3803
+
.name = "AUX C",
3804
+
.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
3805
+
.ops = &hsw_power_well_ops,
3806
+
.id = DISP_PW_ID_NONE,
3807
+
{
3808
+
.hsw.regs = &icl_aux_power_well_regs,
3809
+
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
3810
+
},
3811
+
},
3812
+
{
3813
+
.name = "AUX D",
3814
+
.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
3815
+
.ops = &hsw_power_well_ops,
3816
+
.id = DISP_PW_ID_NONE,
3817
+
{
3818
+
.hsw.regs = &icl_aux_power_well_regs,
3819
+
.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
3820
+
},
3821
+
},
3822
+
{
3823
+
.name = "power well 4",
3824
+
.domains = ICL_PW_4_POWER_DOMAINS,
3825
+
.ops = &hsw_power_well_ops,
3826
+
.id = DISP_PW_ID_NONE,
3827
+
{
3828
+
.hsw.regs = &hsw_power_well_regs,
3829
+
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
3830
+
.hsw.has_fuses = true,
3831
+
.hsw.irq_pipe_mask = BIT(PIPE_C),
3832
+
},
3833
+
},
3834
+
};
3835
+
3691
3836
static const struct i915_power_well_desc tgl_power_wells[] = {
3692
3837
{
3693
3838
.name = "always-on",
···
3977
3832
{
3978
3833
.name = "AUX A",
3979
3834
.domains = TGL_AUX_A_IO_POWER_DOMAINS,
3980
-
.ops = &icl_combo_phy_aux_power_well_ops,
3835
+
.ops = &hsw_power_well_ops,
3981
3836
.id = DISP_PW_ID_NONE,
3982
3837
{
3983
3838
.hsw.regs = &icl_aux_power_well_regs,
···
3987
3842
{
3988
3843
.name = "AUX B",
3989
3844
.domains = TGL_AUX_B_IO_POWER_DOMAINS,
3990
-
.ops = &icl_combo_phy_aux_power_well_ops,
3845
+
.ops = &hsw_power_well_ops,
3991
3846
.id = DISP_PW_ID_NONE,
3992
3847
{
3993
3848
.hsw.regs = &icl_aux_power_well_regs,
···
3997
3852
{
3998
3853
.name = "AUX C",
3999
3854
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
4000
-
.ops = &icl_combo_phy_aux_power_well_ops,
3855
+
.ops = &hsw_power_well_ops,
4001
3856
.id = DISP_PW_ID_NONE,
4002
3857
{
4003
3858
.hsw.regs = &icl_aux_power_well_regs,
···
4307
4162
*/
4308
4163
if (IS_GEN(dev_priv, 12)) {
4309
4164
err = set_power_wells(power_domains, tgl_power_wells);
4165
+
} else if (IS_ELKHARTLAKE(dev_priv)) {
4166
+
err = set_power_wells(power_domains, ehl_power_wells);
4310
4167
} else if (IS_GEN(dev_priv, 11)) {
4311
4168
err = set_power_wells(power_domains, icl_power_wells);
4312
4169
} else if (IS_CANNONLAKE(dev_priv)) {
+1
-2
drivers/gpu/drm/i915/gem/i915_gem_context.c
+1
-2
drivers/gpu/drm/i915/gem/i915_gem_context.c
···
2167
2167
ext_data.fpriv = file->driver_priv;
2168
2168
if (client_is_banned(ext_data.fpriv)) {
2169
2169
DRM_DEBUG("client %s[%d] banned from creating ctx\n",
2170
-
current->comm,
2171
-
pid_nr(get_task_pid(current, PIDTYPE_PID)));
2170
+
current->comm, task_pid_nr(current));
2172
2171
return -EIO;
2173
2172
}
2174
2173
+2
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+2
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
···
2694
2694
err = eb_submit(&eb);
2695
2695
err_request:
2696
2696
add_to_client(eb.request, file);
2697
+
i915_request_get(eb.request);
2697
2698
i915_request_add(eb.request);
2698
2699
2699
2700
if (fences)
···
2710
2709
fput(out_fence->file);
2711
2710
}
2712
2711
}
2712
+
i915_request_put(eb.request);
2713
2713
2714
2714
err_batch_unpin:
2715
2715
if (eb.batch_flags & I915_DISPATCH_SECURE)
+60
-4
drivers/gpu/drm/i915/gvt/dmabuf.c
+60
-4
drivers/gpu/drm/i915/gvt/dmabuf.c
···
36
36
37
37
#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
38
38
39
+
static int vgpu_pin_dma_address(struct intel_vgpu *vgpu,
40
+
unsigned long size,
41
+
dma_addr_t dma_addr)
42
+
{
43
+
int ret = 0;
44
+
45
+
if (intel_gvt_hypervisor_dma_pin_guest_page(vgpu, dma_addr))
46
+
ret = -EINVAL;
47
+
48
+
return ret;
49
+
}
50
+
51
+
static void vgpu_unpin_dma_address(struct intel_vgpu *vgpu,
52
+
dma_addr_t dma_addr)
53
+
{
54
+
intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, dma_addr);
55
+
}
56
+
39
57
static int vgpu_gem_get_pages(
40
58
struct drm_i915_gem_object *obj)
41
59
{
42
60
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
61
+
struct intel_vgpu *vgpu;
43
62
struct sg_table *st;
44
63
struct scatterlist *sg;
45
-
int i, ret;
64
+
int i, j, ret;
46
65
gen8_pte_t __iomem *gtt_entries;
47
66
struct intel_vgpu_fb_info *fb_info;
48
67
u32 page_num;
49
68
50
69
fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info;
51
70
if (WARN_ON(!fb_info))
71
+
return -ENODEV;
72
+
73
+
vgpu = fb_info->obj->vgpu;
74
+
if (WARN_ON(!vgpu))
52
75
return -ENODEV;
53
76
54
77
st = kmalloc(sizeof(*st), GFP_KERNEL);
···
87
64
gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
88
65
(fb_info->start >> PAGE_SHIFT);
89
66
for_each_sg(st->sgl, sg, page_num, i) {
67
+
dma_addr_t dma_addr =
68
+
GEN8_DECODE_PTE(readq(>t_entries[i]));
69
+
if (vgpu_pin_dma_address(vgpu, PAGE_SIZE, dma_addr)) {
70
+
ret = -EINVAL;
71
+
goto out;
72
+
}
73
+
90
74
sg->offset = 0;
91
75
sg->length = PAGE_SIZE;
92
-
sg_dma_address(sg) =
93
-
GEN8_DECODE_PTE(readq(>t_entries[i]));
94
76
sg_dma_len(sg) = PAGE_SIZE;
77
+
sg_dma_address(sg) = dma_addr;
95
78
}
96
79
97
80
__i915_gem_object_set_pages(obj, st, PAGE_SIZE);
81
+
out:
82
+
if (ret) {
83
+
dma_addr_t dma_addr;
98
84
99
-
return 0;
85
+
for_each_sg(st->sgl, sg, i, j) {
86
+
dma_addr = sg_dma_address(sg);
87
+
if (dma_addr)
88
+
vgpu_unpin_dma_address(vgpu, dma_addr);
89
+
}
90
+
sg_free_table(st);
91
+
kfree(st);
92
+
}
93
+
94
+
return ret;
95
+
100
96
}
101
97
102
98
static void vgpu_gem_put_pages(struct drm_i915_gem_object *obj,
103
99
struct sg_table *pages)
104
100
{
101
+
struct scatterlist *sg;
102
+
103
+
if (obj->base.dma_buf) {
104
+
struct intel_vgpu_fb_info *fb_info = obj->gvt_info;
105
+
struct intel_vgpu_dmabuf_obj *obj = fb_info->obj;
106
+
struct intel_vgpu *vgpu = obj->vgpu;
107
+
int i;
108
+
109
+
for_each_sg(pages->sgl, sg, fb_info->size, i)
110
+
vgpu_unpin_dma_address(vgpu,
111
+
sg_dma_address(sg));
112
+
}
113
+
105
114
sg_free_table(pages);
106
115
kfree(pages);
107
116
}
···
218
163
drm_gem_private_object_init(dev, &obj->base,
219
164
roundup(info->size, PAGE_SIZE));
220
165
i915_gem_object_init(obj, &intel_vgpu_gem_ops, &lock_class);
166
+
i915_gem_object_set_readonly(obj);
221
167
222
168
obj->read_domains = I915_GEM_DOMAIN_GTT;
223
169
obj->write_domain = 0;
+16
drivers/gpu/drm/i915/gvt/handlers.c
+16
drivers/gpu/drm/i915/gvt/handlers.c
···
341
341
gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
342
342
engine_mask |= BIT(VCS1);
343
343
}
344
+
if (data & GEN9_GRDOM_GUC) {
345
+
gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
346
+
vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
347
+
}
344
348
engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;
345
349
}
346
350
···
1640
1636
return 0;
1641
1637
}
1642
1638
1639
+
static int guc_status_read(struct intel_vgpu *vgpu,
1640
+
unsigned int offset, void *p_data,
1641
+
unsigned int bytes)
1642
+
{
1643
+
/* keep MIA_IN_RESET before clearing */
1644
+
read_vreg(vgpu, offset, p_data, bytes);
1645
+
vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
1646
+
return 0;
1647
+
}
1648
+
1643
1649
static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1644
1650
unsigned int offset, void *p_data, unsigned int bytes)
1645
1651
{
···
2686
2672
2687
2673
MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2688
2674
MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2675
+
MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
2676
+
2689
2677
return 0;
2690
2678
}
2691
2679
+2
drivers/gpu/drm/i915/gvt/hypercall.h
+2
drivers/gpu/drm/i915/gvt/hypercall.h
···
62
62
unsigned long size, dma_addr_t *dma_addr);
63
63
void (*dma_unmap_guest_page)(unsigned long handle, dma_addr_t dma_addr);
64
64
65
+
int (*dma_pin_guest_page)(unsigned long handle, dma_addr_t dma_addr);
66
+
65
67
int (*map_gfn_to_mfn)(unsigned long handle, unsigned long gfn,
66
68
unsigned long mfn, unsigned int nr, bool map);
67
69
int (*set_trap_area)(unsigned long handle, u64 start, u64 end,
+23
drivers/gpu/drm/i915/gvt/kvmgt.c
+23
drivers/gpu/drm/i915/gvt/kvmgt.c
···
1916
1916
return ret;
1917
1917
}
1918
1918
1919
+
static int kvmgt_dma_pin_guest_page(unsigned long handle, dma_addr_t dma_addr)
1920
+
{
1921
+
struct kvmgt_guest_info *info;
1922
+
struct gvt_dma *entry;
1923
+
int ret = 0;
1924
+
1925
+
if (!handle_valid(handle))
1926
+
return -ENODEV;
1927
+
1928
+
info = (struct kvmgt_guest_info *)handle;
1929
+
1930
+
mutex_lock(&info->vgpu->vdev.cache_lock);
1931
+
entry = __gvt_cache_find_dma_addr(info->vgpu, dma_addr);
1932
+
if (entry)
1933
+
kref_get(&entry->ref);
1934
+
else
1935
+
ret = -ENOMEM;
1936
+
mutex_unlock(&info->vgpu->vdev.cache_lock);
1937
+
1938
+
return ret;
1939
+
}
1940
+
1919
1941
static void __gvt_dma_release(struct kref *ref)
1920
1942
{
1921
1943
struct gvt_dma *entry = container_of(ref, typeof(*entry), ref);
···
2049
2027
.gfn_to_mfn = kvmgt_gfn_to_pfn,
2050
2028
.dma_map_guest_page = kvmgt_dma_map_guest_page,
2051
2029
.dma_unmap_guest_page = kvmgt_dma_unmap_guest_page,
2030
+
.dma_pin_guest_page = kvmgt_dma_pin_guest_page,
2052
2031
.set_opregion = kvmgt_set_opregion,
2053
2032
.set_edid = kvmgt_set_edid,
2054
2033
.get_vfio_device = kvmgt_get_vfio_device,
+15
drivers/gpu/drm/i915/gvt/mpt.h
+15
drivers/gpu/drm/i915/gvt/mpt.h
···
255
255
}
256
256
257
257
/**
258
+
* intel_gvt_hypervisor_dma_pin_guest_page - pin guest dma buf
259
+
* @vgpu: a vGPU
260
+
* @dma_addr: guest dma addr
261
+
*
262
+
* Returns:
263
+
* 0 on success, negative error code if failed.
264
+
*/
265
+
static inline int
266
+
intel_gvt_hypervisor_dma_pin_guest_page(struct intel_vgpu *vgpu,
267
+
dma_addr_t dma_addr)
268
+
{
269
+
return intel_gvt_host.mpt->dma_pin_guest_page(vgpu->handle, dma_addr);
270
+
}
271
+
272
+
/**
258
273
* intel_gvt_hypervisor_map_gfn_to_mfn - map a GFN region to MFN
259
274
* @vgpu: a vGPU
260
275
* @gfn: guest PFN
+2
-2
drivers/gpu/drm/i915/gvt/vgpu.c
+2
-2
drivers/gpu/drm/i915/gvt/vgpu.c
+2
-4
drivers/gpu/drm/i915/i915_reg.h
+2
-4
drivers/gpu/drm/i915/i915_reg.h
···
9405
9405
#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9406
9406
#define _ICL_AUX_ANAOVRD1_A 0x162398
9407
9407
#define _ICL_AUX_ANAOVRD1_B 0x6C398
9408
-
#define _TGL_AUX_ANAOVRD1_C 0x160398
9409
9408
#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9410
9409
_ICL_AUX_ANAOVRD1_A, \
9411
-
_ICL_AUX_ANAOVRD1_B, \
9412
-
_TGL_AUX_ANAOVRD1_C))
9410
+
_ICL_AUX_ANAOVRD1_B))
9413
9411
#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
9414
9412
#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
9415
9413
···
11992
11994
/* This register controls the Display State Buffer (DSB) engines. */
11993
11995
#define _DSBSL_INSTANCE_BASE 0x70B00
11994
11996
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
11995
-
(pipe) * 0x1000 + (id) * 100)
11997
+
(pipe) * 0x1000 + (id) * 0x100)
11996
11998
#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
11997
11999
#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
11998
12000
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+89
-25
drivers/gpu/drm/i915/i915_request.c
+89
-25
drivers/gpu/drm/i915/i915_request.c
···
300
300
}
301
301
302
302
static int
303
-
__i915_request_await_execution(struct i915_request *rq,
304
-
struct i915_request *signal,
305
-
void (*hook)(struct i915_request *rq,
306
-
struct dma_fence *signal),
307
-
gfp_t gfp)
303
+
__await_execution(struct i915_request *rq,
304
+
struct i915_request *signal,
305
+
void (*hook)(struct i915_request *rq,
306
+
struct dma_fence *signal),
307
+
gfp_t gfp)
308
308
{
309
309
struct execute_cb *cb;
310
310
···
341
341
}
342
342
spin_unlock_irq(&signal->lock);
343
343
344
+
/* Copy across semaphore status as we need the same behaviour */
345
+
rq->sched.flags |= signal->sched.flags;
344
346
return 0;
345
347
}
346
348
···
813
811
}
814
812
815
813
static int
816
-
emit_semaphore_wait(struct i915_request *to,
817
-
struct i915_request *from,
818
-
gfp_t gfp)
814
+
__emit_semaphore_wait(struct i915_request *to,
815
+
struct i915_request *from,
816
+
u32 seqno)
819
817
{
820
818
const int has_token = INTEL_GEN(to->i915) >= 12;
821
819
u32 hwsp_offset;
822
-
int len;
820
+
int len, err;
823
821
u32 *cs;
824
822
825
823
GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
826
824
827
-
/* Just emit the first semaphore we see as request space is limited. */
828
-
if (already_busywaiting(to) & from->engine->mask)
829
-
goto await_fence;
830
-
831
-
if (i915_request_await_start(to, from) < 0)
832
-
goto await_fence;
833
-
834
-
/* Only submit our spinner after the signaler is running! */
835
-
if (__i915_request_await_execution(to, from, NULL, gfp))
836
-
goto await_fence;
837
-
838
825
/* We need to pin the signaler's HWSP until we are finished reading. */
839
-
if (intel_timeline_read_hwsp(from, to, &hwsp_offset))
840
-
goto await_fence;
826
+
err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
827
+
if (err)
828
+
return err;
841
829
842
830
len = 4;
843
831
if (has_token)
···
850
858
MI_SEMAPHORE_POLL |
851
859
MI_SEMAPHORE_SAD_GTE_SDD) +
852
860
has_token;
853
-
*cs++ = from->fence.seqno;
861
+
*cs++ = seqno;
854
862
*cs++ = hwsp_offset;
855
863
*cs++ = 0;
856
864
if (has_token) {
···
859
867
}
860
868
861
869
intel_ring_advance(to, cs);
870
+
return 0;
871
+
}
872
+
873
+
static int
874
+
emit_semaphore_wait(struct i915_request *to,
875
+
struct i915_request *from,
876
+
gfp_t gfp)
877
+
{
878
+
/* Just emit the first semaphore we see as request space is limited. */
879
+
if (already_busywaiting(to) & from->engine->mask)
880
+
goto await_fence;
881
+
882
+
if (i915_request_await_start(to, from) < 0)
883
+
goto await_fence;
884
+
885
+
/* Only submit our spinner after the signaler is running! */
886
+
if (__await_execution(to, from, NULL, gfp))
887
+
goto await_fence;
888
+
889
+
if (__emit_semaphore_wait(to, from, from->fence.seqno))
890
+
goto await_fence;
891
+
862
892
to->sched.semaphores |= from->engine->mask;
863
893
to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
864
894
return 0;
···
994
980
return 0;
995
981
}
996
982
983
+
static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
984
+
struct dma_fence *fence)
985
+
{
986
+
return __intel_timeline_sync_is_later(tl,
987
+
fence->context,
988
+
fence->seqno - 1);
989
+
}
990
+
991
+
static int intel_timeline_sync_set_start(struct intel_timeline *tl,
992
+
const struct dma_fence *fence)
993
+
{
994
+
return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
995
+
}
996
+
997
+
static int
998
+
__i915_request_await_execution(struct i915_request *to,
999
+
struct i915_request *from,
1000
+
void (*hook)(struct i915_request *rq,
1001
+
struct dma_fence *signal))
1002
+
{
1003
+
int err;
1004
+
1005
+
/* Submit both requests at the same time */
1006
+
err = __await_execution(to, from, hook, I915_FENCE_GFP);
1007
+
if (err)
1008
+
return err;
1009
+
1010
+
/* Squash repeated depenendices to the same timelines */
1011
+
if (intel_timeline_sync_has_start(i915_request_timeline(to),
1012
+
&from->fence))
1013
+
return 0;
1014
+
1015
+
/* Ensure both start together [after all semaphores in signal] */
1016
+
if (intel_engine_has_semaphores(to->engine))
1017
+
err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1018
+
else
1019
+
err = i915_request_await_start(to, from);
1020
+
if (err < 0)
1021
+
return err;
1022
+
1023
+
/* Couple the dependency tree for PI on this exposed to->fence */
1024
+
if (to->engine->schedule) {
1025
+
err = i915_sched_node_add_dependency(&to->sched, &from->sched);
1026
+
if (err < 0)
1027
+
return err;
1028
+
}
1029
+
1030
+
return intel_timeline_sync_set_start(i915_request_timeline(to),
1031
+
&from->fence);
1032
+
}
1033
+
997
1034
int
998
1035
i915_request_await_execution(struct i915_request *rq,
999
1036
struct dma_fence *fence,
···
1078
1013
if (dma_fence_is_i915(fence))
1079
1014
ret = __i915_request_await_execution(rq,
1080
1015
to_request(fence),
1081
-
hook,
1082
-
I915_FENCE_GFP);
1016
+
hook);
1083
1017
else
1084
1018
ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
1085
1019
I915_FENCE_TIMEOUT,
-1
drivers/gpu/drm/i915/i915_scheduler.c
-1
drivers/gpu/drm/i915/i915_scheduler.c
+1
-2
drivers/gpu/drm/i915/i915_sw_fence_work.c
+1
-2
drivers/gpu/drm/i915/i915_sw_fence_work.c
···
78
78
void dma_fence_work_init(struct dma_fence_work *f,
79
79
const struct dma_fence_work_ops *ops)
80
80
{
81
+
f->ops = ops;
81
82
spin_lock_init(&f->lock);
82
83
dma_fence_init(&f->dma, &fence_ops, &f->lock, 0, 0);
83
84
i915_sw_fence_init(&f->chain, fence_notify);
84
85
INIT_WORK(&f->work, fence_work);
85
-
86
-
f->ops = ops;
87
86
}
88
87
89
88
int dma_fence_work_chain(struct dma_fence_work *f, struct dma_fence *signal)
+2
-2
drivers/gpu/drm/i915/intel_pm.c
+2
-2
drivers/gpu/drm/i915/intel_pm.c
···
4291
4291
&crtc_state->wm.skl.optimal.planes[plane_id];
4292
4292
4293
4293
if (plane_id == PLANE_CURSOR) {
4294
-
if (WARN_ON(wm->wm[level].min_ddb_alloc >
4295
-
total[PLANE_CURSOR])) {
4294
+
if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
4295
+
WARN_ON(wm->wm[level].min_ddb_alloc != U16_MAX);
4296
4296
blocks = U32_MAX;
4297
4297
break;
4298
4298
}