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kernel
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dt-bindings: clock: qcom: add bindings for dispcc on SM8450
Add device tree bindings for the display clock controller on Qualcomm
SM8450 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220908222850.3552050-2-dmitry.baryshkov@linaro.org
authored by
Dmitry Baryshkov
and committed by
Bjorn Andersson
a7edd291
9b518788
+201
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Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller for SM8450
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SM8450.
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See also:
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include/dt-bindings/clock/qcom,sm8450-dispcc.h
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properties:
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compatible:
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enum:
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- qcom,sm8450-dispcc
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clocks:
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minItems: 3
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items:
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- description: Board XO source
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- description: Board Always On XO source
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- description: Display's AHB clock
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- description: sleep clock
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY1
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY0
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- description: VCO DIV clock from DP PHY0
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- description: Link clock from DP PHY1
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- description: VCO DIV clock from DP PHY1
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- description: Link clock from DP PHY2
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- description: VCO DIV clock from DP PHY2
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- description: Link clock from DP PHY3
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- description: VCO DIV clock from DP PHY3
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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power-domains:
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description:
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A phandle and PM domain specifier for the MMCX power domain.
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maxItems: 1
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required-opps:
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description:
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A phandle to an OPP node describing required MMCX performance point.
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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clock-controller@af00000 {
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compatible = "qcom,sm8450-dispcc";
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reg = <0x0af00000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 0>,
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<&dsi1_phy 1>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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...
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include/dt-bindings/clock/qcom,sm8450-dispcc.h
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include/dt-bindings/clock/qcom,sm8450-dispcc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8450_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8450_H
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/* DISP_CC clocks */
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#define DISP_CC_MDSS_AHB1_CLK 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define DISP_CC_MDSS_BYTE1_CLK 7
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#define DISP_CC_MDSS_BYTE1_CLK_SRC 8
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#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9
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#define DISP_CC_MDSS_BYTE1_INTF_CLK 10
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#define DISP_CC_MDSS_DPTX0_AUX_CLK 11
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#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 12
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#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 13
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#define DISP_CC_MDSS_DPTX0_LINK_CLK 14
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#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15
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#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16
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#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21
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#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22
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#define DISP_CC_MDSS_DPTX1_AUX_CLK 23
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#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24
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#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 25
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#define DISP_CC_MDSS_DPTX1_LINK_CLK 26
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#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 27
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#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 28
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#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 29
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 30
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 31
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 32
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 33
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#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 34
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#define DISP_CC_MDSS_DPTX2_AUX_CLK 35
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#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 36
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#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 37
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#define DISP_CC_MDSS_DPTX2_LINK_CLK 38
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#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 39
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#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 40
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#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 41
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 42
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 43
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 44
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 45
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#define DISP_CC_MDSS_DPTX3_AUX_CLK 46
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#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 47
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#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 48
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#define DISP_CC_MDSS_DPTX3_LINK_CLK 49
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#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 50
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#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 51
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#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 52
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 53
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 54
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#define DISP_CC_MDSS_ESC0_CLK 55
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#define DISP_CC_MDSS_ESC0_CLK_SRC 56
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#define DISP_CC_MDSS_ESC1_CLK 57
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#define DISP_CC_MDSS_ESC1_CLK_SRC 58
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#define DISP_CC_MDSS_MDP1_CLK 59
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#define DISP_CC_MDSS_MDP_CLK 60
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#define DISP_CC_MDSS_MDP_CLK_SRC 61
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#define DISP_CC_MDSS_MDP_LUT1_CLK 62
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#define DISP_CC_MDSS_MDP_LUT_CLK 63
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 64
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#define DISP_CC_MDSS_PCLK0_CLK 65
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 66
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#define DISP_CC_MDSS_PCLK1_CLK 67
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#define DISP_CC_MDSS_PCLK1_CLK_SRC 68
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#define DISP_CC_MDSS_ROT1_CLK 69
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#define DISP_CC_MDSS_ROT_CLK 70
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#define DISP_CC_MDSS_ROT_CLK_SRC 71
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#define DISP_CC_MDSS_RSCC_AHB_CLK 72
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 73
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#define DISP_CC_MDSS_VSYNC1_CLK 74
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#define DISP_CC_MDSS_VSYNC_CLK 75
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 76
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#define DISP_CC_PLL0 77
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#define DISP_CC_PLL1 78
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#define DISP_CC_SLEEP_CLK 79
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#define DISP_CC_SLEEP_CLK_SRC 80
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#define DISP_CC_XO_CLK 81
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#define DISP_CC_XO_CLK_SRC 82
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_CORE_INT2_BCR 1
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#define DISP_CC_MDSS_RSCC_BCR 2
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/* DISP_CC GDSCR */
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#define MDSS_GDSC 0
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#define MDSS_INT2_GDSC 1
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#endif