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Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml

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··· 17 17 The Coresight dummy source component is for the specific coresight source 18 18 devices kernel don't have permission to access or configure. For some SOCs, 19 19 there would be Coresight source trace components on sub-processor which 20 20 - are conneted to AP processor via debug bus. For these devices, a dummy driver 20 20 + are connected to AP processor via debug bus. For these devices, a dummy driver 21 21 is needed to register them as Coresight source devices, so that paths can be 22 22 created in the driver. It provides Coresight API for operations on dummy 23 23 source devices, such as enabling and disabling them. It also provides the

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Documentation/devicetree/bindings/cpu/idle-states.yaml

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··· 385 385 386 386 This property is required in idle state nodes of device tree meant 387 387 for RISC-V systems. For more details on the suspend_type parameter 388 388 - refer the SBI specifiation v0.3 (or higher) [7]. 388 388 + refer the SBI specification v0.3 (or higher) [7]. 389 389 390 390 local-timer-stop: 391 391 description:

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Documentation/devicetree/bindings/display/lvds.yaml

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··· 16 16 description: 17 17 This binding extends the data mapping defined in lvds-data-mapping.yaml. 18 18 It supports reversing the bit order on the formats defined there in order 19 19 - to accomodate for even more specialized data formats, since a variety of 19 19 + to accommodate for even more specialized data formats, since a variety of 20 20 data formats and layouts is used to drive LVDS displays. 21 21 22 22 properties:

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Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt

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··· 20 20 memcpy channels in eDMA. 21 21 22 22 Notes: 23 23 - When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request 23 23 + When requesting channel via ti,dra7-dma-crossbar, the DMA client must request 24 24 the DMA event number as crossbar ID (input to the DMA crossbar). 25 25 26 26 For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:

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Documentation/devicetree/bindings/iio/accel/lis302.txt

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··· 36 36 - st,irq{1,2}-disable: disable IRQ 1/2 37 37 - st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition 38 38 - st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition 39 39 - - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready contition 39 39 + - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready condition 40 40 - st,irq{1,2}-click: raise IRQ 1/2 on click condition 41 41 - st,irq-open-drain: consider IRQ lines open-drain 42 42 - st,irq-active-low: make IRQ lines active low

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Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

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··· 60 60 The 4th cell is a phandle to a node describing a set of CPUs this 61 61 interrupt is affine to. The interrupt must be a PPI, and the node 62 62 pointed must be a subnode of the "ppi-partitions" subnode. For 63 63 - interrupt types other than PPI or PPIs that are not partitionned, 63 63 + interrupt types other than PPI or PPIs that are not partitioned, 64 64 this cell must be zero. See the "ppi-partitions" node description 65 65 below. 66 66

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Documentation/devicetree/bindings/leds/awinic,aw200xx.yaml

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··· 66 66 IMAXled = 160000 * (592 / 600.5) * (1 / max-current-switch-number) 67 67 And the minimum output current formula: 68 68 IMINled = 3300 * (592 / 600.5) * (1 / max-current-switch-number) 69 69 - where max-current-switch-number is determinated by led configuration 69 69 + where max-current-switch-number is determined by led configuration 70 70 and depends on how leds are physically connected to the led driver. 71 71 72 72 allOf:

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Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt

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··· 24 24 number of completion messages for which FlexRM will inject 25 25 one MSI interrupt to CPU. 26 26 27 27 - The 3nd cell contains MSI timer value representing time for 27 27 + The 3rd cell contains MSI timer value representing time for 28 28 which FlexRM will wait to accumulate N completion messages 29 29 where N is the value specified by 2nd cell above. If FlexRM 30 30 does not get required number of completion messages in time

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Documentation/devicetree/bindings/media/i2c/thine,thp7312.yaml

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··· 16 16 can be connected to CMOS image sensors from various vendors, supporting both 17 17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2 18 18 or parallel. The hardware is capable of transmitting and receiving MIPI 19 19 - interlaved data strams with data types or multiple virtual channel 19 19 + interleaved data streams with data types or multiple virtual channel 20 20 identifiers. 21 21 22 22 allOf:

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Documentation/devicetree/bindings/media/samsung,exynos4210-fimc.yaml

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··· 77 77 $ref: /schemas/types.yaml#/definitions/uint32-array 78 78 maxItems: 2 79 79 description: | 80 80 - An array specyfing minimum image size in pixels at the FIMC input and 80 80 + An array specifying minimum image size in pixels at the FIMC input and 81 81 output DMA, in the first and second cell respectively. Default value 82 82 is <16 16>. 83 83

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Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml

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··· 25 25 description: 26 26 The PMIC provides intb and errb IRQ lines. The errb IRQ line is used 27 27 for fatal IRQs which will cause the PMIC to shut down power outputs. 28 28 - In many systems this will shut down the SoC contolling the PMIC and 28 28 + In many systems this will shut down the SoC controlling the PMIC and 29 29 connecting/handling the errb can be omitted. However, there are cases 30 30 where the SoC is not powered by the PMIC or has a short time backup 31 31 energy to handle shutdown of critical hardware. In that case it may be

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Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml

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··· 53 53 samsung,s2mps11-wrstbi-ground: 54 54 description: | 55 55 Indicates that WRSTBI pin of PMIC is pulled down. When the system is 56 56 - suspended it will always go down thus triggerring unwanted buck warm 56 56 + suspended it will always go down thus triggering unwanted buck warm 57 57 reset (setting buck voltages to default values). 58 58 type: boolean 59 59

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Documentation/devicetree/bindings/mfd/twl6040.txt

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··· 2 2 3 3 The TWL6040s are 8-channel high quality low-power audio codecs providing audio, 4 4 vibra and GPO functionality on OMAP4+ platforms. 5 5 - They are connected ot the host processor via i2c for commands, McPDM for audio 5 5 + They are connected to the host processor via i2c for commands, McPDM for audio 6 6 data and commands. 7 7 8 8 Required properties:

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Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml

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··· 72 72 description: VDD_RFA_CMN supply regulator handle 73 73 74 74 vddrfa0p8-supply: 75 75 - description: VDD_RFA_0P8 suppply regulator handle 75 75 + description: VDD_RFA_0P8 supply regulator handle 76 76 77 77 vddrfa1p7-supply: 78 78 description: VDD_RFA_1P7 supply regulator handle

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Documentation/devicetree/bindings/phy/apm-xgene-phy.txt

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··· 36 36 3-tuple setting for each (up to 3) supported link 37 37 speed on the host. Range is 0 to 273000 in unit of 38 38 uV. Default is 0. 39 39 - - apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of 39 39 + - apm,tx-pre-cursor2 : 2nd pre-cursor emphasis taps control. Two set of 40 40 3-tuple setting for each (up to 3) supported link 41 41 speed on the host. Range is 0 to 127400 in unit uV. 42 42 Default is 0x0.

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Documentation/devicetree/bindings/phy/mediatek,mt7988-xfi-tphy.yaml

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··· 41 41 description: 42 42 One instance of the T-PHY on MT7988 suffers from a performance 43 43 problem in 10GBase-R mode which needs a work-around in the driver. 44 44 - This flag enables a work-around ajusting an analog phy setting and 44 44 + This flag enables a work-around adjusting an analog phy setting and 45 45 is required for XFI Port0 of the MT7988 SoC to be in compliance with 46 46 the SFP specification. 47 47

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Documentation/devicetree/bindings/phy/mediatek,tphy.yaml

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··· 240 240 The force mode is used to manually switch the shared phy mode between 241 241 USB3 and PCIe, when USB3 phy type is selected by the consumer, and 242 242 force-mode is set, will cause phy's power and pipe toggled and force 243 243 - phy as USB3 mode which switched from default PCIe mode. But perfer to 243 243 + phy as USB3 mode which switched from default PCIe mode. But prefer to 244 244 use the property "mediatek,syscon-type" for newer SoCs that support it. 245 245 type: boolean 246 246

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Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml

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··· 43 43 44 44 qcom,tune-usb2-amplitude: 45 45 $ref: /schemas/types.yaml#/definitions/uint8 46 46 - description: High-Speed trasmit amplitude 46 46 + description: High-Speed transmit amplitude 47 47 minimum: 0 48 48 maximum: 15 49 49 default: 8

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Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml

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··· 11 11 - Alexandre TORGUE <alexandre.torgue@foss.st.com> 12 12 13 13 description: | 14 14 - STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware 14 14 + STMicroelectronics's STM32 MCUs integrate a GPIO and Pin mux/config hardware 15 15 controller. It controls the input/output settings on the available pins and 16 16 also provides ability to multiplex and configure the output of various 17 17 on-chip controllers onto these pads. ··· 164 164 This macro is available here: 165 165 - include/dt-bindings/pinctrl/stm32-pinfunc.h 166 166 Some examples of using macro: 167 167 - /* GPIO A9 set as alernate function 2 */ 167 167 + /* GPIO A9 set as alternate function 2 */ 168 168 ... { 169 169 pinmux = <STM32_PINMUX('A', 9, AF2)>; 170 170 };

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Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml

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··· 93 93 Each SCP core has own cache memory. The SRAM and L1TCM are shared by 94 94 cores. The power of cache, SRAM and L1TCM power should be enabled 95 95 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied 96 96 - on differnt SoCs. 96 96 + on different SoCs. 97 97 98 98 The SCP cores do not use an MMU, but has a set of registers to 99 99 control the translations between 32-bit CPU addresses into system bus

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Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml

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··· 78 78 we use nvidia,adjust-baud-rates. 79 79 80 80 As an example, consider there is deviation observed in TX for baud rates as listed below. 0 81 81 - to 9600 has 1% deviation 9600 to 115200 2% deviation. This slight deviation is expcted and 81 81 + to 9600 has 1% deviation 9600 to 115200 2% deviation. This slight deviation is expected and 82 82 Tegra UART is expected to handle it. Due to the issue stated above, baud rate on Tegra UART 83 83 should be set equal to or above deviation observed for avoiding frame errors. Property 84 84 should be set like this:

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Documentation/devicetree/bindings/sound/everest,es8326.yaml

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··· 32 32 description: | 33 33 just the value of reg 57. Bit(3) decides whether the jack polarity is inverted. 34 34 Bit(2) decides whether the button on the headset is inverted. 35 35 - Bit(1)/(0) decides the mic properity to be OMTP/CTIA or auto. 35 35 + Bit(1)/(0) decides the mic property to be OMTP/CTIA or auto. 36 36 minimum: 0x00 37 37 maximum: 0x0f 38 38 default: 0x0f

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Documentation/devicetree/bindings/sound/st,sta350.txt

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··· 77 77 78 78 - st,odd-pwm-speed-mode: 79 79 If present, PWM speed mode run on odd speed mode (341.3 kHz) on all 80 80 - channels. If not present, normal PWM spped mode (384 kHz) will be used. 80 80 + channels. If not present, normal PWM speed mode (384 kHz) will be used. 81 81 82 82 - st,distortion-compensation: 83 83 If present, distortion compensation variable uses DCC coefficient.

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Documentation/devicetree/bindings/thermal/qcom-tsens.yaml

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··· 310 310 311 311 - | 312 312 #include <dt-bindings/interrupt-controller/arm-gic.h> 313 313 - // Example 1 (new calbiration data: for pre v1 IP): 313 313 + // Example 1 (new calibration data: for pre v1 IP): 314 314 thermal-sensor@4a9000 { 315 315 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 316 316 reg = <0x4a9000 0x1000>, /* TM */