+42 -13

drivers/gpu/drm/display/drm_dp_mst_topology.c

reviewed

··· 2339 2339 { 2340 2340 struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; 2341 2341 struct drm_dp_mst_port *port; 2342 2342 - int old_ddps = 0, ret; 2342 2342 + int ret; 2343 2343 u8 new_pdt = DP_PEER_DEVICE_NONE; 2344 2344 bool new_mcs = 0; 2345 2345 bool created = false, send_link_addr = false, changed = false; ··· 2372 2372 */ 2373 2373 drm_modeset_lock(&mgr->base.lock, NULL); 2374 2374 2375 2375 - old_ddps = port->ddps; 2376 2375 changed = port->ddps != port_msg->ddps || 2377 2376 (port->ddps && 2378 2377 (port->ldps != port_msg->legacy_device_plug_status || ··· 2406 2407 * Reprobe PBN caps on both hotplug, and when re-probing the link 2407 2408 * for our parent mstb 2408 2409 */ 2409 2409 - if (old_ddps != port->ddps || !created) { 2410 2410 - if (port->ddps && !port->input) { 2411 2411 - ret = drm_dp_send_enum_path_resources(mgr, mstb, 2412 2412 - port); 2413 2413 - if (ret == 1) 2414 2414 - changed = true; 2415 2415 - } else { 2416 2416 - port->full_pbn = 0; 2417 2417 - } 2410 2410 + if (port->ddps && !port->input) { 2411 2411 + ret = drm_dp_send_enum_path_resources(mgr, mstb, 2412 2412 + port); 2413 2413 + if (ret == 1) 2414 2414 + changed = true; 2415 2415 + } else { 2416 2416 + port->full_pbn = 0; 2418 2417 } 2419 2418 2420 2419 ret = drm_dp_port_set_pdt(port, new_pdt, new_mcs); ··· 2687 2690 mutex_unlock(&mgr->probe_lock); 2688 2691 if (ret > 0) 2689 2692 drm_kms_helper_hotplug_event(dev); 2693 2693 + } 2694 2694 + 2695 2695 + static void drm_dp_mst_queue_probe_work(struct drm_dp_mst_topology_mgr *mgr) 2696 2696 + { 2697 2697 + queue_work(system_long_wq, &mgr->work); 2690 2698 } 2691 2699 2692 2700 static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, ··· 3687 3685 /* Write reset payload */ 3688 3686 drm_dp_dpcd_write_payload(mgr, 0, 0, 0x3f); 3689 3687 3690 3690 - queue_work(system_long_wq, &mgr->work); 3688 3688 + drm_dp_mst_queue_probe_work(mgr); 3691 3689 3692 3690 ret = 0; 3693 3691 } else { ··· 3724 3722 if (port->mstb) 3725 3723 drm_dp_mst_topology_mgr_invalidate_mstb(port->mstb); 3726 3724 } 3725 3725 + 3726 3726 + /** 3727 3727 + * drm_dp_mst_topology_queue_probe - Queue a topology probe 3728 3728 + * @mgr: manager to probe 3729 3729 + * 3730 3730 + * Queue a work to probe the MST topology. Driver's should call this only to 3731 3731 + * sync the topology's HW->SW state after the MST link's parameters have 3732 3732 + * changed in a way the state could've become out-of-sync. This is the case 3733 3733 + * for instance when the link rate between the source and first downstream 3734 3734 + * branch device has switched between UHBR and non-UHBR rates. Except of those 3735 3735 + * cases - for instance when a sink gets plugged/unplugged to a port - the SW 3736 3736 + * state will get updated automatically via MST UP message notifications. 3737 3737 + */ 3738 3738 + void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr) 3739 3739 + { 3740 3740 + mutex_lock(&mgr->lock); 3741 3741 + 3742 3742 + if (drm_WARN_ON(mgr->dev, !mgr->mst_state || !mgr->mst_primary)) 3743 3743 + goto out_unlock; 3744 3744 + 3745 3745 + drm_dp_mst_topology_mgr_invalidate_mstb(mgr->mst_primary); 3746 3746 + drm_dp_mst_queue_probe_work(mgr); 3747 3747 + 3748 3748 + out_unlock: 3749 3749 + mutex_unlock(&mgr->lock); 3750 3750 + } 3751 3751 + EXPORT_SYMBOL(drm_dp_mst_topology_queue_probe); 3727 3752 3728 3753 /** 3729 3754 * drm_dp_mst_topology_mgr_suspend() - suspend the MST manager ··· 3838 3809 * state of our in-memory topology back into sync with reality. So, 3839 3810 * restart the probing process as if we're probing a new hub 3840 3811 */ 3841 3841 - queue_work(system_long_wq, &mgr->work); 3812 3812 + drm_dp_mst_queue_probe_work(mgr); 3842 3813 mutex_unlock(&mgr->lock); 3843 3814 3844 3815 if (sync) {

+7 -7

drivers/gpu/drm/i915/display/dvo_ch7017.c

reviewed

··· 170 170 { 171 171 struct i2c_msg msgs[] = { 172 172 { 173 173 - .addr = dvo->slave_addr, 173 173 + .addr = dvo->target_addr, 174 174 .flags = 0, 175 175 .len = 1, 176 176 .buf = &addr, 177 177 }, 178 178 { 179 179 - .addr = dvo->slave_addr, 179 179 + .addr = dvo->target_addr, 180 180 .flags = I2C_M_RD, 181 181 .len = 1, 182 182 .buf = val, ··· 189 189 { 190 190 u8 buf[2] = { addr, val }; 191 191 struct i2c_msg msg = { 192 192 - .addr = dvo->slave_addr, 192 192 + .addr = dvo->target_addr, 193 193 .flags = 0, 194 194 .len = 2, 195 195 .buf = buf, ··· 197 197 return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1; 198 198 } 199 199 200 200 - /** Probes for a CH7017 on the given bus and slave address. */ 200 200 + /** Probes for a CH7017 on the given bus and target address. */ 201 201 static bool ch7017_init(struct intel_dvo_device *dvo, 202 202 struct i2c_adapter *adapter) 203 203 { ··· 227 227 break; 228 228 default: 229 229 DRM_DEBUG_KMS("ch701x not detected, got %d: from %s " 230 230 - "slave %d.\n", 231 231 - val, adapter->name, dvo->slave_addr); 230 230 + "target %d.\n", 231 231 + val, adapter->name, dvo->target_addr); 232 232 goto fail; 233 233 } 234 234 235 235 DRM_DEBUG_KMS("%s detected on %s, addr %d\n", 236 236 - str, adapter->name, dvo->slave_addr); 236 236 + str, adapter->name, dvo->target_addr); 237 237 return true; 238 238 239 239 fail:

+9 -9

drivers/gpu/drm/i915/display/dvo_ch7xxx.c

reviewed

··· 153 153 154 154 struct i2c_msg msgs[] = { 155 155 { 156 156 - .addr = dvo->slave_addr, 156 156 + .addr = dvo->target_addr, 157 157 .flags = 0, 158 158 .len = 1, 159 159 .buf = out_buf, 160 160 }, 161 161 { 162 162 - .addr = dvo->slave_addr, 162 162 + .addr = dvo->target_addr, 163 163 .flags = I2C_M_RD, 164 164 .len = 1, 165 165 .buf = in_buf, ··· 176 176 177 177 if (!ch7xxx->quiet) { 178 178 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", 179 179 - addr, adapter->name, dvo->slave_addr); 179 179 + addr, adapter->name, dvo->target_addr); 180 180 } 181 181 return false; 182 182 } ··· 188 188 struct i2c_adapter *adapter = dvo->i2c_bus; 189 189 u8 out_buf[2]; 190 190 struct i2c_msg msg = { 191 191 - .addr = dvo->slave_addr, 191 191 + .addr = dvo->target_addr, 192 192 .flags = 0, 193 193 .len = 2, 194 194 .buf = out_buf, ··· 202 202 203 203 if (!ch7xxx->quiet) { 204 204 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 205 205 - addr, adapter->name, dvo->slave_addr); 205 205 + addr, adapter->name, dvo->target_addr); 206 206 } 207 207 208 208 return false; ··· 229 229 230 230 name = ch7xxx_get_id(vendor); 231 231 if (!name) { 232 232 - DRM_DEBUG_KMS("ch7xxx not detected; got VID 0x%02x from %s slave %d.\n", 233 233 - vendor, adapter->name, dvo->slave_addr); 232 232 + DRM_DEBUG_KMS("ch7xxx not detected; got VID 0x%02x from %s target %d.\n", 233 233 + vendor, adapter->name, dvo->target_addr); 234 234 goto out; 235 235 } 236 236 ··· 240 240 241 241 devid = ch7xxx_get_did(device); 242 242 if (!devid) { 243 243 - DRM_DEBUG_KMS("ch7xxx not detected; got DID 0x%02x from %s slave %d.\n", 244 244 - device, adapter->name, dvo->slave_addr); 243 243 + DRM_DEBUG_KMS("ch7xxx not detected; got DID 0x%02x from %s target %d.\n", 244 244 + device, adapter->name, dvo->target_addr); 245 245 goto out; 246 246 } 247 247

+8 -8

drivers/gpu/drm/i915/display/dvo_ivch.c

reviewed

··· 198 198 199 199 struct i2c_msg msgs[] = { 200 200 { 201 201 - .addr = dvo->slave_addr, 201 201 + .addr = dvo->target_addr, 202 202 .flags = I2C_M_RD, 203 203 .len = 0, 204 204 }, ··· 209 209 .buf = out_buf, 210 210 }, 211 211 { 212 212 - .addr = dvo->slave_addr, 212 212 + .addr = dvo->target_addr, 213 213 .flags = I2C_M_RD | I2C_M_NOSTART, 214 214 .len = 2, 215 215 .buf = in_buf, ··· 226 226 if (!priv->quiet) { 227 227 DRM_DEBUG_KMS("Unable to read register 0x%02x from " 228 228 "%s:%02x.\n", 229 229 - addr, adapter->name, dvo->slave_addr); 229 229 + addr, adapter->name, dvo->target_addr); 230 230 } 231 231 return false; 232 232 } ··· 238 238 struct i2c_adapter *adapter = dvo->i2c_bus; 239 239 u8 out_buf[3]; 240 240 struct i2c_msg msg = { 241 241 - .addr = dvo->slave_addr, 241 241 + .addr = dvo->target_addr, 242 242 .flags = 0, 243 243 .len = 3, 244 244 .buf = out_buf, ··· 253 253 254 254 if (!priv->quiet) { 255 255 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 256 256 - addr, adapter->name, dvo->slave_addr); 256 256 + addr, adapter->name, dvo->target_addr); 257 257 } 258 258 259 259 return false; 260 260 } 261 261 262 262 - /* Probes the given bus and slave address for an ivch */ 262 262 + /* Probes the given bus and target address for an ivch */ 263 263 static bool ivch_init(struct intel_dvo_device *dvo, 264 264 struct i2c_adapter *adapter) 265 265 { ··· 283 283 * very unique, check that the value in the base address field matches 284 284 * the address it's responding on. 285 285 */ 286 286 - if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { 286 286 + if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->target_addr) { 287 287 DRM_DEBUG_KMS("ivch detect failed due to address mismatch " 288 288 "(%d vs %d)\n", 289 289 - (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); 289 289 + (temp & VR00_BASE_ADDRESS_MASK), dvo->target_addr); 290 290 goto out; 291 291 } 292 292

+9 -9

drivers/gpu/drm/i915/display/dvo_ns2501.c

reviewed

··· 398 398 399 399 struct i2c_msg msgs[] = { 400 400 { 401 401 - .addr = dvo->slave_addr, 401 401 + .addr = dvo->target_addr, 402 402 .flags = 0, 403 403 .len = 1, 404 404 .buf = out_buf, 405 405 }, 406 406 { 407 407 - .addr = dvo->slave_addr, 407 407 + .addr = dvo->target_addr, 408 408 .flags = I2C_M_RD, 409 409 .len = 1, 410 410 .buf = in_buf, ··· 422 422 if (!ns->quiet) { 423 423 DRM_DEBUG_KMS 424 424 ("Unable to read register 0x%02x from %s:0x%02x.\n", addr, 425 425 - adapter->name, dvo->slave_addr); 425 425 + adapter->name, dvo->target_addr); 426 426 } 427 427 428 428 return false; ··· 441 441 u8 out_buf[2]; 442 442 443 443 struct i2c_msg msg = { 444 444 - .addr = dvo->slave_addr, 444 444 + .addr = dvo->target_addr, 445 445 .flags = 0, 446 446 .len = 2, 447 447 .buf = out_buf, ··· 456 456 457 457 if (!ns->quiet) { 458 458 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d\n", 459 459 - addr, adapter->name, dvo->slave_addr); 459 459 + addr, adapter->name, dvo->target_addr); 460 460 } 461 461 462 462 return false; ··· 487 487 goto out; 488 488 489 489 if (ch != (NS2501_VID & 0xff)) { 490 490 - DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Slave %d.\n", 491 491 - ch, adapter->name, dvo->slave_addr); 490 490 + DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Target %d.\n", 491 491 + ch, adapter->name, dvo->target_addr); 492 492 goto out; 493 493 } 494 494 ··· 496 496 goto out; 497 497 498 498 if (ch != (NS2501_DID & 0xff)) { 499 499 - DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Slave %d.\n", 500 500 - ch, adapter->name, dvo->slave_addr); 499 499 + DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Target %d.\n", 500 500 + ch, adapter->name, dvo->target_addr); 501 501 goto out; 502 502 } 503 503 ns->quiet = false;

+9 -9

drivers/gpu/drm/i915/display/dvo_sil164.c

reviewed

··· 79 79 80 80 struct i2c_msg msgs[] = { 81 81 { 82 82 - .addr = dvo->slave_addr, 82 82 + .addr = dvo->target_addr, 83 83 .flags = 0, 84 84 .len = 1, 85 85 .buf = out_buf, 86 86 }, 87 87 { 88 88 - .addr = dvo->slave_addr, 88 88 + .addr = dvo->target_addr, 89 89 .flags = I2C_M_RD, 90 90 .len = 1, 91 91 .buf = in_buf, ··· 102 102 103 103 if (!sil->quiet) { 104 104 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", 105 105 - addr, adapter->name, dvo->slave_addr); 105 105 + addr, adapter->name, dvo->target_addr); 106 106 } 107 107 return false; 108 108 } ··· 113 113 struct i2c_adapter *adapter = dvo->i2c_bus; 114 114 u8 out_buf[2]; 115 115 struct i2c_msg msg = { 116 116 - .addr = dvo->slave_addr, 116 116 + .addr = dvo->target_addr, 117 117 .flags = 0, 118 118 .len = 2, 119 119 .buf = out_buf, ··· 127 127 128 128 if (!sil->quiet) { 129 129 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 130 130 - addr, adapter->name, dvo->slave_addr); 130 130 + addr, adapter->name, dvo->target_addr); 131 131 } 132 132 133 133 return false; ··· 153 153 goto out; 154 154 155 155 if (ch != (SIL164_VID & 0xff)) { 156 156 - DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n", 157 157 - ch, adapter->name, dvo->slave_addr); 156 156 + DRM_DEBUG_KMS("sil164 not detected got %d: from %s Target %d.\n", 157 157 + ch, adapter->name, dvo->target_addr); 158 158 goto out; 159 159 } 160 160 ··· 162 162 goto out; 163 163 164 164 if (ch != (SIL164_DID & 0xff)) { 165 165 - DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n", 166 166 - ch, adapter->name, dvo->slave_addr); 165 165 + DRM_DEBUG_KMS("sil164 not detected got %d: from %s Target %d.\n", 166 166 + ch, adapter->name, dvo->target_addr); 167 167 goto out; 168 168 } 169 169 sil->quiet = false;

+9 -9

drivers/gpu/drm/i915/display/dvo_tfp410.c

reviewed

··· 100 100 101 101 struct i2c_msg msgs[] = { 102 102 { 103 103 - .addr = dvo->slave_addr, 103 103 + .addr = dvo->target_addr, 104 104 .flags = 0, 105 105 .len = 1, 106 106 .buf = out_buf, 107 107 }, 108 108 { 109 109 - .addr = dvo->slave_addr, 109 109 + .addr = dvo->target_addr, 110 110 .flags = I2C_M_RD, 111 111 .len = 1, 112 112 .buf = in_buf, ··· 123 123 124 124 if (!tfp->quiet) { 125 125 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", 126 126 - addr, adapter->name, dvo->slave_addr); 126 126 + addr, adapter->name, dvo->target_addr); 127 127 } 128 128 return false; 129 129 } ··· 134 134 struct i2c_adapter *adapter = dvo->i2c_bus; 135 135 u8 out_buf[2]; 136 136 struct i2c_msg msg = { 137 137 - .addr = dvo->slave_addr, 137 137 + .addr = dvo->target_addr, 138 138 .flags = 0, 139 139 .len = 2, 140 140 .buf = out_buf, ··· 148 148 149 149 if (!tfp->quiet) { 150 150 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 151 151 - addr, adapter->name, dvo->slave_addr); 151 151 + addr, adapter->name, dvo->target_addr); 152 152 } 153 153 154 154 return false; ··· 183 183 184 184 if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) { 185 185 DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s " 186 186 - "Slave %d.\n", 187 187 - id, adapter->name, dvo->slave_addr); 186 186 + "Target %d.\n", 187 187 + id, adapter->name, dvo->target_addr); 188 188 goto out; 189 189 } 190 190 191 191 if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) { 192 192 DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s " 193 193 - "Slave %d.\n", 194 194 - id, adapter->name, dvo->slave_addr); 193 193 + "Target %d.\n", 194 194 + id, adapter->name, dvo->target_addr); 195 195 goto out; 196 196 } 197 197 tfp->quiet = false;

+2 -1

drivers/gpu/drm/i915/display/g4x_dp.c

reviewed

··· 1279 1279 bool g4x_dp_init(struct drm_i915_private *dev_priv, 1280 1280 i915_reg_t output_reg, enum port port) 1281 1281 { 1282 1282 + struct intel_display *display = &dev_priv->display; 1282 1283 const struct intel_bios_encoder_data *devdata; 1283 1284 struct intel_digital_port *dig_port; 1284 1285 struct intel_encoder *intel_encoder; ··· 1289 1288 if (!assert_port_valid(dev_priv, port)) 1290 1289 return false; 1291 1290 1292 1292 - devdata = intel_bios_encoder_data_lookup(dev_priv, port); 1291 1291 + devdata = intel_bios_encoder_data_lookup(display, port); 1293 1292 1294 1293 /* FIXME bail? */ 1295 1294 if (!devdata)

+2 -1

drivers/gpu/drm/i915/display/g4x_hdmi.c

reviewed

··· 686 686 void g4x_hdmi_init(struct drm_i915_private *dev_priv, 687 687 i915_reg_t hdmi_reg, enum port port) 688 688 { 689 689 + struct intel_display *display = &dev_priv->display; 689 690 const struct intel_bios_encoder_data *devdata; 690 691 struct intel_digital_port *dig_port; 691 692 struct intel_encoder *intel_encoder; ··· 698 697 if (!assert_hdmi_port_valid(dev_priv, port)) 699 698 return; 700 699 701 701 - devdata = intel_bios_encoder_data_lookup(dev_priv, port); 700 700 + devdata = intel_bios_encoder_data_lookup(display, port); 702 701 703 702 /* FIXME bail? */ 704 703 if (!devdata)

+1 -1

drivers/gpu/drm/i915/display/i9xx_wm.c

reviewed

··· 4028 4028 dev_priv->display.funcs.wm = &g4x_wm_funcs; 4029 4029 } else if (IS_PINEVIEW(dev_priv)) { 4030 4030 if (!pnv_get_cxsr_latency(dev_priv)) { 4031 4031 - drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n"); 4031 4031 + drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n"); 4032 4032 /* Disable CxSR and never update its watermark again */ 4033 4033 intel_set_memory_cxsr(dev_priv, false); 4034 4034 dev_priv->display.funcs.wm = &nop_funcs;

+7 -5

drivers/gpu/drm/i915/display/icl_dsi.c

reviewed

··· 27 27 28 28 #include <drm/display/drm_dsc_helper.h> 29 29 #include <drm/drm_atomic_helper.h> 30 30 + #include <drm/drm_fixed.h> 30 31 #include <drm/drm_mipi_dsi.h> 31 32 32 33 #include "i915_reg.h" ··· 331 330 int bpp; 332 331 333 332 if (crtc_state->dsc.compression_enable) 334 334 - bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); 333 333 + bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 335 334 else 336 335 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 337 336 ··· 864 863 * compressed and non-compressed bpp. 865 864 */ 866 865 if (crtc_state->dsc.compression_enable) { 867 867 - mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); 866 866 + mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 868 867 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 869 868 } 870 869 ··· 888 887 int bpp, line_time_us, byte_clk_period_ns; 889 888 890 889 if (crtc_state->dsc.compression_enable) 891 891 - bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); 890 890 + bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 892 891 else 893 892 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 894 893 ··· 1471 1470 &pipe_config->hw.adjusted_mode; 1472 1471 1473 1472 if (pipe_config->dsc.compressed_bpp_x16) { 1474 1474 - int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16); 1473 1473 + int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); 1475 1474 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1476 1475 1477 1476 adjusted_mode->crtc_htotal = ··· 1945 1944 void icl_dsi_init(struct drm_i915_private *dev_priv, 1946 1945 const struct intel_bios_encoder_data *devdata) 1947 1946 { 1947 1947 + struct intel_display *display = &dev_priv->display; 1948 1948 struct intel_dsi *intel_dsi; 1949 1949 struct intel_encoder *encoder; 1950 1950 struct intel_connector *intel_connector; ··· 2009 2007 2010 2008 intel_dsi->panel_power_off_time = ktime_get_boottime(); 2011 2009 2012 2012 - intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL); 2010 2010 + intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL); 2013 2011 2014 2012 mutex_lock(&dev_priv->drm.mode_config.mutex); 2015 2013 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);

+8 -9

drivers/gpu/drm/i915/display/intel_acpi.c

reviewed

··· 183 183 { 184 184 } 185 185 186 186 - void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915) 186 186 + void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display) 187 187 { 188 188 - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 188 188 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 189 189 acpi_handle dhandle; 190 190 union acpi_object *obj; 191 191 ··· 263 263 return display_type; 264 264 } 265 265 266 266 - void intel_acpi_device_id_update(struct drm_i915_private *dev_priv) 266 266 + void intel_acpi_device_id_update(struct intel_display *display) 267 267 { 268 268 - struct drm_device *drm_dev = &dev_priv->drm; 269 268 struct intel_connector *connector; 270 269 struct drm_connector_list_iter conn_iter; 271 270 u8 display_index[16] = {}; 272 271 273 272 /* Populate the ACPI IDs for all connectors for a given drm_device */ 274 274 - drm_connector_list_iter_begin(drm_dev, &conn_iter); 273 273 + drm_connector_list_iter_begin(display->drm, &conn_iter); 275 274 for_each_intel_connector_iter(connector, &conn_iter) { 276 275 u32 device_id, type; 277 276 ··· 287 288 } 288 289 289 290 /* NOTE: The connector order must be final before this is called. */ 290 290 - void intel_acpi_assign_connector_fwnodes(struct drm_i915_private *i915) 291 291 + void intel_acpi_assign_connector_fwnodes(struct intel_display *display) 291 292 { 293 293 + struct drm_device *drm_dev = display->drm; 292 294 struct drm_connector_list_iter conn_iter; 293 293 - struct drm_device *drm_dev = &i915->drm; 294 295 struct fwnode_handle *fwnode = NULL; 295 296 struct drm_connector *connector; 296 297 struct acpi_device *adev; ··· 332 333 fwnode_handle_put(fwnode); 333 334 } 334 335 335 335 - void intel_acpi_video_register(struct drm_i915_private *i915) 336 336 + void intel_acpi_video_register(struct intel_display *display) 336 337 { 337 338 struct drm_connector_list_iter conn_iter; 338 339 struct drm_connector *connector; ··· 346 347 * a native backlight later and acpi_video_register_backlight() should 347 348 * only be called after any native backlights have been registered. 348 349 */ 349 349 - drm_connector_list_iter_begin(&i915->drm, &conn_iter); 350 350 + drm_connector_list_iter_begin(display->drm, &conn_iter); 350 351 drm_for_each_connector_iter(connector, &conn_iter) { 351 352 struct intel_panel *panel = &to_intel_connector(connector)->panel; 352 353

+9 -9

drivers/gpu/drm/i915/display/intel_acpi.h

reviewed

··· 6 6 #ifndef __INTEL_ACPI_H__ 7 7 #define __INTEL_ACPI_H__ 8 8 9 9 - struct drm_i915_private; 9 9 + struct intel_display; 10 10 11 11 #ifdef CONFIG_ACPI 12 12 void intel_register_dsm_handler(void); 13 13 void intel_unregister_dsm_handler(void); 14 14 - void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915); 15 15 - void intel_acpi_device_id_update(struct drm_i915_private *i915); 16 16 - void intel_acpi_assign_connector_fwnodes(struct drm_i915_private *i915); 17 17 - void intel_acpi_video_register(struct drm_i915_private *i915); 14 14 + void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display); 15 15 + void intel_acpi_device_id_update(struct intel_display *display); 16 16 + void intel_acpi_assign_connector_fwnodes(struct intel_display *display); 17 17 + void intel_acpi_video_register(struct intel_display *display); 18 18 #else 19 19 static inline void intel_register_dsm_handler(void) { return; } 20 20 static inline void intel_unregister_dsm_handler(void) { return; } 21 21 static inline 22 22 - void intel_dsm_get_bios_data_funcs_supported(struct drm_i915_private *i915) { return; } 22 22 + void intel_dsm_get_bios_data_funcs_supported(struct intel_display *display) { return; } 23 23 static inline 24 24 - void intel_acpi_device_id_update(struct drm_i915_private *i915) { return; } 24 24 + void intel_acpi_device_id_update(struct intel_display *display) { return; } 25 25 static inline 26 26 - void intel_acpi_assign_connector_fwnodes(struct drm_i915_private *i915) { return; } 26 26 + void intel_acpi_assign_connector_fwnodes(struct intel_display *display) { return; } 27 27 static inline 28 28 - void intel_acpi_video_register(struct drm_i915_private *i915) { return; } 28 28 + void intel_acpi_video_register(struct intel_display *display) { return; } 29 29 #endif /* CONFIG_ACPI */ 30 30 31 31 #endif /* __INTEL_ACPI_H__ */

+1 -1

drivers/gpu/drm/i915/display/intel_alpm.c

reviewed

··· 280 280 if (DISPLAY_VER(i915) < 20) 281 281 return; 282 282 283 283 - if (!intel_dp_as_sdp_supported(intel_dp)) 283 283 + if (!intel_dp->as_sdp_supported) 284 284 return; 285 285 286 286 if (crtc_state->has_psr)

+3 -2

drivers/gpu/drm/i915/display/intel_audio.c

reviewed

··· 26 26 27 27 #include <drm/drm_edid.h> 28 28 #include <drm/drm_eld.h> 29 29 + #include <drm/drm_fixed.h> 29 30 #include <drm/intel/i915_component.h> 30 31 31 32 #include "i915_drv.h" ··· 453 452 lanes = crtc_state->lane_count; 454 453 455 454 drm_dbg_kms(&i915->drm, 456 456 - "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " BPP_X16_FMT " cdclk = %u\n", 457 457 - h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16), cdclk); 455 455 + "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", 456 456 + h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); 458 457 459 458 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) 460 459 return 0;

+9 -6

drivers/gpu/drm/i915/display/intel_backlight.c

reviewed

··· 455 455 mutex_lock(&i915->display.backlight.lock); 456 456 457 457 if (panel->backlight.device) 458 458 - panel->backlight.device->props.power = FB_BLANK_POWERDOWN; 458 458 + panel->backlight.device->props.power = BACKLIGHT_POWER_OFF; 459 459 panel->backlight.enabled = false; 460 460 panel->backlight.funcs->disable(old_conn_state, 0); 461 461 ··· 773 773 panel->backlight.funcs->enable(crtc_state, conn_state, panel->backlight.level); 774 774 panel->backlight.enabled = true; 775 775 if (panel->backlight.device) 776 776 - panel->backlight.device->props.power = FB_BLANK_UNBLANK; 776 776 + panel->backlight.device->props.power = BACKLIGHT_POWER_ON; 777 777 } 778 778 779 779 void intel_backlight_enable(const struct intel_crtc_state *crtc_state, ··· 870 870 */ 871 871 if (panel->backlight.enabled) { 872 872 if (panel->backlight.power) { 873 873 - bool enable = bd->props.power == FB_BLANK_UNBLANK && 873 873 + bool enable = bd->props.power == BACKLIGHT_POWER_ON && 874 874 bd->props.brightness != 0; 875 875 panel->backlight.power(connector, enable); 876 876 } 877 877 } else { 878 878 - bd->props.power = FB_BLANK_POWERDOWN; 878 878 + bd->props.power = BACKLIGHT_POWER_OFF; 879 879 } 880 880 881 881 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); ··· 945 945 props.max_brightness); 946 946 947 947 if (panel->backlight.enabled) 948 948 - props.power = FB_BLANK_UNBLANK; 948 948 + props.power = BACKLIGHT_POWER_ON; 949 949 else 950 950 - props.power = FB_BLANK_POWERDOWN; 950 950 + props.power = BACKLIGHT_POWER_OFF; 951 951 952 952 name = kstrdup_const("intel_backlight", GFP_KERNEL); 953 953 if (!name) ··· 1449 1449 1450 1450 static int cnp_num_backlight_controllers(struct drm_i915_private *i915) 1451 1451 { 1452 1452 + if (INTEL_PCH_TYPE(i915) >= PCH_MTL) 1453 1453 + return 2; 1454 1454 + 1452 1455 if (INTEL_PCH_TYPE(i915) >= PCH_DG1) 1453 1456 return 1; 1454 1457

+453 -428

drivers/gpu/drm/i915/display/intel_bios.c

reviewed

··· 30 30 #include <drm/display/drm_dp_helper.h> 31 31 #include <drm/display/drm_dsc_helper.h> 32 32 #include <drm/drm_edid.h> 33 33 + #include <drm/drm_fixed.h> 33 34 34 35 #include "i915_drv.h" 35 36 #include "i915_reg.h" ··· 66 65 67 66 /* Wrapper for VBT child device config */ 68 67 struct intel_bios_encoder_data { 69 69 - struct drm_i915_private *i915; 68 68 + struct intel_display *display; 70 69 71 70 struct child_device_config child; 72 71 struct dsc_compression_parameters_entry *dsc; 73 72 struct list_head node; 74 73 }; 75 74 76 76 - #define SLAVE_ADDR1 0x70 77 77 - #define SLAVE_ADDR2 0x72 75 75 + #define TARGET_ADDR1 0x70 76 76 + #define TARGET_ADDR2 0x72 78 77 79 78 /* Get BDB block size given a pointer to Block ID. */ 80 79 static u32 _get_blocksize(const u8 *block_base) ··· 145 144 }; 146 145 147 146 static const void * 148 148 - bdb_find_section(struct drm_i915_private *i915, 147 147 + bdb_find_section(struct intel_display *display, 149 148 enum bdb_block_id section_id) 150 149 { 151 150 struct bdb_block_entry *entry; 152 151 153 153 - list_for_each_entry(entry, &i915->display.vbt.bdb_blocks, node) { 152 152 + list_for_each_entry(entry, &display->vbt.bdb_blocks, node) { 154 153 if (entry->section_id == section_id) 155 154 return entry->data + 3; 156 155 } ··· 200 199 .min_size = sizeof(struct bdb_generic_dtd), }, 201 200 }; 202 201 203 203 - static size_t lfp_data_min_size(struct drm_i915_private *i915) 202 202 + static size_t lfp_data_min_size(struct intel_display *display) 204 203 { 205 204 const struct bdb_lfp_data_ptrs *ptrs; 206 205 size_t size; 207 206 208 208 - ptrs = bdb_find_section(i915, BDB_LFP_DATA_PTRS); 207 207 + ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS); 209 208 if (!ptrs) 210 209 return 0; 211 210 ··· 360 359 next->offset = prev->offset + size; 361 360 } 362 361 363 363 - static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, 362 362 + static void *generate_lfp_data_ptrs(struct intel_display *display, 364 363 const void *bdb) 365 364 { 366 365 int i, size, table_size, block_size, offset, fp_timing_size; ··· 374 373 * include block 41 and thus we don't need to 375 374 * generate one. 376 375 */ 377 377 - if (i915->display.vbt.version < 155) 376 376 + if (display->vbt.version < 155) 378 377 return NULL; 379 378 380 379 fp_timing_size = 38; ··· 383 382 if (!block) 384 383 return NULL; 385 384 386 386 - drm_dbg_kms(&i915->drm, "Generating LFP data table pointers\n"); 385 385 + drm_dbg_kms(display->drm, "Generating LFP data table pointers\n"); 387 386 388 387 block_size = get_blocksize(block); 389 388 ··· 451 450 } 452 451 453 452 static void 454 454 - init_bdb_block(struct drm_i915_private *i915, 453 453 + init_bdb_block(struct intel_display *display, 455 454 const void *bdb, enum bdb_block_id section_id, 456 455 size_t min_size) 457 456 { ··· 464 463 465 464 /* Modern VBTs lack the LFP data table pointers block, make one up */ 466 465 if (!block && section_id == BDB_LFP_DATA_PTRS) { 467 467 - temp_block = generate_lfp_data_ptrs(i915, bdb); 466 466 + temp_block = generate_lfp_data_ptrs(display, bdb); 468 467 if (temp_block) 469 468 block = temp_block + 3; 470 469 } 471 470 if (!block) 472 471 return; 473 472 474 474 - drm_WARN(&i915->drm, min_size == 0, 473 473 + drm_WARN(display->drm, min_size == 0, 475 474 "Block %d min_size is zero\n", section_id); 476 475 477 476 block_size = get_blocksize(block); ··· 495 494 496 495 kfree(temp_block); 497 496 498 498 - drm_dbg_kms(&i915->drm, "Found BDB block %d (size %zu, min size %zu)\n", 497 497 + drm_dbg_kms(display->drm, 498 498 + "Found BDB block %d (size %zu, min size %zu)\n", 499 499 section_id, block_size, min_size); 500 500 501 501 if (section_id == BDB_LFP_DATA_PTRS && 502 502 !fixup_lfp_data_ptrs(bdb, entry->data + 3)) { 503 503 - drm_err(&i915->drm, "VBT has malformed LFP data table pointers\n"); 503 503 + drm_err(display->drm, 504 504 + "VBT has malformed LFP data table pointers\n"); 504 505 kfree(entry); 505 506 return; 506 507 } 507 508 508 508 - list_add_tail(&entry->node, &i915->display.vbt.bdb_blocks); 509 509 + list_add_tail(&entry->node, &display->vbt.bdb_blocks); 509 510 } 510 511 511 511 - static void init_bdb_blocks(struct drm_i915_private *i915, 512 512 + static void init_bdb_blocks(struct intel_display *display, 512 513 const void *bdb) 513 514 { 514 515 int i; ··· 520 517 size_t min_size = bdb_blocks[i].min_size; 521 518 522 519 if (section_id == BDB_LFP_DATA) 523 523 - min_size = lfp_data_min_size(i915); 520 520 + min_size = lfp_data_min_size(display); 524 521 525 525 - init_bdb_block(i915, bdb, section_id, min_size); 522 522 + init_bdb_block(display, bdb, section_id, min_size); 526 523 } 527 524 } 528 525 529 526 static void 530 530 - fill_detail_timing_data(struct drm_i915_private *i915, 527 527 + fill_detail_timing_data(struct intel_display *display, 531 528 struct drm_display_mode *panel_fixed_mode, 532 529 const struct bdb_edid_dtd *dvo_timing) 533 530 { ··· 570 567 571 568 /* Some VBTs have bogus h/vsync_end values */ 572 569 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) { 573 573 - drm_dbg_kms(&i915->drm, "reducing hsync_end %d->%d\n", 570 570 + drm_dbg_kms(display->drm, "reducing hsync_end %d->%d\n", 574 571 panel_fixed_mode->hsync_end, panel_fixed_mode->htotal); 575 572 panel_fixed_mode->hsync_end = panel_fixed_mode->htotal; 576 573 } 577 574 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) { 578 578 - drm_dbg_kms(&i915->drm, "reducing vsync_end %d->%d\n", 575 575 + drm_dbg_kms(display->drm, "reducing vsync_end %d->%d\n", 579 576 panel_fixed_mode->vsync_end, panel_fixed_mode->vtotal); 580 577 panel_fixed_mode->vsync_end = panel_fixed_mode->vtotal; 581 578 } ··· 620 617 return NULL; 621 618 } 622 619 623 623 - static int opregion_get_panel_type(struct drm_i915_private *i915, 620 620 + static int opregion_get_panel_type(struct intel_display *display, 624 621 const struct intel_bios_encoder_data *devdata, 625 622 const struct drm_edid *drm_edid, bool use_fallback) 626 623 { 627 627 - return intel_opregion_get_panel_type(i915); 624 624 + return intel_opregion_get_panel_type(display); 628 625 } 629 626 630 630 - static int vbt_get_panel_type(struct drm_i915_private *i915, 627 627 + static int vbt_get_panel_type(struct intel_display *display, 631 628 const struct intel_bios_encoder_data *devdata, 632 629 const struct drm_edid *drm_edid, bool use_fallback) 633 630 { 634 631 const struct bdb_lfp_options *lfp_options; 635 632 636 636 - lfp_options = bdb_find_section(i915, BDB_LFP_OPTIONS); 633 633 + lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS); 637 634 if (!lfp_options) 638 635 return -1; 639 636 640 637 if (lfp_options->panel_type > 0xf && 641 638 lfp_options->panel_type != 0xff) { 642 642 - drm_dbg_kms(&i915->drm, "Invalid VBT panel type 0x%x\n", 639 639 + drm_dbg_kms(display->drm, "Invalid VBT panel type 0x%x\n", 643 640 lfp_options->panel_type); 644 641 return -1; 645 642 } ··· 647 644 if (devdata && devdata->child.handle == DEVICE_HANDLE_LFP2) 648 645 return lfp_options->panel_type2; 649 646 650 650 - drm_WARN_ON(&i915->drm, devdata && devdata->child.handle != DEVICE_HANDLE_LFP1); 647 647 + drm_WARN_ON(display->drm, 648 648 + devdata && devdata->child.handle != DEVICE_HANDLE_LFP1); 651 649 652 650 return lfp_options->panel_type; 653 651 } 654 652 655 655 - static int pnpid_get_panel_type(struct drm_i915_private *i915, 653 653 + static int pnpid_get_panel_type(struct intel_display *display, 656 654 const struct intel_bios_encoder_data *devdata, 657 655 const struct drm_edid *drm_edid, bool use_fallback) 658 656 { ··· 672 668 product_id_nodate.week_of_manufacture = 0; 673 669 product_id_nodate.year_of_manufacture = 0; 674 670 675 675 - p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, "EDID"); 671 671 + p = drm_dbg_printer(display->drm, DRM_UT_KMS, "EDID"); 676 672 drm_edid_print_product_id(&p, &product_id, true); 677 673 678 678 - ptrs = bdb_find_section(i915, BDB_LFP_DATA_PTRS); 674 674 + ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS); 679 675 if (!ptrs) 680 676 return -1; 681 677 682 682 - data = bdb_find_section(i915, BDB_LFP_DATA); 678 678 + data = bdb_find_section(display, BDB_LFP_DATA); 683 679 if (!data) 684 680 return -1; 685 681 ··· 703 699 return best; 704 700 } 705 701 706 706 - static int fallback_get_panel_type(struct drm_i915_private *i915, 702 702 + static int fallback_get_panel_type(struct intel_display *display, 707 703 const struct intel_bios_encoder_data *devdata, 708 704 const struct drm_edid *drm_edid, bool use_fallback) 709 705 { ··· 717 713 PANEL_TYPE_FALLBACK, 718 714 }; 719 715 720 720 - static int get_panel_type(struct drm_i915_private *i915, 716 716 + static int get_panel_type(struct intel_display *display, 721 717 const struct intel_bios_encoder_data *devdata, 722 718 const struct drm_edid *drm_edid, bool use_fallback) 723 719 { 724 720 struct { 725 721 const char *name; 726 726 - int (*get_panel_type)(struct drm_i915_private *i915, 722 722 + int (*get_panel_type)(struct intel_display *display, 727 723 const struct intel_bios_encoder_data *devdata, 728 724 const struct drm_edid *drm_edid, bool use_fallback); 729 725 int panel_type; ··· 748 744 int i; 749 745 750 746 for (i = 0; i < ARRAY_SIZE(panel_types); i++) { 751 751 - panel_types[i].panel_type = panel_types[i].get_panel_type(i915, devdata, 747 747 + panel_types[i].panel_type = panel_types[i].get_panel_type(display, devdata, 752 748 drm_edid, use_fallback); 753 749 754 754 - drm_WARN_ON(&i915->drm, panel_types[i].panel_type > 0xf && 750 750 + drm_WARN_ON(display->drm, panel_types[i].panel_type > 0xf && 755 751 panel_types[i].panel_type != 0xff); 756 752 757 753 if (panel_types[i].panel_type >= 0) 758 758 - drm_dbg_kms(&i915->drm, "Panel type (%s): %d\n", 754 754 + drm_dbg_kms(display->drm, "Panel type (%s): %d\n", 759 755 panel_types[i].name, panel_types[i].panel_type); 760 756 } 761 757 ··· 770 766 else 771 767 i = PANEL_TYPE_FALLBACK; 772 768 773 773 - drm_dbg_kms(&i915->drm, "Selected panel type (%s): %d\n", 769 769 + drm_dbg_kms(display->drm, "Selected panel type (%s): %d\n", 774 770 panel_types[i].name, panel_types[i].panel_type); 775 771 776 772 return panel_types[i].panel_type; ··· 788 784 789 785 /* Parse general panel options */ 790 786 static void 791 791 - parse_panel_options(struct drm_i915_private *i915, 787 787 + parse_panel_options(struct intel_display *display, 792 788 struct intel_panel *panel) 793 789 { 794 790 const struct bdb_lfp_options *lfp_options; 795 791 int panel_type = panel->vbt.panel_type; 796 792 int drrs_mode; 797 793 798 798 - lfp_options = bdb_find_section(i915, BDB_LFP_OPTIONS); 794 794 + lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS); 799 795 if (!lfp_options) 800 796 return; 801 797 ··· 819 815 switch (drrs_mode) { 820 816 case 0: 821 817 panel->vbt.drrs_type = DRRS_TYPE_STATIC; 822 822 - drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n"); 818 818 + drm_dbg_kms(display->drm, "DRRS supported mode is static\n"); 823 819 break; 824 820 case 2: 825 821 panel->vbt.drrs_type = DRRS_TYPE_SEAMLESS; 826 826 - drm_dbg_kms(&i915->drm, 822 822 + drm_dbg_kms(display->drm, 827 823 "DRRS supported mode is seamless\n"); 828 824 break; 829 825 default: 830 826 panel->vbt.drrs_type = DRRS_TYPE_NONE; 831 831 - drm_dbg_kms(&i915->drm, 827 827 + drm_dbg_kms(display->drm, 832 828 "DRRS not supported (VBT input)\n"); 833 829 break; 834 830 } 835 831 } 836 832 837 833 static void 838 838 - parse_lfp_panel_dtd(struct drm_i915_private *i915, 834 834 + parse_lfp_panel_dtd(struct intel_display *display, 839 835 struct intel_panel *panel, 840 836 const struct bdb_lfp_data *lfp_data, 841 837 const struct bdb_lfp_data_ptrs *lfp_data_ptrs) ··· 853 849 if (!panel_fixed_mode) 854 850 return; 855 851 856 856 - fill_detail_timing_data(i915, panel_fixed_mode, panel_dvo_timing); 852 852 + fill_detail_timing_data(display, panel_fixed_mode, panel_dvo_timing); 857 853 858 854 panel->vbt.lfp_vbt_mode = panel_fixed_mode; 859 855 860 860 - drm_dbg_kms(&i915->drm, 856 856 + drm_dbg_kms(display->drm, 861 857 "Found panel mode in BIOS VBT legacy lfp table: " DRM_MODE_FMT "\n", 862 858 DRM_MODE_ARG(panel_fixed_mode)); 863 859 ··· 869 865 if (fp_timing->x_res == panel_fixed_mode->hdisplay && 870 866 fp_timing->y_res == panel_fixed_mode->vdisplay) { 871 867 panel->vbt.bios_lvds_val = fp_timing->lvds_reg_val; 872 872 - drm_dbg_kms(&i915->drm, 868 868 + drm_dbg_kms(display->drm, 873 869 "VBT initial LVDS value %x\n", 874 870 panel->vbt.bios_lvds_val); 875 871 } 876 872 } 877 873 878 874 static void 879 879 - parse_lfp_data(struct drm_i915_private *i915, 875 875 + parse_lfp_data(struct intel_display *display, 880 876 struct intel_panel *panel) 881 877 { 882 878 const struct bdb_lfp_data *data; ··· 886 882 struct drm_printer p; 887 883 int panel_type = panel->vbt.panel_type; 888 884 889 889 - ptrs = bdb_find_section(i915, BDB_LFP_DATA_PTRS); 885 885 + ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS); 890 886 if (!ptrs) 891 887 return; 892 888 893 893 - data = bdb_find_section(i915, BDB_LFP_DATA); 889 889 + data = bdb_find_section(display, BDB_LFP_DATA); 894 890 if (!data) 895 891 return; 896 892 897 893 if (!panel->vbt.lfp_vbt_mode) 898 898 - parse_lfp_panel_dtd(i915, panel, data, ptrs); 894 894 + parse_lfp_panel_dtd(display, panel, data, ptrs); 899 895 900 896 pnp_id = get_lfp_pnp_id(data, ptrs, panel_type); 901 897 902 902 - p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, "Panel"); 898 898 + p = drm_dbg_printer(display->drm, DRM_UT_KMS, "Panel"); 903 899 drm_edid_print_product_id(&p, pnp_id, false); 904 900 905 901 tail = get_lfp_data_tail(data, ptrs); 906 902 if (!tail) 907 903 return; 908 904 909 909 - drm_dbg_kms(&i915->drm, "Panel name: %.*s\n", 905 905 + drm_dbg_kms(display->drm, "Panel name: %.*s\n", 910 906 (int)sizeof(tail->panel_name[0].name), 911 907 tail->panel_name[panel_type].name); 912 908 913 913 - if (i915->display.vbt.version >= 188) { 909 909 + if (display->vbt.version >= 188) { 914 910 panel->vbt.seamless_drrs_min_refresh_rate = 915 911 tail->seamless_drrs_min_refresh_rate[panel_type]; 916 916 - drm_dbg_kms(&i915->drm, 912 912 + drm_dbg_kms(display->drm, 917 913 "Seamless DRRS min refresh rate: %d Hz\n", 918 914 panel->vbt.seamless_drrs_min_refresh_rate); 919 915 } 920 916 } 921 917 922 918 static void 923 923 - parse_generic_dtd(struct drm_i915_private *i915, 919 919 + parse_generic_dtd(struct intel_display *display, 924 920 struct intel_panel *panel) 925 921 { 926 922 const struct bdb_generic_dtd *generic_dtd; ··· 936 932 * first on VBT >= 229, but still fall back to trying the old LFP 937 933 * block if that fails. 938 934 */ 939 939 - if (i915->display.vbt.version < 229) 935 935 + if (display->vbt.version < 229) 940 936 return; 941 937 942 942 - generic_dtd = bdb_find_section(i915, BDB_GENERIC_DTD); 938 938 + generic_dtd = bdb_find_section(display, BDB_GENERIC_DTD); 943 939 if (!generic_dtd) 944 940 return; 945 941 946 942 if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) { 947 947 - drm_err(&i915->drm, "GDTD size %u is too small.\n", 943 943 + drm_err(display->drm, "GDTD size %u is too small.\n", 948 944 generic_dtd->gdtd_size); 949 945 return; 950 946 } else if (generic_dtd->gdtd_size != 951 947 sizeof(struct generic_dtd_entry)) { 952 952 - drm_err(&i915->drm, "Unexpected GDTD size %u\n", 948 948 + drm_err(display->drm, "Unexpected GDTD size %u\n", 953 949 generic_dtd->gdtd_size); 954 950 /* DTD has unknown fields, but keep going */ 955 951 } ··· 957 953 num_dtd = (get_blocksize(generic_dtd) - 958 954 sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size; 959 955 if (panel->vbt.panel_type >= num_dtd) { 960 960 - drm_err(&i915->drm, 956 956 + drm_err(display->drm, 961 957 "Panel type %d not found in table of %d DTD's\n", 962 958 panel->vbt.panel_type, num_dtd); 963 959 return; ··· 1002 998 else 1003 999 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; 1004 1000 1005 1005 - drm_dbg_kms(&i915->drm, 1001 1001 + drm_dbg_kms(display->drm, 1006 1002 "Found panel mode in BIOS VBT generic dtd table: " DRM_MODE_FMT "\n", 1007 1003 DRM_MODE_ARG(panel_fixed_mode)); 1008 1004 ··· 1010 1006 } 1011 1007 1012 1008 static void 1013 1013 - parse_lfp_backlight(struct drm_i915_private *i915, 1009 1009 + parse_lfp_backlight(struct intel_display *display, 1014 1010 struct intel_panel *panel) 1015 1011 { 1016 1012 const struct bdb_lfp_backlight *backlight_data; ··· 1018 1014 int panel_type = panel->vbt.panel_type; 1019 1015 u16 level; 1020 1016 1021 1021 - backlight_data = bdb_find_section(i915, BDB_LFP_BACKLIGHT); 1017 1017 + backlight_data = bdb_find_section(display, BDB_LFP_BACKLIGHT); 1022 1018 if (!backlight_data) 1023 1019 return; 1024 1020 1025 1021 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { 1026 1026 - drm_dbg_kms(&i915->drm, 1022 1022 + drm_dbg_kms(display->drm, 1027 1023 "Unsupported backlight data entry size %u\n", 1028 1024 backlight_data->entry_size); 1029 1025 return; ··· 1033 1029 1034 1030 panel->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; 1035 1031 if (!panel->vbt.backlight.present) { 1036 1036 - drm_dbg_kms(&i915->drm, 1032 1032 + drm_dbg_kms(display->drm, 1037 1033 "PWM backlight not present in VBT (type %u)\n", 1038 1034 entry->type); 1039 1035 return; ··· 1041 1037 1042 1038 panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; 1043 1039 panel->vbt.backlight.controller = 0; 1044 1044 - if (i915->display.vbt.version >= 191) { 1040 1040 + if (display->vbt.version >= 191) { 1045 1041 const struct lfp_backlight_control_method *method; 1046 1042 1047 1043 method = &backlight_data->backlight_control[panel_type]; ··· 1052 1048 panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; 1053 1049 panel->vbt.backlight.active_low_pwm = entry->active_low_pwm; 1054 1050 1055 1055 - if (i915->display.vbt.version >= 234) { 1051 1051 + if (display->vbt.version >= 234) { 1056 1052 u16 min_level; 1057 1053 bool scale; 1058 1054 1059 1055 level = backlight_data->brightness_level[panel_type].level; 1060 1056 min_level = backlight_data->brightness_min_level[panel_type].level; 1061 1057 1062 1062 - if (i915->display.vbt.version >= 236) 1058 1058 + if (display->vbt.version >= 236) 1063 1059 scale = backlight_data->brightness_precision_bits[panel_type] == 16; 1064 1060 else 1065 1061 scale = level > 255; ··· 1068 1064 min_level = min_level / 255; 1069 1065 1070 1066 if (min_level > 255) { 1071 1071 - drm_warn(&i915->drm, "Brightness min level > 255\n"); 1067 1067 + drm_warn(display->drm, "Brightness min level > 255\n"); 1072 1068 level = 255; 1073 1069 } 1074 1070 panel->vbt.backlight.min_brightness = min_level; ··· 1080 1076 panel->vbt.backlight.min_brightness = entry->min_brightness; 1081 1077 } 1082 1078 1083 1083 - if (i915->display.vbt.version >= 239) 1079 1079 + if (display->vbt.version >= 239) 1084 1080 panel->vbt.backlight.hdr_dpcd_refresh_timeout = 1085 1081 DIV_ROUND_UP(backlight_data->hdr_dpcd_refresh_timeout[panel_type], 100); 1086 1082 else 1087 1083 panel->vbt.backlight.hdr_dpcd_refresh_timeout = 30; 1088 1084 1089 1089 - drm_dbg_kms(&i915->drm, 1085 1085 + drm_dbg_kms(display->drm, 1090 1086 "VBT backlight PWM modulation frequency %u Hz, " 1091 1087 "active %s, min brightness %u, level %u, controller %u\n", 1092 1088 panel->vbt.backlight.pwm_freq_hz, ··· 1097 1093 } 1098 1094 1099 1095 static void 1100 1100 - parse_sdvo_lvds_data(struct drm_i915_private *i915, 1096 1096 + parse_sdvo_lvds_data(struct intel_display *display, 1101 1097 struct intel_panel *panel) 1102 1098 { 1103 1099 const struct bdb_sdvo_lvds_dtd *dtd; 1104 1100 struct drm_display_mode *panel_fixed_mode; 1105 1101 int index; 1106 1102 1107 1107 - index = i915->display.params.vbt_sdvo_panel_type; 1103 1103 + index = display->params.vbt_sdvo_panel_type; 1108 1104 if (index == -2) { 1109 1109 - drm_dbg_kms(&i915->drm, 1105 1105 + drm_dbg_kms(display->drm, 1110 1106 "Ignore SDVO LVDS mode from BIOS VBT tables.\n"); 1111 1107 return; 1112 1108 } ··· 1114 1110 if (index == -1) { 1115 1111 const struct bdb_sdvo_lvds_options *sdvo_lvds_options; 1116 1112 1117 1117 - sdvo_lvds_options = bdb_find_section(i915, BDB_SDVO_LVDS_OPTIONS); 1113 1113 + sdvo_lvds_options = bdb_find_section(display, BDB_SDVO_LVDS_OPTIONS); 1118 1114 if (!sdvo_lvds_options) 1119 1115 return; 1120 1116 1121 1117 index = sdvo_lvds_options->panel_type; 1122 1118 } 1123 1119 1124 1124 - dtd = bdb_find_section(i915, BDB_SDVO_LVDS_DTD); 1120 1120 + dtd = bdb_find_section(display, BDB_SDVO_LVDS_DTD); 1125 1121 if (!dtd) 1126 1122 return; 1127 1123 ··· 1132 1128 * it here to be sure. 1133 1129 */ 1134 1130 if (index >= ARRAY_SIZE(dtd->dtd)) { 1135 1135 - drm_err(&i915->drm, "index %d is larger than dtd->dtd[4] array\n", 1131 1131 + drm_err(display->drm, 1132 1132 + "index %d is larger than dtd->dtd[4] array\n", 1136 1133 index); 1137 1134 return; 1138 1135 } ··· 1142 1137 if (!panel_fixed_mode) 1143 1138 return; 1144 1139 1145 1145 - fill_detail_timing_data(i915, panel_fixed_mode, &dtd->dtd[index]); 1140 1140 + fill_detail_timing_data(display, panel_fixed_mode, &dtd->dtd[index]); 1146 1141 1147 1142 panel->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; 1148 1143 1149 1149 - drm_dbg_kms(&i915->drm, 1144 1144 + drm_dbg_kms(display->drm, 1150 1145 "Found SDVO LVDS mode in BIOS VBT tables: " DRM_MODE_FMT "\n", 1151 1146 DRM_MODE_ARG(panel_fixed_mode)); 1152 1147 } 1153 1148 1154 1154 - static int intel_bios_ssc_frequency(struct drm_i915_private *i915, 1149 1149 + static int intel_bios_ssc_frequency(struct intel_display *display, 1155 1150 bool alternate) 1156 1151 { 1157 1157 - switch (DISPLAY_VER(i915)) { 1152 1152 + switch (DISPLAY_VER(display)) { 1158 1153 case 2: 1159 1154 return alternate ? 66667 : 48000; 1160 1155 case 3: ··· 1166 1161 } 1167 1162 1168 1163 static void 1169 1169 - parse_general_features(struct drm_i915_private *i915) 1164 1164 + parse_general_features(struct intel_display *display) 1170 1165 { 1166 1166 + struct drm_i915_private *i915 = to_i915(display->drm); 1171 1167 const struct bdb_general_features *general; 1172 1168 1173 1173 - general = bdb_find_section(i915, BDB_GENERAL_FEATURES); 1169 1169 + general = bdb_find_section(display, BDB_GENERAL_FEATURES); 1174 1170 if (!general) 1175 1171 return; 1176 1172 1177 1177 - i915->display.vbt.int_tv_support = general->int_tv_support; 1173 1173 + display->vbt.int_tv_support = general->int_tv_support; 1178 1174 /* int_crt_support can't be trusted on earlier platforms */ 1179 1179 - if (i915->display.vbt.version >= 155 && 1180 1180 - (HAS_DDI(i915) || IS_VALLEYVIEW(i915))) 1181 1181 - i915->display.vbt.int_crt_support = general->int_crt_support; 1182 1182 - i915->display.vbt.lvds_use_ssc = general->enable_ssc; 1183 1183 - i915->display.vbt.lvds_ssc_freq = 1184 1184 - intel_bios_ssc_frequency(i915, general->ssc_freq); 1185 1185 - i915->display.vbt.display_clock_mode = general->display_clock_mode; 1186 1186 - i915->display.vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; 1187 1187 - if (i915->display.vbt.version >= 181) { 1188 1188 - i915->display.vbt.orientation = general->rotate_180 ? 1175 1175 + if (display->vbt.version >= 155 && 1176 1176 + (HAS_DDI(display) || IS_VALLEYVIEW(i915))) 1177 1177 + display->vbt.int_crt_support = general->int_crt_support; 1178 1178 + display->vbt.lvds_use_ssc = general->enable_ssc; 1179 1179 + display->vbt.lvds_ssc_freq = 1180 1180 + intel_bios_ssc_frequency(display, general->ssc_freq); 1181 1181 + display->vbt.display_clock_mode = general->display_clock_mode; 1182 1182 + display->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; 1183 1183 + if (display->vbt.version >= 181) { 1184 1184 + display->vbt.orientation = general->rotate_180 ? 1189 1185 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP : 1190 1186 DRM_MODE_PANEL_ORIENTATION_NORMAL; 1191 1187 } else { 1192 1192 - i915->display.vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1188 1188 + display->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1193 1189 } 1194 1190 1195 1195 - if (i915->display.vbt.version >= 249 && general->afc_startup_config) { 1196 1196 - i915->display.vbt.override_afc_startup = true; 1197 1197 - i915->display.vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7; 1191 1191 + if (display->vbt.version >= 249 && general->afc_startup_config) { 1192 1192 + display->vbt.override_afc_startup = true; 1193 1193 + display->vbt.override_afc_startup_val = general->afc_startup_config == 1 ? 0 : 7; 1198 1194 } 1199 1195 1200 1200 - drm_dbg_kms(&i915->drm, 1196 1196 + drm_dbg_kms(display->drm, 1201 1197 "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", 1202 1202 - i915->display.vbt.int_tv_support, 1203 1203 - i915->display.vbt.int_crt_support, 1204 1204 - i915->display.vbt.lvds_use_ssc, 1205 1205 - i915->display.vbt.lvds_ssc_freq, 1206 1206 - i915->display.vbt.display_clock_mode, 1207 1207 - i915->display.vbt.fdi_rx_polarity_inverted); 1198 1198 + display->vbt.int_tv_support, 1199 1199 + display->vbt.int_crt_support, 1200 1200 + display->vbt.lvds_use_ssc, 1201 1201 + display->vbt.lvds_ssc_freq, 1202 1202 + display->vbt.display_clock_mode, 1203 1203 + display->vbt.fdi_rx_polarity_inverted); 1208 1204 } 1209 1205 1210 1206 static const struct child_device_config * ··· 1215 1209 } 1216 1210 1217 1211 static void 1218 1218 - parse_sdvo_device_mapping(struct drm_i915_private *i915) 1212 1212 + parse_sdvo_device_mapping(struct intel_display *display) 1219 1213 { 1220 1214 const struct intel_bios_encoder_data *devdata; 1221 1215 int count = 0; ··· 1224 1218 * Only parse SDVO mappings on gens that could have SDVO. This isn't 1225 1219 * accurate and doesn't have to be, as long as it's not too strict. 1226 1220 */ 1227 1227 - if (!IS_DISPLAY_VER(i915, 3, 7)) { 1228 1228 - drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n"); 1221 1221 + if (!IS_DISPLAY_VER(display, 3, 7)) { 1222 1222 + drm_dbg_kms(display->drm, "Skipping SDVO device mapping\n"); 1229 1223 return; 1230 1224 } 1231 1225 1232 1232 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { 1226 1226 + list_for_each_entry(devdata, &display->vbt.display_devices, node) { 1233 1227 const struct child_device_config *child = &devdata->child; 1234 1228 struct sdvo_device_mapping *mapping; 1235 1229 1236 1236 - if (child->slave_addr != SLAVE_ADDR1 && 1237 1237 - child->slave_addr != SLAVE_ADDR2) { 1230 1230 + if (child->target_addr != TARGET_ADDR1 && 1231 1231 + child->target_addr != TARGET_ADDR2) { 1238 1232 /* 1239 1239 - * If the slave address is neither 0x70 nor 0x72, 1233 1233 + * If the target address is neither 0x70 nor 0x72, 1240 1234 * it is not a SDVO device. Skip it. 1241 1235 */ 1242 1236 continue; ··· 1244 1238 if (child->dvo_port != DEVICE_PORT_DVOB && 1245 1239 child->dvo_port != DEVICE_PORT_DVOC) { 1246 1240 /* skip the incorrect SDVO port */ 1247 1247 - drm_dbg_kms(&i915->drm, 1241 1241 + drm_dbg_kms(display->drm, 1248 1242 "Incorrect SDVO port. Skip it\n"); 1249 1243 continue; 1250 1244 } 1251 1251 - drm_dbg_kms(&i915->drm, 1252 1252 - "the SDVO device with slave addr %2x is found on" 1245 1245 + drm_dbg_kms(display->drm, 1246 1246 + "the SDVO device with target addr %2x is found on" 1253 1247 " %s port\n", 1254 1254 - child->slave_addr, 1248 1248 + child->target_addr, 1255 1249 (child->dvo_port == DEVICE_PORT_DVOB) ? 1256 1250 "SDVOB" : "SDVOC"); 1257 1257 - mapping = &i915->display.vbt.sdvo_mappings[child->dvo_port - 1]; 1251 1251 + mapping = &display->vbt.sdvo_mappings[child->dvo_port - 1]; 1258 1252 if (!mapping->initialized) { 1259 1253 mapping->dvo_port = child->dvo_port; 1260 1260 - mapping->slave_addr = child->slave_addr; 1254 1254 + mapping->target_addr = child->target_addr; 1261 1255 mapping->dvo_wiring = child->dvo_wiring; 1262 1256 mapping->ddc_pin = child->ddc_pin; 1263 1257 mapping->i2c_pin = child->i2c_pin; 1264 1258 mapping->initialized = 1; 1265 1265 - drm_dbg_kms(&i915->drm, 1259 1259 + drm_dbg_kms(display->drm, 1266 1260 "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", 1267 1267 - mapping->dvo_port, mapping->slave_addr, 1261 1261 + mapping->dvo_port, mapping->target_addr, 1268 1262 mapping->dvo_wiring, mapping->ddc_pin, 1269 1263 mapping->i2c_pin); 1270 1264 } else { 1271 1271 - drm_dbg_kms(&i915->drm, 1265 1265 + drm_dbg_kms(display->drm, 1272 1266 "Maybe one SDVO port is shared by " 1273 1267 "two SDVO device.\n"); 1274 1268 } 1275 1275 - if (child->slave2_addr) { 1269 1269 + if (child->target2_addr) { 1276 1270 /* Maybe this is a SDVO device with multiple inputs */ 1277 1271 /* And the mapping info is not added */ 1278 1278 - drm_dbg_kms(&i915->drm, 1279 1279 - "there exists the slave2_addr. Maybe this" 1272 1272 + drm_dbg_kms(display->drm, 1273 1273 + "there exists the target2_addr. Maybe this" 1280 1274 " is a SDVO device with multiple inputs.\n"); 1281 1275 } 1282 1276 count++; ··· 1284 1278 1285 1279 if (!count) { 1286 1280 /* No SDVO device info is found */ 1287 1287 - drm_dbg_kms(&i915->drm, 1281 1281 + drm_dbg_kms(display->drm, 1288 1282 "No SDVO device info is found in VBT\n"); 1289 1283 } 1290 1284 } 1291 1285 1292 1286 static void 1293 1293 - parse_driver_features(struct drm_i915_private *i915) 1287 1287 + parse_driver_features(struct intel_display *display) 1294 1288 { 1295 1289 const struct bdb_driver_features *driver; 1296 1290 1297 1297 - driver = bdb_find_section(i915, BDB_DRIVER_FEATURES); 1291 1291 + driver = bdb_find_section(display, BDB_DRIVER_FEATURES); 1298 1292 if (!driver) 1299 1293 return; 1300 1294 1301 1301 - if (DISPLAY_VER(i915) >= 5) { 1295 1295 + if (DISPLAY_VER(display) >= 5) { 1302 1296 /* 1303 1297 * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS 1304 1298 * to mean "eDP". The VBT spec doesn't agree with that 1305 1299 * interpretation, but real world VBTs seem to. 1306 1300 */ 1307 1301 if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS) 1308 1308 - i915->display.vbt.int_lvds_support = 0; 1302 1302 + display->vbt.int_lvds_support = 0; 1309 1303 } else { 1310 1304 /* 1311 1305 * FIXME it's not clear which BDB version has the LVDS config ··· 1318 1312 * in the wild with the bits correctly populated. Version 1319 1313 * 108 (on i85x) does not have the bits correctly populated. 1320 1314 */ 1321 1321 - if (i915->display.vbt.version >= 134 && 1315 1315 + if (display->vbt.version >= 134 && 1322 1316 driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS && 1323 1317 driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS) 1324 1324 - i915->display.vbt.int_lvds_support = 0; 1318 1318 + display->vbt.int_lvds_support = 0; 1325 1319 } 1326 1320 } 1327 1321 1328 1322 static void 1329 1329 - parse_panel_driver_features(struct drm_i915_private *i915, 1323 1323 + parse_panel_driver_features(struct intel_display *display, 1330 1324 struct intel_panel *panel) 1331 1325 { 1332 1326 const struct bdb_driver_features *driver; 1333 1327 1334 1334 - driver = bdb_find_section(i915, BDB_DRIVER_FEATURES); 1328 1328 + driver = bdb_find_section(display, BDB_DRIVER_FEATURES); 1335 1329 if (!driver) 1336 1330 return; 1337 1331 1338 1338 - if (i915->display.vbt.version < 228) { 1339 1339 - drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n", 1332 1332 + if (display->vbt.version < 228) { 1333 1333 + drm_dbg_kms(display->drm, "DRRS State Enabled:%d\n", 1340 1334 driver->drrs_enabled); 1341 1335 /* 1342 1336 * If DRRS is not supported, drrs_type has to be set to 0. ··· 1360 1354 } 1361 1355 1362 1356 static void 1363 1363 - parse_power_conservation_features(struct drm_i915_private *i915, 1357 1357 + parse_power_conservation_features(struct intel_display *display, 1364 1358 struct intel_panel *panel) 1365 1359 { 1366 1360 const struct bdb_lfp_power *power; ··· 1368 1362 1369 1363 panel->vbt.vrr = true; /* matches Windows behaviour */ 1370 1364 1371 1371 - if (i915->display.vbt.version < 228) 1365 1365 + if (display->vbt.version < 228) 1372 1366 return; 1373 1367 1374 1374 - power = bdb_find_section(i915, BDB_LFP_POWER); 1368 1368 + power = bdb_find_section(display, BDB_LFP_POWER); 1375 1369 if (!power) 1376 1370 return; 1377 1371 ··· 1394 1388 panel->vbt.drrs_type = DRRS_TYPE_NONE; 1395 1389 } 1396 1390 1397 1397 - if (i915->display.vbt.version >= 232) 1391 1391 + if (display->vbt.version >= 232) 1398 1392 panel->vbt.edp.hobl = panel_bool(power->hobl, panel_type); 1399 1393 1400 1400 - if (i915->display.vbt.version >= 233) 1394 1394 + if (display->vbt.version >= 233) 1401 1395 panel->vbt.vrr = panel_bool(power->vrr_feature_enabled, 1402 1396 panel_type); 1403 1397 } 1404 1398 1405 1399 static void 1406 1406 - parse_edp(struct drm_i915_private *i915, 1400 1400 + parse_edp(struct intel_display *display, 1407 1401 struct intel_panel *panel) 1408 1402 { 1409 1403 const struct bdb_edp *edp; ··· 1411 1405 const struct edp_fast_link_params *edp_link_params; 1412 1406 int panel_type = panel->vbt.panel_type; 1413 1407 1414 1414 - edp = bdb_find_section(i915, BDB_EDP); 1408 1408 + edp = bdb_find_section(display, BDB_EDP); 1415 1409 if (!edp) 1416 1410 return; 1417 1411 ··· 1433 1427 1434 1428 panel->vbt.edp.pps = *edp_pps; 1435 1429 1436 1436 - if (i915->display.vbt.version >= 224) { 1430 1430 + if (display->vbt.version >= 224) { 1437 1431 panel->vbt.edp.rate = 1438 1432 edp->edp_fast_link_training_rate[panel_type] * 20; 1439 1433 } else { ··· 1448 1442 panel->vbt.edp.rate = 540000; 1449 1443 break; 1450 1444 default: 1451 1451 - drm_dbg_kms(&i915->drm, 1445 1445 + drm_dbg_kms(display->drm, 1452 1446 "VBT has unknown eDP link rate value %u\n", 1453 1447 edp_link_params->rate); 1454 1448 break; ··· 1466 1460 panel->vbt.edp.lanes = 4; 1467 1461 break; 1468 1462 default: 1469 1469 - drm_dbg_kms(&i915->drm, 1463 1463 + drm_dbg_kms(display->drm, 1470 1464 "VBT has unknown eDP lane count value %u\n", 1471 1465 edp_link_params->lanes); 1472 1466 break; ··· 1486 1480 panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; 1487 1481 break; 1488 1482 default: 1489 1489 - drm_dbg_kms(&i915->drm, 1483 1483 + drm_dbg_kms(display->drm, 1490 1484 "VBT has unknown eDP pre-emphasis value %u\n", 1491 1485 edp_link_params->preemphasis); 1492 1486 break; ··· 1506 1500 panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 1507 1501 break; 1508 1502 default: 1509 1509 - drm_dbg_kms(&i915->drm, 1503 1503 + drm_dbg_kms(display->drm, 1510 1504 "VBT has unknown eDP voltage swing value %u\n", 1511 1505 edp_link_params->vswing); 1512 1506 break; 1513 1507 } 1514 1508 1515 1515 - if (i915->display.vbt.version >= 173) { 1509 1509 + if (display->vbt.version >= 173) { 1516 1510 u8 vswing; 1517 1511 1518 1512 /* Don't read from VBT if module parameter has valid value*/ 1519 1519 - if (i915->display.params.edp_vswing) { 1513 1513 + if (display->params.edp_vswing) { 1520 1514 panel->vbt.edp.low_vswing = 1521 1521 - i915->display.params.edp_vswing == 1; 1515 1515 + display->params.edp_vswing == 1; 1522 1516 } else { 1523 1517 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; 1524 1518 panel->vbt.edp.low_vswing = vswing == 0; ··· 1528 1522 panel->vbt.edp.drrs_msa_timing_delay = 1529 1523 panel_bits(edp->sdrrs_msa_timing_delay, panel_type, 2); 1530 1524 1531 1531 - if (i915->display.vbt.version >= 244) 1525 1525 + if (display->vbt.version >= 244) 1532 1526 panel->vbt.edp.max_link_rate = 1533 1527 edp->edp_max_port_link_rate[panel_type] * 20; 1534 1528 1535 1535 - if (i915->display.vbt.version >= 251) 1529 1529 + if (display->vbt.version >= 251) 1536 1530 panel->vbt.edp.dsc_disable = 1537 1531 panel_bool(edp->edp_dsc_disable, panel_type); 1538 1532 } 1539 1533 1540 1534 static void 1541 1541 - parse_psr(struct drm_i915_private *i915, 1535 1535 + parse_psr(struct intel_display *display, 1542 1536 struct intel_panel *panel) 1543 1537 { 1538 1538 + struct drm_i915_private *i915 = to_i915(display->drm); 1544 1539 const struct bdb_psr *psr; 1545 1540 const struct psr_table *psr_table; 1546 1541 int panel_type = panel->vbt.panel_type; 1547 1542 1548 1548 - psr = bdb_find_section(i915, BDB_PSR); 1543 1543 + psr = bdb_find_section(display, BDB_PSR); 1549 1544 if (!psr) { 1550 1550 - drm_dbg_kms(&i915->drm, "No PSR BDB found.\n"); 1545 1545 + drm_dbg_kms(display->drm, "No PSR BDB found.\n"); 1551 1546 return; 1552 1547 } 1553 1548 ··· 1565 1558 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us 1566 1559 * Old decimal value is wake up time in multiples of 100 us. 1567 1560 */ 1568 1568 - if (i915->display.vbt.version >= 205 && 1569 1569 - (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) { 1561 1561 + if (display->vbt.version >= 205 && 1562 1562 + (DISPLAY_VER(display) >= 9 && !IS_BROXTON(i915))) { 1570 1563 switch (psr_table->tp1_wakeup_time) { 1571 1564 case 0: 1572 1565 panel->vbt.psr.tp1_wakeup_time_us = 500; ··· 1578 1571 panel->vbt.psr.tp1_wakeup_time_us = 0; 1579 1572 break; 1580 1573 default: 1581 1581 - drm_dbg_kms(&i915->drm, 1574 1574 + drm_dbg_kms(display->drm, 1582 1575 "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", 1583 1576 psr_table->tp1_wakeup_time); 1584 1577 fallthrough; ··· 1598 1591 panel->vbt.psr.tp2_tp3_wakeup_time_us = 0; 1599 1592 break; 1600 1593 default: 1601 1601 - drm_dbg_kms(&i915->drm, 1594 1594 + drm_dbg_kms(display->drm, 1602 1595 "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", 1603 1596 psr_table->tp2_tp3_wakeup_time); 1604 1597 fallthrough; ··· 1611 1604 panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100; 1612 1605 } 1613 1606 1614 1614 - if (i915->display.vbt.version >= 226) { 1607 1607 + if (display->vbt.version >= 226) { 1615 1608 u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time; 1616 1609 1617 1610 wakeup_time = panel_bits(wakeup_time, panel_type, 2); ··· 1637 1630 } 1638 1631 } 1639 1632 1640 1640 - static void parse_dsi_backlight_ports(struct drm_i915_private *i915, 1633 1633 + static void parse_dsi_backlight_ports(struct intel_display *display, 1641 1634 struct intel_panel *panel, 1642 1635 enum port port) 1643 1636 { 1644 1644 - enum port port_bc = DISPLAY_VER(i915) >= 11 ? PORT_B : PORT_C; 1637 1637 + enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C; 1645 1638 1646 1646 - if (!panel->vbt.dsi.config->dual_link || i915->display.vbt.version < 197) { 1639 1639 + if (!panel->vbt.dsi.config->dual_link || display->vbt.version < 197) { 1647 1640 panel->vbt.dsi.bl_ports = BIT(port); 1648 1641 if (panel->vbt.dsi.config->cabc_supported) 1649 1642 panel->vbt.dsi.cabc_ports = BIT(port); ··· 1683 1676 } 1684 1677 1685 1678 static void 1686 1686 - parse_mipi_config(struct drm_i915_private *i915, 1679 1679 + parse_mipi_config(struct intel_display *display, 1687 1680 struct intel_panel *panel) 1688 1681 { 1689 1682 const struct bdb_mipi_config *start; ··· 1693 1686 enum port port; 1694 1687 1695 1688 /* parse MIPI blocks only if LFP type is MIPI */ 1696 1696 - if (!intel_bios_is_dsi_present(i915, &port)) 1689 1689 + if (!intel_bios_is_dsi_present(display, &port)) 1697 1690 return; 1698 1691 1699 1692 /* Initialize this to undefined indicating no generic MIPI support */ 1700 1693 panel->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; 1701 1694 1702 1702 - /* Block #40 is already parsed and panel_fixed_mode is 1703 1703 - * stored in i915->lfp_vbt_mode 1704 1704 - * resuse this when needed 1705 1705 - */ 1706 1706 - 1707 1707 - /* Parse #52 for panel index used from panel_type already 1708 1708 - * parsed 1709 1709 - */ 1710 1710 - start = bdb_find_section(i915, BDB_MIPI_CONFIG); 1695 1695 + start = bdb_find_section(display, BDB_MIPI_CONFIG); 1711 1696 if (!start) { 1712 1712 - drm_dbg_kms(&i915->drm, "No MIPI config BDB found"); 1697 1697 + drm_dbg_kms(display->drm, "No MIPI config BDB found"); 1713 1698 return; 1714 1699 } 1715 1700 1716 1716 - drm_dbg(&i915->drm, "Found MIPI Config block, panel index = %d\n", 1701 1701 + drm_dbg(display->drm, "Found MIPI Config block, panel index = %d\n", 1717 1702 panel_type); 1718 1703 1719 1704 /* ··· 1726 1727 return; 1727 1728 } 1728 1729 1729 1729 - parse_dsi_backlight_ports(i915, panel, port); 1730 1730 + parse_dsi_backlight_ports(display, panel, port); 1730 1731 1731 1732 /* FIXME is the 90 vs. 270 correct? */ 1732 1733 switch (config->rotation) { ··· 1758 1759 1759 1760 /* Find the sequence block and size for the given panel. */ 1760 1761 static const u8 * 1761 1761 - find_panel_sequence_block(struct drm_i915_private *i915, 1762 1762 + find_panel_sequence_block(struct intel_display *display, 1762 1763 const struct bdb_mipi_sequence *sequence, 1763 1764 u16 panel_id, u32 *seq_size) 1764 1765 { ··· 1776 1777 1777 1778 for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) { 1778 1779 if (index + header_size > total) { 1779 1779 - drm_err(&i915->drm, "Invalid sequence block (header)\n"); 1780 1780 + drm_err(display->drm, 1781 1781 + "Invalid sequence block (header)\n"); 1780 1782 return NULL; 1781 1783 } 1782 1784 ··· 1790 1790 index += header_size; 1791 1791 1792 1792 if (index + current_size > total) { 1793 1793 - drm_err(&i915->drm, "Invalid sequence block\n"); 1793 1793 + drm_err(display->drm, "Invalid sequence block\n"); 1794 1794 return NULL; 1795 1795 } 1796 1796 ··· 1802 1802 index += current_size; 1803 1803 } 1804 1804 1805 1805 - drm_err(&i915->drm, "Sequence block detected but no valid configuration\n"); 1805 1805 + drm_err(display->drm, 1806 1806 + "Sequence block detected but no valid configuration\n"); 1806 1807 1807 1808 return NULL; 1808 1809 } 1809 1810 1810 1810 - static int goto_next_sequence(struct drm_i915_private *i915, 1811 1811 + static int goto_next_sequence(struct intel_display *display, 1811 1812 const u8 *data, int index, int total) 1812 1813 { 1813 1814 u16 len; ··· 1839 1838 len = *(data + index + 6) + 7; 1840 1839 break; 1841 1840 default: 1842 1842 - drm_err(&i915->drm, "Unknown operation byte\n"); 1841 1841 + drm_err(display->drm, "Unknown operation byte\n"); 1843 1842 return 0; 1844 1843 } 1845 1844 } ··· 1847 1846 return 0; 1848 1847 } 1849 1848 1850 1850 - static int goto_next_sequence_v3(struct drm_i915_private *i915, 1849 1849 + static int goto_next_sequence_v3(struct intel_display *display, 1851 1850 const u8 *data, int index, int total) 1852 1851 { 1853 1852 int seq_end; ··· 1859 1858 * checking on the structure. 1860 1859 */ 1861 1860 if (total < 5) { 1862 1862 - drm_err(&i915->drm, "Too small sequence size\n"); 1861 1861 + drm_err(display->drm, "Too small sequence size\n"); 1863 1862 return 0; 1864 1863 } 1865 1864 ··· 1876 1875 1877 1876 seq_end = index + size_of_sequence; 1878 1877 if (seq_end > total) { 1879 1879 - drm_err(&i915->drm, "Invalid sequence size\n"); 1878 1878 + drm_err(display->drm, "Invalid sequence size\n"); 1880 1879 return 0; 1881 1880 } 1882 1881 ··· 1886 1885 1887 1886 if (operation_byte == MIPI_SEQ_ELEM_END) { 1888 1887 if (index != seq_end) { 1889 1889 - drm_err(&i915->drm, "Invalid element structure\n"); 1888 1888 + drm_err(display->drm, 1889 1889 + "Invalid element structure\n"); 1890 1890 return 0; 1891 1891 } 1892 1892 return index; ··· 1909 1907 case MIPI_SEQ_ELEM_PMIC: 1910 1908 break; 1911 1909 default: 1912 1912 - drm_err(&i915->drm, "Unknown operation byte %u\n", 1910 1910 + drm_err(display->drm, "Unknown operation byte %u\n", 1913 1911 operation_byte); 1914 1912 break; 1915 1913 } ··· 1922 1920 * Get len of pre-fixed deassert fragment from a v1 init OTP sequence, 1923 1921 * skip all delay + gpio operands and stop at the first DSI packet op. 1924 1922 */ 1925 1925 - static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915, 1923 1923 + static int get_init_otp_deassert_fragment_len(struct intel_display *display, 1926 1924 struct intel_panel *panel) 1927 1925 { 1928 1926 const u8 *data = panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; 1929 1927 int index, len; 1930 1928 1931 1931 - if (drm_WARN_ON(&i915->drm, 1929 1929 + if (drm_WARN_ON(display->drm, 1932 1930 !data || panel->vbt.dsi.seq_version != 1)) 1933 1931 return 0; 1934 1932 ··· 1957 1955 * these devices we split the init OTP sequence into a deassert sequence and 1958 1956 * the actual init OTP part. 1959 1957 */ 1960 1960 - static void vlv_fixup_mipi_sequences(struct drm_i915_private *i915, 1958 1958 + static void vlv_fixup_mipi_sequences(struct intel_display *display, 1961 1959 struct intel_panel *panel) 1962 1960 { 1963 1961 u8 *init_otp; ··· 1975 1973 return; 1976 1974 1977 1975 /* The deassert-sequence ends at the first DSI packet */ 1978 1978 - len = get_init_otp_deassert_fragment_len(i915, panel); 1976 1976 + len = get_init_otp_deassert_fragment_len(display, panel); 1979 1977 if (!len) 1980 1978 return; 1981 1979 1982 1982 - drm_dbg_kms(&i915->drm, 1980 1980 + drm_dbg_kms(display->drm, 1983 1981 "Using init OTP fragment to deassert reset\n"); 1984 1982 1985 1983 /* Copy the fragment, update seq byte and terminate it */ ··· 2012 2010 * or examine the contents of the sequences to 2013 2011 * avoid false positives? 2014 2012 */ 2015 2015 - static void icl_fixup_mipi_sequences(struct drm_i915_private *i915, 2013 2013 + static void icl_fixup_mipi_sequences(struct intel_display *display, 2016 2014 struct intel_panel *panel) 2017 2015 { 2018 2016 if (!panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] && 2019 2017 panel->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON]) { 2020 2020 - drm_dbg_kms(&i915->drm, "Broken VBT: Swapping INIT_OTP and DISPLAY_ON sequences\n"); 2018 2018 + drm_dbg_kms(display->drm, 2019 2019 + "Broken VBT: Swapping INIT_OTP and DISPLAY_ON sequences\n"); 2021 2020 2022 2021 swap(panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP], 2023 2022 panel->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON]); 2024 2023 } 2025 2024 } 2026 2025 2027 2027 - static void fixup_mipi_sequences(struct drm_i915_private *i915, 2026 2026 + static void fixup_mipi_sequences(struct intel_display *display, 2028 2027 struct intel_panel *panel) 2029 2028 { 2030 2030 - if (DISPLAY_VER(i915) >= 11) 2031 2031 - icl_fixup_mipi_sequences(i915, panel); 2029 2029 + struct drm_i915_private *i915 = to_i915(display->drm); 2030 2030 + 2031 2031 + if (DISPLAY_VER(display) >= 11) 2032 2032 + icl_fixup_mipi_sequences(display, panel); 2032 2033 else if (IS_VALLEYVIEW(i915)) 2033 2033 - vlv_fixup_mipi_sequences(i915, panel); 2034 2034 + vlv_fixup_mipi_sequences(display, panel); 2034 2035 } 2035 2036 2036 2037 static void 2037 2037 - parse_mipi_sequence(struct drm_i915_private *i915, 2038 2038 + parse_mipi_sequence(struct intel_display *display, 2038 2039 struct intel_panel *panel) 2039 2040 { 2040 2041 int panel_type = panel->vbt.panel_type; ··· 2051 2046 if (panel->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID) 2052 2047 return; 2053 2048 2054 2054 - sequence = bdb_find_section(i915, BDB_MIPI_SEQUENCE); 2049 2049 + sequence = bdb_find_section(display, BDB_MIPI_SEQUENCE); 2055 2050 if (!sequence) { 2056 2056 - drm_dbg_kms(&i915->drm, 2051 2051 + drm_dbg_kms(display->drm, 2057 2052 "No MIPI Sequence found, parsing complete\n"); 2058 2053 return; 2059 2054 } 2060 2055 2061 2056 /* Fail gracefully for forward incompatible sequence block. */ 2062 2057 if (sequence->version >= 4) { 2063 2063 - drm_err(&i915->drm, 2058 2058 + drm_err(display->drm, 2064 2059 "Unable to parse MIPI Sequence Block v%u\n", 2065 2060 sequence->version); 2066 2061 return; 2067 2062 } 2068 2063 2069 2069 - drm_dbg(&i915->drm, "Found MIPI sequence block v%u\n", 2064 2064 + drm_dbg(display->drm, "Found MIPI sequence block v%u\n", 2070 2065 sequence->version); 2071 2066 2072 2072 - seq_data = find_panel_sequence_block(i915, sequence, panel_type, &seq_size); 2067 2067 + seq_data = find_panel_sequence_block(display, sequence, panel_type, &seq_size); 2073 2068 if (!seq_data) 2074 2069 return; 2075 2070 ··· 2084 2079 break; 2085 2080 2086 2081 if (seq_id >= MIPI_SEQ_MAX) { 2087 2087 - drm_err(&i915->drm, "Unknown sequence %u\n", 2082 2082 + drm_err(display->drm, "Unknown sequence %u\n", 2088 2083 seq_id); 2089 2084 goto err; 2090 2085 } 2091 2086 2092 2087 /* Log about presence of sequences we won't run. */ 2093 2088 if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF) 2094 2094 - drm_dbg_kms(&i915->drm, 2089 2089 + drm_dbg_kms(display->drm, 2095 2090 "Unsupported sequence %u\n", seq_id); 2096 2091 2097 2092 panel->vbt.dsi.sequence[seq_id] = data + index; 2098 2093 2099 2094 if (sequence->version >= 3) 2100 2100 - index = goto_next_sequence_v3(i915, data, index, seq_size); 2095 2095 + index = goto_next_sequence_v3(display, data, index, seq_size); 2101 2096 else 2102 2102 - index = goto_next_sequence(i915, data, index, seq_size); 2097 2097 + index = goto_next_sequence(display, data, index, seq_size); 2103 2098 if (!index) { 2104 2104 - drm_err(&i915->drm, "Invalid sequence %u\n", 2099 2099 + drm_err(display->drm, "Invalid sequence %u\n", 2105 2100 seq_id); 2106 2101 goto err; 2107 2102 } ··· 2111 2106 panel->vbt.dsi.size = seq_size; 2112 2107 panel->vbt.dsi.seq_version = sequence->version; 2113 2108 2114 2114 - fixup_mipi_sequences(i915, panel); 2109 2109 + fixup_mipi_sequences(display, panel); 2115 2110 2116 2116 - drm_dbg(&i915->drm, "MIPI related VBT parsing complete\n"); 2111 2111 + drm_dbg(display->drm, "MIPI related VBT parsing complete\n"); 2117 2112 return; 2118 2113 2119 2114 err: ··· 2122 2117 } 2123 2118 2124 2119 static void 2125 2125 - parse_compression_parameters(struct drm_i915_private *i915) 2120 2120 + parse_compression_parameters(struct intel_display *display) 2126 2121 { 2127 2122 const struct bdb_compression_parameters *params; 2128 2123 struct intel_bios_encoder_data *devdata; 2129 2124 u16 block_size; 2130 2125 int index; 2131 2126 2132 2132 - if (i915->display.vbt.version < 198) 2127 2127 + if (display->vbt.version < 198) 2133 2128 return; 2134 2129 2135 2135 - params = bdb_find_section(i915, BDB_COMPRESSION_PARAMETERS); 2130 2130 + params = bdb_find_section(display, BDB_COMPRESSION_PARAMETERS); 2136 2131 if (params) { 2137 2132 /* Sanity checks */ 2138 2133 if (params->entry_size != sizeof(params->data[0])) { 2139 2139 - drm_dbg_kms(&i915->drm, 2134 2134 + drm_dbg_kms(display->drm, 2140 2135 "VBT: unsupported compression param entry size\n"); 2141 2136 return; 2142 2137 } 2143 2138 2144 2139 block_size = get_blocksize(params); 2145 2140 if (block_size < sizeof(*params)) { 2146 2146 - drm_dbg_kms(&i915->drm, 2141 2141 + drm_dbg_kms(display->drm, 2147 2142 "VBT: expected 16 compression param entries\n"); 2148 2143 return; 2149 2144 } 2150 2145 } 2151 2146 2152 2152 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { 2147 2147 + list_for_each_entry(devdata, &display->vbt.display_devices, node) { 2153 2148 const struct child_device_config *child = &devdata->child; 2154 2149 2155 2150 if (!child->compression_enable) 2156 2151 continue; 2157 2152 2158 2153 if (!params) { 2159 2159 - drm_dbg_kms(&i915->drm, 2154 2154 + drm_dbg_kms(display->drm, 2160 2155 "VBT: compression params not available\n"); 2161 2156 continue; 2162 2157 } 2163 2158 2164 2159 if (child->compression_method_cps) { 2165 2165 - drm_dbg_kms(&i915->drm, 2160 2160 + drm_dbg_kms(display->drm, 2166 2161 "VBT: CPS compression not supported\n"); 2167 2162 continue; 2168 2163 } ··· 2174 2169 } 2175 2170 } 2176 2171 2177 2177 - static u8 translate_iboost(struct drm_i915_private *i915, u8 val) 2172 2172 + static u8 translate_iboost(struct intel_display *display, u8 val) 2178 2173 { 2179 2174 static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ 2180 2175 2181 2176 if (val >= ARRAY_SIZE(mapping)) { 2182 2182 - drm_dbg_kms(&i915->drm, 2177 2177 + drm_dbg_kms(display->drm, 2183 2178 "Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); 2184 2179 return 0; 2185 2180 } ··· 2236 2231 [GMBUS_PIN_12_TC4_ICP] = ADLP_DDC_BUS_PORT_TC4, 2237 2232 }; 2238 2233 2239 2239 - static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) 2234 2234 + static u8 map_ddc_pin(struct intel_display *display, u8 vbt_pin) 2240 2235 { 2236 2236 + struct drm_i915_private *i915 = to_i915(display->drm); 2241 2237 const u8 *ddc_pin_map; 2242 2238 int i, n_entries; 2243 2239 ··· 2253 2247 } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { 2254 2248 ddc_pin_map = rkl_pch_tgp_ddc_pin_map; 2255 2249 n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); 2256 2256 - } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) { 2250 2250 + } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(display) == 9) { 2257 2251 ddc_pin_map = gen9bc_tgp_ddc_pin_map; 2258 2252 n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); 2259 2253 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { ··· 2272 2266 return i; 2273 2267 } 2274 2268 2275 2275 - drm_dbg_kms(&i915->drm, 2269 2269 + drm_dbg_kms(display->drm, 2276 2270 "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", 2277 2271 vbt_pin); 2278 2272 return 0; ··· 2330 2324 return PORT_NONE; 2331 2325 } 2332 2326 2333 2333 - static enum port dvo_port_to_port(struct drm_i915_private *i915, 2327 2327 + static enum port dvo_port_to_port(struct intel_display *display, 2334 2328 u8 dvo_port) 2335 2329 { 2330 2330 + struct drm_i915_private *i915 = to_i915(display->drm); 2336 2331 /* 2337 2332 * Each DDI port can have more than one value on the "DVO Port" field, 2338 2333 * so look for all the possible values for each port. ··· 2385 2378 [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, 2386 2379 }; 2387 2380 2388 2388 - if (DISPLAY_VER(i915) >= 13) 2381 2381 + if (DISPLAY_VER(display) >= 13) 2389 2382 return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping), 2390 2383 ARRAY_SIZE(xelpd_port_mapping[0]), 2391 2384 xelpd_port_mapping, ··· 2408 2401 } 2409 2402 2410 2403 static enum port 2411 2411 - dsi_dvo_port_to_port(struct drm_i915_private *i915, u8 dvo_port) 2404 2404 + dsi_dvo_port_to_port(struct intel_display *display, u8 dvo_port) 2412 2405 { 2413 2406 switch (dvo_port) { 2414 2407 case DVO_PORT_MIPIA: 2415 2408 return PORT_A; 2416 2409 case DVO_PORT_MIPIC: 2417 2417 - if (DISPLAY_VER(i915) >= 11) 2410 2410 + if (DISPLAY_VER(display) >= 11) 2418 2411 return PORT_B; 2419 2412 else 2420 2413 return PORT_C; ··· 2425 2418 2426 2419 enum port intel_bios_encoder_port(const struct intel_bios_encoder_data *devdata) 2427 2420 { 2428 2428 - struct drm_i915_private *i915 = devdata->i915; 2421 2421 + struct intel_display *display = devdata->display; 2429 2422 const struct child_device_config *child = &devdata->child; 2430 2423 enum port port; 2431 2424 2432 2432 - port = dvo_port_to_port(i915, child->dvo_port); 2433 2433 - if (port == PORT_NONE && DISPLAY_VER(i915) >= 11) 2434 2434 - port = dsi_dvo_port_to_port(i915, child->dvo_port); 2425 2425 + port = dvo_port_to_port(display, child->dvo_port); 2426 2426 + if (port == PORT_NONE && DISPLAY_VER(display) >= 11) 2427 2427 + port = dsi_dvo_port_to_port(display, child->dvo_port); 2435 2428 2436 2429 return port; 2437 2430 } ··· 2476 2469 2477 2470 int intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata) 2478 2471 { 2479 2479 - if (!devdata || devdata->i915->display.vbt.version < 216) 2472 2472 + if (!devdata || devdata->display->vbt.version < 216) 2480 2473 return 0; 2481 2474 2482 2482 - if (devdata->i915->display.vbt.version >= 230) 2475 2475 + if (devdata->display->vbt.version >= 230) 2483 2476 return parse_bdb_230_dp_max_link_rate(devdata->child.dp_max_link_rate); 2484 2477 else 2485 2478 return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate); ··· 2487 2480 2488 2481 int intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata) 2489 2482 { 2490 2490 - if (!devdata || devdata->i915->display.vbt.version < 244) 2483 2483 + if (!devdata || devdata->display->vbt.version < 244) 2491 2484 return 0; 2492 2485 2493 2486 return devdata->child.dp_max_lane_count + 1; ··· 2496 2489 static void sanitize_device_type(struct intel_bios_encoder_data *devdata, 2497 2490 enum port port) 2498 2491 { 2499 2499 - struct drm_i915_private *i915 = devdata->i915; 2492 2492 + struct intel_display *display = devdata->display; 2500 2493 bool is_hdmi; 2501 2494 2502 2502 - if (port != PORT_A || DISPLAY_VER(i915) >= 12) 2495 2495 + if (port != PORT_A || DISPLAY_VER(display) >= 12) 2503 2496 return; 2504 2497 2505 2498 if (!intel_bios_encoder_supports_dvi(devdata)) ··· 2507 2500 2508 2501 is_hdmi = intel_bios_encoder_supports_hdmi(devdata); 2509 2502 2510 2510 - drm_dbg_kms(&i915->drm, "VBT claims port A supports DVI%s, ignoring\n", 2503 2503 + drm_dbg_kms(display->drm, "VBT claims port A supports DVI%s, ignoring\n", 2511 2504 is_hdmi ? "/HDMI" : ""); 2512 2505 2513 2506 devdata->child.device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING; ··· 2517 2510 static void sanitize_hdmi_level_shift(struct intel_bios_encoder_data *devdata, 2518 2511 enum port port) 2519 2512 { 2520 2520 - struct drm_i915_private *i915 = devdata->i915; 2513 2513 + struct intel_display *display = devdata->display; 2514 2514 + struct drm_i915_private *i915 = to_i915(display->drm); 2521 2515 2522 2516 if (!intel_bios_encoder_supports_dvi(devdata)) 2523 2517 return; ··· 2529 2521 * up to 11, whereas the BDW max is 9. 2530 2522 */ 2531 2523 if (IS_BROADWELL(i915) && devdata->child.hdmi_level_shifter_value > 9) { 2532 2532 - drm_dbg_kms(&i915->drm, "Bogus port %c VBT HDMI level shift %d, adjusting to %d\n", 2524 2524 + drm_dbg_kms(display->drm, 2525 2525 + "Bogus port %c VBT HDMI level shift %d, adjusting to %d\n", 2533 2526 port_name(port), devdata->child.hdmi_level_shifter_value, 9); 2534 2527 2535 2528 devdata->child.hdmi_level_shifter_value = 9; ··· 2578 2569 bool 2579 2570 intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata) 2580 2571 { 2581 2581 - return devdata && HAS_LSPCON(devdata->i915) && devdata->child.lspcon; 2572 2572 + return devdata && HAS_LSPCON(devdata->display) && devdata->child.lspcon; 2582 2573 } 2583 2574 2584 2575 /* This is an index in the HDMI/DVI DDI buffer translation table, or -1 */ 2585 2576 int intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata) 2586 2577 { 2587 2587 - if (!devdata || devdata->i915->display.vbt.version < 158 || 2588 2588 - DISPLAY_VER(devdata->i915) >= 14) 2578 2578 + if (!devdata || devdata->display->vbt.version < 158 || 2579 2579 + DISPLAY_VER(devdata->display) >= 14) 2589 2580 return -1; 2590 2581 2591 2582 return devdata->child.hdmi_level_shifter_value; ··· 2593 2584 2594 2585 int intel_bios_hdmi_max_tmds_clock(const struct intel_bios_encoder_data *devdata) 2595 2586 { 2596 2596 - if (!devdata || devdata->i915->display.vbt.version < 204) 2587 2587 + if (!devdata || devdata->display->vbt.version < 204) 2597 2588 return 0; 2598 2589 2599 2590 switch (devdata->child.hdmi_max_data_rate) { ··· 2615 2606 } 2616 2607 } 2617 2608 2618 2618 - static bool is_port_valid(struct drm_i915_private *i915, enum port port) 2609 2609 + static bool is_port_valid(struct intel_display *display, enum port port) 2619 2610 { 2611 2611 + struct drm_i915_private *i915 = to_i915(display->drm); 2620 2612 /* 2621 2613 * On some ICL SKUs port F is not present, but broken VBTs mark 2622 2614 * the port as present. Only try to initialize port F for the ··· 2631 2621 2632 2622 static void print_ddi_port(const struct intel_bios_encoder_data *devdata) 2633 2623 { 2634 2634 - struct drm_i915_private *i915 = devdata->i915; 2624 2624 + struct intel_display *display = devdata->display; 2635 2625 const struct child_device_config *child = &devdata->child; 2636 2626 bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb, supports_tbt; 2637 2627 int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock; ··· 2651 2641 supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata); 2652 2642 supports_tbt = intel_bios_encoder_supports_tbt(devdata); 2653 2643 2654 2654 - drm_dbg_kms(&i915->drm, 2644 2644 + drm_dbg_kms(display->drm, 2655 2645 "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d DSI:%d DP++:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n", 2656 2646 port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, is_dsi, 2657 2647 intel_bios_encoder_supports_dp_dual_mode(devdata), ··· 2661 2651 2662 2652 hdmi_level_shift = intel_bios_hdmi_level_shift(devdata); 2663 2653 if (hdmi_level_shift >= 0) { 2664 2664 - drm_dbg_kms(&i915->drm, 2654 2654 + drm_dbg_kms(display->drm, 2665 2655 "Port %c VBT HDMI level shift: %d\n", 2666 2656 port_name(port), hdmi_level_shift); 2667 2657 } 2668 2658 2669 2659 max_tmds_clock = intel_bios_hdmi_max_tmds_clock(devdata); 2670 2660 if (max_tmds_clock) 2671 2671 - drm_dbg_kms(&i915->drm, 2661 2661 + drm_dbg_kms(display->drm, 2672 2662 "Port %c VBT HDMI max TMDS clock: %d kHz\n", 2673 2663 port_name(port), max_tmds_clock); 2674 2664 2675 2665 /* I_boost config for SKL and above */ 2676 2666 dp_boost_level = intel_bios_dp_boost_level(devdata); 2677 2667 if (dp_boost_level) 2678 2678 - drm_dbg_kms(&i915->drm, 2668 2668 + drm_dbg_kms(display->drm, 2679 2669 "Port %c VBT (e)DP boost level: %d\n", 2680 2670 port_name(port), dp_boost_level); 2681 2671 2682 2672 hdmi_boost_level = intel_bios_hdmi_boost_level(devdata); 2683 2673 if (hdmi_boost_level) 2684 2684 - drm_dbg_kms(&i915->drm, 2674 2674 + drm_dbg_kms(display->drm, 2685 2675 "Port %c VBT HDMI boost level: %d\n", 2686 2676 port_name(port), hdmi_boost_level); 2687 2677 2688 2678 dp_max_link_rate = intel_bios_dp_max_link_rate(devdata); 2689 2679 if (dp_max_link_rate) 2690 2690 - drm_dbg_kms(&i915->drm, 2680 2680 + drm_dbg_kms(display->drm, 2691 2681 "Port %c VBT DP max link rate: %d\n", 2692 2682 port_name(port), dp_max_link_rate); 2693 2683 ··· 2695 2685 * FIXME need to implement support for VBT 2696 2686 * vswing/preemph tables should this ever trigger. 2697 2687 */ 2698 2698 - drm_WARN(&i915->drm, child->use_vbt_vswing, 2688 2688 + drm_WARN(display->drm, child->use_vbt_vswing, 2699 2689 "Port %c asks to use VBT vswing/preemph tables\n", 2700 2690 port_name(port)); 2701 2691 } 2702 2692 2703 2693 static void parse_ddi_port(struct intel_bios_encoder_data *devdata) 2704 2694 { 2705 2705 - struct drm_i915_private *i915 = devdata->i915; 2695 2695 + struct intel_display *display = devdata->display; 2706 2696 enum port port; 2707 2697 2708 2698 port = intel_bios_encoder_port(devdata); 2709 2699 if (port == PORT_NONE) 2710 2700 return; 2711 2701 2712 2712 - if (!is_port_valid(i915, port)) { 2713 2713 - drm_dbg_kms(&i915->drm, 2702 2702 + if (!is_port_valid(display, port)) { 2703 2703 + drm_dbg_kms(display->drm, 2714 2704 "VBT reports port %c as supported, but that can't be true: skipping\n", 2715 2705 port_name(port)); 2716 2706 return; ··· 2720 2710 sanitize_hdmi_level_shift(devdata, port); 2721 2711 } 2722 2712 2723 2723 - static bool has_ddi_port_info(struct drm_i915_private *i915) 2713 2713 + static bool has_ddi_port_info(struct intel_display *display) 2724 2714 { 2725 2725 - return DISPLAY_VER(i915) >= 5 || IS_G4X(i915); 2715 2715 + struct drm_i915_private *i915 = to_i915(display->drm); 2716 2716 + 2717 2717 + return DISPLAY_VER(display) >= 5 || IS_G4X(i915); 2726 2718 } 2727 2719 2728 2728 - static void parse_ddi_ports(struct drm_i915_private *i915) 2720 2720 + static void parse_ddi_ports(struct intel_display *display) 2729 2721 { 2730 2722 struct intel_bios_encoder_data *devdata; 2731 2723 2732 2732 - if (!has_ddi_port_info(i915)) 2724 2724 + if (!has_ddi_port_info(display)) 2733 2725 return; 2734 2726 2735 2735 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) 2727 2727 + list_for_each_entry(devdata, &display->vbt.display_devices, node) 2736 2728 parse_ddi_port(devdata); 2737 2729 2738 2738 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) 2730 2730 + list_for_each_entry(devdata, &display->vbt.display_devices, node) 2739 2731 print_ddi_port(devdata); 2740 2732 } 2741 2733 ··· 2763 2751 return 22; 2764 2752 } 2765 2753 2766 2766 - static bool child_device_size_valid(struct drm_i915_private *i915, int size) 2754 2754 + static bool child_device_size_valid(struct intel_display *display, int size) 2767 2755 { 2768 2756 int expected_size; 2769 2757 2770 2770 - expected_size = child_device_expected_size(i915->display.vbt.version); 2758 2758 + expected_size = child_device_expected_size(display->vbt.version); 2771 2759 if (expected_size < 0) { 2772 2760 expected_size = sizeof(struct child_device_config); 2773 2773 - drm_dbg(&i915->drm, 2761 2761 + drm_dbg(display->drm, 2774 2762 "Expected child device config size for VBT version %u not known; assuming %d\n", 2775 2775 - i915->display.vbt.version, expected_size); 2763 2763 + display->vbt.version, expected_size); 2776 2764 } 2777 2765 2778 2766 /* Flag an error for unexpected size, but continue anyway. */ 2779 2767 if (size != expected_size) 2780 2780 - drm_err(&i915->drm, 2768 2768 + drm_err(display->drm, 2781 2769 "Unexpected child device config size %d (expected %d for VBT version %u)\n", 2782 2782 - size, expected_size, i915->display.vbt.version); 2770 2770 + size, expected_size, display->vbt.version); 2783 2771 2784 2772 /* The legacy sized child device config is the minimum we need. */ 2785 2773 if (size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { 2786 2786 - drm_dbg_kms(&i915->drm, 2774 2774 + drm_dbg_kms(display->drm, 2787 2775 "Child device config size %d is too small.\n", 2788 2776 size); 2789 2777 return false; ··· 2793 2781 } 2794 2782 2795 2783 static void 2796 2796 - parse_general_definitions(struct drm_i915_private *i915) 2784 2784 + parse_general_definitions(struct intel_display *display) 2797 2785 { 2786 2786 + struct drm_i915_private *i915 = to_i915(display->drm); 2798 2787 const struct bdb_general_definitions *defs; 2799 2788 struct intel_bios_encoder_data *devdata; 2800 2789 const struct child_device_config *child; ··· 2803 2790 u16 block_size; 2804 2791 int bus_pin; 2805 2792 2806 2806 - defs = bdb_find_section(i915, BDB_GENERAL_DEFINITIONS); 2793 2793 + defs = bdb_find_section(display, BDB_GENERAL_DEFINITIONS); 2807 2794 if (!defs) { 2808 2808 - drm_dbg_kms(&i915->drm, 2795 2795 + drm_dbg_kms(display->drm, 2809 2796 "No general definition block is found, no devices defined.\n"); 2810 2797 return; 2811 2798 } 2812 2799 2813 2800 block_size = get_blocksize(defs); 2814 2801 if (block_size < sizeof(*defs)) { 2815 2815 - drm_dbg_kms(&i915->drm, 2802 2802 + drm_dbg_kms(display->drm, 2816 2803 "General definitions block too small (%u)\n", 2817 2804 block_size); 2818 2805 return; 2819 2806 } 2820 2807 2821 2808 bus_pin = defs->crt_ddc_gmbus_pin; 2822 2822 - drm_dbg_kms(&i915->drm, "crt_ddc_bus_pin: %d\n", bus_pin); 2809 2809 + drm_dbg_kms(display->drm, "crt_ddc_bus_pin: %d\n", bus_pin); 2823 2810 if (intel_gmbus_is_valid_pin(i915, bus_pin)) 2824 2824 - i915->display.vbt.crt_ddc_pin = bus_pin; 2811 2811 + display->vbt.crt_ddc_pin = bus_pin; 2825 2812 2826 2826 - if (!child_device_size_valid(i915, defs->child_dev_size)) 2813 2813 + if (!child_device_size_valid(display, defs->child_dev_size)) 2827 2814 return; 2828 2815 2829 2816 /* get the number of child device */ ··· 2834 2821 if (!child->device_type) 2835 2822 continue; 2836 2823 2837 2837 - drm_dbg_kms(&i915->drm, 2824 2824 + drm_dbg_kms(display->drm, 2838 2825 "Found VBT child device with type 0x%x\n", 2839 2826 child->device_type); 2840 2827 ··· 2842 2829 if (!devdata) 2843 2830 break; 2844 2831 2845 2845 - devdata->i915 = i915; 2832 2832 + devdata->display = display; 2846 2833 2847 2834 /* 2848 2835 * Copy as much as we know (sizeof) and is available ··· 2852 2839 memcpy(&devdata->child, child, 2853 2840 min_t(size_t, defs->child_dev_size, sizeof(*child))); 2854 2841 2855 2855 - list_add_tail(&devdata->node, &i915->display.vbt.display_devices); 2842 2842 + list_add_tail(&devdata->node, &display->vbt.display_devices); 2856 2843 } 2857 2844 2858 2858 - if (list_empty(&i915->display.vbt.display_devices)) 2859 2859 - drm_dbg_kms(&i915->drm, 2845 2845 + if (list_empty(&display->vbt.display_devices)) 2846 2846 + drm_dbg_kms(display->drm, 2860 2847 "no child dev is parsed from VBT\n"); 2861 2848 } 2862 2849 2863 2850 /* Common defaults which may be overridden by VBT. */ 2864 2851 static void 2865 2865 - init_vbt_defaults(struct drm_i915_private *i915) 2852 2852 + init_vbt_defaults(struct intel_display *display) 2866 2853 { 2867 2867 - i915->display.vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; 2854 2854 + struct drm_i915_private *i915 = to_i915(display->drm); 2855 2855 + 2856 2856 + display->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; 2868 2857 2869 2858 /* general features */ 2870 2870 - i915->display.vbt.int_tv_support = 1; 2871 2871 - i915->display.vbt.int_crt_support = 1; 2859 2859 + display->vbt.int_tv_support = 1; 2860 2860 + display->vbt.int_crt_support = 1; 2872 2861 2873 2862 /* driver features */ 2874 2874 - i915->display.vbt.int_lvds_support = 1; 2863 2863 + display->vbt.int_lvds_support = 1; 2875 2864 2876 2865 /* Default to using SSC */ 2877 2877 - i915->display.vbt.lvds_use_ssc = 1; 2866 2866 + display->vbt.lvds_use_ssc = 1; 2878 2867 /* 2879 2868 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference 2880 2869 * clock for LVDS. 2881 2870 */ 2882 2882 - i915->display.vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915, 2883 2883 - !HAS_PCH_SPLIT(i915)); 2884 2884 - drm_dbg_kms(&i915->drm, "Set default to SSC at %d kHz\n", 2885 2885 - i915->display.vbt.lvds_ssc_freq); 2871 2871 + display->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(display, 2872 2872 + !HAS_PCH_SPLIT(i915)); 2873 2873 + drm_dbg_kms(display->drm, "Set default to SSC at %d kHz\n", 2874 2874 + display->vbt.lvds_ssc_freq); 2886 2875 } 2887 2876 2888 2877 /* Common defaults which may be overridden by VBT. */ ··· 2900 2885 2901 2886 /* Defaults to initialize only if there is no VBT. */ 2902 2887 static void 2903 2903 - init_vbt_missing_defaults(struct drm_i915_private *i915) 2888 2888 + init_vbt_missing_defaults(struct intel_display *display) 2904 2889 { 2905 2905 - unsigned int ports = DISPLAY_RUNTIME_INFO(i915)->port_mask; 2890 2890 + struct drm_i915_private *i915 = to_i915(display->drm); 2891 2891 + unsigned int ports = DISPLAY_RUNTIME_INFO(display)->port_mask; 2906 2892 enum port port; 2907 2893 2908 2908 - if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915)) 2894 2894 + if (!HAS_DDI(display) && !IS_CHERRYVIEW(i915)) 2909 2895 return; 2910 2896 2911 2897 for_each_port_masked(port, ports) { ··· 2926 2910 if (!devdata) 2927 2911 break; 2928 2912 2929 2929 - devdata->i915 = i915; 2913 2913 + devdata->display = display; 2930 2914 child = &devdata->child; 2931 2915 2932 2916 if (port == PORT_F) ··· 2945 2929 if (port == PORT_A) 2946 2930 child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR; 2947 2931 2948 2948 - list_add_tail(&devdata->node, &i915->display.vbt.display_devices); 2932 2932 + list_add_tail(&devdata->node, &display->vbt.display_devices); 2949 2933 2950 2950 - drm_dbg_kms(&i915->drm, 2934 2934 + drm_dbg_kms(display->drm, 2951 2935 "Generating default VBT child device with type 0x04%x on port %c\n", 2952 2936 child->device_type, port_name(port)); 2953 2937 } 2954 2938 2955 2939 /* Bypass some minimum baseline VBT version checks */ 2956 2956 - i915->display.vbt.version = 155; 2940 2940 + display->vbt.version = 155; 2957 2941 } 2958 2942 2959 2943 static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) ··· 2965 2949 2966 2950 /** 2967 2951 * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT 2968 2968 - * @i915: the device 2952 2952 + * @display: display device 2969 2953 * @buf: pointer to a buffer to validate 2970 2954 * @size: size of the buffer 2971 2955 * 2972 2956 * Returns true on valid VBT. 2973 2957 */ 2974 2974 - bool intel_bios_is_valid_vbt(struct drm_i915_private *i915, 2958 2958 + bool intel_bios_is_valid_vbt(struct intel_display *display, 2975 2959 const void *buf, size_t size) 2976 2960 { 2977 2961 const struct vbt_header *vbt = buf; ··· 2981 2965 return false; 2982 2966 2983 2967 if (sizeof(struct vbt_header) > size) { 2984 2984 - drm_dbg_kms(&i915->drm, "VBT header incomplete\n"); 2968 2968 + drm_dbg_kms(display->drm, "VBT header incomplete\n"); 2985 2969 return false; 2986 2970 } 2987 2971 2988 2972 if (memcmp(vbt->signature, "$VBT", 4)) { 2989 2989 - drm_dbg_kms(&i915->drm, "VBT invalid signature\n"); 2973 2973 + drm_dbg_kms(display->drm, "VBT invalid signature\n"); 2990 2974 return false; 2991 2975 } 2992 2976 2993 2977 if (vbt->vbt_size > size) { 2994 2994 - drm_dbg_kms(&i915->drm, "VBT incomplete (vbt_size overflows)\n"); 2978 2978 + drm_dbg_kms(display->drm, 2979 2979 + "VBT incomplete (vbt_size overflows)\n"); 2995 2980 return false; 2996 2981 } 2997 2982 ··· 3002 2985 vbt->bdb_offset, 3003 2986 sizeof(struct bdb_header), 3004 2987 size)) { 3005 3005 - drm_dbg_kms(&i915->drm, "BDB header incomplete\n"); 2988 2988 + drm_dbg_kms(display->drm, "BDB header incomplete\n"); 3006 2989 return false; 3007 2990 } 3008 2991 3009 2992 bdb = get_bdb_header(vbt); 3010 2993 if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) { 3011 3011 - drm_dbg_kms(&i915->drm, "BDB incomplete\n"); 2994 2994 + drm_dbg_kms(display->drm, "BDB incomplete\n"); 3012 2995 return false; 3013 2996 } 3014 2997 3015 2998 return vbt; 3016 2999 } 3017 3000 3018 3018 - static struct vbt_header *firmware_get_vbt(struct drm_i915_private *i915, 3001 3001 + static struct vbt_header *firmware_get_vbt(struct intel_display *display, 3019 3002 size_t *size) 3020 3003 { 3021 3004 struct vbt_header *vbt = NULL; 3022 3005 const struct firmware *fw = NULL; 3023 3023 - const char *name = i915->display.params.vbt_firmware; 3006 3006 + const char *name = display->params.vbt_firmware; 3024 3007 int ret; 3025 3008 3026 3009 if (!name || !*name) 3027 3010 return NULL; 3028 3011 3029 3029 - ret = request_firmware(&fw, name, i915->drm.dev); 3012 3012 + ret = request_firmware(&fw, name, display->drm->dev); 3030 3013 if (ret) { 3031 3031 - drm_err(&i915->drm, 3014 3014 + drm_err(display->drm, 3032 3015 "Requesting VBT firmware \"%s\" failed (%d)\n", 3033 3016 name, ret); 3034 3017 return NULL; 3035 3018 } 3036 3019 3037 3037 - if (intel_bios_is_valid_vbt(i915, fw->data, fw->size)) { 3020 3020 + if (intel_bios_is_valid_vbt(display, fw->data, fw->size)) { 3038 3021 vbt = kmemdup(fw->data, fw->size, GFP_KERNEL); 3039 3022 if (vbt) { 3040 3040 - drm_dbg_kms(&i915->drm, 3023 3023 + drm_dbg_kms(display->drm, 3041 3024 "Found valid VBT firmware \"%s\"\n", name); 3042 3025 if (size) 3043 3026 *size = fw->size; 3044 3027 } 3045 3028 } else { 3046 3046 - drm_dbg_kms(&i915->drm, "Invalid VBT firmware \"%s\"\n", 3029 3029 + drm_dbg_kms(display->drm, "Invalid VBT firmware \"%s\"\n", 3047 3030 name); 3048 3031 } 3049 3032 ··· 3059 3042 return intel_uncore_read(uncore, PRIMARY_SPI_TRIGGER); 3060 3043 } 3061 3044 3062 3062 - static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915, 3045 3045 + static struct vbt_header *spi_oprom_get_vbt(struct intel_display *display, 3063 3046 size_t *size) 3064 3047 { 3048 3048 + struct drm_i915_private *i915 = to_i915(display->drm); 3065 3049 u32 count, data, found, store = 0; 3066 3050 u32 static_region, oprom_offset; 3067 3051 u32 oprom_size = 0x200000; ··· 3099 3081 for (count = 0; count < vbt_size; count += 4) 3100 3082 *(vbt + store++) = intel_spi_read(&i915->uncore, found + count); 3101 3083 3102 3102 - if (!intel_bios_is_valid_vbt(i915, vbt, vbt_size)) 3084 3084 + if (!intel_bios_is_valid_vbt(display, vbt, vbt_size)) 3103 3085 goto err_free_vbt; 3104 3086 3105 3105 - drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n"); 3087 3087 + drm_dbg_kms(display->drm, "Found valid VBT in SPI flash\n"); 3106 3088 3107 3089 if (size) 3108 3090 *size = vbt_size; ··· 3115 3097 return NULL; 3116 3098 } 3117 3099 3118 3118 - static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915, 3100 3100 + static struct vbt_header *oprom_get_vbt(struct intel_display *display, 3119 3101 size_t *sizep) 3120 3102 { 3121 3121 - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 3103 3103 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 3122 3104 void __iomem *p = NULL, *oprom; 3123 3105 struct vbt_header *vbt; 3124 3106 u16 vbt_size; ··· 3142 3124 goto err_unmap_oprom; 3143 3125 3144 3126 if (sizeof(struct vbt_header) > size) { 3145 3145 - drm_dbg(&i915->drm, "VBT header incomplete\n"); 3127 3127 + drm_dbg(display->drm, "VBT header incomplete\n"); 3146 3128 goto err_unmap_oprom; 3147 3129 } 3148 3130 3149 3131 vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size)); 3150 3132 if (vbt_size > size) { 3151 3151 - drm_dbg(&i915->drm, 3133 3133 + drm_dbg(display->drm, 3152 3134 "VBT incomplete (vbt_size overflows)\n"); 3153 3135 goto err_unmap_oprom; 3154 3136 } ··· 3160 3142 3161 3143 memcpy_fromio(vbt, p, vbt_size); 3162 3144 3163 3163 - if (!intel_bios_is_valid_vbt(i915, vbt, vbt_size)) 3145 3145 + if (!intel_bios_is_valid_vbt(display, vbt, vbt_size)) 3164 3146 goto err_free_vbt; 3165 3147 3166 3148 pci_unmap_rom(pdev, oprom); ··· 3168 3150 if (sizep) 3169 3151 *sizep = vbt_size; 3170 3152 3171 3171 - drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n"); 3153 3153 + drm_dbg_kms(display->drm, "Found valid VBT in PCI ROM\n"); 3172 3154 3173 3155 return vbt; 3174 3156 ··· 3180 3162 return NULL; 3181 3163 } 3182 3164 3183 3183 - static const struct vbt_header *intel_bios_get_vbt(struct drm_i915_private *i915, 3165 3165 + static const struct vbt_header *intel_bios_get_vbt(struct intel_display *display, 3184 3166 size_t *sizep) 3185 3167 { 3168 3168 + struct drm_i915_private *i915 = to_i915(display->drm); 3186 3169 const struct vbt_header *vbt = NULL; 3187 3170 intel_wakeref_t wakeref; 3188 3171 3189 3189 - vbt = firmware_get_vbt(i915, sizep); 3172 3172 + vbt = firmware_get_vbt(display, sizep); 3190 3173 3191 3174 if (!vbt) 3192 3192 - vbt = intel_opregion_get_vbt(i915, sizep); 3175 3175 + vbt = intel_opregion_get_vbt(display, sizep); 3193 3176 3194 3177 /* 3195 3178 * If the OpRegion does not have VBT, look in SPI flash ··· 3198 3179 */ 3199 3180 if (!vbt && IS_DGFX(i915)) 3200 3181 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 3201 3201 - vbt = spi_oprom_get_vbt(i915, sizep); 3182 3182 + vbt = spi_oprom_get_vbt(display, sizep); 3202 3183 3203 3184 if (!vbt) 3204 3185 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 3205 3205 - vbt = oprom_get_vbt(i915, sizep); 3186 3186 + vbt = oprom_get_vbt(display, sizep); 3206 3187 3207 3188 return vbt; 3208 3189 } 3209 3190 3210 3191 /** 3211 3192 * intel_bios_init - find VBT and initialize settings from the BIOS 3212 3212 - * @i915: i915 device instance 3193 3193 + * @display: display device instance 3213 3194 * 3214 3195 * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT 3215 3196 * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also 3216 3197 * initialize some defaults if the VBT is not present at all. 3217 3198 */ 3218 3218 - void intel_bios_init(struct drm_i915_private *i915) 3199 3199 + void intel_bios_init(struct intel_display *display) 3219 3200 { 3220 3201 const struct vbt_header *vbt; 3221 3202 const struct bdb_header *bdb; 3222 3203 3223 3223 - INIT_LIST_HEAD(&i915->display.vbt.display_devices); 3224 3224 - INIT_LIST_HEAD(&i915->display.vbt.bdb_blocks); 3204 3204 + INIT_LIST_HEAD(&display->vbt.display_devices); 3205 3205 + INIT_LIST_HEAD(&display->vbt.bdb_blocks); 3225 3206 3226 3226 - if (!HAS_DISPLAY(i915)) { 3227 3227 - drm_dbg_kms(&i915->drm, 3207 3207 + if (!HAS_DISPLAY(display)) { 3208 3208 + drm_dbg_kms(display->drm, 3228 3209 "Skipping VBT init due to disabled display.\n"); 3229 3210 return; 3230 3211 } 3231 3212 3232 3232 - init_vbt_defaults(i915); 3213 3213 + init_vbt_defaults(display); 3233 3214 3234 3234 - vbt = intel_bios_get_vbt(i915, NULL); 3215 3215 + vbt = intel_bios_get_vbt(display, NULL); 3235 3216 3236 3217 if (!vbt) 3237 3218 goto out; 3238 3219 3239 3220 bdb = get_bdb_header(vbt); 3240 3240 - i915->display.vbt.version = bdb->version; 3221 3221 + display->vbt.version = bdb->version; 3241 3222 3242 3242 - drm_dbg_kms(&i915->drm, 3223 3223 + drm_dbg_kms(display->drm, 3243 3224 "VBT signature \"%.*s\", BDB version %d\n", 3244 3244 - (int)sizeof(vbt->signature), vbt->signature, i915->display.vbt.version); 3225 3225 + (int)sizeof(vbt->signature), vbt->signature, 3226 3226 + display->vbt.version); 3245 3227 3246 3246 - init_bdb_blocks(i915, bdb); 3228 3228 + init_bdb_blocks(display, bdb); 3247 3229 3248 3230 /* Grab useful general definitions */ 3249 3249 - parse_general_features(i915); 3250 3250 - parse_general_definitions(i915); 3251 3251 - parse_driver_features(i915); 3231 3231 + parse_general_features(display); 3232 3232 + parse_general_definitions(display); 3233 3233 + parse_driver_features(display); 3252 3234 3253 3235 /* Depends on child device list */ 3254 3254 - parse_compression_parameters(i915); 3236 3236 + parse_compression_parameters(display); 3255 3237 3256 3238 out: 3257 3239 if (!vbt) { 3258 3258 - drm_info(&i915->drm, 3240 3240 + drm_info(display->drm, 3259 3241 "Failed to find VBIOS tables (VBT)\n"); 3260 3260 - init_vbt_missing_defaults(i915); 3242 3242 + init_vbt_missing_defaults(display); 3261 3243 } 3262 3244 3263 3245 /* Further processing on pre-parsed or generated child device data */ 3264 3264 - parse_sdvo_device_mapping(i915); 3265 3265 - parse_ddi_ports(i915); 3246 3246 + parse_sdvo_device_mapping(display); 3247 3247 + parse_ddi_ports(display); 3266 3248 3267 3249 kfree(vbt); 3268 3250 } 3269 3251 3270 3270 - static void intel_bios_init_panel(struct drm_i915_private *i915, 3252 3252 + static void intel_bios_init_panel(struct intel_display *display, 3271 3253 struct intel_panel *panel, 3272 3254 const struct intel_bios_encoder_data *devdata, 3273 3255 const struct drm_edid *drm_edid, ··· 3276 3256 { 3277 3257 /* already have it? */ 3278 3258 if (panel->vbt.panel_type >= 0) { 3279 3279 - drm_WARN_ON(&i915->drm, !use_fallback); 3259 3259 + drm_WARN_ON(display->drm, !use_fallback); 3280 3260 return; 3281 3261 } 3282 3262 3283 3283 - panel->vbt.panel_type = get_panel_type(i915, devdata, 3263 3263 + panel->vbt.panel_type = get_panel_type(display, devdata, 3284 3264 drm_edid, use_fallback); 3285 3265 if (panel->vbt.panel_type < 0) { 3286 3286 - drm_WARN_ON(&i915->drm, use_fallback); 3266 3266 + drm_WARN_ON(display->drm, use_fallback); 3287 3267 return; 3288 3268 } 3289 3269 3290 3270 init_vbt_panel_defaults(panel); 3291 3271 3292 3292 - parse_panel_options(i915, panel); 3293 3293 - parse_generic_dtd(i915, panel); 3294 3294 - parse_lfp_data(i915, panel); 3295 3295 - parse_lfp_backlight(i915, panel); 3296 3296 - parse_sdvo_lvds_data(i915, panel); 3297 3297 - parse_panel_driver_features(i915, panel); 3298 3298 - parse_power_conservation_features(i915, panel); 3299 3299 - parse_edp(i915, panel); 3300 3300 - parse_psr(i915, panel); 3301 3301 - parse_mipi_config(i915, panel); 3302 3302 - parse_mipi_sequence(i915, panel); 3272 3272 + parse_panel_options(display, panel); 3273 3273 + parse_generic_dtd(display, panel); 3274 3274 + parse_lfp_data(display, panel); 3275 3275 + parse_lfp_backlight(display, panel); 3276 3276 + parse_sdvo_lvds_data(display, panel); 3277 3277 + parse_panel_driver_features(display, panel); 3278 3278 + parse_power_conservation_features(display, panel); 3279 3279 + parse_edp(display, panel); 3280 3280 + parse_psr(display, panel); 3281 3281 + parse_mipi_config(display, panel); 3282 3282 + parse_mipi_sequence(display, panel); 3303 3283 } 3304 3284 3305 3305 - void intel_bios_init_panel_early(struct drm_i915_private *i915, 3285 3285 + void intel_bios_init_panel_early(struct intel_display *display, 3306 3286 struct intel_panel *panel, 3307 3287 const struct intel_bios_encoder_data *devdata) 3308 3288 { 3309 3309 - intel_bios_init_panel(i915, panel, devdata, NULL, false); 3289 3289 + intel_bios_init_panel(display, panel, devdata, NULL, false); 3310 3290 } 3311 3291 3312 3312 - void intel_bios_init_panel_late(struct drm_i915_private *i915, 3292 3292 + void intel_bios_init_panel_late(struct intel_display *display, 3313 3293 struct intel_panel *panel, 3314 3294 const struct intel_bios_encoder_data *devdata, 3315 3295 const struct drm_edid *drm_edid) 3316 3296 { 3317 3317 - intel_bios_init_panel(i915, panel, devdata, drm_edid, true); 3297 3297 + intel_bios_init_panel(display, panel, devdata, drm_edid, true); 3318 3298 } 3319 3299 3320 3300 /** 3321 3301 * intel_bios_driver_remove - Free any resources allocated by intel_bios_init() 3322 3322 - * @i915: i915 device instance 3302 3302 + * @display: display device instance 3323 3303 */ 3324 3324 - void intel_bios_driver_remove(struct drm_i915_private *i915) 3304 3304 + void intel_bios_driver_remove(struct intel_display *display) 3325 3305 { 3326 3306 struct intel_bios_encoder_data *devdata, *nd; 3327 3307 struct bdb_block_entry *entry, *ne; 3328 3308 3329 3329 - list_for_each_entry_safe(devdata, nd, &i915->display.vbt.display_devices, node) { 3309 3309 + list_for_each_entry_safe(devdata, nd, &display->vbt.display_devices, 3310 3310 + node) { 3330 3311 list_del(&devdata->node); 3331 3312 kfree(devdata->dsc); 3332 3313 kfree(devdata); 3333 3314 } 3334 3315 3335 3335 - list_for_each_entry_safe(entry, ne, &i915->display.vbt.bdb_blocks, node) { 3316 3316 + list_for_each_entry_safe(entry, ne, &display->vbt.bdb_blocks, node) { 3336 3317 list_del(&entry->node); 3337 3318 kfree(entry); 3338 3319 } ··· 3357 3336 3358 3337 /** 3359 3338 * intel_bios_is_tv_present - is integrated TV present in VBT 3360 3360 - * @i915: i915 device instance 3339 3339 + * @display: display device instance 3361 3340 * 3362 3341 * Return true if TV is present. If no child devices were parsed from VBT, 3363 3342 * assume TV is present. 3364 3343 */ 3365 3365 - bool intel_bios_is_tv_present(struct drm_i915_private *i915) 3344 3344 + bool intel_bios_is_tv_present(struct intel_display *display) 3366 3345 { 3367 3346 const struct intel_bios_encoder_data *devdata; 3368 3347 3369 3369 - if (!i915->display.vbt.int_tv_support) 3348 3348 + if (!display->vbt.int_tv_support) 3370 3349 return false; 3371 3350 3372 3372 - if (list_empty(&i915->display.vbt.display_devices)) 3351 3351 + if (list_empty(&display->vbt.display_devices)) 3373 3352 return true; 3374 3353 3375 3375 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { 3354 3354 + list_for_each_entry(devdata, &display->vbt.display_devices, node) { 3376 3355 const struct child_device_config *child = &devdata->child; 3377 3356 3378 3357 /* ··· 3398 3377 3399 3378 /** 3400 3379 * intel_bios_is_lvds_present - is LVDS present in VBT 3401 3401 - * @i915: i915 device instance 3380 3380 + * @display: display device instance 3402 3381 * @i2c_pin: i2c pin for LVDS if present 3403 3382 * 3404 3383 * Return true if LVDS is present. If no child devices were parsed from VBT, 3405 3384 * assume LVDS is present. 3406 3385 */ 3407 3407 - bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin) 3386 3386 + bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin) 3408 3387 { 3388 3388 + struct drm_i915_private *i915 = to_i915(display->drm); 3409 3389 const struct intel_bios_encoder_data *devdata; 3410 3390 3411 3411 - if (list_empty(&i915->display.vbt.display_devices)) 3391 3391 + if (list_empty(&display->vbt.display_devices)) 3412 3392 return true; 3413 3393 3414 3414 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { 3394 3394 + list_for_each_entry(devdata, &display->vbt.display_devices, node) { 3415 3395 const struct child_device_config *child = &devdata->child; 3416 3396 3417 3397 /* If the device type is not LFP, continue. ··· 3439 3417 * additional data. Trust that if the VBT was written into 3440 3418 * the OpRegion then they have validated the LVDS's existence. 3441 3419 */ 3442 3442 - return intel_opregion_vbt_present(i915); 3420 3420 + return intel_opregion_vbt_present(display); 3443 3421 } 3444 3422 3445 3423 return false; ··· 3447 3425 3448 3426 /** 3449 3427 * intel_bios_is_port_present - is the specified digital port present 3450 3450 - * @i915: i915 device instance 3428 3428 + * @display: display device instance 3451 3429 * @port: port to check 3452 3430 * 3453 3431 * Return true if the device in %port is present. 3454 3432 */ 3455 3455 - bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port) 3433 3433 + bool intel_bios_is_port_present(struct intel_display *display, enum port port) 3456 3434 { 3457 3435 const struct intel_bios_encoder_data *devdata; 3458 3436 3459 3459 - if (WARN_ON(!has_ddi_port_info(i915))) 3437 3437 + if (WARN_ON(!has_ddi_port_info(display))) 3460 3438 return true; 3461 3439 3462 3462 - if (!is_port_valid(i915, port)) 3440 3440 + if (!is_port_valid(display, port)) 3463 3441 return false; 3464 3442 3465 3465 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { 3443 3443 + list_for_each_entry(devdata, &display->vbt.display_devices, node) { 3466 3444 const struct child_device_config *child = &devdata->child; 3467 3445 3468 3468 - if (dvo_port_to_port(i915, child->dvo_port) == port) 3446 3446 + if (dvo_port_to_port(display, child->dvo_port) == port) 3469 3447 return true; 3470 3448 } 3471 3449 ··· 3496 3474 3497 3475 /** 3498 3476 * intel_bios_is_dsi_present - is DSI present in VBT 3499 3499 - * @i915: i915 device instance 3477 3477 + * @display: display device instance 3500 3478 * @port: port for DSI if present 3501 3479 * 3502 3480 * Return true if DSI is present, and return the port in %port. 3503 3481 */ 3504 3504 - bool intel_bios_is_dsi_present(struct drm_i915_private *i915, 3482 3482 + bool intel_bios_is_dsi_present(struct intel_display *display, 3505 3483 enum port *port) 3506 3484 { 3507 3485 const struct intel_bios_encoder_data *devdata; 3508 3486 3509 3509 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { 3487 3487 + list_for_each_entry(devdata, &display->vbt.display_devices, node) { 3510 3488 const struct child_device_config *child = &devdata->child; 3511 3489 u8 dvo_port = child->dvo_port; 3512 3490 3513 3491 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) 3514 3492 continue; 3515 3493 3516 3516 - if (dsi_dvo_port_to_port(i915, dvo_port) == PORT_NONE) { 3517 3517 - drm_dbg_kms(&i915->drm, 3494 3494 + if (dsi_dvo_port_to_port(display, dvo_port) == PORT_NONE) { 3495 3495 + drm_dbg_kms(display->drm, 3518 3496 "VBT has unsupported DSI port %c\n", 3519 3497 port_name(dvo_port - DVO_PORT_MIPIA)); 3520 3498 continue; 3521 3499 } 3522 3500 3523 3501 if (port) 3524 3524 - *port = dsi_dvo_port_to_port(i915, dvo_port); 3502 3502 + *port = dsi_dvo_port_to_port(display, dvo_port); 3525 3503 return true; 3526 3504 } 3527 3505 ··· 3532 3510 struct dsc_compression_parameters_entry *dsc, 3533 3511 int dsc_max_bpc) 3534 3512 { 3535 3535 - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 3513 3513 + struct intel_display *display = to_intel_display(crtc_state); 3536 3514 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 3537 3515 int bpc = 8; 3538 3516 ··· 3546 3524 else if (dsc->support_8bpc && dsc_max_bpc >= 8) 3547 3525 bpc = 8; 3548 3526 else 3549 3549 - drm_dbg_kms(&i915->drm, "VBT: Unsupported BPC %d for DCS\n", 3527 3527 + drm_dbg_kms(display->drm, "VBT: Unsupported BPC %d for DCS\n", 3550 3528 dsc_max_bpc); 3551 3529 3552 3530 crtc_state->pipe_bpp = bpc * 3; 3553 3531 3554 3554 - crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp, 3555 3555 - VBT_DSC_MAX_BPP(dsc->max_bpp))); 3532 3532 + crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp, 3533 3533 + VBT_DSC_MAX_BPP(dsc->max_bpp))); 3556 3534 3557 3535 /* 3558 3536 * FIXME: This is ugly, and slice count should take DSC engine ··· 3567 3545 } else { 3568 3546 /* FIXME */ 3569 3547 if (!(dsc->slices_per_line & BIT(0))) 3570 3570 - drm_dbg_kms(&i915->drm, "VBT: Unsupported DSC slice count for DSI\n"); 3548 3548 + drm_dbg_kms(display->drm, 3549 3549 + "VBT: Unsupported DSC slice count for DSI\n"); 3571 3550 3572 3551 crtc_state->dsc.slice_count = 1; 3573 3552 } 3574 3553 3575 3554 if (crtc_state->hw.adjusted_mode.crtc_hdisplay % 3576 3555 crtc_state->dsc.slice_count != 0) 3577 3577 - drm_dbg_kms(&i915->drm, "VBT: DSC hdisplay %d not divisible by slice count %d\n", 3556 3556 + drm_dbg_kms(display->drm, 3557 3557 + "VBT: DSC hdisplay %d not divisible by slice count %d\n", 3578 3558 crtc_state->hw.adjusted_mode.crtc_hdisplay, 3579 3559 crtc_state->dsc.slice_count); 3580 3560 ··· 3600 3576 struct intel_crtc_state *crtc_state, 3601 3577 int dsc_max_bpc) 3602 3578 { 3603 3603 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3579 3579 + struct intel_display *display = to_intel_display(encoder); 3604 3580 const struct intel_bios_encoder_data *devdata; 3605 3581 3606 3606 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { 3582 3582 + list_for_each_entry(devdata, &display->vbt.display_devices, node) { 3607 3583 const struct child_device_config *child = &devdata->child; 3608 3584 3609 3585 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) 3610 3586 continue; 3611 3587 3612 3612 - if (dsi_dvo_port_to_port(i915, child->dvo_port) == encoder->port) { 3588 3588 + if (dsi_dvo_port_to_port(display, child->dvo_port) == encoder->port) { 3613 3589 if (!devdata->dsc) 3614 3590 return false; 3615 3591 ··· 3669 3645 [AUX_CH_I] = DP_AUX_I, /* aka AUX_CH_USBC6 */ 3670 3646 }; 3671 3647 3672 3672 - static enum aux_ch map_aux_ch(struct drm_i915_private *i915, u8 aux_channel) 3648 3648 + static enum aux_ch map_aux_ch(struct intel_display *display, u8 aux_channel) 3673 3649 { 3650 3650 + struct drm_i915_private *i915 = to_i915(display->drm); 3674 3651 const u8 *aux_ch_map; 3675 3652 int i, n_entries; 3676 3653 3677 3677 - if (DISPLAY_VER(i915) >= 13) { 3654 3654 + if (DISPLAY_VER(display) >= 13) { 3678 3655 aux_ch_map = adlp_aux_ch_map; 3679 3656 n_entries = ARRAY_SIZE(adlp_aux_ch_map); 3680 3657 } else if (IS_ALDERLAKE_S(i915)) { ··· 3694 3669 return i; 3695 3670 } 3696 3671 3697 3697 - drm_dbg_kms(&i915->drm, 3672 3672 + drm_dbg_kms(display->drm, 3698 3673 "Ignoring alternate AUX CH: VBT claims AUX 0x%x, which is not valid for this platform\n", 3699 3674 aux_channel); 3700 3675 ··· 3706 3681 if (!devdata || !devdata->child.aux_channel) 3707 3682 return AUX_CH_NONE; 3708 3683 3709 3709 - return map_aux_ch(devdata->i915, devdata->child.aux_channel); 3684 3684 + return map_aux_ch(devdata->display, devdata->child.aux_channel); 3710 3685 } 3711 3686 3712 3687 bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata) 3713 3688 { 3714 3714 - struct drm_i915_private *i915; 3689 3689 + struct intel_display *display; 3715 3690 u8 aux_channel; 3716 3691 int count = 0; 3717 3692 3718 3693 if (!devdata || !devdata->child.aux_channel) 3719 3694 return false; 3720 3695 3721 3721 - i915 = devdata->i915; 3696 3696 + display = devdata->display; 3722 3697 aux_channel = devdata->child.aux_channel; 3723 3698 3724 3724 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { 3699 3699 + list_for_each_entry(devdata, &display->vbt.display_devices, node) { 3725 3700 if (intel_bios_encoder_supports_dp(devdata) && 3726 3701 aux_channel == devdata->child.aux_channel) 3727 3702 count++; ··· 3732 3707 3733 3708 int intel_bios_dp_boost_level(const struct intel_bios_encoder_data *devdata) 3734 3709 { 3735 3735 - if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost) 3710 3710 + if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost) 3736 3711 return 0; 3737 3712 3738 3738 - return translate_iboost(devdata->i915, devdata->child.dp_iboost_level); 3713 3713 + return translate_iboost(devdata->display, devdata->child.dp_iboost_level); 3739 3714 } 3740 3715 3741 3716 int intel_bios_hdmi_boost_level(const struct intel_bios_encoder_data *devdata) 3742 3717 { 3743 3743 - if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost) 3718 3718 + if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost) 3744 3719 return 0; 3745 3720 3746 3746 - return translate_iboost(devdata->i915, devdata->child.hdmi_iboost_level); 3721 3721 + return translate_iboost(devdata->display, devdata->child.hdmi_iboost_level); 3747 3722 } 3748 3723 3749 3724 int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata) ··· 3751 3726 if (!devdata || !devdata->child.ddc_pin) 3752 3727 return 0; 3753 3728 3754 3754 - return map_ddc_pin(devdata->i915, devdata->child.ddc_pin); 3729 3729 + return map_ddc_pin(devdata->display, devdata->child.ddc_pin); 3755 3730 } 3756 3731 3757 3732 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata) 3758 3733 { 3759 3759 - return devdata->i915->display.vbt.version >= 195 && devdata->child.dp_usb_type_c; 3734 3734 + return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c; 3760 3735 } 3761 3736 3762 3737 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata) 3763 3738 { 3764 3764 - return devdata->i915->display.vbt.version >= 209 && devdata->child.tbt; 3739 3739 + return devdata->display->vbt.version >= 209 && devdata->child.tbt; 3765 3740 } 3766 3741 3767 3742 bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata) ··· 3775 3750 } 3776 3751 3777 3752 const struct intel_bios_encoder_data * 3778 3778 - intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port) 3753 3753 + intel_bios_encoder_data_lookup(struct intel_display *display, enum port port) 3779 3754 { 3780 3755 struct intel_bios_encoder_data *devdata; 3781 3756 3782 3782 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { 3757 3757 + list_for_each_entry(devdata, &display->vbt.display_devices, node) { 3783 3758 if (intel_bios_encoder_port(devdata) == port) 3784 3759 return devdata; 3785 3760 } ··· 3787 3762 return NULL; 3788 3763 } 3789 3764 3790 3790 - void intel_bios_for_each_encoder(struct drm_i915_private *i915, 3791 3791 - void (*func)(struct drm_i915_private *i915, 3765 3765 + void intel_bios_for_each_encoder(struct intel_display *display, 3766 3766 + void (*func)(struct intel_display *display, 3792 3767 const struct intel_bios_encoder_data *devdata)) 3793 3768 { 3794 3769 struct intel_bios_encoder_data *devdata; 3795 3770 3796 3796 - list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) 3797 3797 - func(i915, devdata); 3771 3771 + list_for_each_entry(devdata, &display->vbt.display_devices, node) 3772 3772 + func(display, devdata); 3798 3773 } 3799 3774 3800 3775 static int intel_bios_vbt_show(struct seq_file *m, void *unused) 3801 3776 { 3802 3802 - struct drm_i915_private *i915 = m->private; 3777 3777 + struct intel_display *display = m->private; 3803 3778 const void *vbt; 3804 3779 size_t vbt_size; 3805 3780 3806 3806 - vbt = intel_bios_get_vbt(i915, &vbt_size); 3781 3781 + vbt = intel_bios_get_vbt(display, &vbt_size); 3807 3782 3808 3783 if (vbt) { 3809 3784 seq_write(m, vbt, vbt_size); ··· 3815 3790 3816 3791 DEFINE_SHOW_ATTRIBUTE(intel_bios_vbt); 3817 3792 3818 3818 - void intel_bios_debugfs_register(struct drm_i915_private *i915) 3793 3793 + void intel_bios_debugfs_register(struct intel_display *display) 3819 3794 { 3820 3820 - struct drm_minor *minor = i915->drm.primary; 3795 3795 + struct drm_minor *minor = display->drm->primary; 3821 3796 3822 3797 debugfs_create_file("i915_vbt", 0444, minor->debugfs_root, 3823 3823 - i915, &intel_bios_vbt_fops); 3798 3798 + display, &intel_bios_vbt_fops); 3824 3799 }

+14 -14

drivers/gpu/drm/i915/display/intel_bios.h

reviewed

··· 33 33 #include <linux/types.h> 34 34 35 35 struct drm_edid; 36 36 - struct drm_i915_private; 37 36 struct intel_bios_encoder_data; 38 37 struct intel_crtc_state; 38 38 + struct intel_display; 39 39 struct intel_encoder; 40 40 struct intel_panel; 41 41 enum aux_ch; ··· 232 232 u16 panel_power_cycle_delay; 233 233 } __packed; 234 234 235 235 - void intel_bios_init(struct drm_i915_private *dev_priv); 236 236 - void intel_bios_init_panel_early(struct drm_i915_private *dev_priv, 235 235 + void intel_bios_init(struct intel_display *display); 236 236 + void intel_bios_init_panel_early(struct intel_display *display, 237 237 struct intel_panel *panel, 238 238 const struct intel_bios_encoder_data *devdata); 239 239 - void intel_bios_init_panel_late(struct drm_i915_private *dev_priv, 239 239 + void intel_bios_init_panel_late(struct intel_display *display, 240 240 struct intel_panel *panel, 241 241 const struct intel_bios_encoder_data *devdata, 242 242 const struct drm_edid *drm_edid); 243 243 void intel_bios_fini_panel(struct intel_panel *panel); 244 244 - void intel_bios_driver_remove(struct drm_i915_private *dev_priv); 245 245 - bool intel_bios_is_valid_vbt(struct drm_i915_private *i915, 244 244 + void intel_bios_driver_remove(struct intel_display *display); 245 245 + bool intel_bios_is_valid_vbt(struct intel_display *display, 246 246 const void *buf, size_t size); 247 247 - bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); 248 248 - bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); 249 249 - bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); 250 250 - bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); 247 247 + bool intel_bios_is_tv_present(struct intel_display *display); 248 248 + bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin); 249 249 + bool intel_bios_is_port_present(struct intel_display *display, enum port port); 250 250 + bool intel_bios_is_dsi_present(struct intel_display *display, enum port *port); 251 251 bool intel_bios_get_dsc_params(struct intel_encoder *encoder, 252 252 struct intel_crtc_state *crtc_state, 253 253 int dsc_max_bpc); 254 254 255 255 const struct intel_bios_encoder_data * 256 256 - intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port); 256 256 + intel_bios_encoder_data_lookup(struct intel_display *display, enum port port); 257 257 258 258 bool intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata); 259 259 bool intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata); ··· 277 277 int intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata); 278 278 int intel_bios_hdmi_max_tmds_clock(const struct intel_bios_encoder_data *devdata); 279 279 280 280 - void intel_bios_for_each_encoder(struct drm_i915_private *i915, 281 281 - void (*func)(struct drm_i915_private *i915, 280 280 + void intel_bios_for_each_encoder(struct intel_display *display, 281 281 + void (*func)(struct intel_display *display, 282 282 const struct intel_bios_encoder_data *devdata)); 283 283 284 284 - void intel_bios_debugfs_register(struct drm_i915_private *i915); 284 284 + void intel_bios_debugfs_register(struct intel_display *display); 285 285 286 286 #endif /* _INTEL_BIOS_H_ */

+4 -1

drivers/gpu/drm/i915/display/intel_cdclk.c

reviewed

··· 23 23 24 24 #include <linux/time.h> 25 25 26 26 + #include <drm/drm_fixed.h> 27 27 + 26 28 #include "soc/intel_dram.h" 29 29 + 27 30 #include "hsw_ips.h" 28 31 #include "i915_reg.h" 29 32 #include "intel_atomic.h" ··· 2753 2750 */ 2754 2751 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; 2755 2752 int min_cdclk_bj = 2756 2756 - (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) * 2753 2753 + (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * 2757 2754 pixel_clock) / (2 * bigjoiner_interface_bits); 2758 2755 2759 2756 min_cdclk = max(min_cdclk, min_cdclk_bj);

+5 -3

drivers/gpu/drm/i915/display/intel_combo_phy.c

reviewed

··· 159 159 160 160 static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) 161 161 { 162 162 - bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A); 163 163 - bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D); 164 164 - bool dsi_present = intel_bios_is_dsi_present(i915, NULL); 162 162 + struct intel_display *display = &i915->display; 163 163 + 164 164 + bool ddi_a_present = intel_bios_is_port_present(display, PORT_A); 165 165 + bool ddi_d_present = intel_bios_is_port_present(display, PORT_D); 166 166 + bool dsi_present = intel_bios_is_dsi_present(display, NULL); 165 167 166 168 /* 167 169 * VBT's 'dvo port' field for child devices references the DDI, not

+3

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

reviewed

··· 10 10 #include "intel_crtc_state_dump.h" 11 11 #include "intel_display_types.h" 12 12 #include "intel_hdmi.h" 13 13 + #include "intel_vdsc.h" 13 14 #include "intel_vrr.h" 14 15 15 16 static void intel_dump_crtc_timings(struct drm_printer *p, ··· 369 368 vlv_dump_csc(&p, "cgm csc", &pipe_config->csc); 370 369 else if (IS_VALLEYVIEW(i915)) 371 370 vlv_dump_csc(&p, "wgc csc", &pipe_config->csc); 371 371 + 372 372 + intel_vdsc_state_dump(&p, 0, pipe_config); 372 373 373 374 dump_planes: 374 375 if (!state)

+5 -3

drivers/gpu/drm/i915/display/intel_ddi.c

reviewed

··· 4172 4172 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4173 4173 crtc_state); 4174 4174 4175 4175 - if (intel_encoder_is_dp(encoder)) 4175 4175 + if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4176 4176 + (!crtc_state && intel_encoder_is_dp(encoder))) 4176 4177 intel_dp_sync_state(encoder, crtc_state); 4177 4178 } 4178 4179 ··· 4854 4853 return false; 4855 4854 } 4856 4855 4857 4857 - void intel_ddi_init(struct drm_i915_private *dev_priv, 4856 4856 + void intel_ddi_init(struct intel_display *display, 4858 4857 const struct intel_bios_encoder_data *devdata) 4859 4858 { 4859 4859 + struct drm_i915_private *dev_priv = to_i915(display->drm); 4860 4860 struct intel_digital_port *dig_port; 4861 4861 struct intel_encoder *encoder; 4862 4862 bool init_hdmi, init_dp; ··· 4974 4972 } else { 4975 4973 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4976 4974 DRM_MODE_ENCODER_TMDS, 4977 4977 - "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4975 4975 + "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4978 4976 } 4979 4977 4980 4978 intel_encoder_link_check_init(encoder, intel_ddi_link_check);

+2 -1

drivers/gpu/drm/i915/display/intel_ddi.h

reviewed

··· 15 15 struct intel_connector; 16 16 struct intel_crtc; 17 17 struct intel_crtc_state; 18 18 + struct intel_display; 18 19 struct intel_dp; 19 20 struct intel_dpll_hw_state; 20 21 struct intel_encoder; ··· 54 53 const struct intel_crtc_state *crtc_state); 55 54 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 56 55 enum port port); 57 57 - void intel_ddi_init(struct drm_i915_private *dev_priv, 56 56 + void intel_ddi_init(struct intel_display *display, 58 57 const struct intel_bios_encoder_data *devdata); 59 58 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); 60 59 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,

+27 -17

drivers/gpu/drm/i915/display/intel_display.c

reviewed

··· 39 39 #include <drm/drm_atomic_uapi.h> 40 40 #include <drm/drm_damage_helper.h> 41 41 #include <drm/drm_edid.h> 42 42 + #include <drm/drm_fixed.h> 42 43 #include <drm/drm_fourcc.h> 43 44 #include <drm/drm_probe_helper.h> 44 45 #include <drm/drm_rect.h> ··· 1015 1014 old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; 1016 1015 } 1017 1016 1018 1018 - static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, 1019 1019 - const struct intel_crtc_state *new_crtc_state) 1017 1017 + static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state, 1018 1018 + struct intel_crtc *crtc) 1020 1019 { 1020 1020 + const struct intel_crtc_state *old_crtc_state = 1021 1021 + intel_atomic_get_old_crtc_state(state, crtc); 1022 1022 + const struct intel_crtc_state *new_crtc_state = 1023 1023 + intel_atomic_get_new_crtc_state(state, crtc); 1024 1024 + 1021 1025 if (!new_crtc_state->hw.active) 1022 1026 return false; 1023 1027 ··· 1032 1026 vrr_params_changed(old_crtc_state, new_crtc_state))); 1033 1027 } 1034 1028 1035 1035 - static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, 1036 1036 - const struct intel_crtc_state *new_crtc_state) 1029 1029 + static bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 1030 1030 + struct intel_crtc *crtc) 1037 1031 { 1032 1032 + const struct intel_crtc_state *old_crtc_state = 1033 1033 + intel_atomic_get_old_crtc_state(state, crtc); 1034 1034 + const struct intel_crtc_state *new_crtc_state = 1035 1035 + intel_atomic_get_new_crtc_state(state, crtc); 1036 1036 + 1038 1037 if (!old_crtc_state->hw.active) 1039 1038 return false; 1040 1039 ··· 1192 1181 intel_atomic_get_new_crtc_state(state, crtc); 1193 1182 enum pipe pipe = crtc->pipe; 1194 1183 1195 1195 - if (vrr_disabling(old_crtc_state, new_crtc_state)) { 1184 1184 + if (intel_crtc_vrr_disabling(state, crtc)) { 1196 1185 intel_vrr_disable(old_crtc_state); 1197 1186 intel_crtc_update_active_timings(old_crtc_state, false); 1198 1187 } ··· 4680 4669 crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe); 4681 4670 crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe]; 4682 4671 4683 4683 - if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) { 4672 4672 + if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) { 4684 4673 drm_dbg_kms(&i915->drm, 4685 4685 - "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n", 4674 4674 + "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n", 4686 4675 crtc->base.base.id, crtc->base.name, 4687 4687 - BPP_X16_ARGS(crtc_state->max_link_bpp_x16)); 4676 4676 + FXP_Q4_ARGS(crtc_state->max_link_bpp_x16)); 4688 4677 crtc_state->bw_constrained = true; 4689 4678 } 4690 4679 ··· 5111 5100 if (current_config->name != pipe_config->name) { \ 5112 5101 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \ 5113 5102 __stringify(name) " is not bool"); \ 5114 5114 - pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5103 5103 + pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5115 5104 "(expected %s, found %s)", \ 5116 5105 str_yes_no(current_config->name), \ 5117 5106 str_yes_no(pipe_config->name)); \ ··· 6841 6830 struct intel_crtc *crtc) 6842 6831 { 6843 6832 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6844 6844 - const struct intel_crtc_state *old_crtc_state = 6845 6845 - intel_atomic_get_old_crtc_state(state, crtc); 6846 6833 const struct intel_crtc_state *new_crtc_state = 6847 6834 intel_atomic_get_new_crtc_state(state, crtc); 6848 6835 ··· 6853 6844 !intel_crtc_needs_modeset(new_crtc_state)) 6854 6845 skl_detach_scalers(new_crtc_state); 6855 6846 6856 6856 - if (vrr_enabling(old_crtc_state, new_crtc_state)) 6847 6847 + if (intel_crtc_vrr_enabling(state, crtc)) 6857 6848 intel_vrr_enable(new_crtc_state); 6858 6849 } 6859 6850 ··· 6953 6944 * 6954 6945 * FIXME Should be synchronized with the start of vblank somehow... 6955 6946 */ 6956 6956 - if (vrr_enabling(old_crtc_state, new_crtc_state) || 6947 6947 + if (intel_crtc_vrr_enabling(state, crtc) || 6957 6948 new_crtc_state->update_m_n || new_crtc_state->update_lrr) 6958 6949 intel_crtc_update_active_timings(new_crtc_state, 6959 6950 new_crtc_state->vrr.enable); ··· 7786 7777 7787 7778 void intel_setup_outputs(struct drm_i915_private *dev_priv) 7788 7779 { 7780 7780 + struct intel_display *display = &dev_priv->display; 7789 7781 struct intel_encoder *encoder; 7790 7782 bool dpd_is_edp = false; 7791 7783 ··· 7799 7789 if (intel_ddi_crt_present(dev_priv)) 7800 7790 intel_crt_init(dev_priv); 7801 7791 7802 7802 - intel_bios_for_each_encoder(dev_priv, intel_ddi_init); 7792 7792 + intel_bios_for_each_encoder(display, intel_ddi_init); 7803 7793 7804 7794 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 7805 7795 vlv_dsi_init(dev_priv); ··· 7861 7851 * HDMI ports that the VBT claim are DP or eDP. 7862 7852 */ 7863 7853 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); 7864 7864 - has_port = intel_bios_is_port_present(dev_priv, PORT_B); 7854 7854 + has_port = intel_bios_is_port_present(display, PORT_B); 7865 7855 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 7866 7856 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); 7867 7857 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7868 7858 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 7869 7859 7870 7860 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); 7871 7871 - has_port = intel_bios_is_port_present(dev_priv, PORT_C); 7861 7861 + has_port = intel_bios_is_port_present(display, PORT_C); 7872 7862 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 7873 7863 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); 7874 7864 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) ··· 7879 7869 * eDP not supported on port D, 7880 7870 * so no need to worry about it 7881 7871 */ 7882 7882 - has_port = intel_bios_is_port_present(dev_priv, PORT_D); 7872 7872 + has_port = intel_bios_is_port_present(display, PORT_D); 7883 7873 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 7884 7874 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); 7885 7875 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)

+1 -1

drivers/gpu/drm/i915/display/intel_display_core.h

reviewed

··· 237 237 struct sdvo_device_mapping { 238 238 u8 initialized; 239 239 u8 dvo_port; 240 240 - u8 slave_addr; 240 240 + u8 target_addr; 241 241 u8 dvo_wiring; 242 242 u8 i2c_pin; 243 243 u8 ddc_pin;

+10 -5

drivers/gpu/drm/i915/display/intel_display_debugfs.c

reviewed

··· 36 36 #include "intel_pps.h" 37 37 #include "intel_psr.h" 38 38 #include "intel_psr_regs.h" 39 39 + #include "intel_vdsc.h" 39 40 #include "intel_wm.h" 40 41 41 42 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) ··· 493 492 seq_printf(m, "%sMax update: %lluns\n", 494 493 hdr, crtc->debug.vbl.max); 495 494 seq_printf(m, "%sAverage update: %lluns\n", 496 496 - hdr, div64_u64(crtc->debug.vbl.sum, count)); 495 495 + hdr, div64_u64(crtc->debug.vbl.sum, count)); 497 496 seq_printf(m, "%sOverruns > %uus: %u\n", 498 497 hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over); 499 498 } ··· 552 551 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) 553 552 { 554 553 struct drm_i915_private *dev_priv = node_to_i915(m->private); 554 554 + struct drm_printer p = drm_seq_file_printer(m); 555 555 const struct intel_crtc_state *crtc_state = 556 556 to_intel_crtc_state(crtc->base.state); 557 557 struct intel_encoder *encoder; ··· 582 580 seq_printf(m, "\tLinked to 0x%x pipes as a %s\n", 583 581 crtc_state->joiner_pipes, 584 582 intel_crtc_is_joiner_secondary(crtc_state) ? "slave" : "master"); 583 583 + 584 584 + intel_vdsc_state_dump(&p, 1, crtc_state); 585 585 586 586 for_each_intel_encoder_mask(&dev_priv->drm, encoder, 587 587 crtc_state->uapi.encoder_mask) ··· 1012 1008 return ret; 1013 1009 } 1014 1010 1015 1015 - intel_fbc_reset_underrun(dev_priv); 1011 1011 + intel_fbc_reset_underrun(&dev_priv->display); 1016 1012 1017 1013 return cnt; 1018 1014 } ··· 1049 1045 1050 1046 void intel_display_debugfs_register(struct drm_i915_private *i915) 1051 1047 { 1048 1048 + struct intel_display *display = &i915->display; 1052 1049 struct drm_minor *minor = i915->drm.primary; 1053 1050 int i; 1054 1051 ··· 1065 1060 ARRAY_SIZE(intel_display_debugfs_list), 1066 1061 minor->debugfs_root, minor); 1067 1062 1068 1068 - intel_bios_debugfs_register(i915); 1063 1063 + intel_bios_debugfs_register(display); 1069 1064 intel_cdclk_debugfs_register(i915); 1070 1065 intel_dmc_debugfs_register(i915); 1071 1071 - intel_fbc_debugfs_register(i915); 1066 1066 + intel_fbc_debugfs_register(display); 1072 1067 intel_hpd_debugfs_register(i915); 1073 1073 - intel_opregion_debugfs_register(i915); 1068 1068 + intel_opregion_debugfs_register(display); 1074 1069 intel_psr_debugfs_register(i915); 1075 1070 intel_wm_debugfs_register(i915); 1076 1071 intel_display_debugfs_params(i915);

+6 -4

drivers/gpu/drm/i915/display/intel_display_device.c

reviewed

··· 1529 1529 */ 1530 1530 bool intel_display_device_enabled(struct drm_i915_private *i915) 1531 1531 { 1532 1532 - /* Only valid when HAS_DISPLAY() is true */ 1533 1533 - drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915)); 1532 1532 + struct intel_display *display = &i915->display; 1534 1533 1535 1535 - return !i915->display.params.disable_display && 1536 1536 - !intel_opregion_headless_sku(i915); 1534 1534 + /* Only valid when HAS_DISPLAY() is true */ 1535 1535 + drm_WARN_ON(display->drm, !HAS_DISPLAY(display)); 1536 1536 + 1537 1537 + return !display->params.disable_display && 1538 1538 + !intel_opregion_headless_sku(display); 1537 1539 }

+16 -10

drivers/gpu/drm/i915/display/intel_display_driver.c

reviewed

··· 217 217 return ret; 218 218 } 219 219 220 220 - intel_bios_init(i915); 220 220 + intel_bios_init(display); 221 221 222 222 ret = intel_vga_register(i915); 223 223 if (ret) ··· 265 265 266 266 intel_init_quirks(display); 267 267 268 268 - intel_fbc_init(i915); 268 268 + intel_fbc_init(display); 269 269 270 270 return 0; 271 271 ··· 275 275 cleanup_vga: 276 276 intel_vga_unregister(i915); 277 277 cleanup_bios: 278 278 - intel_bios_driver_remove(i915); 278 278 + intel_bios_driver_remove(display); 279 279 280 280 return ret; 281 281 } ··· 416 416 /* part #2: call after irq install, but before gem init */ 417 417 int intel_display_driver_probe_nogem(struct drm_i915_private *i915) 418 418 { 419 419 - struct drm_device *dev = &i915->drm; 419 419 + struct intel_display *display = &i915->display; 420 420 + struct drm_device *dev = display->drm; 420 421 enum pipe pipe; 421 422 int ret; 422 423 ··· 467 466 468 467 drm_modeset_lock_all(dev); 469 468 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 470 470 - intel_acpi_assign_connector_fwnodes(i915); 469 469 + intel_acpi_assign_connector_fwnodes(display); 471 470 drm_modeset_unlock_all(dev); 472 471 473 472 intel_initial_plane_config(i915); ··· 527 526 528 527 void intel_display_driver_register(struct drm_i915_private *i915) 529 528 { 529 529 + struct intel_display *display = &i915->display; 530 530 struct drm_printer p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, 531 531 "i915 display info:"); 532 532 ··· 535 533 return; 536 534 537 535 /* Must be done after probing outputs */ 538 538 - intel_opregion_register(i915); 539 539 - intel_acpi_video_register(i915); 536 536 + intel_opregion_register(display); 537 537 + intel_acpi_video_register(display); 540 538 541 539 intel_audio_init(i915); 542 540 ··· 609 607 destroy_workqueue(i915->display.wq.flip); 610 608 destroy_workqueue(i915->display.wq.modeset); 611 609 612 612 - intel_fbc_cleanup(i915); 610 610 + intel_fbc_cleanup(&i915->display); 613 611 } 614 612 615 613 /* part #3: call after gem init */ 616 614 void intel_display_driver_remove_nogem(struct drm_i915_private *i915) 617 615 { 616 616 + struct intel_display *display = &i915->display; 617 617 + 618 618 intel_dmc_fini(i915); 619 619 620 620 intel_power_domains_driver_remove(i915); 621 621 622 622 intel_vga_unregister(i915); 623 623 624 624 - intel_bios_driver_remove(i915); 624 624 + intel_bios_driver_remove(display); 625 625 } 626 626 627 627 void intel_display_driver_unregister(struct drm_i915_private *i915) 628 628 { 629 629 + struct intel_display *display = &i915->display; 630 630 + 629 631 if (!HAS_DISPLAY(i915)) 630 632 return; 631 633 ··· 649 643 drm_atomic_helper_shutdown(&i915->drm); 650 644 651 645 acpi_video_unregister(); 652 652 - intel_opregion_unregister(i915); 646 646 + intel_opregion_unregister(display); 653 647 } 654 648 655 649 /*

+27 -9

drivers/gpu/drm/i915/display/intel_display_irq.c

reviewed

··· 270 270 271 271 static bool i915_has_asle(struct drm_i915_private *i915) 272 272 { 273 273 + struct intel_display *display = &i915->display; 274 274 + 273 275 if (!IS_PINEVIEW(i915) && !IS_MOBILE(i915)) 274 276 return false; 275 277 276 276 - return intel_opregion_asle_present(i915); 278 278 + return intel_opregion_asle_present(display); 277 279 } 278 280 279 281 /** ··· 499 497 void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, 500 498 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 501 499 { 500 500 + struct intel_display *display = &dev_priv->display; 501 501 + 502 502 bool blc_event = false; 503 503 enum pipe pipe; 504 504 ··· 519 515 } 520 516 521 517 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 522 522 - intel_opregion_asle_intr(dev_priv); 518 518 + intel_opregion_asle_intr(display); 523 519 } 524 520 525 521 void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, 526 522 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 527 523 { 524 524 + struct intel_display *display = &dev_priv->display; 528 525 bool blc_event = false; 529 526 enum pipe pipe; 530 527 ··· 544 539 } 545 540 546 541 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 547 547 - intel_opregion_asle_intr(dev_priv); 542 542 + intel_opregion_asle_intr(display); 548 543 549 544 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 550 545 intel_gmbus_irq_handler(dev_priv); ··· 700 695 701 696 void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) 702 697 { 698 698 + struct intel_display *display = &dev_priv->display; 703 699 enum pipe pipe; 704 700 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 705 701 ··· 711 705 intel_dp_aux_irq_handler(dev_priv); 712 706 713 707 if (de_iir & DE_GSE) 714 714 - intel_opregion_asle_intr(dev_priv); 708 708 + intel_opregion_asle_intr(display); 715 709 716 710 if (de_iir & DE_POISON) 717 711 drm_err(&dev_priv->drm, "Poison interrupt\n"); ··· 749 743 750 744 void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) 751 745 { 746 746 + struct intel_display *display = &dev_priv->display; 752 747 enum pipe pipe; 753 748 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 754 749 ··· 777 770 intel_dp_aux_irq_handler(dev_priv); 778 771 779 772 if (de_iir & DE_GSE_IVB) 780 780 - intel_opregion_asle_intr(dev_priv); 773 773 + intel_opregion_asle_intr(display); 781 774 782 775 for_each_pipe(dev_priv, pipe) { 783 776 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) ··· 901 894 static void 902 895 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 903 896 { 897 897 + struct intel_display *display = &dev_priv->display; 904 898 bool found = false; 905 899 906 900 if (DISPLAY_VER(dev_priv) >= 14) { ··· 914 906 intel_pmdemand_irq_handler(dev_priv); 915 907 found = true; 916 908 } 909 909 + 910 910 + if (iir & XELPDP_RM_TIMEOUT) { 911 911 + u32 val = intel_uncore_read(&dev_priv->uncore, 912 912 + RM_TIMEOUT_REG_CAPTURE); 913 913 + drm_warn(&dev_priv->drm, "Register Access Timeout = 0x%x\n", val); 914 914 + found = true; 915 915 + } 917 916 } else if (iir & GEN8_DE_MISC_GSE) { 918 918 - intel_opregion_asle_intr(dev_priv); 917 917 + intel_opregion_asle_intr(display); 919 918 found = true; 920 919 } 921 920 ··· 1226 1211 1227 1212 void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir) 1228 1213 { 1214 1214 + struct intel_display *display = &i915->display; 1215 1215 + 1229 1216 if (iir & GEN11_GU_MISC_GSE) 1230 1230 - intel_opregion_asle_intr(i915); 1217 1217 + intel_opregion_asle_intr(display); 1231 1218 } 1232 1219 1233 1220 void gen11_display_irq_handler(struct drm_i915_private *i915) ··· 1697 1680 1698 1681 void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 1699 1682 { 1683 1683 + struct intel_display *display = &dev_priv->display; 1700 1684 struct intel_uncore *uncore = &dev_priv->uncore; 1701 1685 1702 1686 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | ··· 1728 1710 1729 1711 if (DISPLAY_VER(dev_priv) >= 14) { 1730 1712 de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR | 1731 1731 - XELPDP_PMDEMAND_RSP; 1713 1713 + XELPDP_PMDEMAND_RSP | XELPDP_RM_TIMEOUT; 1732 1714 } else if (DISPLAY_VER(dev_priv) >= 11) { 1733 1715 enum port port; 1734 1716 1735 1735 - if (intel_bios_is_dsi_present(dev_priv, &port)) 1717 1717 + if (intel_bios_is_dsi_present(display, &port)) 1736 1718 de_port_masked |= DSI0_TE | DSI1_TE; 1737 1719 } 1738 1720

+8

drivers/gpu/drm/i915/display/intel_display_power.c

reviewed

··· 1704 1704 /* Wa_14011503030:xelpd */ 1705 1705 if (DISPLAY_VER(dev_priv) == 13) 1706 1706 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1707 1707 + 1708 1708 + /* Wa_15013987218 */ 1709 1709 + if (DISPLAY_VER(dev_priv) == 20) { 1710 1710 + intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1711 1711 + 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE); 1712 1712 + intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1713 1713 + PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0); 1714 1714 + } 1707 1715 } 1708 1716 1709 1717 static void icl_display_core_uninit(struct drm_i915_private *dev_priv)

+22 -23

drivers/gpu/drm/i915/display/intel_display_types.h

reviewed

··· 1754 1754 u8 lane_count; 1755 1755 u8 sink_count; 1756 1756 bool link_trained; 1757 1757 + bool needs_modeset_retry; 1757 1758 bool use_max_params; 1758 1759 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 1759 1760 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; ··· 1778 1777 int common_rates[DP_MAX_SUPPORTED_RATES]; 1779 1778 struct { 1780 1779 /* TODO: move the rest of link specific fields to here */ 1780 1780 + /* common rate,lane_count configs in bw order */ 1781 1781 + int num_configs; 1782 1782 + #define INTEL_DP_MAX_LANE_COUNT 4 1783 1783 + #define INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS (ilog2(INTEL_DP_MAX_LANE_COUNT) + 1) 1784 1784 + #define INTEL_DP_LANE_COUNT_EXP_BITS order_base_2(INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS) 1785 1785 + #define INTEL_DP_LINK_RATE_IDX_BITS (BITS_PER_TYPE(u8) - INTEL_DP_LANE_COUNT_EXP_BITS) 1786 1786 + #define INTEL_DP_MAX_LINK_CONFIGS (DP_MAX_SUPPORTED_RATES * \ 1787 1787 + INTEL_DP_MAX_SUPPORTED_LANE_CONFIGS) 1788 1788 + struct intel_dp_link_config { 1789 1789 + u8 link_rate_idx:INTEL_DP_LINK_RATE_IDX_BITS; 1790 1790 + u8 lane_count_exp:INTEL_DP_LANE_COUNT_EXP_BITS; 1791 1791 + } configs[INTEL_DP_MAX_LINK_CONFIGS]; 1781 1792 /* Max lane count for the current link */ 1782 1793 int max_lane_count; 1783 1794 /* Max rate for the current link */ 1784 1795 int max_rate; 1796 1796 + /* 1797 1797 + * Link parameters for which the MST topology was probed. 1798 1798 + * Tracking these ensures that the MST path resources are 1799 1799 + * re-enumerated whenever the link is retrained with new link 1800 1800 + * parameters, as required by the DP standard. 1801 1801 + */ 1802 1802 + int mst_probed_lane_count; 1803 1803 + int mst_probed_rate; 1785 1804 int force_lane_count; 1786 1805 int force_rate; 1787 1806 bool retrain_disabled; ··· 1827 1806 1828 1807 /* connector directly attached - won't be use for modeset in mst world */ 1829 1808 struct intel_connector *attached_connector; 1809 1809 + bool as_sdp_supported; 1830 1810 1831 1811 struct drm_dp_tunnel *tunnel; 1832 1812 bool tunnel_suspended:1; ··· 2198 2176 to_intel_frontbuffer(struct drm_framebuffer *fb) 2199 2177 { 2200 2178 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; 2201 2201 - } 2202 2202 - 2203 2203 - static inline int to_bpp_int(int bpp_x16) 2204 2204 - { 2205 2205 - return bpp_x16 >> 4; 2206 2206 - } 2207 2207 - 2208 2208 - static inline int to_bpp_frac(int bpp_x16) 2209 2209 - { 2210 2210 - return bpp_x16 & 0xf; 2211 2211 - } 2212 2212 - 2213 2213 - #define BPP_X16_FMT "%d.%04d" 2214 2214 - #define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625) 2215 2215 - 2216 2216 - static inline int to_bpp_int_roundup(int bpp_x16) 2217 2217 - { 2218 2218 - return (bpp_x16 + 0xf) >> 4; 2219 2219 - } 2220 2220 - 2221 2221 - static inline int to_bpp_x16(int bpp) 2222 2222 - { 2223 2223 - return bpp << 4; 2224 2179 } 2225 2180 2226 2181 /*

+177 -109

drivers/gpu/drm/i915/display/intel_dp.c

reviewed

··· 29 29 #include <linux/i2c.h> 30 30 #include <linux/notifier.h> 31 31 #include <linux/slab.h> 32 32 + #include <linux/sort.h> 32 33 #include <linux/string_helpers.h> 33 34 #include <linux/timekeeping.h> 34 35 #include <linux/types.h> ··· 43 42 #include <drm/drm_atomic_helper.h> 44 43 #include <drm/drm_crtc.h> 45 44 #include <drm/drm_edid.h> 45 45 + #include <drm/drm_fixed.h> 46 46 #include <drm/drm_probe_helper.h> 47 47 48 48 #include "g4x_dp.h" ··· 129 127 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 130 128 131 129 return dig_port->base.type == INTEL_OUTPUT_EDP; 132 132 - } 133 133 - 134 134 - bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp) 135 135 - { 136 136 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 137 137 - 138 138 - return HAS_AS_SDP(i915) && 139 139 - drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); 140 130 } 141 131 142 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp); ··· 636 642 return -1; 637 643 } 638 644 645 645 + static int intel_dp_link_config_rate(struct intel_dp *intel_dp, 646 646 + const struct intel_dp_link_config *lc) 647 647 + { 648 648 + return intel_dp_common_rate(intel_dp, lc->link_rate_idx); 649 649 + } 650 650 + 651 651 + static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc) 652 652 + { 653 653 + return 1 << lc->lane_count_exp; 654 654 + } 655 655 + 656 656 + static int intel_dp_link_config_bw(struct intel_dp *intel_dp, 657 657 + const struct intel_dp_link_config *lc) 658 658 + { 659 659 + return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc), 660 660 + intel_dp_link_config_lane_count(lc)); 661 661 + } 662 662 + 663 663 + static int link_config_cmp_by_bw(const void *a, const void *b, const void *p) 664 664 + { 665 665 + struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */ 666 666 + const struct intel_dp_link_config *lc_a = a; 667 667 + const struct intel_dp_link_config *lc_b = b; 668 668 + int bw_a = intel_dp_link_config_bw(intel_dp, lc_a); 669 669 + int bw_b = intel_dp_link_config_bw(intel_dp, lc_b); 670 670 + 671 671 + if (bw_a != bw_b) 672 672 + return bw_a - bw_b; 673 673 + 674 674 + return intel_dp_link_config_rate(intel_dp, lc_a) - 675 675 + intel_dp_link_config_rate(intel_dp, lc_b); 676 676 + } 677 677 + 678 678 + static void intel_dp_link_config_init(struct intel_dp *intel_dp) 679 679 + { 680 680 + struct drm_i915_private *i915 = dp_to_i915(intel_dp); 681 681 + struct intel_dp_link_config *lc; 682 682 + int num_common_lane_configs; 683 683 + int i; 684 684 + int j; 685 685 + 686 686 + if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp)))) 687 687 + return; 688 688 + 689 689 + num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1; 690 690 + 691 691 + if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_configs > 692 692 + ARRAY_SIZE(intel_dp->link.configs))) 693 693 + return; 694 694 + 695 695 + intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs; 696 696 + 697 697 + lc = &intel_dp->link.configs[0]; 698 698 + for (i = 0; i < intel_dp->num_common_rates; i++) { 699 699 + for (j = 0; j < num_common_lane_configs; j++) { 700 700 + lc->lane_count_exp = j; 701 701 + lc->link_rate_idx = i; 702 702 + 703 703 + lc++; 704 704 + } 705 705 + } 706 706 + 707 707 + sort_r(intel_dp->link.configs, intel_dp->link.num_configs, 708 708 + sizeof(intel_dp->link.configs[0]), 709 709 + link_config_cmp_by_bw, NULL, 710 710 + intel_dp); 711 711 + } 712 712 + 713 713 + void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) 714 714 + { 715 715 + struct drm_i915_private *i915 = dp_to_i915(intel_dp); 716 716 + const struct intel_dp_link_config *lc; 717 717 + 718 718 + if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs)) 719 719 + idx = 0; 720 720 + 721 721 + lc = &intel_dp->link.configs[idx]; 722 722 + 723 723 + *link_rate = intel_dp_link_config_rate(intel_dp, lc); 724 724 + *lane_count = intel_dp_link_config_lane_count(lc); 725 725 + } 726 726 + 727 727 + int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) 728 728 + { 729 729 + int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, 730 730 + link_rate); 731 731 + int lane_count_exp = ilog2(lane_count); 732 732 + int i; 733 733 + 734 734 + for (i = 0; i < intel_dp->link.num_configs; i++) { 735 735 + const struct intel_dp_link_config *lc = &intel_dp->link.configs[i]; 736 736 + 737 737 + if (lc->lane_count_exp == lane_count_exp && 738 738 + lc->link_rate_idx == link_rate_idx) 739 739 + return i; 740 740 + } 741 741 + 742 742 + return -1; 743 743 + } 744 744 + 639 745 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 640 746 { 641 747 struct drm_i915_private *i915 = dp_to_i915(intel_dp); ··· 754 660 intel_dp->common_rates[0] = 162000; 755 661 intel_dp->num_common_rates = 1; 756 662 } 663 663 + 664 664 + intel_dp_link_config_init(intel_dp); 757 665 } 758 666 759 667 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, ··· 1694 1598 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1695 1599 int mode_rate, link_rate, link_avail; 1696 1600 1697 1697 - for (bpp = to_bpp_int(limits->link.max_bpp_x16); 1698 1698 - bpp >= to_bpp_int(limits->link.min_bpp_x16); 1601 1601 + for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1602 1602 + bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1699 1603 bpp -= 2 * 3) { 1700 1604 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1701 1605 ··· 2023 1927 timeslots); 2024 1928 if (ret == 0) { 2025 1929 pipe_config->dsc.compressed_bpp_x16 = 2026 2026 - to_bpp_x16(valid_dsc_bpp[i]); 1930 1930 + fxp_q4_from_int(valid_dsc_bpp[i]); 2027 1931 return 0; 2028 1932 } 2029 1933 } ··· 2066 1970 compressed_bppx16 >= dsc_min_bpp; 2067 1971 compressed_bppx16 -= bppx16_step) { 2068 1972 if (intel_dp->force_dsc_fractional_bpp_en && 2069 2069 - !to_bpp_frac(compressed_bppx16)) 1973 1973 + !fxp_q4_to_frac(compressed_bppx16)) 2070 1974 continue; 2071 1975 ret = dsc_compute_link_config(intel_dp, 2072 1976 pipe_config, ··· 2076 1980 if (ret == 0) { 2077 1981 pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16; 2078 1982 if (intel_dp->force_dsc_fractional_bpp_en && 2079 2079 - to_bpp_frac(compressed_bppx16)) 1983 1983 + fxp_q4_to_frac(compressed_bppx16)) 2080 1984 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n"); 2081 1985 2082 1986 return 0; ··· 2101 2005 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 2102 2006 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config); 2103 2007 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2104 2104 - dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); 2008 2008 + dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16)); 2105 2009 2106 2010 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2107 2011 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, ··· 2113 2017 adjusted_mode->hdisplay, 2114 2018 pipe_config->joiner_pipes); 2115 2019 dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp); 2116 2116 - dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); 2020 2020 + dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); 2117 2021 2118 2022 if (DISPLAY_VER(i915) >= 13) 2119 2023 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits, ··· 2263 2167 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 2264 2168 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config); 2265 2169 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2266 2266 - dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); 2170 2170 + dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16)); 2267 2171 2268 2172 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2269 2173 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2270 2174 pipe_config, 2271 2175 pipe_bpp / 3); 2272 2176 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2273 2273 - dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); 2177 2177 + dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); 2274 2178 2275 2179 /* Compressed BPP should be less than the Input DSC bpp */ 2276 2180 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2277 2181 2278 2182 pipe_config->dsc.compressed_bpp_x16 = 2279 2279 - to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp)); 2183 2183 + fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp)); 2280 2184 2281 2185 pipe_config->pipe_bpp = pipe_bpp; 2282 2186 ··· 2366 2270 if (ret < 0) { 2367 2271 drm_dbg_kms(&dev_priv->drm, 2368 2272 "Cannot compute valid DSC parameters for Input Bpp = %d" 2369 2369 - "Compressed BPP = " BPP_X16_FMT "\n", 2273 2273 + "Compressed BPP = " FXP_Q4_FMT "\n", 2370 2274 pipe_config->pipe_bpp, 2371 2371 - BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16)); 2275 2275 + FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16)); 2372 2276 return ret; 2373 2277 } 2374 2278 2375 2279 pipe_config->dsc.compression_enable = true; 2376 2280 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " 2377 2377 - "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n", 2281 2281 + "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n", 2378 2282 pipe_config->pipe_bpp, 2379 2379 - BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16), 2283 2283 + FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2380 2284 pipe_config->dsc.slice_count); 2381 2285 2382 2286 return 0; ··· 2408 2312 int max_link_bpp_x16; 2409 2313 2410 2314 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, 2411 2411 - to_bpp_x16(limits->pipe.max_bpp)); 2315 2315 + fxp_q4_from_int(limits->pipe.max_bpp)); 2412 2316 2413 2317 if (!dsc) { 2414 2414 - max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3)); 2318 2318 + max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3)); 2415 2319 2416 2416 - if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp)) 2320 2320 + if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp)) 2417 2321 return false; 2418 2322 2419 2419 - limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp); 2323 2323 + limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp); 2420 2324 } else { 2421 2325 /* 2422 2326 * TODO: set the DSC link limits already here, atm these are ··· 2429 2333 limits->link.max_bpp_x16 = max_link_bpp_x16; 2430 2334 2431 2335 drm_dbg_kms(&i915->drm, 2432 2432 - "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n", 2336 2336 + "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n", 2433 2337 encoder->base.base.id, encoder->base.name, 2434 2338 crtc->base.base.id, crtc->base.name, 2435 2339 adjusted_mode->crtc_clock, ··· 2437 2341 limits->max_lane_count, 2438 2342 limits->max_rate, 2439 2343 limits->pipe.max_bpp, 2440 2440 - BPP_X16_ARGS(limits->link.max_bpp_x16)); 2344 2344 + FXP_Q4_ARGS(limits->link.max_bpp_x16)); 2441 2345 2442 2346 return true; 2443 2347 } ··· 2489 2393 const struct drm_display_mode *adjusted_mode = 2490 2394 &crtc_state->hw.adjusted_mode; 2491 2395 int bpp = crtc_state->dsc.compression_enable ? 2492 2492 - to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2396 2396 + fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2493 2397 crtc_state->pipe_bpp; 2494 2398 2495 2399 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); ··· 2568 2472 } 2569 2473 2570 2474 drm_dbg_kms(&i915->drm, 2571 2571 - "DP lane count %d clock %d bpp input %d compressed " BPP_X16_FMT " link rate required %d available %d\n", 2475 2475 + "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n", 2572 2476 pipe_config->lane_count, pipe_config->port_clock, 2573 2477 pipe_config->pipe_bpp, 2574 2574 - BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16), 2478 2478 + FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2575 2479 intel_dp_config_required_rate(pipe_config), 2576 2480 intel_dp_max_link_data_rate(intel_dp, 2577 2481 pipe_config->port_clock, ··· 2721 2625 const struct drm_display_mode *adjusted_mode = 2722 2626 &crtc_state->hw.adjusted_mode; 2723 2627 2724 2724 - if (!crtc_state->vrr.enable || 2725 2725 - !intel_dp_as_sdp_supported(intel_dp)) 2628 2628 + if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported) 2726 2629 return; 2727 2630 2728 2631 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); ··· 2970 2875 drm_connector_put(&connector->base); 2971 2876 } 2972 2877 2973 2973 - /* NOTE: @state is only valid for MST links and can be %NULL for SST. */ 2974 2878 void 2975 2879 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 2976 2880 struct intel_encoder *encoder, ··· 2978 2884 struct intel_connector *connector; 2979 2885 struct intel_digital_connector_state *conn_state; 2980 2886 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2981 2981 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2982 2887 int i; 2888 2888 + 2889 2889 + if (intel_dp->needs_modeset_retry) 2890 2890 + return; 2891 2891 + 2892 2892 + intel_dp->needs_modeset_retry = true; 2983 2893 2984 2894 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 2985 2895 intel_dp_queue_modeset_retry_work(intel_dp->attached_connector); 2986 2896 2987 2897 return; 2988 2898 } 2989 2989 - 2990 2990 - if (drm_WARN_ON(&i915->drm, !state)) 2991 2991 - return; 2992 2899 2993 2900 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 2994 2901 if (!conn_state->base.crtc) ··· 3062 2967 if (pipe_config->dsc.compression_enable) 3063 2968 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3064 2969 else 3065 3065 - link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format, 3066 3066 - pipe_config->pipe_bpp)); 2970 2970 + link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, 2971 2971 + pipe_config->pipe_bpp)); 3067 2972 3068 2973 if (intel_dp->mso_link_count) { 3069 2974 int n = intel_dp->mso_link_count; ··· 3118 3023 { 3119 3024 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3120 3025 intel_dp->link_trained = false; 3026 3026 + intel_dp->needs_modeset_retry = false; 3121 3027 intel_dp->link_rate = link_rate; 3122 3028 intel_dp->lane_count = lane_count; 3123 3029 } ··· 3127 3031 { 3128 3032 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); 3129 3033 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); 3034 3034 + intel_dp->link.mst_probed_lane_count = 0; 3035 3035 + intel_dp->link.mst_probed_rate = 0; 3130 3036 intel_dp->link.retrain_disabled = false; 3131 3037 intel_dp->link.seq_train_failures = 0; 3132 3038 } ··· 3464 3366 3465 3367 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); 3466 3368 3467 3467 - if (crtc_state) 3369 3369 + if (crtc_state) { 3468 3370 intel_dp_reset_link_params(intel_dp); 3371 3371 + intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 3372 3372 + intel_dp->link_trained = true; 3373 3373 + } 3469 3374 } 3470 3375 3471 3376 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, ··· 3535 3434 3536 3435 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 3537 3436 { 3538 3538 - int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 3437 3437 + static const int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 3539 3438 int i; 3540 3439 3541 3440 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { ··· 4255 4154 4256 4155 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; 4257 4156 4157 4157 + if (intel_dp->is_mst) 4158 4158 + intel_dp_mst_prepare_probe(intel_dp); 4159 4159 + 4258 4160 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 4259 4161 4260 4162 /* Avoid stale info on the next detect cycle. */ ··· 4487 4383 if (!enable && HAS_DSC(dev_priv)) 4488 4384 val &= ~VDIP_ENABLE_PPS; 4489 4385 4490 4490 - /* When PSR is enabled, this routine doesn't disable VSC DIP */ 4491 4491 - if (!crtc_state->has_psr) 4386 4386 + /* 4387 4387 + * This routine disables VSC DIP if the function is called 4388 4388 + * to disable SDP or if it does not have PSR 4389 4389 + */ 4390 4390 + if (!enable || !crtc_state->has_psr) 4492 4391 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 4493 4392 4494 4393 intel_de_write(dev_priv, reg, val); ··· 5358 5251 { 5359 5252 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5360 5253 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5361 5361 - struct intel_crtc *crtc; 5362 5362 - bool mst_output = false; 5363 5254 u8 pipe_mask; 5364 5255 int ret; 5365 5256 ··· 5386 5281 encoder->base.base.id, encoder->base.name, 5387 5282 str_yes_no(intel_dp->link.force_retrain)); 5388 5283 5389 5389 - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { 5390 5390 - const struct intel_crtc_state *crtc_state = 5391 5391 - to_intel_crtc_state(crtc->base.state); 5284 5284 + ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); 5285 5285 + if (ret == -EDEADLK) 5286 5286 + return ret; 5392 5287 5393 5393 - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 5394 5394 - mst_output = true; 5395 5395 - break; 5396 5396 - } 5288 5288 + intel_dp->link.force_retrain = false; 5397 5289 5398 5398 - /* Suppress underruns caused by re-training */ 5399 5399 - intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 5400 5400 - if (crtc_state->has_pch_encoder) 5401 5401 - intel_set_pch_fifo_underrun_reporting(dev_priv, 5402 5402 - intel_crtc_pch_transcoder(crtc), false); 5403 5403 - } 5404 5404 - 5405 5405 - /* TODO: use a modeset for SST as well. */ 5406 5406 - if (mst_output) { 5407 5407 - ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); 5408 5408 - 5409 5409 - if (ret && ret != -EDEADLK) 5410 5410 - drm_dbg_kms(&dev_priv->drm, 5411 5411 - "[ENCODER:%d:%s] link retraining failed: %pe\n", 5412 5412 - encoder->base.base.id, encoder->base.name, 5413 5413 - ERR_PTR(ret)); 5414 5414 - 5415 5415 - goto out; 5416 5416 - } 5417 5417 - 5418 5418 - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { 5419 5419 - const struct intel_crtc_state *crtc_state = 5420 5420 - to_intel_crtc_state(crtc->base.state); 5421 5421 - 5422 5422 - intel_dp->link_trained = false; 5423 5423 - 5424 5424 - intel_dp_check_frl_training(intel_dp); 5425 5425 - intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 5426 5426 - intel_dp_start_link_train(NULL, intel_dp, crtc_state); 5427 5427 - intel_dp_stop_link_train(intel_dp, crtc_state); 5428 5428 - break; 5429 5429 - } 5430 5430 - 5431 5431 - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { 5432 5432 - const struct intel_crtc_state *crtc_state = 5433 5433 - to_intel_crtc_state(crtc->base.state); 5434 5434 - 5435 5435 - /* Keep underrun reporting disabled until things are stable */ 5436 5436 - intel_crtc_wait_for_next_vblank(crtc); 5437 5437 - 5438 5438 - intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 5439 5439 - if (crtc_state->has_pch_encoder) 5440 5440 - intel_set_pch_fifo_underrun_reporting(dev_priv, 5441 5441 - intel_crtc_pch_transcoder(crtc), true); 5442 5442 - } 5443 5443 - 5444 5444 - out: 5445 5445 - if (ret != -EDEADLK) 5446 5446 - intel_dp->link.force_retrain = false; 5290 5290 + if (ret) 5291 5291 + drm_dbg_kms(&dev_priv->drm, 5292 5292 + "[ENCODER:%d:%s] link retraining failed: %pe\n", 5293 5293 + encoder->base.base.id, encoder->base.name, 5294 5294 + ERR_PTR(ret)); 5447 5295 5448 5296 return ret; 5449 5297 } 5450 5298 5451 5299 void intel_dp_link_check(struct intel_encoder *encoder) 5452 5300 { 5453 5453 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 5454 5301 struct drm_modeset_acquire_ctx ctx; 5455 5302 int ret; 5456 5303 5457 5304 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 5458 5305 ret = intel_dp_retrain_link(encoder, &ctx); 5459 5459 - 5460 5460 - drm_WARN_ON(&i915->drm, ret); 5461 5306 } 5462 5307 5463 5308 void intel_dp_check_link_state(struct intel_dp *intel_dp) ··· 5957 5902 connector); 5958 5903 } 5959 5904 5905 5905 + static void 5906 5906 + intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) 5907 5907 + { 5908 5908 + struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5909 5909 + 5910 5910 + intel_dp->as_sdp_supported = HAS_AS_SDP(i915) && 5911 5911 + drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); 5912 5912 + } 5913 5913 + 5960 5914 static int 5961 5915 intel_dp_detect(struct drm_connector *connector, 5962 5916 struct drm_modeset_acquire_ctx *ctx, ··· 6024 5960 6025 5961 intel_dp_detect_dsc_caps(intel_dp, intel_connector); 6026 5962 6027 6027 - intel_dp_mst_configure(intel_dp); 5963 5963 + intel_dp_detect_sdp_caps(intel_dp); 6028 5964 6029 5965 if (intel_dp->reset_link_params) { 6030 5966 intel_dp_reset_link_params(intel_dp); 6031 5967 intel_dp->reset_link_params = false; 6032 5968 } 5969 5969 + 5970 5970 + intel_dp_mst_configure(intel_dp); 6033 5971 6034 5972 intel_dp_print_rates(intel_dp); 6035 5973 ··· 6503 6437 6504 6438 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port) 6505 6439 { 6440 6440 + struct intel_display *display = &i915->display; 6506 6441 const struct intel_bios_encoder_data *devdata = 6507 6507 - intel_bios_encoder_data_lookup(i915, port); 6442 6442 + intel_bios_encoder_data_lookup(display, port); 6508 6443 6509 6444 return _intel_dp_is_port_edp(i915, devdata, port); 6510 6445 } ··· 6608 6541 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 6609 6542 struct intel_connector *intel_connector) 6610 6543 { 6544 6544 + struct intel_display *display = to_intel_display(intel_dp); 6611 6545 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6612 6546 struct drm_connector *connector = &intel_connector->base; 6613 6547 struct drm_display_mode *fixed_mode; ··· 6634 6566 return false; 6635 6567 } 6636 6568 6637 6637 - intel_bios_init_panel_early(dev_priv, &intel_connector->panel, 6569 6569 + intel_bios_init_panel_early(display, &intel_connector->panel, 6638 6570 encoder->devdata); 6639 6571 6640 6572 if (!intel_pps_init(intel_dp)) { ··· 6731 6663 drm_edid = ERR_PTR(-ENOENT); 6732 6664 } 6733 6665 6734 6734 - intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, 6666 6666 + intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, 6735 6667 IS_ERR(drm_edid) ? NULL : drm_edid); 6736 6668 6737 6669 intel_panel_add_edid_fixed_modes(intel_connector, true);

+2 -1

drivers/gpu/drm/i915/display/intel_dp.h

reviewed

··· 85 85 struct drm_connector_state *conn_state); 86 86 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); 87 87 bool intel_dp_is_edp(struct intel_dp *intel_dp); 88 88 - bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp); 89 88 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); 90 89 bool intel_dp_has_dsc(const struct intel_connector *connector); 91 90 int intel_dp_link_symbol_size(int rate); ··· 107 108 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); 108 109 int intel_dp_common_rate(struct intel_dp *intel_dp, int index); 109 110 int intel_dp_rate_index(const int *rates, int len, int rate); 111 111 + int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count); 112 112 + void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count); 110 113 void intel_dp_update_sink_caps(struct intel_dp *intel_dp); 111 114 void intel_dp_reset_link_params(struct intel_dp *intel_dp); 112 115

+10 -3

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

reviewed

··· 150 150 ssize_t ret; 151 151 u8 bcaps; 152 152 153 153 - ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps); 153 153 + ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps); 154 154 if (ret) 155 155 return ret; 156 156 ··· 675 675 int intel_dp_hdcp2_get_capability(struct intel_connector *connector, 676 676 bool *capable) 677 677 { 678 678 - struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 679 679 - struct drm_dp_aux *aux = &dig_port->dp.aux; 678 678 + struct intel_digital_port *dig_port; 679 679 + struct drm_dp_aux *aux; 680 680 + 681 681 + *capable = false; 682 682 + if (!intel_attached_encoder(connector)) 683 683 + return -EINVAL; 684 684 + 685 685 + dig_port = intel_attached_dig_port(connector); 686 686 + aux = &dig_port->dp.aux; 680 687 681 688 return _intel_dp_hdcp2_get_capability(aux, capable); 682 689 }

+97 -35

drivers/gpu/drm/i915/display/intel_dp_link_training.c

reviewed

··· 21 21 * IN THE SOFTWARE. 22 22 */ 23 23 24 24 + #include <drm/display/drm_dp_helper.h> 25 25 + 24 26 #include "i915_drv.h" 25 27 #include "intel_display_types.h" 26 28 #include "intel_dp.h" ··· 116 114 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 117 115 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 118 116 119 119 - return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1; 117 117 + if (drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) != 1) 118 118 + return false; 119 119 + 120 120 + intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 121 121 + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val; 122 122 + 123 123 + return true; 120 124 } 121 125 122 126 static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) ··· 182 174 * still taking into account any LTTPR common lane- rate/count limits. 183 175 */ 184 176 if (lttpr_count < 0) 185 185 - return 0; 177 177 + goto out_reset_lttpr_count; 186 178 187 179 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 188 180 lt_dbg(intel_dp, DP_PHY_DPRX, ··· 705 697 return true; 706 698 } 707 699 708 708 - static void 709 709 - intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, 710 710 - const struct intel_crtc_state *crtc_state) 700 700 + void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr) 711 701 { 712 702 u8 link_config[2]; 713 703 714 714 - link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 715 715 - link_config[1] = intel_dp_is_uhbr(crtc_state) ? 704 704 + link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 705 705 + link_config[1] = drm_dp_is_uhbr_rate(link_rate) ? 716 706 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 717 707 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 718 708 } 719 709 720 720 - static void 721 721 - intel_dp_update_link_bw_set(struct intel_dp *intel_dp, 722 722 - const struct intel_crtc_state *crtc_state, 723 723 - u8 link_bw, u8 rate_select) 710 710 + static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, 711 711 + const struct intel_crtc_state *crtc_state) 724 712 { 725 725 - u8 lane_count = crtc_state->lane_count; 713 713 + intel_dp_link_training_set_mode(intel_dp, 714 714 + crtc_state->port_clock, crtc_state->vrr.flipline); 715 715 + } 726 716 727 727 - if (crtc_state->enhanced_framing) 717 717 + void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, 718 718 + int link_bw, int rate_select, int lane_count, 719 719 + bool enhanced_framing) 720 720 + { 721 721 + if (enhanced_framing) 728 722 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 729 723 730 724 if (link_bw) { ··· 748 738 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); 749 739 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select); 750 740 } 741 741 + } 742 742 + 743 743 + static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp, 744 744 + const struct intel_crtc_state *crtc_state, 745 745 + u8 link_bw, u8 rate_select) 746 746 + { 747 747 + intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count, 748 748 + crtc_state->enhanced_framing); 751 749 } 752 750 753 751 /* ··· 1170 1152 return true; 1171 1153 } 1172 1154 1155 1155 + static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp, 1156 1156 + const struct intel_crtc_state *crtc_state, 1157 1157 + int *new_link_rate, int *new_lane_count) 1158 1158 + { 1159 1159 + int link_rate; 1160 1160 + int lane_count; 1161 1161 + int i; 1162 1162 + 1163 1163 + i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 1164 1164 + for (i--; i >= 0; i--) { 1165 1165 + intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count); 1166 1166 + 1167 1167 + if ((intel_dp->link.force_rate && 1168 1168 + intel_dp->link.force_rate != link_rate) || 1169 1169 + (intel_dp->link.force_lane_count && 1170 1170 + intel_dp->link.force_lane_count != lane_count)) 1171 1171 + continue; 1172 1172 + 1173 1173 + break; 1174 1174 + } 1175 1175 + 1176 1176 + if (i < 0) 1177 1177 + return false; 1178 1178 + 1179 1179 + *new_link_rate = link_rate; 1180 1180 + *new_lane_count = lane_count; 1181 1181 + 1182 1182 + return true; 1183 1183 + } 1184 1184 + 1173 1185 static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) 1174 1186 { 1175 1187 int rate_index; ··· 1235 1187 return current_lane_count >> 1; 1236 1188 } 1237 1189 1190 1190 + static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp, 1191 1191 + const struct intel_crtc_state *crtc_state, 1192 1192 + int *new_link_rate, int *new_lane_count) 1193 1193 + { 1194 1194 + int link_rate; 1195 1195 + int lane_count; 1196 1196 + 1197 1197 + lane_count = crtc_state->lane_count; 1198 1198 + link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); 1199 1199 + if (link_rate < 0) { 1200 1200 + lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); 1201 1201 + link_rate = intel_dp_max_common_rate(intel_dp); 1202 1202 + } 1203 1203 + 1204 1204 + if (lane_count < 0) 1205 1205 + return false; 1206 1206 + 1207 1207 + *new_link_rate = link_rate; 1208 1208 + *new_lane_count = lane_count; 1209 1209 + 1210 1210 + return true; 1211 1211 + } 1212 1212 + 1213 1213 + static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, 1214 1214 + int *new_link_rate, int *new_lane_count) 1215 1215 + { 1216 1216 + /* TODO: Use the same fallback logic on SST as on MST. */ 1217 1217 + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1218 1218 + return reduce_link_params_in_bw_order(intel_dp, crtc_state, 1219 1219 + new_link_rate, new_lane_count); 1220 1220 + else 1221 1221 + return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state, 1222 1222 + new_link_rate, new_lane_count); 1223 1223 + } 1224 1224 + 1238 1225 static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 1239 1226 const struct intel_crtc_state *crtc_state) 1240 1227 { ··· 1283 1200 return 0; 1284 1201 } 1285 1202 1286 1286 - new_lane_count = crtc_state->lane_count; 1287 1287 - new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); 1288 1288 - if (new_link_rate < 0) { 1289 1289 - new_lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); 1290 1290 - new_link_rate = intel_dp_max_common_rate(intel_dp); 1291 1291 - } 1292 1292 - 1293 1293 - if (new_lane_count < 0) 1203 1203 + if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count)) 1294 1204 return -1; 1295 1205 1296 1206 if (intel_dp_is_edp(intel_dp) && ··· 1304 1228 return 0; 1305 1229 } 1306 1230 1307 1307 - /* NOTE: @state is only valid for MST links and can be %NULL for SST. */ 1308 1231 static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, 1309 1232 struct intel_dp *intel_dp, 1310 1233 const struct intel_crtc_state *crtc_state) 1311 1234 { 1312 1312 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1313 1235 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1314 1236 1315 1237 if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { ··· 1322 1248 } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { 1323 1249 return false; 1324 1250 } 1325 1325 - 1326 1326 - if (drm_WARN_ON(&i915->drm, 1327 1327 - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 1328 1328 - !state)) 1329 1329 - return false; 1330 1251 1331 1252 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1332 1253 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); ··· 1581 1512 * retraining with reduced link rate/lane parameters if the link training 1582 1513 * fails. 1583 1514 * After calling this function intel_dp_stop_link_train() must be called. 1584 1584 - * 1585 1585 - * NOTE: @state is only valid for MST links and can be %NULL for SST. 1586 1515 */ 1587 1516 void intel_dp_start_link_train(struct intel_atomic_state *state, 1588 1517 struct intel_dp *intel_dp, ··· 1596 1529 * could've been prevented by an active link. 1597 1530 */ 1598 1531 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1599 1599 - 1600 1600 - if (drm_WARN_ON(&i915->drm, 1601 1601 - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 1602 1602 - !state)) 1603 1603 - return; 1604 1532 1605 1533 if (lttpr_count < 0) 1606 1534 /* Still continue with enabling the port and link training. */

+6

drivers/gpu/drm/i915/display/intel_dp_link_training.h

reviewed

··· 16 16 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]); 17 17 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp); 18 18 19 19 + void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, 20 20 + int link_rate, bool is_vrr); 21 21 + void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, 22 22 + int link_bw, int rate_select, int lane_count, 23 23 + bool enhanced_framing); 24 24 + 19 25 void intel_dp_get_adjust_train(struct intel_dp *intel_dp, 20 26 const struct intel_crtc_state *crtc_state, 21 27 enum drm_dp_phy dp_phy,

+82 -18

drivers/gpu/drm/i915/display/intel_dp_mst.c

reviewed

··· 43 43 #include "intel_dp_hdcp.h" 44 44 #include "intel_dp_mst.h" 45 45 #include "intel_dp_tunnel.h" 46 46 + #include "intel_dp_link_training.h" 46 47 #include "intel_dpio_phy.h" 47 48 #include "intel_hdcp.h" 48 49 #include "intel_hotplug.h" ··· 212 211 213 212 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); 214 213 215 215 - link_bpp_x16 = to_bpp_x16(dsc ? bpp : 216 216 - intel_dp_output_bpp(crtc_state->output_format, bpp)); 214 214 + link_bpp_x16 = fxp_q4_from_int(dsc ? bpp : 215 215 + intel_dp_output_bpp(crtc_state->output_format, bpp)); 217 216 218 217 local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector, 219 218 false, dsc, link_bpp_x16); ··· 290 289 if (!dsc) 291 290 crtc_state->pipe_bpp = bpp; 292 291 else 293 293 - crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp); 292 292 + crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp); 294 293 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc); 295 294 } 296 295 ··· 309 308 * YUV420 is only half of the pipe bpp value. 310 309 */ 311 310 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, 312 312 - to_bpp_int(limits->link.max_bpp_x16), 313 313 - to_bpp_int(limits->link.min_bpp_x16), 311 311 + fxp_q4_to_int(limits->link.max_bpp_x16), 312 312 + fxp_q4_to_int(limits->link.min_bpp_x16), 314 313 limits, 315 314 conn_state, 2 * 3, false); 316 315 ··· 375 374 crtc_state, 376 375 max_bpp / 3); 377 376 max_compressed_bpp = min(max_compressed_bpp, 378 378 - to_bpp_int(limits->link.max_bpp_x16)); 377 377 + fxp_q4_to_int(limits->link.max_bpp_x16)); 379 378 380 379 min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); 381 380 min_compressed_bpp = max(min_compressed_bpp, 382 382 - to_bpp_int_roundup(limits->link.min_bpp_x16)); 381 381 + fxp_q4_to_int_roundup(limits->link.min_bpp_x16)); 383 382 384 383 drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n", 385 384 min_compressed_bpp, max_compressed_bpp); ··· 479 478 crtc->base.base.id, crtc->base.name, 480 479 connector->base.base.id, connector->base.name); 481 480 482 482 - if (limits->link.max_bpp_x16 < to_bpp_x16(24)) 481 481 + if (limits->link.max_bpp_x16 < fxp_q4_from_int(24)) 483 482 return false; 484 483 485 485 - limits->link.min_bpp_x16 = to_bpp_x16(24); 484 484 + limits->link.min_bpp_x16 = fxp_q4_from_int(24); 486 485 487 486 return true; 488 487 } ··· 490 489 drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate); 491 490 492 491 if (limits->max_rate < 540000) 493 493 - min_bpp_x16 = to_bpp_x16(13); 492 492 + min_bpp_x16 = fxp_q4_from_int(13); 494 493 else if (limits->max_rate < 810000) 495 495 - min_bpp_x16 = to_bpp_x16(10); 494 494 + min_bpp_x16 = fxp_q4_from_int(10); 496 495 497 496 if (limits->link.min_bpp_x16 >= min_bpp_x16) 498 497 return true; 499 498 500 499 drm_dbg_kms(&i915->drm, 501 501 - "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " in DSC mode due to hblank expansion quirk\n", 500 500 + "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " FXP_Q4_FMT " in DSC mode due to hblank expansion quirk\n", 502 501 crtc->base.base.id, crtc->base.name, 503 502 connector->base.base.id, connector->base.name, 504 504 - BPP_X16_ARGS(min_bpp_x16)); 503 503 + FXP_Q4_ARGS(min_bpp_x16)); 505 504 506 505 if (limits->link.max_bpp_x16 < min_bpp_x16) 507 506 return false; ··· 1114 1113 to_intel_crtc(pipe_config->uapi.crtc)); 1115 1114 } 1116 1115 1116 1116 + static bool intel_mst_probed_link_params_valid(struct intel_dp *intel_dp, 1117 1117 + int link_rate, int lane_count) 1118 1118 + { 1119 1119 + return intel_dp->link.mst_probed_rate == link_rate && 1120 1120 + intel_dp->link.mst_probed_lane_count == lane_count; 1121 1121 + } 1122 1122 + 1123 1123 + static void intel_mst_set_probed_link_params(struct intel_dp *intel_dp, 1124 1124 + int link_rate, int lane_count) 1125 1125 + { 1126 1126 + intel_dp->link.mst_probed_rate = link_rate; 1127 1127 + intel_dp->link.mst_probed_lane_count = lane_count; 1128 1128 + } 1129 1129 + 1130 1130 + static void intel_mst_reprobe_topology(struct intel_dp *intel_dp, 1131 1131 + const struct intel_crtc_state *crtc_state) 1132 1132 + { 1133 1133 + if (intel_mst_probed_link_params_valid(intel_dp, 1134 1134 + crtc_state->port_clock, crtc_state->lane_count)) 1135 1135 + return; 1136 1136 + 1137 1137 + drm_dp_mst_topology_queue_probe(&intel_dp->mst_mgr); 1138 1138 + 1139 1139 + intel_mst_set_probed_link_params(intel_dp, 1140 1140 + crtc_state->port_clock, crtc_state->lane_count); 1141 1141 + } 1142 1142 + 1117 1143 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, 1118 1144 struct intel_encoder *encoder, 1119 1145 const struct intel_crtc_state *pipe_config, ··· 1177 1149 1178 1150 intel_dp_sink_enable_decompression(state, connector, pipe_config); 1179 1151 1180 1180 - if (first_mst_stream) 1152 1152 + if (first_mst_stream) { 1181 1153 dig_port->base.pre_enable(state, &dig_port->base, 1182 1154 pipe_config, NULL); 1155 1155 + 1156 1156 + intel_mst_reprobe_topology(intel_dp, pipe_config); 1157 1157 + } 1183 1158 1184 1159 intel_dp->active_mst_links++; 1185 1160 1186 1161 ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state, 1187 1162 drm_atomic_get_mst_payload_state(mst_state, connector->port)); 1188 1163 if (ret < 0) 1189 1189 - drm_dbg_kms(&dev_priv->drm, "Failed to create MST payload for %s: %d\n", 1190 1190 - connector->base.name, ret); 1164 1164 + intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config); 1191 1165 1192 1166 /* 1193 1167 * Before Gen 12 this is not done as part of ··· 1253 1223 enum transcoder trans = pipe_config->cpu_transcoder; 1254 1224 bool first_mst_stream = intel_dp->active_mst_links == 1; 1255 1225 struct intel_crtc *pipe_crtc; 1226 1226 + int ret; 1256 1227 1257 1228 drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); 1258 1229 ··· 1285 1254 if (first_mst_stream) 1286 1255 intel_ddi_wait_for_fec_status(encoder, pipe_config, true); 1287 1256 1288 1288 - drm_dp_add_payload_part2(&intel_dp->mst_mgr, 1289 1289 - drm_atomic_get_mst_payload_state(mst_state, connector->port)); 1257 1257 + ret = drm_dp_add_payload_part2(&intel_dp->mst_mgr, 1258 1258 + drm_atomic_get_mst_payload_state(mst_state, 1259 1259 + connector->port)); 1260 1260 + if (ret < 0) 1261 1261 + intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config); 1290 1262 1291 1263 if (DISPLAY_VER(dev_priv) >= 12) 1292 1264 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans), ··· 2031 1997 } 2032 1998 2033 1999 return false; 2000 2000 + } 2001 2001 + 2002 2002 + /** 2003 2003 + * intel_dp_mst_prepare_probe - Prepare an MST link for topology probing 2004 2004 + * @intel_dp: DP port object 2005 2005 + * 2006 2006 + * Prepare an MST link for topology probing, programming the target 2007 2007 + * link parameters to DPCD. This step is a requirement of the enumaration 2008 2008 + * of path resources during probing. 2009 2009 + */ 2010 2010 + void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp) 2011 2011 + { 2012 2012 + int link_rate = intel_dp_max_link_rate(intel_dp); 2013 2013 + int lane_count = intel_dp_max_lane_count(intel_dp); 2014 2014 + u8 rate_select; 2015 2015 + u8 link_bw; 2016 2016 + 2017 2017 + if (intel_dp->link_trained) 2018 2018 + return; 2019 2019 + 2020 2020 + if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count)) 2021 2021 + return; 2022 2022 + 2023 2023 + intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select); 2024 2024 + 2025 2025 + intel_dp_link_training_set_mode(intel_dp, link_rate, false); 2026 2026 + intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count, 2027 2027 + drm_dp_enhanced_frame_cap(intel_dp->dpcd)); 2028 2028 + 2029 2029 + intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count); 2034 2030 }

+1

drivers/gpu/drm/i915/display/intel_dp_mst.h

reviewed

··· 27 27 struct intel_link_bw_limits *limits); 28 28 bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, 29 29 struct intel_crtc *crtc); 30 30 + void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp); 30 31 31 32 #endif /* __INTEL_DP_MST_H__ */

+1 -1

drivers/gpu/drm/i915/display/intel_dsi.h

reviewed

··· 66 66 /* number of DSI lanes */ 67 67 unsigned int lane_count; 68 68 69 69 - /* i2c bus associated with the slave device */ 69 69 + /* i2c bus associated with the target device */ 70 70 int i2c_bus_num; 71 71 72 72 /*

+10 -10

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

reviewed

··· 56 56 #define MIPI_PORT_SHIFT 3 57 57 58 58 struct i2c_adapter_lookup { 59 59 - u16 slave_addr; 59 59 + u16 target_addr; 60 60 struct intel_dsi *intel_dsi; 61 61 acpi_handle dev_handle; 62 62 }; ··· 443 443 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 444 444 return 1; 445 445 446 446 - if (lookup->slave_addr != sb->slave_address) 446 446 + if (lookup->target_addr != sb->slave_address) 447 447 return 1; 448 448 449 449 status = acpi_get_handle(lookup->dev_handle, ··· 460 460 } 461 461 462 462 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 463 463 - const u16 slave_addr) 463 463 + const u16 target_addr) 464 464 { 465 465 struct drm_device *drm_dev = intel_dsi->base.base.dev; 466 466 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev); 467 467 struct i2c_adapter_lookup lookup = { 468 468 - .slave_addr = slave_addr, 468 468 + .target_addr = target_addr, 469 469 .intel_dsi = intel_dsi, 470 470 .dev_handle = acpi_device_handle(adev), 471 471 }; ··· 476 476 } 477 477 #else 478 478 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 479 479 - const u16 slave_addr) 479 479 + const u16 target_addr) 480 480 { 481 481 } 482 482 #endif ··· 488 488 struct i2c_msg msg; 489 489 int ret; 490 490 u8 vbt_i2c_bus_num = *(data + 2); 491 491 - u16 slave_addr = *(u16 *)(data + 3); 491 491 + u16 target_addr = *(u16 *)(data + 3); 492 492 u8 reg_offset = *(data + 5); 493 493 u8 payload_size = *(data + 6); 494 494 u8 *payload_data; 495 495 496 496 - drm_dbg_kms(&i915->drm, "bus %d client-addr 0x%02x reg 0x%02x data %*ph\n", 497 497 - vbt_i2c_bus_num, slave_addr, reg_offset, payload_size, data + 7); 496 496 + drm_dbg_kms(&i915->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n", 497 497 + vbt_i2c_bus_num, target_addr, reg_offset, payload_size, data + 7); 498 498 499 499 if (intel_dsi->i2c_bus_num < 0) { 500 500 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 501 501 - i2c_acpi_find_adapter(intel_dsi, slave_addr); 501 501 + i2c_acpi_find_adapter(intel_dsi, target_addr); 502 502 } 503 503 504 504 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); ··· 514 514 payload_data[0] = reg_offset; 515 515 memcpy(&payload_data[1], (data + 7), payload_size); 516 516 517 517 - msg.addr = slave_addr; 517 517 + msg.addr = target_addr; 518 518 msg.flags = 0; 519 519 msg.len = payload_size + 1; 520 520 msg.buf = payload_data;

+7 -7

drivers/gpu/drm/i915/display/intel_dvo.c

reviewed

··· 60 60 .type = INTEL_DVO_CHIP_TMDS, 61 61 .name = "sil164", 62 62 .port = PORT_C, 63 63 - .slave_addr = SIL164_ADDR, 63 63 + .target_addr = SIL164_ADDR, 64 64 .dev_ops = &sil164_ops, 65 65 }, 66 66 { 67 67 .type = INTEL_DVO_CHIP_TMDS, 68 68 .name = "ch7xxx", 69 69 .port = PORT_C, 70 70 - .slave_addr = CH7xxx_ADDR, 70 70 + .target_addr = CH7xxx_ADDR, 71 71 .dev_ops = &ch7xxx_ops, 72 72 }, 73 73 { 74 74 .type = INTEL_DVO_CHIP_TMDS, 75 75 .name = "ch7xxx", 76 76 .port = PORT_C, 77 77 - .slave_addr = 0x75, /* For some ch7010 */ 77 77 + .target_addr = 0x75, /* For some ch7010 */ 78 78 .dev_ops = &ch7xxx_ops, 79 79 }, 80 80 { 81 81 .type = INTEL_DVO_CHIP_LVDS, 82 82 .name = "ivch", 83 83 .port = PORT_A, 84 84 - .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ 84 84 + .target_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ 85 85 .dev_ops = &ivch_ops, 86 86 }, 87 87 { 88 88 .type = INTEL_DVO_CHIP_TMDS, 89 89 .name = "tfp410", 90 90 .port = PORT_C, 91 91 - .slave_addr = TFP410_ADDR, 91 91 + .target_addr = TFP410_ADDR, 92 92 .dev_ops = &tfp410_ops, 93 93 }, 94 94 { 95 95 .type = INTEL_DVO_CHIP_LVDS, 96 96 .name = "ch7017", 97 97 .port = PORT_C, 98 98 - .slave_addr = 0x75, 98 98 + .target_addr = 0x75, 99 99 .gpio = GMBUS_PIN_DPB, 100 100 .dev_ops = &ch7017_ops, 101 101 }, ··· 103 103 .type = INTEL_DVO_CHIP_LVDS_NO_FIXED, 104 104 .name = "ns2501", 105 105 .port = PORT_B, 106 106 - .slave_addr = NS2501_ADDR, 106 106 + .target_addr = NS2501_ADDR, 107 107 .dev_ops = &ns2501_ops, 108 108 }, 109 109 };

+1 -1

drivers/gpu/drm/i915/display/intel_dvo_dev.h

reviewed

··· 38 38 enum port port; 39 39 /* GPIO register used for i2c bus to control this device */ 40 40 u32 gpio; 41 41 - int slave_addr; 41 41 + int target_addr; 42 42 43 43 const struct intel_dvo_dev_ops *dev_ops; 44 44 void *dev_priv;

+313 -234

drivers/gpu/drm/i915/display/intel_fbc.c

reviewed

··· 61 61 #include "intel_fbc_regs.h" 62 62 #include "intel_frontbuffer.h" 63 63 64 64 - #define for_each_fbc_id(__dev_priv, __fbc_id) \ 64 64 + #define for_each_fbc_id(__display, __fbc_id) \ 65 65 for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \ 66 66 - for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id)) 66 66 + for_each_if(DISPLAY_RUNTIME_INFO(__display)->fbc_mask & BIT(__fbc_id)) 67 67 68 68 - #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \ 69 69 - for_each_fbc_id((__dev_priv), (__fbc_id)) \ 70 70 - for_each_if((__fbc) = (__dev_priv)->display.fbc[(__fbc_id)]) 68 68 + #define for_each_intel_fbc(__display, __fbc, __fbc_id) \ 69 69 + for_each_fbc_id((__display), (__fbc_id)) \ 70 70 + for_each_if((__fbc) = (__display)->fbc[(__fbc_id)]) 71 71 72 72 struct intel_fbc_funcs { 73 73 void (*activate)(struct intel_fbc *fbc); ··· 90 90 }; 91 91 92 92 struct intel_fbc { 93 93 - struct drm_i915_private *i915; 93 93 + struct intel_display *display; 94 94 const struct intel_fbc_funcs *funcs; 95 95 96 96 /* ··· 140 140 return stride; 141 141 } 142 142 143 143 - /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */ 144 144 - static unsigned int _intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 143 143 + static unsigned int intel_fbc_cfb_cpp(void) 145 144 { 146 146 - unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ 145 145 + return 4; /* FBC always 4 bytes per pixel */ 146 146 + } 147 147 + 148 148 + /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */ 149 149 + static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state) 150 150 + { 151 151 + unsigned int cpp = intel_fbc_cfb_cpp(); 147 152 148 153 return intel_fbc_plane_stride(plane_state) * cpp; 149 154 } 150 155 151 156 /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ 152 152 - static unsigned int skl_fbc_min_cfb_stride(const struct intel_plane_state *plane_state) 157 157 + static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, 158 158 + unsigned int cpp, unsigned int width) 153 159 { 154 154 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 155 160 unsigned int limit = 4; /* 1:4 compression limit is the worst case */ 156 156 - unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ 157 157 - unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; 158 161 unsigned int height = 4; /* FBC segment is 4 lines */ 159 162 unsigned int stride; 160 163 ··· 168 165 * Wa_16011863758: icl+ 169 166 * Avoid some hardware segment address miscalculation. 170 167 */ 171 171 - if (DISPLAY_VER(i915) >= 11) 168 168 + if (DISPLAY_VER(display) >= 11) 172 169 stride += 64; 173 170 174 171 /* ··· 182 179 } 183 180 184 181 /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */ 185 185 - static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 182 182 + static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, 183 183 + unsigned int cpp, unsigned int width, 184 184 + unsigned int stride) 186 185 { 187 187 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 188 188 - unsigned int stride = _intel_fbc_cfb_stride(plane_state); 189 189 - 190 186 /* 191 187 * At least some of the platforms require each 4 line segment to 192 188 * be 512 byte aligned. Aligning each line to 512 bytes guarantees 193 189 * that regardless of the compression limit we choose later. 194 190 */ 195 195 - if (DISPLAY_VER(i915) >= 9) 196 196 - return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(plane_state)); 191 191 + if (DISPLAY_VER(display) >= 9) 192 192 + return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); 197 193 else 198 194 return stride; 199 195 } 200 196 197 197 + static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 198 198 + { 199 199 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 200 200 + unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); 201 201 + unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; 202 202 + unsigned int cpp = intel_fbc_cfb_cpp(); 203 203 + 204 204 + return _intel_fbc_cfb_stride(display, cpp, width, stride); 205 205 + } 206 206 + 207 207 + /* 208 208 + * Maximum height the hardware will compress, on HSW+ 209 209 + * additional lines (up to the actual plane height) will 210 210 + * remain uncompressed. 211 211 + */ 212 212 + static unsigned int intel_fbc_max_cfb_height(struct intel_display *display) 213 213 + { 214 214 + struct drm_i915_private *i915 = to_i915(display->drm); 215 215 + 216 216 + if (DISPLAY_VER(display) >= 8) 217 217 + return 2560; 218 218 + else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) 219 219 + return 2048; 220 220 + else 221 221 + return 1536; 222 222 + } 223 223 + 224 224 + static unsigned int _intel_fbc_cfb_size(struct intel_display *display, 225 225 + unsigned int height, unsigned int stride) 226 226 + { 227 227 + return min(height, intel_fbc_max_cfb_height(display)) * stride; 228 228 + } 229 229 + 201 230 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state) 202 231 { 203 203 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 204 204 - int lines = drm_rect_height(&plane_state->uapi.src) >> 16; 232 232 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 233 233 + unsigned int height = drm_rect_height(&plane_state->uapi.src) >> 16; 205 234 206 206 - if (DISPLAY_VER(i915) == 7) 207 207 - lines = min(lines, 2048); 208 208 - else if (DISPLAY_VER(i915) >= 8) 209 209 - lines = min(lines, 2560); 210 210 - 211 211 - return lines * intel_fbc_cfb_stride(plane_state); 235 235 + return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state)); 212 236 } 213 237 214 238 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state) 215 239 { 216 216 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 240 240 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 217 241 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state); 218 218 - unsigned int stride = _intel_fbc_cfb_stride(plane_state); 242 242 + unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); 219 243 const struct drm_framebuffer *fb = plane_state->hw.fb; 220 244 221 245 /* ··· 253 223 * we always need to use the override there. 254 224 */ 255 225 if (stride != stride_aligned || 256 256 - (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) 226 226 + (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) 257 227 return stride_aligned * 4 / 64; 258 228 259 229 return 0; 260 230 } 261 231 232 232 + static bool intel_fbc_has_fences(struct intel_display *display) 233 233 + { 234 234 + struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); 235 235 + 236 236 + return intel_gt_support_legacy_fencing(to_gt(i915)); 237 237 + } 238 238 + 262 239 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) 263 240 { 264 241 const struct intel_fbc_state *fbc_state = &fbc->state; 265 265 - struct drm_i915_private *i915 = fbc->i915; 242 242 + struct intel_display *display = fbc->display; 243 243 + struct drm_i915_private *i915 = to_i915(display->drm); 266 244 unsigned int cfb_stride; 267 245 u32 fbc_ctl; 268 246 269 247 cfb_stride = fbc_state->cfb_stride / fbc->limit; 270 248 271 249 /* FBC_CTL wants 32B or 64B units */ 272 272 - if (DISPLAY_VER(i915) == 2) 250 250 + if (DISPLAY_VER(display) == 2) 273 251 cfb_stride = (cfb_stride / 32) - 1; 274 252 else 275 253 cfb_stride = (cfb_stride / 64) - 1; ··· 311 273 312 274 static void i8xx_fbc_deactivate(struct intel_fbc *fbc) 313 275 { 314 314 - struct drm_i915_private *i915 = fbc->i915; 276 276 + struct intel_display *display = fbc->display; 315 277 u32 fbc_ctl; 316 278 317 279 /* Disable compression */ 318 318 - fbc_ctl = intel_de_read(i915, FBC_CONTROL); 280 280 + fbc_ctl = intel_de_read(display, FBC_CONTROL); 319 281 if ((fbc_ctl & FBC_CTL_EN) == 0) 320 282 return; 321 283 322 284 fbc_ctl &= ~FBC_CTL_EN; 323 323 - intel_de_write(i915, FBC_CONTROL, fbc_ctl); 285 285 + intel_de_write(display, FBC_CONTROL, fbc_ctl); 324 286 325 287 /* Wait for compressing bit to clear */ 326 326 - if (intel_de_wait_for_clear(i915, FBC_STATUS, 288 288 + if (intel_de_wait_for_clear(display, FBC_STATUS, 327 289 FBC_STAT_COMPRESSING, 10)) { 328 328 - drm_dbg_kms(&i915->drm, "FBC idle timed out\n"); 290 290 + drm_dbg_kms(display->drm, "FBC idle timed out\n"); 329 291 return; 330 292 } 331 293 } ··· 333 295 static void i8xx_fbc_activate(struct intel_fbc *fbc) 334 296 { 335 297 const struct intel_fbc_state *fbc_state = &fbc->state; 336 336 - struct drm_i915_private *i915 = fbc->i915; 298 298 + struct intel_display *display = fbc->display; 337 299 int i; 338 300 339 301 /* Clear old tags */ 340 302 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 341 341 - intel_de_write(i915, FBC_TAG(i), 0); 303 303 + intel_de_write(display, FBC_TAG(i), 0); 342 304 343 343 - if (DISPLAY_VER(i915) == 4) { 344 344 - intel_de_write(i915, FBC_CONTROL2, 305 305 + if (DISPLAY_VER(display) == 4) { 306 306 + intel_de_write(display, FBC_CONTROL2, 345 307 i965_fbc_ctl2(fbc)); 346 346 - intel_de_write(i915, FBC_FENCE_OFF, 308 308 + intel_de_write(display, FBC_FENCE_OFF, 347 309 fbc_state->fence_y_offset); 348 310 } 349 311 350 350 - intel_de_write(i915, FBC_CONTROL, 312 312 + intel_de_write(display, FBC_CONTROL, 351 313 FBC_CTL_EN | i8xx_fbc_ctl(fbc)); 352 314 } 353 315 354 316 static bool i8xx_fbc_is_active(struct intel_fbc *fbc) 355 317 { 356 356 - return intel_de_read(fbc->i915, FBC_CONTROL) & FBC_CTL_EN; 318 318 + return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN; 357 319 } 358 320 359 321 static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc) 360 322 { 361 361 - return intel_de_read(fbc->i915, FBC_STATUS) & 323 323 + return intel_de_read(fbc->display, FBC_STATUS) & 362 324 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); 363 325 } 364 326 ··· 366 328 { 367 329 struct intel_fbc_state *fbc_state = &fbc->state; 368 330 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 369 369 - struct drm_i915_private *dev_priv = fbc->i915; 331 331 + struct drm_i915_private *dev_priv = to_i915(fbc->display->drm); 370 332 371 333 intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 372 334 intel_de_read_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane))); ··· 374 336 375 337 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) 376 338 { 377 377 - struct drm_i915_private *i915 = fbc->i915; 339 339 + struct intel_display *display = fbc->display; 340 340 + struct drm_i915_private *i915 = to_i915(display->drm); 378 341 379 379 - drm_WARN_ON(&i915->drm, 342 342 + drm_WARN_ON(display->drm, 380 343 range_overflows_end_t(u64, i915_gem_stolen_area_address(i915), 381 344 i915_gem_stolen_node_offset(&fbc->compressed_fb), 382 345 U32_MAX)); 383 383 - drm_WARN_ON(&i915->drm, 346 346 + drm_WARN_ON(display->drm, 384 347 range_overflows_end_t(u64, i915_gem_stolen_area_address(i915), 385 348 i915_gem_stolen_node_offset(&fbc->compressed_llb), 386 349 U32_MAX)); ··· 404 365 { 405 366 struct intel_fbc_state *fbc_state = &fbc->state; 406 367 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 407 407 - struct drm_i915_private *dev_priv = fbc->i915; 368 368 + struct drm_i915_private *dev_priv = to_i915(fbc->display->drm); 408 369 409 370 intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 410 371 intel_de_read_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane))); ··· 437 398 static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) 438 399 { 439 400 const struct intel_fbc_state *fbc_state = &fbc->state; 440 440 - struct drm_i915_private *i915 = fbc->i915; 401 401 + struct intel_display *display = fbc->display; 402 402 + struct drm_i915_private *i915 = to_i915(display->drm); 441 403 u32 dpfc_ctl; 442 404 443 405 dpfc_ctl = g4x_dpfc_ctl_limit(fbc) | ··· 450 410 if (fbc_state->fence_id >= 0) { 451 411 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X; 452 412 453 453 - if (DISPLAY_VER(i915) < 6) 413 413 + if (DISPLAY_VER(display) < 6) 454 414 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id); 455 415 } 456 416 ··· 460 420 static void g4x_fbc_activate(struct intel_fbc *fbc) 461 421 { 462 422 const struct intel_fbc_state *fbc_state = &fbc->state; 463 463 - struct drm_i915_private *i915 = fbc->i915; 423 423 + struct intel_display *display = fbc->display; 464 424 465 465 - intel_de_write(i915, DPFC_FENCE_YOFF, 425 425 + intel_de_write(display, DPFC_FENCE_YOFF, 466 426 fbc_state->fence_y_offset); 467 427 468 468 - intel_de_write(i915, DPFC_CONTROL, 428 428 + intel_de_write(display, DPFC_CONTROL, 469 429 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 470 430 } 471 431 472 432 static void g4x_fbc_deactivate(struct intel_fbc *fbc) 473 433 { 474 474 - struct drm_i915_private *i915 = fbc->i915; 434 434 + struct intel_display *display = fbc->display; 475 435 u32 dpfc_ctl; 476 436 477 437 /* Disable compression */ 478 478 - dpfc_ctl = intel_de_read(i915, DPFC_CONTROL); 438 438 + dpfc_ctl = intel_de_read(display, DPFC_CONTROL); 479 439 if (dpfc_ctl & DPFC_CTL_EN) { 480 440 dpfc_ctl &= ~DPFC_CTL_EN; 481 481 - intel_de_write(i915, DPFC_CONTROL, dpfc_ctl); 441 441 + intel_de_write(display, DPFC_CONTROL, dpfc_ctl); 482 442 } 483 443 } 484 444 485 445 static bool g4x_fbc_is_active(struct intel_fbc *fbc) 486 446 { 487 487 - return intel_de_read(fbc->i915, DPFC_CONTROL) & DPFC_CTL_EN; 447 447 + return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN; 488 448 } 489 449 490 450 static bool g4x_fbc_is_compressing(struct intel_fbc *fbc) 491 451 { 492 492 - return intel_de_read(fbc->i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK; 452 452 + return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK; 493 453 } 494 454 495 455 static void g4x_fbc_program_cfb(struct intel_fbc *fbc) 496 456 { 497 497 - struct drm_i915_private *i915 = fbc->i915; 457 457 + struct intel_display *display = fbc->display; 498 458 499 499 - intel_de_write(i915, DPFC_CB_BASE, 459 459 + intel_de_write(display, DPFC_CB_BASE, 500 460 i915_gem_stolen_node_offset(&fbc->compressed_fb)); 501 461 } 502 462 ··· 512 472 static void ilk_fbc_activate(struct intel_fbc *fbc) 513 473 { 514 474 struct intel_fbc_state *fbc_state = &fbc->state; 515 515 - struct drm_i915_private *i915 = fbc->i915; 475 475 + struct intel_display *display = fbc->display; 516 476 517 517 - intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id), 477 477 + intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id), 518 478 fbc_state->fence_y_offset); 519 479 520 520 - intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), 480 480 + intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), 521 481 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 522 482 } 523 483 524 484 static void ilk_fbc_deactivate(struct intel_fbc *fbc) 525 485 { 526 526 - struct drm_i915_private *i915 = fbc->i915; 486 486 + struct intel_display *display = fbc->display; 527 487 u32 dpfc_ctl; 528 488 529 489 /* Disable compression */ 530 530 - dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id)); 490 490 + dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); 531 491 if (dpfc_ctl & DPFC_CTL_EN) { 532 492 dpfc_ctl &= ~DPFC_CTL_EN; 533 533 - intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 493 493 + intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 534 494 } 535 495 } 536 496 537 497 static bool ilk_fbc_is_active(struct intel_fbc *fbc) 538 498 { 539 539 - return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN; 499 499 + return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN; 540 500 } 541 501 542 502 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc) 543 503 { 544 544 - return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK; 504 504 + return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK; 545 505 } 546 506 547 507 static void ilk_fbc_program_cfb(struct intel_fbc *fbc) 548 508 { 549 549 - struct drm_i915_private *i915 = fbc->i915; 509 509 + struct intel_display *display = fbc->display; 550 510 551 551 - intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), 511 511 + intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id), 552 512 i915_gem_stolen_node_offset(&fbc->compressed_fb)); 553 513 } 554 514 ··· 564 524 static void snb_fbc_program_fence(struct intel_fbc *fbc) 565 525 { 566 526 const struct intel_fbc_state *fbc_state = &fbc->state; 567 567 - struct drm_i915_private *i915 = fbc->i915; 527 527 + struct intel_display *display = fbc->display; 568 528 u32 ctl = 0; 569 529 570 530 if (fbc_state->fence_id >= 0) 571 531 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id); 572 532 573 573 - intel_de_write(i915, SNB_DPFC_CTL_SA, ctl); 574 574 - intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset); 533 533 + intel_de_write(display, SNB_DPFC_CTL_SA, ctl); 534 534 + intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset); 575 535 } 576 536 577 537 static void snb_fbc_activate(struct intel_fbc *fbc) ··· 583 543 584 544 static void snb_fbc_nuke(struct intel_fbc *fbc) 585 545 { 586 586 - struct drm_i915_private *i915 = fbc->i915; 546 546 + struct intel_display *display = fbc->display; 587 547 588 588 - intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE); 589 589 - intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id)); 548 548 + intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE); 549 549 + intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id)); 590 550 } 591 551 592 552 static const struct intel_fbc_funcs snb_fbc_funcs = { ··· 601 561 static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) 602 562 { 603 563 const struct intel_fbc_state *fbc_state = &fbc->state; 604 604 - struct drm_i915_private *i915 = fbc->i915; 564 564 + struct intel_display *display = fbc->display; 605 565 u32 val = 0; 606 566 607 567 if (fbc_state->override_cfb_stride) 608 568 val |= FBC_STRIDE_OVERRIDE | 609 569 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 610 570 611 611 - intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val); 571 571 + intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val); 612 572 } 613 573 614 574 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) 615 575 { 616 576 const struct intel_fbc_state *fbc_state = &fbc->state; 617 617 - struct drm_i915_private *i915 = fbc->i915; 577 577 + struct intel_display *display = fbc->display; 618 578 u32 val = 0; 619 579 620 580 /* Display WA #0529: skl, kbl, bxt. */ ··· 622 582 val |= CHICKEN_FBC_STRIDE_OVERRIDE | 623 583 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 624 584 625 625 - intel_de_rmw(i915, CHICKEN_MISC_4, 585 585 + intel_de_rmw(display, CHICKEN_MISC_4, 626 586 CHICKEN_FBC_STRIDE_OVERRIDE | 627 587 CHICKEN_FBC_STRIDE_MASK, val); 628 588 } ··· 630 590 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) 631 591 { 632 592 const struct intel_fbc_state *fbc_state = &fbc->state; 633 633 - struct drm_i915_private *i915 = fbc->i915; 593 593 + struct intel_display *display = fbc->display; 594 594 + struct drm_i915_private *i915 = to_i915(display->drm); 634 595 u32 dpfc_ctl; 635 596 636 597 dpfc_ctl = g4x_dpfc_ctl_limit(fbc); ··· 639 598 if (IS_IVYBRIDGE(i915)) 640 599 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); 641 600 642 642 - if (DISPLAY_VER(i915) >= 20) 601 601 + if (DISPLAY_VER(display) >= 20) 643 602 dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id); 644 603 645 604 if (fbc_state->fence_id >= 0) ··· 653 612 654 613 static void ivb_fbc_activate(struct intel_fbc *fbc) 655 614 { 656 656 - struct drm_i915_private *i915 = fbc->i915; 615 615 + struct intel_display *display = fbc->display; 657 616 u32 dpfc_ctl; 658 617 659 659 - if (DISPLAY_VER(i915) >= 10) 618 618 + if (DISPLAY_VER(display) >= 10) 660 619 glk_fbc_program_cfb_stride(fbc); 661 661 - else if (DISPLAY_VER(i915) == 9) 620 620 + else if (DISPLAY_VER(display) == 9) 662 621 skl_fbc_program_cfb_stride(fbc); 663 622 664 664 - if (intel_gt_support_legacy_fencing(to_gt(i915))) 623 623 + if (intel_fbc_has_fences(display)) 665 624 snb_fbc_program_fence(fbc); 666 625 667 626 /* wa_14019417088 Alternative WA*/ 668 627 dpfc_ctl = ivb_dpfc_ctl(fbc); 669 669 - if (DISPLAY_VER(i915) >= 20) 670 670 - intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 628 628 + if (DISPLAY_VER(display) >= 20) 629 629 + intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 671 630 672 672 - intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), 631 631 + intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), 673 632 DPFC_CTL_EN | dpfc_ctl); 674 633 } 675 634 676 635 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) 677 636 { 678 678 - return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB; 637 637 + return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB; 679 638 } 680 639 681 640 static void ivb_fbc_set_false_color(struct intel_fbc *fbc, 682 641 bool enable) 683 642 { 684 684 - intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id), 643 643 + intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id), 685 644 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0); 686 645 } 687 646 ··· 726 685 727 686 static void intel_fbc_nuke(struct intel_fbc *fbc) 728 687 { 729 729 - struct drm_i915_private *i915 = fbc->i915; 688 688 + struct intel_display *display = fbc->display; 730 689 731 690 lockdep_assert_held(&fbc->lock); 732 732 - drm_WARN_ON(&i915->drm, fbc->flip_pending); 691 691 + drm_WARN_ON(display->drm, fbc->flip_pending); 733 692 734 693 trace_intel_fbc_nuke(fbc->state.plane); 735 694 ··· 756 715 fbc->no_fbc_reason = reason; 757 716 } 758 717 759 759 - static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915) 718 718 + static u64 intel_fbc_cfb_base_max(struct intel_display *display) 760 719 { 761 761 - if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) 720 720 + struct drm_i915_private *i915 = to_i915(display->drm); 721 721 + 722 722 + if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) 762 723 return BIT_ULL(28); 763 724 else 764 725 return BIT_ULL(32); 765 726 } 766 727 767 767 - static u64 intel_fbc_stolen_end(struct drm_i915_private *i915) 728 728 + static u64 intel_fbc_stolen_end(struct intel_display *display) 768 729 { 730 730 + struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); 769 731 u64 end; 770 732 771 733 /* The FBC hardware for BDW/SKL doesn't have access to the stolen ··· 776 732 * If we enable FBC using a CFB on that memory range we'll get FIFO 777 733 * underruns, even if that range is not reserved by the BIOS. */ 778 734 if (IS_BROADWELL(i915) || 779 779 - (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915))) 735 735 + (DISPLAY_VER(display) == 9 && !IS_BROXTON(i915))) 780 736 end = i915_gem_stolen_area_size(i915) - 8 * 1024 * 1024; 781 737 else 782 738 end = U64_MAX; 783 739 784 784 - return min(end, intel_fbc_cfb_base_max(i915)); 740 740 + return min(end, intel_fbc_cfb_base_max(display)); 785 741 } 786 742 787 743 static int intel_fbc_min_limit(const struct intel_plane_state *plane_state) ··· 789 745 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1; 790 746 } 791 747 792 792 - static int intel_fbc_max_limit(struct drm_i915_private *i915) 748 748 + static int intel_fbc_max_limit(struct intel_display *display) 793 749 { 750 750 + struct drm_i915_private *i915 = to_i915(display->drm); 751 751 + 794 752 /* WaFbcOnly1to1Ratio:ctg */ 795 753 if (IS_G4X(i915)) 796 754 return 1; ··· 807 761 static int find_compression_limit(struct intel_fbc *fbc, 808 762 unsigned int size, int min_limit) 809 763 { 810 810 - struct drm_i915_private *i915 = fbc->i915; 811 811 - u64 end = intel_fbc_stolen_end(i915); 764 764 + struct intel_display *display = fbc->display; 765 765 + struct drm_i915_private *i915 = to_i915(display->drm); 766 766 + u64 end = intel_fbc_stolen_end(display); 812 767 int ret, limit = min_limit; 813 768 814 769 size /= limit; ··· 820 773 if (ret == 0) 821 774 return limit; 822 775 823 823 - for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) { 776 776 + for (; limit <= intel_fbc_max_limit(display); limit <<= 1) { 824 777 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb, 825 778 size >>= 1, 4096, 0, end); 826 779 if (ret == 0) ··· 833 786 static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, 834 787 unsigned int size, int min_limit) 835 788 { 836 836 - struct drm_i915_private *i915 = fbc->i915; 789 789 + struct intel_display *display = fbc->display; 790 790 + struct drm_i915_private *i915 = to_i915(display->drm); 837 791 int ret; 838 792 839 839 - drm_WARN_ON(&i915->drm, 793 793 + drm_WARN_ON(display->drm, 840 794 i915_gem_stolen_node_allocated(&fbc->compressed_fb)); 841 841 - drm_WARN_ON(&i915->drm, 795 795 + drm_WARN_ON(display->drm, 842 796 i915_gem_stolen_node_allocated(&fbc->compressed_llb)); 843 797 844 844 - if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) { 798 798 + if (DISPLAY_VER(display) < 5 && !IS_G4X(i915)) { 845 799 ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb, 846 800 4096, 4096); 847 801 if (ret) ··· 853 805 if (!ret) 854 806 goto err_llb; 855 807 else if (ret > min_limit) 856 856 - drm_info_once(&i915->drm, 808 808 + drm_info_once(display->drm, 857 809 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); 858 810 859 811 fbc->limit = ret; 860 812 861 861 - drm_dbg_kms(&i915->drm, 813 813 + drm_dbg_kms(display->drm, 862 814 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n", 863 815 i915_gem_stolen_node_size(&fbc->compressed_fb), fbc->limit); 864 816 return 0; ··· 868 820 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb); 869 821 err: 870 822 if (i915_gem_stolen_initialized(i915)) 871 871 - drm_info_once(&i915->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 823 823 + drm_info_once(display->drm, 824 824 + "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 872 825 return -ENOSPC; 873 826 } 874 827 ··· 880 831 881 832 static void intel_fbc_program_workarounds(struct intel_fbc *fbc) 882 833 { 883 883 - struct drm_i915_private *i915 = fbc->i915; 834 834 + struct intel_display *display = fbc->display; 835 835 + struct drm_i915_private *i915 = to_i915(display->drm); 884 836 885 837 if (IS_SKYLAKE(i915) || IS_BROXTON(i915)) { 886 838 /* 887 839 * WaFbcHighMemBwCorruptionAvoidance:skl,bxt 888 840 * Display WA #0883: skl,bxt 889 841 */ 890 890 - intel_de_rmw(i915, ILK_DPFC_CHICKEN(fbc->id), 842 842 + intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 891 843 0, DPFC_DISABLE_DUMMY0); 892 844 } 893 845 ··· 898 848 * WaFbcNukeOnHostModify:skl,kbl,cfl 899 849 * Display WA #0873: skl,kbl,cfl 900 850 */ 901 901 - intel_de_rmw(i915, ILK_DPFC_CHICKEN(fbc->id), 851 851 + intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 902 852 0, DPFC_NUKE_ON_ANY_MODIFICATION); 903 853 } 904 854 905 855 /* Wa_1409120013:icl,jsl,tgl,dg1 */ 906 906 - if (IS_DISPLAY_VER(i915, 11, 12)) 907 907 - intel_de_rmw(i915, ILK_DPFC_CHICKEN(fbc->id), 856 856 + if (IS_DISPLAY_VER(display, 11, 12)) 857 857 + intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 908 858 0, DPFC_CHICKEN_COMP_DUMMY_PIXEL); 909 859 910 860 /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */ 911 911 - if (DISPLAY_VER(i915) >= 11 && !IS_DG2(i915)) 912 912 - intel_de_rmw(i915, ILK_DPFC_CHICKEN(fbc->id), 861 861 + if (DISPLAY_VER(display) >= 11 && !IS_DG2(i915)) 862 862 + intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 913 863 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION); 914 864 } 915 865 916 866 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) 917 867 { 918 918 - struct drm_i915_private *i915 = fbc->i915; 868 868 + struct intel_display *display = fbc->display; 869 869 + struct drm_i915_private *i915 = to_i915(display->drm); 919 870 920 871 if (WARN_ON(intel_fbc_hw_is_active(fbc))) 921 872 return; ··· 927 876 i915_gem_stolen_remove_node(i915, &fbc->compressed_fb); 928 877 } 929 878 930 930 - void intel_fbc_cleanup(struct drm_i915_private *i915) 879 879 + void intel_fbc_cleanup(struct intel_display *display) 931 880 { 932 881 struct intel_fbc *fbc; 933 882 enum intel_fbc_id fbc_id; 934 883 935 935 - for_each_intel_fbc(i915, fbc, fbc_id) { 884 884 + for_each_intel_fbc(display, fbc, fbc_id) { 936 885 mutex_lock(&fbc->lock); 937 886 __intel_fbc_cleanup_cfb(fbc); 938 887 mutex_unlock(&fbc->lock); ··· 984 933 985 934 static bool stride_is_valid(const struct intel_plane_state *plane_state) 986 935 { 987 987 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 936 936 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 937 937 + struct drm_i915_private *i915 = to_i915(display->drm); 988 938 989 989 - if (DISPLAY_VER(i915) >= 11) 939 939 + if (DISPLAY_VER(display) >= 11) 990 940 return icl_fbc_stride_is_valid(plane_state); 991 991 - else if (DISPLAY_VER(i915) >= 9) 941 941 + else if (DISPLAY_VER(display) >= 9) 992 942 return skl_fbc_stride_is_valid(plane_state); 993 993 - else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) 943 943 + else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) 994 944 return g4x_fbc_stride_is_valid(plane_state); 995 995 - else if (DISPLAY_VER(i915) == 4) 945 945 + else if (DISPLAY_VER(display) == 4) 996 946 return i965_fbc_stride_is_valid(plane_state); 997 947 else 998 948 return i8xx_fbc_stride_is_valid(plane_state); ··· 1001 949 1002 950 static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1003 951 { 1004 1004 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 952 952 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1005 953 const struct drm_framebuffer *fb = plane_state->hw.fb; 1006 954 1007 955 switch (fb->format->format) { ··· 1011 959 case DRM_FORMAT_XRGB1555: 1012 960 case DRM_FORMAT_RGB565: 1013 961 /* 16bpp not supported on gen2 */ 1014 1014 - if (DISPLAY_VER(i915) == 2) 962 962 + if (DISPLAY_VER(display) == 2) 1015 963 return false; 1016 964 return true; 1017 965 default: ··· 1021 969 1022 970 static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1023 971 { 1024 1024 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 972 972 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 973 973 + struct drm_i915_private *i915 = to_i915(display->drm); 1025 974 const struct drm_framebuffer *fb = plane_state->hw.fb; 1026 975 1027 976 switch (fb->format->format) { ··· 1057 1004 1058 1005 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) 1059 1006 { 1060 1060 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1007 1007 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1008 1008 + struct drm_i915_private *i915 = to_i915(display->drm); 1061 1009 1062 1062 - if (DISPLAY_VER(i915) >= 20) 1010 1010 + if (DISPLAY_VER(display) >= 20) 1063 1011 return lnl_fbc_pixel_format_is_valid(plane_state); 1064 1064 - else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) 1012 1012 + else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) 1065 1013 return g4x_fbc_pixel_format_is_valid(plane_state); 1066 1014 else 1067 1015 return i8xx_fbc_pixel_format_is_valid(plane_state); ··· 1092 1038 1093 1039 static bool rotation_is_valid(const struct intel_plane_state *plane_state) 1094 1040 { 1095 1095 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1041 1041 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1042 1042 + struct drm_i915_private *i915 = to_i915(display->drm); 1096 1043 1097 1097 - if (DISPLAY_VER(i915) >= 9) 1044 1044 + if (DISPLAY_VER(display) >= 9) 1098 1045 return skl_fbc_rotation_is_valid(plane_state); 1099 1099 - else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) 1046 1046 + else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) 1100 1047 return g4x_fbc_rotation_is_valid(plane_state); 1101 1048 else 1102 1049 return i8xx_fbc_rotation_is_valid(plane_state); 1050 1050 + } 1051 1051 + 1052 1052 + static void intel_fbc_max_surface_size(struct intel_display *display, 1053 1053 + unsigned int *w, unsigned int *h) 1054 1054 + { 1055 1055 + struct drm_i915_private *i915 = to_i915(display->drm); 1056 1056 + 1057 1057 + if (DISPLAY_VER(display) >= 11) { 1058 1058 + *w = 8192; 1059 1059 + *h = 4096; 1060 1060 + } else if (DISPLAY_VER(display) >= 10) { 1061 1061 + *w = 5120; 1062 1062 + *h = 4096; 1063 1063 + } else if (DISPLAY_VER(display) >= 7) { 1064 1064 + *w = 4096; 1065 1065 + *h = 4096; 1066 1066 + } else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) { 1067 1067 + *w = 4096; 1068 1068 + *h = 2048; 1069 1069 + } else { 1070 1070 + *w = 2048; 1071 1071 + *h = 1536; 1072 1072 + } 1103 1073 } 1104 1074 1105 1075 /* ··· 1132 1054 * the X and Y offset registers. That's why we include the src x/y offsets 1133 1055 * instead of just looking at the plane size. 1134 1056 */ 1135 1135 - static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state) 1057 1057 + static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state) 1136 1058 { 1137 1137 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1059 1059 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1138 1060 unsigned int effective_w, effective_h, max_w, max_h; 1139 1061 1140 1140 - if (DISPLAY_VER(i915) >= 11) { 1141 1141 - max_w = 8192; 1142 1142 - max_h = 4096; 1143 1143 - } else if (DISPLAY_VER(i915) >= 10) { 1144 1144 - max_w = 5120; 1145 1145 - max_h = 4096; 1146 1146 - } else if (DISPLAY_VER(i915) >= 7) { 1147 1147 - max_w = 4096; 1148 1148 - max_h = 4096; 1149 1149 - } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) { 1150 1150 - max_w = 4096; 1151 1151 - max_h = 2048; 1152 1152 - } else { 1153 1153 - max_w = 2048; 1154 1154 - max_h = 1536; 1155 1155 - } 1062 1062 + intel_fbc_max_surface_size(display, &max_w, &max_h); 1156 1063 1157 1064 effective_w = plane_state->view.color_plane[0].x + 1158 1065 (drm_rect_width(&plane_state->uapi.src) >> 16); ··· 1147 1084 return effective_w <= max_w && effective_h <= max_h; 1148 1085 } 1149 1086 1087 1087 + static void intel_fbc_max_plane_size(struct intel_display *display, 1088 1088 + unsigned int *w, unsigned int *h) 1089 1089 + { 1090 1090 + struct drm_i915_private *i915 = to_i915(display->drm); 1091 1091 + 1092 1092 + if (DISPLAY_VER(display) >= 10) { 1093 1093 + *w = 5120; 1094 1094 + *h = 4096; 1095 1095 + } else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(i915)) { 1096 1096 + *w = 4096; 1097 1097 + *h = 4096; 1098 1098 + } else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) { 1099 1099 + *w = 4096; 1100 1100 + *h = 2048; 1101 1101 + } else { 1102 1102 + *w = 2048; 1103 1103 + *h = 1536; 1104 1104 + } 1105 1105 + } 1106 1106 + 1150 1107 static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state) 1151 1108 { 1152 1152 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1109 1109 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1153 1110 unsigned int w, h, max_w, max_h; 1154 1111 1155 1155 - if (DISPLAY_VER(i915) >= 10) { 1156 1156 - max_w = 5120; 1157 1157 - max_h = 4096; 1158 1158 - } else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) { 1159 1159 - max_w = 4096; 1160 1160 - max_h = 4096; 1161 1161 - } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) { 1162 1162 - max_w = 4096; 1163 1163 - max_h = 2048; 1164 1164 - } else { 1165 1165 - max_w = 2048; 1166 1166 - max_h = 1536; 1167 1167 - } 1112 1112 + intel_fbc_max_plane_size(display, &max_w, &max_h); 1168 1113 1169 1114 w = drm_rect_width(&plane_state->uapi.src) >> 16; 1170 1115 h = drm_rect_height(&plane_state->uapi.src) >> 16; ··· 1194 1123 1195 1124 static bool tiling_is_valid(const struct intel_plane_state *plane_state) 1196 1125 { 1197 1197 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1126 1126 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1198 1127 1199 1199 - if (DISPLAY_VER(i915) >= 9) 1128 1128 + if (DISPLAY_VER(display) >= 9) 1200 1129 return skl_fbc_tiling_valid(plane_state); 1201 1130 else 1202 1131 return i8xx_fbc_tiling_valid(plane_state); ··· 1206 1135 struct intel_crtc *crtc, 1207 1136 struct intel_plane *plane) 1208 1137 { 1209 1209 - struct drm_i915_private *i915 = to_i915(state->base.dev); 1138 1138 + struct intel_display *display = to_intel_display(state->base.dev); 1210 1139 const struct intel_crtc_state *crtc_state = 1211 1140 intel_atomic_get_new_crtc_state(state, crtc); 1212 1141 const struct intel_plane_state *plane_state = ··· 1224 1153 1225 1154 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state); 1226 1155 1227 1227 - drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE && 1228 1228 - !intel_gt_support_legacy_fencing(to_gt(i915))); 1156 1156 + drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE && 1157 1157 + !intel_fbc_has_fences(display)); 1229 1158 1230 1159 if (plane_state->flags & PLANE_HAS_FENCE) 1231 1160 fbc_state->fence_id = i915_vma_fence_id(plane_state->ggtt_vma); ··· 1239 1168 1240 1169 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) 1241 1170 { 1242 1242 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1171 1171 + struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1243 1172 1244 1173 /* 1245 1174 * The use of a CPU fence is one of two ways to detect writes by the ··· 1253 1182 * so have no fence associated with it) due to aperture constraints 1254 1183 * at the time of pinning. 1255 1184 */ 1256 1256 - return DISPLAY_VER(i915) >= 9 || 1185 1185 + return DISPLAY_VER(display) >= 9 || 1257 1186 (plane_state->flags & PLANE_HAS_FENCE && 1258 1187 i915_vma_fence_id(plane_state->ggtt_vma) != -1); 1259 1188 } ··· 1278 1207 static int intel_fbc_check_plane(struct intel_atomic_state *state, 1279 1208 struct intel_plane *plane) 1280 1209 { 1281 1281 - struct drm_i915_private *i915 = to_i915(state->base.dev); 1210 1210 + struct intel_display *display = to_intel_display(state->base.dev); 1211 1211 + struct drm_i915_private *i915 = to_i915(display->drm); 1282 1212 struct intel_plane_state *plane_state = 1283 1213 intel_atomic_get_new_plane_state(state, plane); 1284 1214 const struct drm_framebuffer *fb = plane_state->hw.fb; ··· 1300 1228 return 0; 1301 1229 } 1302 1230 1303 1303 - if (!i915->display.params.enable_fbc) { 1231 1231 + if (!display->params.enable_fbc) { 1304 1232 plane_state->no_fbc_reason = "disabled per module param or by default"; 1305 1233 return 0; 1306 1234 } ··· 1338 1266 * Recommendation is to keep this combination disabled 1339 1267 * Bspec: 50422 HSD: 14010260002 1340 1268 */ 1341 1341 - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update && 1269 1269 + if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && 1342 1270 !crtc_state->has_panel_replay) { 1343 1271 plane_state->no_fbc_reason = "PSR2 enabled"; 1344 1272 return 0; 1345 1273 } 1346 1274 1347 1275 /* Wa_14016291713 */ 1348 1348 - if ((IS_DISPLAY_VER(i915, 12, 13) || 1276 1276 + if ((IS_DISPLAY_VER(display, 12, 13) || 1349 1277 IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) && 1350 1278 crtc_state->has_psr && !crtc_state->has_panel_replay) { 1351 1279 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; ··· 1372 1300 return 0; 1373 1301 } 1374 1302 1375 1375 - if (DISPLAY_VER(i915) < 20 && 1303 1303 + if (DISPLAY_VER(display) < 20 && 1376 1304 plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && 1377 1305 fb->format->has_alpha) { 1378 1306 plane_state->no_fbc_reason = "per-pixel alpha not supported"; ··· 1384 1312 return 0; 1385 1313 } 1386 1314 1387 1387 - if (!intel_fbc_hw_tracking_covers_screen(plane_state)) { 1315 1315 + if (!intel_fbc_surface_size_ok(plane_state)) { 1388 1316 plane_state->no_fbc_reason = "surface size too big"; 1389 1317 return 0; 1390 1318 } ··· 1394 1322 * having a Y offset that isn't divisible by 4 causes FIFO underrun 1395 1323 * and screen flicker. 1396 1324 */ 1397 1397 - if (DISPLAY_VER(i915) >= 9 && 1325 1325 + if (DISPLAY_VER(display) >= 9 && 1398 1326 plane_state->view.color_plane[0].y & 3) { 1399 1327 plane_state->no_fbc_reason = "plane start Y offset misaligned"; 1400 1328 return 0; 1401 1329 } 1402 1330 1403 1331 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ 1404 1404 - if (DISPLAY_VER(i915) >= 11 && 1332 1332 + if (DISPLAY_VER(display) >= 11 && 1405 1333 (plane_state->view.color_plane[0].y + 1406 1334 (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) { 1407 1335 plane_state->no_fbc_reason = "plane end Y offset misaligned"; ··· 1477 1405 struct intel_crtc *crtc, 1478 1406 struct intel_plane *plane) 1479 1407 { 1480 1480 - struct drm_i915_private *i915 = to_i915(state->base.dev); 1408 1408 + struct intel_display *display = to_intel_display(state->base.dev); 1481 1409 struct intel_fbc *fbc = plane->fbc; 1482 1410 bool need_vblank_wait = false; 1483 1411 ··· 1503 1431 * and skipping the extra vblank wait before the plane update 1504 1432 * if at least one frame has already passed. 1505 1433 */ 1506 1506 - if (fbc->activated && DISPLAY_VER(i915) >= 10) 1434 1434 + if (fbc->activated && DISPLAY_VER(display) >= 10) 1507 1435 need_vblank_wait = true; 1508 1436 fbc->activated = false; 1509 1437 ··· 1537 1465 1538 1466 static void __intel_fbc_disable(struct intel_fbc *fbc) 1539 1467 { 1540 1540 - struct drm_i915_private *i915 = fbc->i915; 1468 1468 + struct intel_display *display = fbc->display; 1541 1469 struct intel_plane *plane = fbc->state.plane; 1542 1470 1543 1471 lockdep_assert_held(&fbc->lock); 1544 1544 - drm_WARN_ON(&i915->drm, fbc->active); 1472 1472 + drm_WARN_ON(display->drm, fbc->active); 1545 1473 1546 1546 - drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n", 1474 1474 + drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n", 1547 1475 plane->base.base.id, plane->base.name); 1548 1476 1549 1477 __intel_fbc_cleanup_cfb(fbc); ··· 1620 1548 struct intel_fbc *fbc; 1621 1549 enum intel_fbc_id fbc_id; 1622 1550 1623 1623 - for_each_intel_fbc(i915, fbc, fbc_id) 1551 1551 + for_each_intel_fbc(&i915->display, fbc, fbc_id) 1624 1552 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin); 1625 1553 1626 1554 } ··· 1659 1587 struct intel_fbc *fbc; 1660 1588 enum intel_fbc_id fbc_id; 1661 1589 1662 1662 - for_each_intel_fbc(i915, fbc, fbc_id) 1590 1590 + for_each_intel_fbc(&i915->display, fbc, fbc_id) 1663 1591 __intel_fbc_flush(fbc, frontbuffer_bits, origin); 1664 1592 } 1665 1593 ··· 1684 1612 struct intel_crtc *crtc, 1685 1613 struct intel_plane *plane) 1686 1614 { 1687 1687 - struct drm_i915_private *i915 = to_i915(state->base.dev); 1615 1615 + struct intel_display *display = to_intel_display(state->base.dev); 1688 1616 const struct intel_plane_state *plane_state = 1689 1617 intel_atomic_get_new_plane_state(state, plane); 1690 1618 struct intel_fbc *fbc = plane->fbc; ··· 1703 1631 __intel_fbc_disable(fbc); 1704 1632 } 1705 1633 1706 1706 - drm_WARN_ON(&i915->drm, fbc->active); 1634 1634 + drm_WARN_ON(display->drm, fbc->active); 1707 1635 1708 1636 fbc->no_fbc_reason = plane_state->no_fbc_reason; 1709 1637 if (fbc->no_fbc_reason) ··· 1725 1653 return; 1726 1654 } 1727 1655 1728 1728 - drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n", 1656 1656 + drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n", 1729 1657 plane->base.base.id, plane->base.name); 1730 1658 fbc->no_fbc_reason = "FBC enabled but not active yet\n"; 1731 1659 ··· 1743 1671 */ 1744 1672 void intel_fbc_disable(struct intel_crtc *crtc) 1745 1673 { 1746 1746 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1674 1674 + struct intel_display *display = to_intel_display(crtc->base.dev); 1747 1675 struct intel_plane *plane; 1748 1676 1749 1749 - for_each_intel_plane(&i915->drm, plane) { 1677 1677 + for_each_intel_plane(display->drm, plane) { 1750 1678 struct intel_fbc *fbc = plane->fbc; 1751 1679 1752 1680 if (!fbc || plane->pipe != crtc->pipe) ··· 1791 1719 static void intel_fbc_underrun_work_fn(struct work_struct *work) 1792 1720 { 1793 1721 struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work); 1794 1794 - struct drm_i915_private *i915 = fbc->i915; 1722 1722 + struct intel_display *display = fbc->display; 1723 1723 + struct drm_i915_private *i915 = to_i915(display->drm); 1795 1724 1796 1725 mutex_lock(&fbc->lock); 1797 1726 ··· 1800 1727 if (fbc->underrun_detected || !fbc->state.plane) 1801 1728 goto out; 1802 1729 1803 1803 - drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n"); 1730 1730 + drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n"); 1804 1731 fbc->underrun_detected = true; 1805 1732 1806 1733 intel_fbc_deactivate(fbc, "FIFO underrun"); ··· 1813 1740 1814 1741 static void __intel_fbc_reset_underrun(struct intel_fbc *fbc) 1815 1742 { 1816 1816 - struct drm_i915_private *i915 = fbc->i915; 1743 1743 + struct intel_display *display = fbc->display; 1817 1744 1818 1745 cancel_work_sync(&fbc->underrun_work); 1819 1746 1820 1747 mutex_lock(&fbc->lock); 1821 1748 1822 1749 if (fbc->underrun_detected) { 1823 1823 - drm_dbg_kms(&i915->drm, 1750 1750 + drm_dbg_kms(display->drm, 1824 1751 "Re-allowing FBC after fifo underrun\n"); 1825 1752 fbc->no_fbc_reason = "FIFO underrun cleared"; 1826 1753 } ··· 1831 1758 1832 1759 /* 1833 1760 * intel_fbc_reset_underrun - reset FBC fifo underrun status. 1834 1834 - * @i915: the i915 device 1761 1761 + * @display: display 1835 1762 * 1836 1763 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we 1837 1764 * want to re-enable FBC after an underrun to increase test coverage. 1838 1765 */ 1839 1839 - void intel_fbc_reset_underrun(struct drm_i915_private *i915) 1766 1766 + void intel_fbc_reset_underrun(struct intel_display *display) 1840 1767 { 1841 1768 struct intel_fbc *fbc; 1842 1769 enum intel_fbc_id fbc_id; 1843 1770 1844 1844 - for_each_intel_fbc(i915, fbc, fbc_id) 1771 1771 + for_each_intel_fbc(display, fbc, fbc_id) 1845 1772 __intel_fbc_reset_underrun(fbc); 1846 1773 } 1847 1774 1848 1775 static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc) 1849 1776 { 1777 1777 + struct drm_i915_private *i915 = to_i915(fbc->display->drm); 1778 1778 + 1850 1779 /* 1851 1780 * There's no guarantee that underrun_detected won't be set to true 1852 1781 * right after this check and before the work is scheduled, but that's ··· 1860 1785 if (READ_ONCE(fbc->underrun_detected)) 1861 1786 return; 1862 1787 1863 1863 - queue_work(fbc->i915->unordered_wq, &fbc->underrun_work); 1788 1788 + queue_work(i915->unordered_wq, &fbc->underrun_work); 1864 1789 } 1865 1790 1866 1791 /** 1867 1792 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun 1868 1868 - * @i915: i915 device 1793 1793 + * @display: display 1869 1794 * 1870 1795 * Without FBC, most underruns are harmless and don't really cause too many 1871 1796 * problems, except for an annoying message on dmesg. With FBC, underruns can ··· 1877 1802 * 1878 1803 * This function is called from the IRQ handler. 1879 1804 */ 1880 1880 - void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915) 1805 1805 + void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display) 1881 1806 { 1882 1807 struct intel_fbc *fbc; 1883 1808 enum intel_fbc_id fbc_id; 1884 1809 1885 1885 - for_each_intel_fbc(i915, fbc, fbc_id) 1810 1810 + for_each_intel_fbc(display, fbc, fbc_id) 1886 1811 __intel_fbc_handle_fifo_underrun_irq(fbc); 1887 1812 } 1888 1813 ··· 1895 1820 * space to change the value during runtime without sanitizing it again. IGT 1896 1821 * relies on being able to change i915.enable_fbc at runtime. 1897 1822 */ 1898 1898 - static int intel_sanitize_fbc_option(struct drm_i915_private *i915) 1823 1823 + static int intel_sanitize_fbc_option(struct intel_display *display) 1899 1824 { 1900 1900 - if (i915->display.params.enable_fbc >= 0) 1901 1901 - return !!i915->display.params.enable_fbc; 1825 1825 + struct drm_i915_private *i915 = to_i915(display->drm); 1902 1826 1903 1903 - if (!HAS_FBC(i915)) 1827 1827 + if (display->params.enable_fbc >= 0) 1828 1828 + return !!display->params.enable_fbc; 1829 1829 + 1830 1830 + if (!HAS_FBC(display)) 1904 1831 return 0; 1905 1832 1906 1906 - if (IS_BROADWELL(i915) || DISPLAY_VER(i915) >= 9) 1833 1833 + if (IS_BROADWELL(i915) || DISPLAY_VER(display) >= 9) 1907 1834 return 1; 1908 1835 1909 1836 return 0; ··· 1916 1839 plane->fbc = fbc; 1917 1840 } 1918 1841 1919 1919 - static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915, 1842 1842 + static struct intel_fbc *intel_fbc_create(struct intel_display *display, 1920 1843 enum intel_fbc_id fbc_id) 1921 1844 { 1845 1845 + struct drm_i915_private *i915 = to_i915(display->drm); 1922 1846 struct intel_fbc *fbc; 1923 1847 1924 1848 fbc = kzalloc(sizeof(*fbc), GFP_KERNEL); ··· 1927 1849 return NULL; 1928 1850 1929 1851 fbc->id = fbc_id; 1930 1930 - fbc->i915 = i915; 1852 1852 + fbc->display = display; 1931 1853 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); 1932 1854 mutex_init(&fbc->lock); 1933 1855 1934 1934 - if (DISPLAY_VER(i915) >= 7) 1856 1856 + if (DISPLAY_VER(display) >= 7) 1935 1857 fbc->funcs = &ivb_fbc_funcs; 1936 1936 - else if (DISPLAY_VER(i915) == 6) 1858 1858 + else if (DISPLAY_VER(display) == 6) 1937 1859 fbc->funcs = &snb_fbc_funcs; 1938 1938 - else if (DISPLAY_VER(i915) == 5) 1860 1860 + else if (DISPLAY_VER(display) == 5) 1939 1861 fbc->funcs = &ilk_fbc_funcs; 1940 1862 else if (IS_G4X(i915)) 1941 1863 fbc->funcs = &g4x_fbc_funcs; 1942 1942 - else if (DISPLAY_VER(i915) == 4) 1864 1864 + else if (DISPLAY_VER(display) == 4) 1943 1865 fbc->funcs = &i965_fbc_funcs; 1944 1866 else 1945 1867 fbc->funcs = &i8xx_fbc_funcs; ··· 1949 1871 1950 1872 /** 1951 1873 * intel_fbc_init - Initialize FBC 1952 1952 - * @i915: the i915 device 1874 1874 + * @display: display 1953 1875 * 1954 1876 * This function might be called during PM init process. 1955 1877 */ 1956 1956 - void intel_fbc_init(struct drm_i915_private *i915) 1878 1878 + void intel_fbc_init(struct intel_display *display) 1957 1879 { 1958 1880 enum intel_fbc_id fbc_id; 1959 1881 1960 1960 - i915->display.params.enable_fbc = intel_sanitize_fbc_option(i915); 1961 1961 - drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n", 1962 1962 - i915->display.params.enable_fbc); 1882 1882 + display->params.enable_fbc = intel_sanitize_fbc_option(display); 1883 1883 + drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n", 1884 1884 + display->params.enable_fbc); 1963 1885 1964 1964 - for_each_fbc_id(i915, fbc_id) 1965 1965 - i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id); 1886 1886 + for_each_fbc_id(display, fbc_id) 1887 1887 + display->fbc[fbc_id] = intel_fbc_create(display, fbc_id); 1966 1888 } 1967 1889 1968 1890 /** 1969 1891 * intel_fbc_sanitize - Sanitize FBC 1970 1970 - * @i915: the i915 device 1892 1892 + * @display: display 1971 1893 * 1972 1894 * Make sure FBC is initially disabled since we have no 1973 1895 * idea eg. into which parts of stolen it might be scribbling 1974 1896 * into. 1975 1897 */ 1976 1976 - void intel_fbc_sanitize(struct drm_i915_private *i915) 1898 1898 + void intel_fbc_sanitize(struct intel_display *display) 1977 1899 { 1978 1900 struct intel_fbc *fbc; 1979 1901 enum intel_fbc_id fbc_id; 1980 1902 1981 1981 - for_each_intel_fbc(i915, fbc, fbc_id) { 1903 1903 + for_each_intel_fbc(display, fbc, fbc_id) { 1982 1904 if (intel_fbc_hw_is_active(fbc)) 1983 1905 intel_fbc_hw_deactivate(fbc); 1984 1906 } ··· 1987 1909 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused) 1988 1910 { 1989 1911 struct intel_fbc *fbc = m->private; 1990 1990 - struct drm_i915_private *i915 = fbc->i915; 1912 1912 + struct intel_display *display = fbc->display; 1913 1913 + struct drm_i915_private *i915 = to_i915(display->drm); 1991 1914 struct intel_plane *plane; 1992 1915 intel_wakeref_t wakeref; 1993 1916 1994 1994 - drm_modeset_lock_all(&i915->drm); 1917 1917 + drm_modeset_lock_all(display->drm); 1995 1918 1996 1919 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1997 1920 mutex_lock(&fbc->lock); ··· 2005 1926 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); 2006 1927 } 2007 1928 2008 2008 - for_each_intel_plane(&i915->drm, plane) { 1929 1929 + for_each_intel_plane(display->drm, plane) { 2009 1930 const struct intel_plane_state *plane_state = 2010 1931 to_intel_plane_state(plane->base.state); 2011 1932 ··· 2021 1942 mutex_unlock(&fbc->lock); 2022 1943 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 2023 1944 2024 2024 - drm_modeset_unlock_all(&i915->drm); 1945 1945 + drm_modeset_unlock_all(display->drm); 2025 1946 2026 1947 return 0; 2027 1948 } ··· 2078 1999 } 2079 2000 2080 2001 /* FIXME: remove this once igt is on board with per-crtc stuff */ 2081 2081 - void intel_fbc_debugfs_register(struct drm_i915_private *i915) 2002 2002 + void intel_fbc_debugfs_register(struct intel_display *display) 2082 2003 { 2083 2083 - struct drm_minor *minor = i915->drm.primary; 2004 2004 + struct drm_minor *minor = display->drm->primary; 2084 2005 struct intel_fbc *fbc; 2085 2006 2086 2086 - fbc = i915->display.fbc[INTEL_FBC_A]; 2007 2007 + fbc = display->fbc[INTEL_FBC_A]; 2087 2008 if (fbc) 2088 2009 intel_fbc_debugfs_add(fbc, minor->debugfs_root); 2089 2010 }

+7 -6

drivers/gpu/drm/i915/display/intel_fbc.h

reviewed

··· 13 13 struct intel_atomic_state; 14 14 struct intel_crtc; 15 15 struct intel_crtc_state; 16 16 + struct intel_display; 16 17 struct intel_fbc; 17 18 struct intel_plane; 18 19 struct intel_plane_state; ··· 32 31 struct intel_crtc *crtc); 33 32 void intel_fbc_post_update(struct intel_atomic_state *state, 34 33 struct intel_crtc *crtc); 35 35 - void intel_fbc_init(struct drm_i915_private *dev_priv); 36 36 - void intel_fbc_cleanup(struct drm_i915_private *dev_priv); 37 37 - void intel_fbc_sanitize(struct drm_i915_private *dev_priv); 34 34 + void intel_fbc_init(struct intel_display *display); 35 35 + void intel_fbc_cleanup(struct intel_display *display); 36 36 + void intel_fbc_sanitize(struct intel_display *display); 38 37 void intel_fbc_update(struct intel_atomic_state *state, 39 38 struct intel_crtc *crtc); 40 39 void intel_fbc_disable(struct intel_crtc *crtc); ··· 44 43 void intel_fbc_flush(struct drm_i915_private *dev_priv, 45 44 unsigned int frontbuffer_bits, enum fb_op_origin origin); 46 45 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane); 47 47 - void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915); 48 48 - void intel_fbc_reset_underrun(struct drm_i915_private *i915); 46 46 + void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display); 47 47 + void intel_fbc_reset_underrun(struct intel_display *display); 49 48 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc); 50 50 - void intel_fbc_debugfs_register(struct drm_i915_private *i915); 49 49 + void intel_fbc_debugfs_register(struct intel_display *display); 51 50 52 51 #endif /* __INTEL_FBC_H__ */

+4 -2

drivers/gpu/drm/i915/display/intel_fdi.c

reviewed

··· 5 5 6 6 #include <linux/string_helpers.h> 7 7 8 8 + #include <drm/drm_fixed.h> 9 9 + 8 10 #include "i915_reg.h" 9 11 #include "intel_atomic.h" 10 12 #include "intel_crtc.h" ··· 306 304 bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state) 307 305 { 308 306 int pipe_bpp = min(crtc_state->pipe_bpp, 309 309 - to_bpp_int(crtc_state->max_link_bpp_x16)); 307 307 + fxp_q4_to_int(crtc_state->max_link_bpp_x16)); 310 308 311 309 pipe_bpp = rounddown(pipe_bpp, 2 * 3); 312 310 ··· 342 340 343 341 pipe_config->fdi_lanes = lane; 344 342 345 345 - intel_link_compute_m_n(to_bpp_x16(pipe_config->pipe_bpp), 343 343 + intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp), 346 344 lane, fdi_dotclock, 347 345 link_bw, 348 346 intel_dp_bw_fec_overhead(false),

+1 -1

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

reviewed

··· 440 440 drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); 441 441 } 442 442 443 443 - intel_fbc_handle_fifo_underrun_irq(dev_priv); 443 443 + intel_fbc_handle_fifo_underrun_irq(&dev_priv->display); 444 444 } 445 445 446 446 /**

+2 -2

drivers/gpu/drm/i915/display/intel_gmbus.c

reviewed

··· 478 478 /* 479 479 * HW spec says that 512Bytes in Burst read need special treatment. 480 480 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 481 481 - * an I2C slave, which supports such a lengthy burst read too for experiments. 481 481 + * an I2C target, which supports such a lengthy burst read too for experiments. 482 482 * 483 483 * So until things get clarified on HW support, to avoid the burst read length 484 484 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. ··· 701 701 702 702 /* Toggle the Software Clear Interrupt bit. This has the effect 703 703 * of resetting the GMBUS controller and so clearing the 704 704 - * BUS_ERROR raised by the slave's NAK. 704 704 + * BUS_ERROR raised by the target's NAK. 705 705 */ 706 706 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT); 707 707 intel_de_write_fw(i915, GMBUS1(i915), 0);

+6 -1

drivers/gpu/drm/i915/display/intel_hdcp.c

reviewed

··· 203 203 /* Is HDCP1.4 capable on Platform and Sink */ 204 204 bool intel_hdcp_get_capability(struct intel_connector *connector) 205 205 { 206 206 - struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 206 206 + struct intel_digital_port *dig_port; 207 207 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 208 208 bool capable = false; 209 209 u8 bksv[5]; 210 210 + 211 211 + if (!intel_attached_encoder(connector)) 212 212 + return capable; 213 213 + 214 214 + dig_port = intel_attached_dig_port(connector); 210 215 211 216 if (!shim) 212 217 return capable;

+3 -1

drivers/gpu/drm/i915/display/intel_link_bw.c

reviewed

··· 3 3 * Copyright © 2023 Intel Corporation 4 4 */ 5 5 6 6 + #include <drm/drm_fixed.h> 7 7 + 6 8 #include "i915_drv.h" 7 9 8 10 #include "intel_atomic.h" ··· 95 93 * is based on the pipe bpp value, set the actual link bpp 96 94 * limit here once the MST BW allocation is fixed. 97 95 */ 98 98 - link_bpp_x16 = to_bpp_x16(crtc_state->pipe_bpp); 96 96 + link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp); 99 97 100 98 if (link_bpp_x16 > max_bpp_x16) { 101 99 max_bpp_x16 = link_bpp_x16;

+3 -2

drivers/gpu/drm/i915/display/intel_lvds.c

reviewed

··· 838 838 */ 839 839 void intel_lvds_init(struct drm_i915_private *i915) 840 840 { 841 841 + struct intel_display *display = &i915->display; 841 842 struct intel_lvds_encoder *lvds_encoder; 842 843 struct intel_connector *connector; 843 844 const struct drm_edid *drm_edid; ··· 873 872 } 874 873 875 874 ddc_pin = GMBUS_PIN_PANEL; 876 876 - if (!intel_bios_is_lvds_present(i915, &ddc_pin)) { 875 875 + if (!intel_bios_is_lvds_present(display, &ddc_pin)) { 877 876 if ((lvds & LVDS_PORT_EN) == 0) { 878 877 drm_dbg_kms(&i915->drm, 879 878 "LVDS is not present in VBT\n"); ··· 967 966 } else { 968 967 drm_edid = ERR_PTR(-ENOENT); 969 968 } 970 970 - intel_bios_init_panel_late(i915, &connector->panel, NULL, 969 969 + intel_bios_init_panel_late(display, &connector->panel, NULL, 971 970 IS_ERR(drm_edid) ? NULL : drm_edid); 972 971 973 972 /* Try EDID first */

+1 -1

drivers/gpu/drm/i915/display/intel_modeset_setup.c

reviewed

··· 966 966 } 967 967 } 968 968 969 969 - intel_fbc_sanitize(i915); 969 969 + intel_fbc_sanitize(&i915->display); 970 970 971 971 intel_sanitize_plane_mapping(i915); 972 972

+160 -160

drivers/gpu/drm/i915/display/intel_opregion.c

reviewed

··· 252 252 #define OPREGION_SIZE (8 * 1024) 253 253 254 254 struct intel_opregion { 255 255 - struct drm_i915_private *i915; 255 255 + struct intel_display *display; 256 256 257 257 struct opregion_header *header; 258 258 struct opregion_acpi *acpi; ··· 268 268 struct notifier_block acpi_notifier; 269 269 }; 270 270 271 271 - static int check_swsci_function(struct drm_i915_private *i915, u32 function) 271 271 + static int check_swsci_function(struct intel_display *display, u32 function) 272 272 { 273 273 - struct intel_opregion *opregion = i915->display.opregion; 273 273 + struct intel_opregion *opregion = display->opregion; 274 274 struct opregion_swsci *swsci; 275 275 u32 main_function, sub_function; 276 276 ··· 300 300 return 0; 301 301 } 302 302 303 303 - static int swsci(struct drm_i915_private *dev_priv, 303 303 + static int swsci(struct intel_display *display, 304 304 u32 function, u32 parm, u32 *parm_out) 305 305 { 306 306 struct opregion_swsci *swsci; 307 307 - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 307 307 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 308 308 u32 scic, dslp; 309 309 u16 swsci_val; 310 310 int ret; 311 311 312 312 - ret = check_swsci_function(dev_priv, function); 312 312 + ret = check_swsci_function(display, function); 313 313 if (ret) 314 314 return ret; 315 315 316 316 - swsci = dev_priv->display.opregion->swsci; 316 316 + swsci = display->opregion->swsci; 317 317 318 318 /* Driver sleep timeout in ms. */ 319 319 dslp = swsci->dslp; ··· 331 331 /* The spec tells us to do this, but we are the only user... */ 332 332 scic = swsci->scic; 333 333 if (scic & SWSCI_SCIC_INDICATOR) { 334 334 - drm_dbg(&dev_priv->drm, "SWSCI request already in progress\n"); 334 334 + drm_dbg(display->drm, "SWSCI request already in progress\n"); 335 335 return -EBUSY; 336 336 } 337 337 ··· 355 355 /* Poll for the result. */ 356 356 #define C (((scic = swsci->scic) & SWSCI_SCIC_INDICATOR) == 0) 357 357 if (wait_for(C, dslp)) { 358 358 - drm_dbg(&dev_priv->drm, "SWSCI request timed out\n"); 358 358 + drm_dbg(display->drm, "SWSCI request timed out\n"); 359 359 return -ETIMEDOUT; 360 360 } 361 361 ··· 364 364 365 365 /* Note: scic == 0 is an error! */ 366 366 if (scic != SWSCI_SCIC_EXIT_STATUS_SUCCESS) { 367 367 - drm_dbg(&dev_priv->drm, "SWSCI request error %u\n", scic); 367 367 + drm_dbg(display->drm, "SWSCI request error %u\n", scic); 368 368 return -EIO; 369 369 } 370 370 ··· 381 381 #define DISPLAY_TYPE_EXTERNAL_FLAT_PANEL 2 382 382 #define DISPLAY_TYPE_INTERNAL_FLAT_PANEL 3 383 383 384 384 - int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 384 384 + int intel_opregion_notify_encoder(struct intel_encoder *encoder, 385 385 bool enable) 386 386 { 387 387 - struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 387 387 + struct intel_display *display = to_intel_display(encoder); 388 388 u32 parm = 0; 389 389 u32 type = 0; 390 390 u32 port; 391 391 int ret; 392 392 393 393 /* don't care about old stuff for now */ 394 394 - if (!HAS_DDI(dev_priv)) 394 394 + if (!HAS_DDI(display)) 395 395 return 0; 396 396 397 397 /* Avoid port out of bounds checks if SWSCI isn't there. */ 398 398 - ret = check_swsci_function(dev_priv, SWSCI_SBCB_DISPLAY_POWER_STATE); 398 398 + ret = check_swsci_function(display, SWSCI_SBCB_DISPLAY_POWER_STATE); 399 399 if (ret) 400 400 return ret; 401 401 402 402 - if (intel_encoder->type == INTEL_OUTPUT_DSI) 402 402 + if (encoder->type == INTEL_OUTPUT_DSI) 403 403 port = 0; 404 404 else 405 405 - port = intel_encoder->port; 405 405 + port = encoder->port; 406 406 407 407 if (port == PORT_E) { 408 408 port = 0; ··· 419 419 * number is out of bounds after mapping. 420 420 */ 421 421 if (port > 4) { 422 422 - drm_dbg_kms(&dev_priv->drm, 422 422 + drm_dbg_kms(display->drm, 423 423 "[ENCODER:%d:%s] port %c (index %u) out of bounds for display power state notification\n", 424 424 - intel_encoder->base.base.id, intel_encoder->base.name, 425 425 - port_name(intel_encoder->port), port); 424 424 + encoder->base.base.id, encoder->base.name, 425 425 + port_name(encoder->port), port); 426 426 return -EINVAL; 427 427 } 428 428 429 429 if (!enable) 430 430 parm |= 4 << 8; 431 431 432 432 - switch (intel_encoder->type) { 432 432 + switch (encoder->type) { 433 433 case INTEL_OUTPUT_ANALOG: 434 434 type = DISPLAY_TYPE_CRT; 435 435 break; ··· 444 444 type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL; 445 445 break; 446 446 default: 447 447 - drm_WARN_ONCE(&dev_priv->drm, 1, 447 447 + drm_WARN_ONCE(display->drm, 1, 448 448 "unsupported intel_encoder type %d\n", 449 449 - intel_encoder->type); 449 449 + encoder->type); 450 450 return -EINVAL; 451 451 } 452 452 453 453 parm |= type << (16 + port * 3); 454 454 455 455 - return swsci(dev_priv, SWSCI_SBCB_DISPLAY_POWER_STATE, parm, NULL); 455 455 + return swsci(display, SWSCI_SBCB_DISPLAY_POWER_STATE, parm, NULL); 456 456 } 457 457 458 458 static const struct { ··· 466 466 { PCI_D3cold, 0x04 }, 467 467 }; 468 468 469 469 - int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, 469 469 + int intel_opregion_notify_adapter(struct intel_display *display, 470 470 pci_power_t state) 471 471 { 472 472 int i; 473 473 474 474 - if (!HAS_DDI(dev_priv)) 474 474 + if (!HAS_DDI(display)) 475 475 return 0; 476 476 477 477 for (i = 0; i < ARRAY_SIZE(power_state_map); i++) { 478 478 if (state == power_state_map[i].pci_power_state) 479 479 - return swsci(dev_priv, SWSCI_SBCB_ADAPTER_POWER_STATE, 479 479 + return swsci(display, SWSCI_SBCB_ADAPTER_POWER_STATE, 480 480 power_state_map[i].parm, NULL); 481 481 } 482 482 483 483 return -EINVAL; 484 484 } 485 485 486 486 - static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp) 486 486 + static u32 asle_set_backlight(struct intel_display *display, u32 bclp) 487 487 { 488 488 struct intel_connector *connector; 489 489 struct drm_connector_list_iter conn_iter; 490 490 - struct opregion_asle *asle = dev_priv->display.opregion->asle; 490 490 + struct opregion_asle *asle = display->opregion->asle; 491 491 492 492 - drm_dbg(&dev_priv->drm, "bclp = 0x%08x\n", bclp); 492 492 + drm_dbg(display->drm, "bclp = 0x%08x\n", bclp); 493 493 494 494 if (acpi_video_get_backlight_type() == acpi_backlight_native) { 495 495 - drm_dbg_kms(&dev_priv->drm, 495 495 + drm_dbg_kms(display->drm, 496 496 "opregion backlight request ignored\n"); 497 497 return 0; 498 498 } ··· 504 504 if (bclp > 255) 505 505 return ASLC_BACKLIGHT_FAILED; 506 506 507 507 - drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, NULL); 507 507 + drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); 508 508 509 509 /* 510 510 * Update backlight on all connectors that support backlight (usually 511 511 * only one). 512 512 */ 513 513 - drm_dbg_kms(&dev_priv->drm, "updating opregion backlight %d/255\n", 513 513 + drm_dbg_kms(display->drm, "updating opregion backlight %d/255\n", 514 514 bclp); 515 515 - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 515 515 + drm_connector_list_iter_begin(display->drm, &conn_iter); 516 516 for_each_intel_connector_iter(connector, &conn_iter) 517 517 intel_backlight_set_acpi(connector->base.state, bclp, 255); 518 518 drm_connector_list_iter_end(&conn_iter); 519 519 asle->cblv = DIV_ROUND_UP(bclp * 100, 255) | ASLE_CBLV_VALID; 520 520 521 521 - drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex); 521 521 + drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 522 522 523 523 524 524 return 0; 525 525 } 526 526 527 527 - static u32 asle_set_als_illum(struct drm_i915_private *dev_priv, u32 alsi) 527 527 + static u32 asle_set_als_illum(struct intel_display *display, u32 alsi) 528 528 { 529 529 /* alsi is the current ALS reading in lux. 0 indicates below sensor 530 530 range, 0xffff indicates above sensor range. 1-0xfffe are valid */ 531 531 - drm_dbg(&dev_priv->drm, "Illum is not supported\n"); 531 531 + drm_dbg(display->drm, "Illum is not supported\n"); 532 532 return ASLC_ALS_ILLUM_FAILED; 533 533 } 534 534 535 535 - static u32 asle_set_pwm_freq(struct drm_i915_private *dev_priv, u32 pfmb) 535 535 + static u32 asle_set_pwm_freq(struct intel_display *display, u32 pfmb) 536 536 { 537 537 - drm_dbg(&dev_priv->drm, "PWM freq is not supported\n"); 537 537 + drm_dbg(display->drm, "PWM freq is not supported\n"); 538 538 return ASLC_PWM_FREQ_FAILED; 539 539 } 540 540 541 541 - static u32 asle_set_pfit(struct drm_i915_private *dev_priv, u32 pfit) 541 541 + static u32 asle_set_pfit(struct intel_display *display, u32 pfit) 542 542 { 543 543 /* Panel fitting is currently controlled by the X code, so this is a 544 544 noop until modesetting support works fully */ 545 545 - drm_dbg(&dev_priv->drm, "Pfit is not supported\n"); 545 545 + drm_dbg(display->drm, "Pfit is not supported\n"); 546 546 return ASLC_PFIT_FAILED; 547 547 } 548 548 549 549 - static u32 asle_set_supported_rotation_angles(struct drm_i915_private *dev_priv, u32 srot) 549 549 + static u32 asle_set_supported_rotation_angles(struct intel_display *display, u32 srot) 550 550 { 551 551 - drm_dbg(&dev_priv->drm, "SROT is not supported\n"); 551 551 + drm_dbg(display->drm, "SROT is not supported\n"); 552 552 return ASLC_ROTATION_ANGLES_FAILED; 553 553 } 554 554 555 555 - static u32 asle_set_button_array(struct drm_i915_private *dev_priv, u32 iuer) 555 555 + static u32 asle_set_button_array(struct intel_display *display, u32 iuer) 556 556 { 557 557 if (!iuer) 558 558 - drm_dbg(&dev_priv->drm, 558 558 + drm_dbg(display->drm, 559 559 "Button array event is not supported (nothing)\n"); 560 560 if (iuer & ASLE_IUER_ROTATION_LOCK_BTN) 561 561 - drm_dbg(&dev_priv->drm, 561 561 + drm_dbg(display->drm, 562 562 "Button array event is not supported (rotation lock)\n"); 563 563 if (iuer & ASLE_IUER_VOLUME_DOWN_BTN) 564 564 - drm_dbg(&dev_priv->drm, 564 564 + drm_dbg(display->drm, 565 565 "Button array event is not supported (volume down)\n"); 566 566 if (iuer & ASLE_IUER_VOLUME_UP_BTN) 567 567 - drm_dbg(&dev_priv->drm, 567 567 + drm_dbg(display->drm, 568 568 "Button array event is not supported (volume up)\n"); 569 569 if (iuer & ASLE_IUER_WINDOWS_BTN) 570 570 - drm_dbg(&dev_priv->drm, 570 570 + drm_dbg(display->drm, 571 571 "Button array event is not supported (windows)\n"); 572 572 if (iuer & ASLE_IUER_POWER_BTN) 573 573 - drm_dbg(&dev_priv->drm, 573 573 + drm_dbg(display->drm, 574 574 "Button array event is not supported (power)\n"); 575 575 576 576 return ASLC_BUTTON_ARRAY_FAILED; 577 577 } 578 578 579 579 - static u32 asle_set_convertible(struct drm_i915_private *dev_priv, u32 iuer) 579 579 + static u32 asle_set_convertible(struct intel_display *display, u32 iuer) 580 580 { 581 581 if (iuer & ASLE_IUER_CONVERTIBLE) 582 582 - drm_dbg(&dev_priv->drm, 582 582 + drm_dbg(display->drm, 583 583 "Convertible is not supported (clamshell)\n"); 584 584 else 585 585 - drm_dbg(&dev_priv->drm, 585 585 + drm_dbg(display->drm, 586 586 "Convertible is not supported (slate)\n"); 587 587 588 588 return ASLC_CONVERTIBLE_FAILED; 589 589 } 590 590 591 591 - static u32 asle_set_docking(struct drm_i915_private *dev_priv, u32 iuer) 591 591 + static u32 asle_set_docking(struct intel_display *display, u32 iuer) 592 592 { 593 593 if (iuer & ASLE_IUER_DOCKING) 594 594 - drm_dbg(&dev_priv->drm, "Docking is not supported (docked)\n"); 594 594 + drm_dbg(display->drm, "Docking is not supported (docked)\n"); 595 595 else 596 596 - drm_dbg(&dev_priv->drm, 596 596 + drm_dbg(display->drm, 597 597 "Docking is not supported (undocked)\n"); 598 598 599 599 return ASLC_DOCKING_FAILED; 600 600 } 601 601 602 602 - static u32 asle_isct_state(struct drm_i915_private *dev_priv) 602 602 + static u32 asle_isct_state(struct intel_display *display) 603 603 { 604 604 - drm_dbg(&dev_priv->drm, "ISCT is not supported\n"); 604 604 + drm_dbg(display->drm, "ISCT is not supported\n"); 605 605 return ASLC_ISCT_STATE_FAILED; 606 606 } 607 607 ··· 609 609 { 610 610 struct intel_opregion *opregion = 611 611 container_of(work, struct intel_opregion, asle_work); 612 612 - struct drm_i915_private *dev_priv = opregion->i915; 612 612 + struct intel_display *display = opregion->display; 613 613 struct opregion_asle *asle = opregion->asle; 614 614 u32 aslc_stat = 0; 615 615 u32 aslc_req; ··· 620 620 aslc_req = asle->aslc; 621 621 622 622 if (!(aslc_req & ASLC_REQ_MSK)) { 623 623 - drm_dbg(&dev_priv->drm, 623 623 + drm_dbg(display->drm, 624 624 "No request on ASLC interrupt 0x%08x\n", aslc_req); 625 625 return; 626 626 } 627 627 628 628 if (aslc_req & ASLC_SET_ALS_ILLUM) 629 629 - aslc_stat |= asle_set_als_illum(dev_priv, asle->alsi); 629 629 + aslc_stat |= asle_set_als_illum(display, asle->alsi); 630 630 631 631 if (aslc_req & ASLC_SET_BACKLIGHT) 632 632 - aslc_stat |= asle_set_backlight(dev_priv, asle->bclp); 632 632 + aslc_stat |= asle_set_backlight(display, asle->bclp); 633 633 634 634 if (aslc_req & ASLC_SET_PFIT) 635 635 - aslc_stat |= asle_set_pfit(dev_priv, asle->pfit); 635 635 + aslc_stat |= asle_set_pfit(display, asle->pfit); 636 636 637 637 if (aslc_req & ASLC_SET_PWM_FREQ) 638 638 - aslc_stat |= asle_set_pwm_freq(dev_priv, asle->pfmb); 638 638 + aslc_stat |= asle_set_pwm_freq(display, asle->pfmb); 639 639 640 640 if (aslc_req & ASLC_SUPPORTED_ROTATION_ANGLES) 641 641 - aslc_stat |= asle_set_supported_rotation_angles(dev_priv, 641 641 + aslc_stat |= asle_set_supported_rotation_angles(display, 642 642 asle->srot); 643 643 644 644 if (aslc_req & ASLC_BUTTON_ARRAY) 645 645 - aslc_stat |= asle_set_button_array(dev_priv, asle->iuer); 645 645 + aslc_stat |= asle_set_button_array(display, asle->iuer); 646 646 647 647 if (aslc_req & ASLC_CONVERTIBLE_INDICATOR) 648 648 - aslc_stat |= asle_set_convertible(dev_priv, asle->iuer); 648 648 + aslc_stat |= asle_set_convertible(display, asle->iuer); 649 649 650 650 if (aslc_req & ASLC_DOCKING_INDICATOR) 651 651 - aslc_stat |= asle_set_docking(dev_priv, asle->iuer); 651 651 + aslc_stat |= asle_set_docking(display, asle->iuer); 652 652 653 653 if (aslc_req & ASLC_ISCT_STATE_CHANGE) 654 654 - aslc_stat |= asle_isct_state(dev_priv); 654 654 + aslc_stat |= asle_isct_state(display); 655 655 656 656 asle->aslc = aslc_stat; 657 657 } 658 658 659 659 - bool intel_opregion_asle_present(struct drm_i915_private *i915) 659 659 + bool intel_opregion_asle_present(struct intel_display *display) 660 660 { 661 661 - return i915->display.opregion && i915->display.opregion->asle; 661 661 + return display->opregion && display->opregion->asle; 662 662 } 663 663 664 664 - void intel_opregion_asle_intr(struct drm_i915_private *i915) 664 664 + void intel_opregion_asle_intr(struct intel_display *display) 665 665 { 666 666 - struct intel_opregion *opregion = i915->display.opregion; 666 666 + struct drm_i915_private *i915 = to_i915(display->drm); 667 667 + struct intel_opregion *opregion = display->opregion; 667 668 668 669 if (opregion && opregion->asle) 669 670 queue_work(i915->unordered_wq, &opregion->asle_work); ··· 721 720 } 722 721 } 723 722 724 724 - static void intel_didl_outputs(struct drm_i915_private *dev_priv) 723 723 + static void intel_didl_outputs(struct intel_display *display) 725 724 { 726 726 - struct intel_opregion *opregion = dev_priv->display.opregion; 725 725 + struct intel_opregion *opregion = display->opregion; 727 726 struct intel_connector *connector; 728 727 struct drm_connector_list_iter conn_iter; 729 728 int i = 0, max_outputs; ··· 738 737 max_outputs = ARRAY_SIZE(opregion->acpi->didl) + 739 738 ARRAY_SIZE(opregion->acpi->did2); 740 739 741 741 - intel_acpi_device_id_update(dev_priv); 740 740 + intel_acpi_device_id_update(display); 742 741 743 743 - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 742 742 + drm_connector_list_iter_begin(display->drm, &conn_iter); 744 743 for_each_intel_connector_iter(connector, &conn_iter) { 745 744 if (i < max_outputs) 746 745 set_did(opregion, i, connector->acpi_device_id); ··· 748 747 } 749 748 drm_connector_list_iter_end(&conn_iter); 750 749 751 751 - drm_dbg_kms(&dev_priv->drm, "%d outputs detected\n", i); 750 750 + drm_dbg_kms(display->drm, "%d outputs detected\n", i); 752 751 753 752 if (i > max_outputs) 754 754 - drm_err(&dev_priv->drm, 753 753 + drm_err(display->drm, 755 754 "More than %d outputs in connector list\n", 756 755 max_outputs); 757 756 ··· 760 759 set_did(opregion, i, 0); 761 760 } 762 761 763 763 - static void intel_setup_cadls(struct drm_i915_private *dev_priv) 762 762 + static void intel_setup_cadls(struct intel_display *display) 764 763 { 765 765 - struct intel_opregion *opregion = dev_priv->display.opregion; 764 764 + struct intel_opregion *opregion = display->opregion; 766 765 struct intel_connector *connector; 767 766 struct drm_connector_list_iter conn_iter; 768 767 int i = 0; ··· 777 776 * Note that internal panels should be at the front of the connector 778 777 * list already, ensuring they're not left out. 779 778 */ 780 780 - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 779 779 + drm_connector_list_iter_begin(display->drm, &conn_iter); 781 780 for_each_intel_connector_iter(connector, &conn_iter) { 782 781 if (i >= ARRAY_SIZE(opregion->acpi->cadl)) 783 782 break; ··· 790 789 opregion->acpi->cadl[i] = 0; 791 790 } 792 791 793 793 - static void swsci_setup(struct drm_i915_private *dev_priv) 792 792 + static void swsci_setup(struct intel_display *display) 794 793 { 795 795 - struct intel_opregion *opregion = dev_priv->display.opregion; 794 794 + struct intel_opregion *opregion = display->opregion; 796 795 bool requested_callbacks = false; 797 796 u32 tmp; 798 797 ··· 801 800 opregion->swsci_sbcb_sub_functions = 1; 802 801 803 802 /* We use GBDA to ask for supported GBDA calls. */ 804 804 - if (swsci(dev_priv, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) { 803 803 + if (swsci(display, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) { 805 804 /* make the bits match the sub-function codes */ 806 805 tmp <<= 1; 807 806 opregion->swsci_gbda_sub_functions |= tmp; ··· 812 811 * must not call interfaces that are not specifically requested by the 813 812 * bios. 814 813 */ 815 815 - if (swsci(dev_priv, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) { 814 814 + if (swsci(display, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) { 816 815 /* here, the bits already match sub-function codes */ 817 816 opregion->swsci_sbcb_sub_functions |= tmp; 818 817 requested_callbacks = true; ··· 823 822 * the callback is _requested_. But we still can't call interfaces that 824 823 * are not requested. 825 824 */ 826 826 - if (swsci(dev_priv, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) { 825 825 + if (swsci(display, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) { 827 826 /* make the bits match the sub-function codes */ 828 827 u32 low = tmp & 0x7ff; 829 828 u32 high = tmp & ~0xfff; /* bit 11 is reserved */ ··· 833 832 if (requested_callbacks) { 834 833 u32 req = opregion->swsci_sbcb_sub_functions; 835 834 if ((req & tmp) != req) 836 836 - drm_dbg(&dev_priv->drm, 835 835 + drm_dbg(display->drm, 837 836 "SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x)\n", 838 837 req, tmp); 839 838 /* XXX: for now, trust the requested callbacks */ ··· 843 842 } 844 843 } 845 844 846 846 - drm_dbg(&dev_priv->drm, 845 845 + drm_dbg(display->drm, 847 846 "SWSCI GBDA callbacks %08x, SBCB callbacks %08x\n", 848 847 opregion->swsci_gbda_sub_functions, 849 848 opregion->swsci_sbcb_sub_functions); ··· 868 867 { } 869 868 }; 870 869 871 871 - int intel_opregion_setup(struct drm_i915_private *dev_priv) 870 870 + int intel_opregion_setup(struct intel_display *display) 872 871 { 873 872 struct intel_opregion *opregion; 874 874 - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 873 873 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 875 874 u32 asls, mboxes; 876 875 char buf[sizeof(OPREGION_SIGNATURE)]; 877 876 int err = 0; ··· 886 885 BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400); 887 886 888 887 pci_read_config_dword(pdev, ASLS, &asls); 889 889 - drm_dbg(&dev_priv->drm, "graphic opregion physical addr: 0x%x\n", 888 888 + drm_dbg(display->drm, "graphic opregion physical addr: 0x%x\n", 890 889 asls); 891 890 if (asls == 0) { 892 892 - drm_dbg(&dev_priv->drm, "ACPI OpRegion not supported!\n"); 891 891 + drm_dbg(display->drm, "ACPI OpRegion not supported!\n"); 893 892 return -ENOTSUPP; 894 893 } 895 894 ··· 897 896 if (!opregion) 898 897 return -ENOMEM; 899 898 900 900 - opregion->i915 = dev_priv; 901 901 - dev_priv->display.opregion = opregion; 899 899 + opregion->display = display; 900 900 + display->opregion = opregion; 902 901 903 902 INIT_WORK(&opregion->asle_work, asle_work); 904 903 ··· 911 910 memcpy(buf, base, sizeof(buf)); 912 911 913 912 if (memcmp(buf, OPREGION_SIGNATURE, 16)) { 914 914 - drm_dbg(&dev_priv->drm, "opregion signature mismatch\n"); 913 913 + drm_dbg(display->drm, "opregion signature mismatch\n"); 915 914 err = -EINVAL; 916 915 goto err_out; 917 916 } 918 917 opregion->header = base; 919 918 920 920 - drm_dbg(&dev_priv->drm, "ACPI OpRegion version %u.%u.%u\n", 919 919 + drm_dbg(display->drm, "ACPI OpRegion version %u.%u.%u\n", 921 920 opregion->header->over.major, 922 921 opregion->header->over.minor, 923 922 opregion->header->over.revision); 924 923 925 924 mboxes = opregion->header->mboxes; 926 925 if (mboxes & MBOX_ACPI) { 927 927 - drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n"); 926 926 + drm_dbg(display->drm, "Public ACPI methods supported\n"); 928 927 opregion->acpi = base + OPREGION_ACPI_OFFSET; 929 928 /* 930 929 * Indicate we handle monitor hotplug events ourselves so we do ··· 939 938 u8 major = opregion->header->over.major; 940 939 941 940 if (major >= 3) { 942 942 - drm_err(&dev_priv->drm, "SWSCI Mailbox #2 present for opregion v3.x, ignoring\n"); 941 941 + drm_err(display->drm, "SWSCI Mailbox #2 present for opregion v3.x, ignoring\n"); 943 942 } else { 944 943 if (major >= 2) 945 945 - drm_dbg(&dev_priv->drm, "SWSCI Mailbox #2 present for opregion v2.x\n"); 946 946 - drm_dbg(&dev_priv->drm, "SWSCI supported\n"); 944 944 + drm_dbg(display->drm, "SWSCI Mailbox #2 present for opregion v2.x\n"); 945 945 + drm_dbg(display->drm, "SWSCI supported\n"); 947 946 opregion->swsci = base + OPREGION_SWSCI_OFFSET; 948 948 - swsci_setup(dev_priv); 947 947 + swsci_setup(display); 949 948 } 950 949 } 951 950 952 951 if (mboxes & MBOX_ASLE) { 953 953 - drm_dbg(&dev_priv->drm, "ASLE supported\n"); 952 952 + drm_dbg(display->drm, "ASLE supported\n"); 954 953 opregion->asle = base + OPREGION_ASLE_OFFSET; 955 954 956 955 opregion->asle->ardy = ASLE_ARDY_NOT_READY; 957 956 } 958 957 959 958 if (mboxes & MBOX_ASLE_EXT) { 960 960 - drm_dbg(&dev_priv->drm, "ASLE extension supported\n"); 959 959 + drm_dbg(display->drm, "ASLE extension supported\n"); 961 960 opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET; 962 961 } 963 962 964 963 if (mboxes & MBOX_BACKLIGHT) { 965 965 - drm_dbg(&dev_priv->drm, "Mailbox #2 for backlight present\n"); 964 964 + drm_dbg(display->drm, "Mailbox #2 for backlight present\n"); 966 965 } 967 966 968 967 if (dmi_check_system(intel_no_opregion_vbt)) ··· 980 979 */ 981 980 if (opregion->header->over.major > 2 || 982 981 opregion->header->over.minor >= 1) { 983 983 - drm_WARN_ON(&dev_priv->drm, rvda < OPREGION_SIZE); 982 982 + drm_WARN_ON(display->drm, rvda < OPREGION_SIZE); 984 983 985 984 rvda += asls; 986 985 } ··· 990 989 991 990 vbt = opregion->rvda; 992 991 vbt_size = opregion->asle->rvds; 993 993 - if (intel_bios_is_valid_vbt(dev_priv, vbt, vbt_size)) { 994 994 - drm_dbg_kms(&dev_priv->drm, 992 992 + if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) { 993 993 + drm_dbg_kms(display->drm, 995 994 "Found valid VBT in ACPI OpRegion (RVDA)\n"); 996 995 opregion->vbt = vbt; 997 996 opregion->vbt_size = vbt_size; 998 997 goto out; 999 998 } else { 1000 1000 - drm_dbg_kms(&dev_priv->drm, 999 999 + drm_dbg_kms(display->drm, 1001 1000 "Invalid VBT in ACPI OpRegion (RVDA)\n"); 1002 1001 memunmap(opregion->rvda); 1003 1002 opregion->rvda = NULL; ··· 1015 1014 vbt_size = (mboxes & MBOX_ASLE_EXT) ? 1016 1015 OPREGION_ASLE_EXT_OFFSET : OPREGION_SIZE; 1017 1016 vbt_size -= OPREGION_VBT_OFFSET; 1018 1018 - if (intel_bios_is_valid_vbt(dev_priv, vbt, vbt_size)) { 1019 1019 - drm_dbg_kms(&dev_priv->drm, 1017 1017 + if (intel_bios_is_valid_vbt(display, vbt, vbt_size)) { 1018 1018 + drm_dbg_kms(display->drm, 1020 1019 "Found valid VBT in ACPI OpRegion (Mailbox #4)\n"); 1021 1020 opregion->vbt = vbt; 1022 1021 opregion->vbt_size = vbt_size; 1023 1022 } else { 1024 1024 - drm_dbg_kms(&dev_priv->drm, 1023 1023 + drm_dbg_kms(display->drm, 1025 1024 "Invalid VBT in ACPI OpRegion (Mailbox #4)\n"); 1026 1025 } 1027 1026 ··· 1032 1031 memunmap(base); 1033 1032 err_memremap: 1034 1033 kfree(opregion); 1035 1035 - dev_priv->display.opregion = NULL; 1034 1034 + display->opregion = NULL; 1036 1035 1037 1036 return err; 1038 1037 } ··· 1055 1054 }; 1056 1055 1057 1056 int 1058 1058 - intel_opregion_get_panel_type(struct drm_i915_private *dev_priv) 1057 1057 + intel_opregion_get_panel_type(struct intel_display *display) 1059 1058 { 1060 1059 u32 panel_details; 1061 1060 int ret; 1062 1061 1063 1063 - ret = swsci(dev_priv, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details); 1062 1062 + ret = swsci(display, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details); 1064 1063 if (ret) 1065 1064 return ret; 1066 1065 1067 1066 ret = (panel_details >> 8) & 0xff; 1068 1067 if (ret > 0x10) { 1069 1069 - drm_dbg_kms(&dev_priv->drm, 1068 1068 + drm_dbg_kms(display->drm, 1070 1069 "Invalid OpRegion panel type 0x%x\n", ret); 1071 1070 return -EINVAL; 1072 1071 } 1073 1072 1074 1073 /* fall back to VBT panel type? */ 1075 1074 if (ret == 0x0) { 1076 1076 - drm_dbg_kms(&dev_priv->drm, "No panel type in OpRegion\n"); 1075 1075 + drm_dbg_kms(display->drm, "No panel type in OpRegion\n"); 1077 1076 return -ENODEV; 1078 1077 } 1079 1078 ··· 1083 1082 * via a quirk list :( 1084 1083 */ 1085 1084 if (!dmi_check_system(intel_use_opregion_panel_type)) { 1086 1086 - drm_dbg_kms(&dev_priv->drm, 1085 1085 + drm_dbg_kms(display->drm, 1087 1086 "Ignoring OpRegion panel type (%d)\n", ret - 1); 1088 1087 return -ENODEV; 1089 1088 } ··· 1093 1092 1094 1093 /** 1095 1094 * intel_opregion_get_edid - Fetch EDID from ACPI OpRegion mailbox #5 1096 1096 - * @intel_connector: eDP connector 1095 1095 + * @connector: eDP connector 1097 1096 * 1098 1097 * This reads the ACPI Opregion mailbox #5 to extract the EDID that is passed 1099 1098 * to it. ··· 1102 1101 * The EDID in the OpRegion, or NULL if there is none or it's invalid. 1103 1102 * 1104 1103 */ 1105 1105 - const struct drm_edid *intel_opregion_get_edid(struct intel_connector *intel_connector) 1104 1104 + const struct drm_edid *intel_opregion_get_edid(struct intel_connector *connector) 1106 1105 { 1107 1107 - struct drm_connector *connector = &intel_connector->base; 1108 1108 - struct drm_i915_private *i915 = to_i915(connector->dev); 1109 1109 - struct intel_opregion *opregion = i915->display.opregion; 1106 1106 + struct intel_display *display = to_intel_display(connector); 1107 1107 + struct intel_opregion *opregion = display->opregion; 1110 1108 const struct drm_edid *drm_edid; 1111 1109 const void *edid; 1112 1110 int len; ··· 1123 1123 drm_edid = drm_edid_alloc(edid, len); 1124 1124 1125 1125 if (!drm_edid_valid(drm_edid)) { 1126 1126 - drm_dbg_kms(&i915->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5)\n"); 1126 1126 + drm_dbg_kms(display->drm, "Invalid EDID in ACPI OpRegion (Mailbox #5)\n"); 1127 1127 drm_edid_free(drm_edid); 1128 1128 drm_edid = NULL; 1129 1129 } ··· 1131 1131 return drm_edid; 1132 1132 } 1133 1133 1134 1134 - bool intel_opregion_vbt_present(struct drm_i915_private *i915) 1134 1134 + bool intel_opregion_vbt_present(struct intel_display *display) 1135 1135 { 1136 1136 - struct intel_opregion *opregion = i915->display.opregion; 1136 1136 + struct intel_opregion *opregion = display->opregion; 1137 1137 1138 1138 if (!opregion || !opregion->vbt) 1139 1139 return false; ··· 1141 1141 return true; 1142 1142 } 1143 1143 1144 1144 - const void *intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size) 1144 1144 + const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size) 1145 1145 { 1146 1146 - struct intel_opregion *opregion = i915->display.opregion; 1146 1146 + struct intel_opregion *opregion = display->opregion; 1147 1147 1148 1148 if (!opregion || !opregion->vbt) 1149 1149 return NULL; ··· 1154 1154 return kmemdup(opregion->vbt, opregion->vbt_size, GFP_KERNEL); 1155 1155 } 1156 1156 1157 1157 - bool intel_opregion_headless_sku(struct drm_i915_private *i915) 1157 1157 + bool intel_opregion_headless_sku(struct intel_display *display) 1158 1158 { 1159 1159 - struct intel_opregion *opregion = i915->display.opregion; 1159 1159 + struct intel_opregion *opregion = display->opregion; 1160 1160 struct opregion_header *header; 1161 1161 1162 1162 if (!opregion) ··· 1171 1171 return opregion->header->pcon & PCON_HEADLESS_SKU; 1172 1172 } 1173 1173 1174 1174 - void intel_opregion_register(struct drm_i915_private *i915) 1174 1174 + void intel_opregion_register(struct intel_display *display) 1175 1175 { 1176 1176 - struct intel_opregion *opregion = i915->display.opregion; 1176 1176 + struct intel_opregion *opregion = display->opregion; 1177 1177 1178 1178 if (!opregion) 1179 1179 return; ··· 1184 1184 register_acpi_notifier(&opregion->acpi_notifier); 1185 1185 } 1186 1186 1187 1187 - intel_opregion_resume(i915); 1187 1187 + intel_opregion_resume(display); 1188 1188 } 1189 1189 1190 1190 - static void intel_opregion_resume_display(struct drm_i915_private *i915) 1190 1190 + static void intel_opregion_resume_display(struct intel_display *display) 1191 1191 { 1192 1192 - struct intel_opregion *opregion = i915->display.opregion; 1192 1192 + struct intel_opregion *opregion = display->opregion; 1193 1193 1194 1194 if (opregion->acpi) { 1195 1195 - intel_didl_outputs(i915); 1196 1196 - intel_setup_cadls(i915); 1195 1195 + intel_didl_outputs(display); 1196 1196 + intel_setup_cadls(display); 1197 1197 1198 1198 /* 1199 1199 * Notify BIOS we are ready to handle ACPI video ext notifs. ··· 1210 1210 } 1211 1211 1212 1212 /* Some platforms abuse the _DSM to enable MUX */ 1213 1213 - intel_dsm_get_bios_data_funcs_supported(i915); 1213 1213 + intel_dsm_get_bios_data_funcs_supported(display); 1214 1214 } 1215 1215 1216 1216 - void intel_opregion_resume(struct drm_i915_private *i915) 1216 1216 + void intel_opregion_resume(struct intel_display *display) 1217 1217 { 1218 1218 - struct intel_opregion *opregion = i915->display.opregion; 1218 1218 + struct intel_opregion *opregion = display->opregion; 1219 1219 1220 1220 if (!opregion) 1221 1221 return; 1222 1222 1223 1223 - if (HAS_DISPLAY(i915)) 1224 1224 - intel_opregion_resume_display(i915); 1223 1223 + if (HAS_DISPLAY(display)) 1224 1224 + intel_opregion_resume_display(display); 1225 1225 1226 1226 - intel_opregion_notify_adapter(i915, PCI_D0); 1226 1226 + intel_opregion_notify_adapter(display, PCI_D0); 1227 1227 } 1228 1228 1229 1229 - static void intel_opregion_suspend_display(struct drm_i915_private *i915) 1229 1229 + static void intel_opregion_suspend_display(struct intel_display *display) 1230 1230 { 1231 1231 - struct intel_opregion *opregion = i915->display.opregion; 1231 1231 + struct intel_opregion *opregion = display->opregion; 1232 1232 1233 1233 if (opregion->asle) 1234 1234 opregion->asle->ardy = ASLE_ARDY_NOT_READY; ··· 1239 1239 opregion->acpi->drdy = 0; 1240 1240 } 1241 1241 1242 1242 - void intel_opregion_suspend(struct drm_i915_private *i915, pci_power_t state) 1242 1242 + void intel_opregion_suspend(struct intel_display *display, pci_power_t state) 1243 1243 { 1244 1244 - struct intel_opregion *opregion = i915->display.opregion; 1244 1244 + struct intel_opregion *opregion = display->opregion; 1245 1245 1246 1246 if (!opregion) 1247 1247 return; 1248 1248 1249 1249 - intel_opregion_notify_adapter(i915, state); 1249 1249 + intel_opregion_notify_adapter(display, state); 1250 1250 1251 1251 - if (HAS_DISPLAY(i915)) 1252 1252 - intel_opregion_suspend_display(i915); 1251 1251 + if (HAS_DISPLAY(display)) 1252 1252 + intel_opregion_suspend_display(display); 1253 1253 } 1254 1254 1255 1255 - void intel_opregion_unregister(struct drm_i915_private *i915) 1255 1255 + void intel_opregion_unregister(struct intel_display *display) 1256 1256 { 1257 1257 - struct intel_opregion *opregion = i915->display.opregion; 1257 1257 + struct intel_opregion *opregion = display->opregion; 1258 1258 1259 1259 - intel_opregion_suspend(i915, PCI_D1); 1259 1259 + intel_opregion_suspend(display, PCI_D1); 1260 1260 1261 1261 if (!opregion) 1262 1262 return; ··· 1267 1267 } 1268 1268 } 1269 1269 1270 1270 - void intel_opregion_cleanup(struct drm_i915_private *i915) 1270 1270 + void intel_opregion_cleanup(struct intel_display *display) 1271 1271 { 1272 1272 - struct intel_opregion *opregion = i915->display.opregion; 1272 1272 + struct intel_opregion *opregion = display->opregion; 1273 1273 1274 1274 if (!opregion) 1275 1275 return; ··· 1278 1278 if (opregion->rvda) 1279 1279 memunmap(opregion->rvda); 1280 1280 kfree(opregion); 1281 1281 - i915->display.opregion = NULL; 1281 1281 + display->opregion = NULL; 1282 1282 } 1283 1283 1284 1284 static int intel_opregion_show(struct seq_file *m, void *unused) 1285 1285 { 1286 1286 - struct drm_i915_private *i915 = m->private; 1287 1287 - struct intel_opregion *opregion = i915->display.opregion; 1286 1286 + struct intel_display *display = m->private; 1287 1287 + struct intel_opregion *opregion = display->opregion; 1288 1288 1289 1289 if (opregion) 1290 1290 seq_write(m, opregion->header, OPREGION_SIZE); ··· 1294 1294 1295 1295 DEFINE_SHOW_ATTRIBUTE(intel_opregion); 1296 1296 1297 1297 - void intel_opregion_debugfs_register(struct drm_i915_private *i915) 1297 1297 + void intel_opregion_debugfs_register(struct intel_display *display) 1298 1298 { 1299 1299 - struct drm_minor *minor = i915->drm.primary; 1299 1299 + struct drm_minor *minor = display->drm->primary; 1300 1300 1301 1301 debugfs_create_file("i915_opregion", 0444, minor->debugfs_root, 1302 1302 - i915, &intel_opregion_fops); 1302 1302 + display, &intel_opregion_fops); 1303 1303 }

+31 -31

drivers/gpu/drm/i915/display/intel_opregion.h

reviewed

··· 28 28 #include <linux/pci.h> 29 29 #include <linux/types.h> 30 30 31 31 - struct drm_i915_private; 32 31 struct intel_connector; 32 32 + struct intel_display; 33 33 struct intel_encoder; 34 34 35 35 #ifdef CONFIG_ACPI 36 36 37 37 - int intel_opregion_setup(struct drm_i915_private *dev_priv); 38 38 - void intel_opregion_cleanup(struct drm_i915_private *i915); 37 37 + int intel_opregion_setup(struct intel_display *display); 38 38 + void intel_opregion_cleanup(struct intel_display *display); 39 39 40 40 - void intel_opregion_register(struct drm_i915_private *dev_priv); 41 41 - void intel_opregion_unregister(struct drm_i915_private *dev_priv); 40 40 + void intel_opregion_register(struct intel_display *display); 41 41 + void intel_opregion_unregister(struct intel_display *display); 42 42 43 43 - void intel_opregion_resume(struct drm_i915_private *dev_priv); 44 44 - void intel_opregion_suspend(struct drm_i915_private *dev_priv, 43 43 + void intel_opregion_resume(struct intel_display *display); 44 44 + void intel_opregion_suspend(struct intel_display *display, 45 45 pci_power_t state); 46 46 47 47 - bool intel_opregion_asle_present(struct drm_i915_private *i915); 48 48 - void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); 49 49 - int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 47 47 + bool intel_opregion_asle_present(struct intel_display *display); 48 48 + void intel_opregion_asle_intr(struct intel_display *display); 49 49 + int intel_opregion_notify_encoder(struct intel_encoder *encoder, 50 50 bool enable); 51 51 - int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, 51 51 + int intel_opregion_notify_adapter(struct intel_display *display, 52 52 pci_power_t state); 53 53 - int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); 53 53 + int intel_opregion_get_panel_type(struct intel_display *display); 54 54 const struct drm_edid *intel_opregion_get_edid(struct intel_connector *connector); 55 55 56 56 - bool intel_opregion_vbt_present(struct drm_i915_private *i915); 57 57 - const void *intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size); 56 56 + bool intel_opregion_vbt_present(struct intel_display *display); 57 57 + const void *intel_opregion_get_vbt(struct intel_display *display, size_t *size); 58 58 59 59 - bool intel_opregion_headless_sku(struct drm_i915_private *i915); 59 59 + bool intel_opregion_headless_sku(struct intel_display *display); 60 60 61 61 - void intel_opregion_debugfs_register(struct drm_i915_private *i915); 61 61 + void intel_opregion_debugfs_register(struct intel_display *display); 62 62 63 63 #else /* CONFIG_ACPI*/ 64 64 65 65 - static inline int intel_opregion_setup(struct drm_i915_private *dev_priv) 65 65 + static inline int intel_opregion_setup(struct intel_display *display) 66 66 { 67 67 return 0; 68 68 } 69 69 70 70 - static inline void intel_opregion_cleanup(struct drm_i915_private *i915) 70 70 + static inline void intel_opregion_cleanup(struct intel_display *display) 71 71 { 72 72 } 73 73 74 74 - static inline void intel_opregion_register(struct drm_i915_private *dev_priv) 74 74 + static inline void intel_opregion_register(struct intel_display *display) 75 75 { 76 76 } 77 77 78 78 - static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) 78 78 + static inline void intel_opregion_unregister(struct intel_display *display) 79 79 { 80 80 } 81 81 82 82 - static inline void intel_opregion_resume(struct drm_i915_private *dev_priv) 82 82 + static inline void intel_opregion_resume(struct intel_display *display) 83 83 { 84 84 } 85 85 86 86 - static inline void intel_opregion_suspend(struct drm_i915_private *dev_priv, 86 86 + static inline void intel_opregion_suspend(struct intel_display *display, 87 87 pci_power_t state) 88 88 { 89 89 } 90 90 91 91 - static inline bool intel_opregion_asle_present(struct drm_i915_private *i915) 91 91 + static inline bool intel_opregion_asle_present(struct intel_display *display) 92 92 { 93 93 return false; 94 94 } 95 95 96 96 - static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) 96 96 + static inline void intel_opregion_asle_intr(struct intel_display *display) 97 97 { 98 98 } 99 99 100 100 static inline int 101 101 - intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 101 101 + intel_opregion_notify_encoder(struct intel_encoder *encoder, bool enable) 102 102 { 103 103 return 0; 104 104 } 105 105 106 106 static inline int 107 107 - intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) 107 107 + intel_opregion_notify_adapter(struct intel_display *display, pci_power_t state) 108 108 { 109 109 return 0; 110 110 } 111 111 112 112 - static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) 112 112 + static inline int intel_opregion_get_panel_type(struct intel_display *display) 113 113 { 114 114 return -ENODEV; 115 115 } ··· 120 120 return NULL; 121 121 } 122 122 123 123 - static inline bool intel_opregion_vbt_present(struct drm_i915_private *i915) 123 123 + static inline bool intel_opregion_vbt_present(struct intel_display *display) 124 124 { 125 125 return false; 126 126 } 127 127 128 128 static inline const void * 129 129 - intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size) 129 129 + intel_opregion_get_vbt(struct intel_display *display, size_t *size) 130 130 { 131 131 return NULL; 132 132 } 133 133 134 134 - static inline bool intel_opregion_headless_sku(struct drm_i915_private *i915) 134 134 + static inline bool intel_opregion_headless_sku(struct intel_display *display) 135 135 { 136 136 return false; 137 137 } 138 138 139 139 - static inline void intel_opregion_debugfs_register(struct drm_i915_private *i915) 139 139 + static inline void intel_opregion_debugfs_register(struct intel_display *display) 140 140 { 141 141 } 142 142

+3

drivers/gpu/drm/i915/display/intel_pps.c

reviewed

··· 351 351 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 352 352 return 2; 353 353 354 354 + if (INTEL_PCH_TYPE(i915) >= PCH_MTL) 355 355 + return 2; 356 356 + 354 357 if (INTEL_PCH_TYPE(i915) >= PCH_DG1) 355 358 return 1; 356 359

+17 -16

drivers/gpu/drm/i915/display/intel_sdvo.c

reviewed

··· 95 95 struct intel_encoder base; 96 96 97 97 struct i2c_adapter *i2c; 98 98 - u8 slave_addr; 98 98 + u8 target_addr; 99 99 100 100 struct intel_sdvo_ddc ddc[3]; 101 101 ··· 255 255 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); 256 256 struct i2c_msg msgs[] = { 257 257 { 258 258 - .addr = intel_sdvo->slave_addr, 258 258 + .addr = intel_sdvo->target_addr, 259 259 .flags = 0, 260 260 .len = 1, 261 261 .buf = &addr, 262 262 }, 263 263 { 264 264 - .addr = intel_sdvo->slave_addr, 264 264 + .addr = intel_sdvo->target_addr, 265 265 .flags = I2C_M_RD, 266 266 .len = 1, 267 267 .buf = ch, ··· 483 483 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 484 484 485 485 for (i = 0; i < args_len; i++) { 486 486 - msgs[i].addr = intel_sdvo->slave_addr; 486 486 + msgs[i].addr = intel_sdvo->target_addr; 487 487 msgs[i].flags = 0; 488 488 msgs[i].len = 2; 489 489 msgs[i].buf = buf + 2 *i; 490 490 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 491 491 buf[2*i + 1] = ((u8*)args)[i]; 492 492 } 493 493 - msgs[i].addr = intel_sdvo->slave_addr; 493 493 + msgs[i].addr = intel_sdvo->target_addr; 494 494 msgs[i].flags = 0; 495 495 msgs[i].len = 2; 496 496 msgs[i].buf = buf + 2*i; ··· 499 499 500 500 /* the following two are to read the response */ 501 501 status = SDVO_I2C_CMD_STATUS; 502 502 - msgs[i+1].addr = intel_sdvo->slave_addr; 502 502 + msgs[i+1].addr = intel_sdvo->target_addr; 503 503 msgs[i+1].flags = 0; 504 504 msgs[i+1].len = 1; 505 505 msgs[i+1].buf = &status; 506 506 507 507 - msgs[i+2].addr = intel_sdvo->slave_addr; 507 507 + msgs[i+2].addr = intel_sdvo->target_addr; 508 508 msgs[i+2].flags = I2C_M_RD; 509 509 msgs[i+2].len = 1; 510 510 msgs[i+2].buf = &status; ··· 2652 2652 else 2653 2653 pin = GMBUS_PIN_DPB; 2654 2654 2655 2655 - drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, slave addr 0x%x\n", 2655 2655 + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n", 2656 2656 sdvo->base.base.base.id, sdvo->base.base.name, 2657 2657 - pin, sdvo->slave_addr); 2657 2657 + pin, sdvo->target_addr); 2658 2658 2659 2659 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2660 2660 ··· 2680 2680 } 2681 2681 2682 2682 static u8 2683 2683 - intel_sdvo_get_slave_addr(struct intel_sdvo *sdvo) 2683 2683 + intel_sdvo_get_target_addr(struct intel_sdvo *sdvo) 2684 2684 { 2685 2685 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev); 2686 2686 const struct sdvo_device_mapping *my_mapping, *other_mapping; ··· 2694 2694 } 2695 2695 2696 2696 /* If the BIOS described our SDVO device, take advantage of it. */ 2697 2697 - if (my_mapping->slave_addr) 2698 2698 - return my_mapping->slave_addr; 2697 2697 + if (my_mapping->target_addr) 2698 2698 + return my_mapping->target_addr; 2699 2699 2700 2700 /* 2701 2701 * If the BIOS only described a different SDVO device, use the 2702 2702 * address that it isn't using. 2703 2703 */ 2704 2704 - if (other_mapping->slave_addr) { 2705 2705 - if (other_mapping->slave_addr == 0x70) 2704 2704 + if (other_mapping->target_addr) { 2705 2705 + if (other_mapping->target_addr == 0x70) 2706 2706 return 0x72; 2707 2707 else 2708 2708 return 0x70; ··· 2919 2919 static bool 2920 2920 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) 2921 2921 { 2922 2922 + struct intel_display *display = to_intel_display(&intel_sdvo->base); 2922 2923 struct drm_encoder *encoder = &intel_sdvo->base.base; 2923 2924 struct drm_i915_private *i915 = to_i915(encoder->dev); 2924 2925 struct drm_connector *connector; ··· 2947 2946 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2948 2947 goto err; 2949 2948 2950 2950 - intel_bios_init_panel_late(i915, &intel_connector->panel, NULL, NULL); 2949 2949 + intel_bios_init_panel_late(display, &intel_connector->panel, NULL, NULL); 2951 2950 2952 2951 /* 2953 2952 * Fetch modes from VBT. For SDVO prefer the VBT mode since some ··· 3406 3405 "SDVO %c", port_name(port)); 3407 3406 3408 3407 intel_sdvo->sdvo_reg = sdvo_reg; 3409 3409 - intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(intel_sdvo) >> 1; 3408 3408 + intel_sdvo->target_addr = intel_sdvo_get_target_addr(intel_sdvo) >> 1; 3410 3409 3411 3410 intel_sdvo_select_i2c_bus(intel_sdvo); 3412 3411

+3

drivers/gpu/drm/i915/display/intel_tc.c

reviewed

··· 393 393 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 394 394 u32 val; 395 395 396 396 + if (DISPLAY_VER(i915) >= 14) 397 397 + return; 398 398 + 396 399 drm_WARN_ON(&i915->drm, 397 400 lane_reversal && tc->mode != TC_PORT_LEGACY); 398 401

+2 -1

drivers/gpu/drm/i915/display/intel_tv.c

reviewed

··· 1930 1930 void 1931 1931 intel_tv_init(struct drm_i915_private *dev_priv) 1932 1932 { 1933 1933 + struct intel_display *display = &dev_priv->display; 1933 1934 struct drm_connector *connector; 1934 1935 struct intel_tv *intel_tv; 1935 1936 struct intel_encoder *intel_encoder; ··· 1940 1939 if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) 1941 1940 return; 1942 1941 1943 1943 - if (!intel_bios_is_tv_present(dev_priv)) { 1942 1942 + if (!intel_bios_is_tv_present(display)) { 1944 1943 drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n"); 1945 1944 return; 1946 1945 }

+2 -1

drivers/gpu/drm/i915/display/intel_vblank.c

reviewed

··· 652 652 */ 653 653 if (intel_color_uses_dsb(new_crtc_state) || 654 654 new_crtc_state->update_m_n || new_crtc_state->update_lrr) 655 655 - evade->min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; 655 655 + evade->min -= intel_mode_vblank_start(adjusted_mode) - 656 656 + intel_mode_vdisplay(adjusted_mode); 656 657 } 657 658 658 659 /* must be called with vblank interrupt already enabled! */

+2 -2

drivers/gpu/drm/i915/display/intel_vbt_defs.h

reviewed

··· 493 493 u16 addin_offset; 494 494 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ 495 495 u8 i2c_pin; 496 496 - u8 slave_addr; 496 496 + u8 target_addr; 497 497 u8 ddc_pin; 498 498 u16 edid_ptr; 499 499 u8 dvo_cfg; /* See DEVICE_CFG_* above */ ··· 502 502 struct { 503 503 u8 dvo2_port; 504 504 u8 i2c2_pin; 505 505 - u8 slave2_addr; 505 505 + u8 target2_addr; 506 506 u8 ddc2_pin; 507 507 } __packed; 508 508 struct {

+26 -25

drivers/gpu/drm/i915/display/intel_vdsc.c

reviewed

··· 8 8 #include <linux/limits.h> 9 9 10 10 #include <drm/display/drm_dsc_helper.h> 11 11 + #include <drm/drm_fixed.h> 11 12 12 13 #include "i915_drv.h" 13 14 #include "intel_crtc.h" ··· 77 76 static void 78 77 calculate_rc_params(struct drm_dsc_config *vdsc_cfg) 79 78 { 80 80 - int bpp = to_bpp_int(vdsc_cfg->bits_per_pixel); 79 79 + int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel); 81 80 int bpc = vdsc_cfg->bits_per_component; 82 81 int qp_bpc_modifier = (bpc - 8) * 2; 83 82 int uncompressed_bpg_rate; ··· 185 184 } 186 185 } else { 187 186 /* fractional bpp part * 10000 (for precision up to 4 decimal places) */ 188 188 - int fractional_bits = to_bpp_frac(vdsc_cfg->bits_per_pixel); 187 187 + int fractional_bits = fxp_q4_to_frac(vdsc_cfg->bits_per_pixel); 189 188 190 189 static const s8 ofs_und6[] = { 191 190 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 ··· 264 263 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 265 264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 266 265 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 267 267 - u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16); 266 266 + u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); 268 267 int err; 269 268 int ret; 270 269 ··· 457 456 pps_val |= DSC_PPS0_422_ENABLE; 458 457 if (vdsc_cfg->vbr_enable) 459 458 pps_val |= DSC_PPS0_VBR_ENABLE; 460 460 - drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 461 459 intel_dsc_pps_write(crtc_state, 0, pps_val); 462 460 463 461 /* PPS 1 */ 464 462 pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel); 465 465 - drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 466 463 intel_dsc_pps_write(crtc_state, 1, pps_val); 467 464 468 465 /* PPS 2 */ 469 466 pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) | 470 467 DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 471 471 - drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 472 468 intel_dsc_pps_write(crtc_state, 2, pps_val); 473 469 474 470 /* PPS 3 */ 475 471 pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) | 476 472 DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width); 477 477 - drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 478 473 intel_dsc_pps_write(crtc_state, 3, pps_val); 479 474 480 475 /* PPS 4 */ 481 476 pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 482 477 DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 483 483 - drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 484 478 intel_dsc_pps_write(crtc_state, 4, pps_val); 485 479 486 480 /* PPS 5 */ 487 481 pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 488 482 DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 489 489 - drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 490 483 intel_dsc_pps_write(crtc_state, 5, pps_val); 491 484 492 485 /* PPS 6 */ ··· 488 493 DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 489 494 DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 490 495 DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 491 491 - drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 492 496 intel_dsc_pps_write(crtc_state, 6, pps_val); 493 497 494 498 /* PPS 7 */ 495 499 pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 496 500 DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 497 497 - drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 498 501 intel_dsc_pps_write(crtc_state, 7, pps_val); 499 502 500 503 /* PPS 8 */ 501 504 pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) | 502 505 DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset); 503 503 - drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 504 506 intel_dsc_pps_write(crtc_state, 8, pps_val); 505 507 506 508 /* PPS 9 */ 507 509 pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 508 510 DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 509 509 - drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 510 511 intel_dsc_pps_write(crtc_state, 9, pps_val); 511 512 512 513 /* PPS 10 */ ··· 510 519 DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 511 520 DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 512 521 DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 513 513 - drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 514 522 intel_dsc_pps_write(crtc_state, 10, pps_val); 515 523 516 524 /* PPS 16 */ ··· 518 528 vdsc_cfg->slice_width) | 519 529 DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 520 530 vdsc_cfg->slice_height); 521 521 - drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 522 531 intel_dsc_pps_write(crtc_state, 16, pps_val); 523 532 524 533 if (DISPLAY_VER(dev_priv) >= 14) { 525 534 /* PPS 17 */ 526 535 pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); 527 527 - drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); 528 536 intel_dsc_pps_write(crtc_state, 17, pps_val); 529 537 530 538 /* PPS 18 */ 531 539 pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | 532 540 DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); 533 533 - drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); 534 541 intel_dsc_pps_write(crtc_state, 18, pps_val); 535 542 } 536 543 537 544 /* Populate the RC_BUF_THRESH registers */ 538 545 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 539 539 - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 546 546 + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) 540 547 rc_buf_thresh_dword[i / 4] |= 541 548 (u32)(vdsc_cfg->rc_buf_thresh[i] << 542 549 BITS_PER_BYTE * (i % 4)); 543 543 - drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i, 544 544 - rc_buf_thresh_dword[i / 4]); 545 545 - } 546 550 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 547 551 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 548 552 rc_buf_thresh_dword[0]); ··· 583 599 584 600 /* Populate the RC_RANGE_PARAMETERS registers */ 585 601 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 586 586 - for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 602 602 + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) 587 603 rc_range_params_dword[i / 2] |= 588 604 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 589 605 RC_BPG_OFFSET_SHIFT) | ··· 591 607 RC_MAX_QP_SHIFT) | 592 608 (vdsc_cfg->rc_range_params[i].range_min_qp << 593 609 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 594 594 - drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i, 595 595 - rc_range_params_dword[i / 2]); 596 596 - } 597 610 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 598 611 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 599 612 rc_range_params_dword[0]); ··· 969 988 intel_dsc_get_pps_config(crtc_state); 970 989 out: 971 990 intel_display_power_put(dev_priv, power_domain, wakeref); 991 991 + } 992 992 + 993 993 + static void intel_vdsc_dump_state(struct drm_printer *p, int indent, 994 994 + const struct intel_crtc_state *crtc_state) 995 995 + { 996 996 + drm_printf_indent(p, indent, 997 997 + "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n", 998 998 + FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), 999 999 + crtc_state->dsc.slice_count, 1000 1000 + str_yes_no(crtc_state->dsc.dsc_split)); 1001 1001 + } 1002 1002 + 1003 1003 + void intel_vdsc_state_dump(struct drm_printer *p, int indent, 1004 1004 + const struct intel_crtc_state *crtc_state) 1005 1005 + { 1006 1006 + if (!crtc_state->dsc.compression_enable) 1007 1007 + return; 1008 1008 + 1009 1009 + intel_vdsc_dump_state(p, indent, crtc_state); 1010 1010 + drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); 972 1011 }

+4

drivers/gpu/drm/i915/display/intel_vdsc.h

reviewed

··· 8 8 9 9 #include <linux/types.h> 10 10 11 11 + struct drm_printer; 12 12 + 11 13 enum transcoder; 12 14 struct intel_crtc; 13 15 struct intel_crtc_state; ··· 29 27 const struct intel_crtc_state *crtc_state); 30 28 void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 31 29 const struct intel_crtc_state *crtc_state); 30 30 + void intel_vdsc_state_dump(struct drm_printer *p, int indent, 31 31 + const struct intel_crtc_state *crtc_state); 32 32 33 33 #endif /* __INTEL_VDSC_H__ */

+1 -2

drivers/gpu/drm/i915/display/intel_vrr.c

reviewed

··· 233 233 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 234 234 } 235 235 236 236 - if (intel_dp_as_sdp_supported(intel_dp) && 237 237 - crtc_state->vrr.enable) { 236 236 + if (intel_dp->as_sdp_supported && crtc_state->vrr.enable) { 238 237 crtc_state->vrr.vsync_start = 239 238 (crtc_state->hw.adjusted_mode.crtc_vtotal - 240 239 crtc_state->hw.adjusted_mode.vsync_start);

+13 -11

drivers/gpu/drm/i915/display/skl_watermark.c

reviewed

··· 2830 2830 } 2831 2831 2832 2832 /* 2833 2833 - * If Fixed Refresh Rate: 2833 2833 + * If Fixed Refresh Rate or For VRR case Vmin = Vmax = Flipline: 2834 2834 * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from 2835 2835 * watermark level1 and up and above. If watermark level 1 is 2836 2836 * invalid program it with all 1's. 2837 2837 * Program PKG_C_LATENCY Added Wake Time = DSB execution time 2838 2838 - * If Variable Refresh Rate: 2838 2838 + * If Variable Refresh Rate where Vmin != Vmax != Flipline: 2839 2839 * Program DEEP PKG_C_LATENCY Pkg C with all 1's. 2840 2840 * Program PKG_C_LATENCY Added Wake Time = 0 2841 2841 */ 2842 2842 static void 2843 2843 - skl_program_dpkgc_latency(struct drm_i915_private *i915, bool vrr_enabled) 2843 2843 + skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc) 2844 2844 { 2845 2845 u32 max_latency = 0; 2846 2846 u32 clear = 0, val = 0; ··· 2849 2849 if (DISPLAY_VER(i915) < 20) 2850 2850 return; 2851 2851 2852 2852 - if (vrr_enabled) { 2853 2853 - max_latency = LNL_PKG_C_LATENCY_MASK; 2854 2854 - added_wake_time = 0; 2855 2855 - } else { 2852 2852 + if (enable_dpkgc) { 2856 2853 max_latency = skl_watermark_max_latency(i915, 1); 2857 2854 if (max_latency == 0) 2858 2855 max_latency = LNL_PKG_C_LATENCY_MASK; 2859 2856 added_wake_time = DSB_EXE_TIME + 2860 2857 i915->display.sagv.block_time_us; 2858 2858 + } else { 2859 2859 + max_latency = LNL_PKG_C_LATENCY_MASK; 2860 2860 + added_wake_time = 0; 2861 2861 } 2862 2862 2863 2863 clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; ··· 2873 2873 struct intel_crtc *crtc; 2874 2874 struct intel_crtc_state __maybe_unused *new_crtc_state; 2875 2875 int ret, i; 2876 2876 - bool vrr_enabled = false; 2876 2876 + bool enable_dpkgc = false; 2877 2877 2878 2878 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2879 2879 ret = skl_build_pipe_wm(state, crtc); ··· 2899 2899 if (ret) 2900 2900 return ret; 2901 2901 2902 2902 - if (new_crtc_state->vrr.enable) 2903 2903 - vrr_enabled = true; 2902 2902 + if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && 2903 2903 + new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || 2904 2904 + !new_crtc_state->vrr.enable) 2905 2905 + enable_dpkgc = true; 2904 2906 } 2905 2907 2906 2906 - skl_program_dpkgc_latency(to_i915(state->base.dev), vrr_enabled); 2908 2908 + skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc); 2907 2909 2908 2910 skl_print_wm_changes(state); 2909 2911

+3 -2

drivers/gpu/drm/i915/display/vlv_dsi.c

reviewed

··· 1880 1880 1881 1881 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1882 1882 { 1883 1883 + struct intel_display *display = &dev_priv->display; 1883 1884 struct intel_dsi *intel_dsi; 1884 1885 struct intel_encoder *encoder; 1885 1886 struct intel_connector *connector; ··· 1892 1891 drm_dbg_kms(&dev_priv->drm, "\n"); 1893 1892 1894 1893 /* There is no detection method for MIPI so rely on VBT */ 1895 1895 - if (!intel_bios_is_dsi_present(dev_priv, &port)) 1894 1894 + if (!intel_bios_is_dsi_present(display, &port)) 1896 1895 return; 1897 1896 1898 1897 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) ··· 1947 1946 1948 1947 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1949 1948 1950 1950 - intel_bios_init_panel_late(dev_priv, &connector->panel, NULL, NULL); 1949 1949 + intel_bios_init_panel_late(display, &connector->panel, NULL, NULL); 1951 1950 1952 1951 if (connector->panel.vbt.dsi.config->dual_link) 1953 1952 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);

+14 -14

drivers/gpu/drm/i915/gvt/edid.c

reviewed

··· 42 42 #define GMBUS1_TOTAL_BYTES_MASK 0x1ff 43 43 #define gmbus1_total_byte_count(v) (((v) >> \ 44 44 GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK) 45 45 - #define gmbus1_slave_addr(v) (((v) & 0xff) >> 1) 46 46 - #define gmbus1_slave_index(v) (((v) >> 8) & 0xff) 45 45 + #define gmbus1_target_addr(v) (((v) & 0xff) >> 1) 46 46 + #define gmbus1_target_index(v) (((v) >> 8) & 0xff) 47 47 #define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7) 48 48 49 49 /* GMBUS0 bits definitions */ ··· 54 54 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid; 55 55 unsigned char chr = 0; 56 56 57 57 - if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) { 57 57 + if (edid->state == I2C_NOT_SPECIFIED || !edid->target_selected) { 58 58 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n"); 59 59 return 0; 60 60 } ··· 179 179 void *p_data, unsigned int bytes) 180 180 { 181 181 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; 182 182 - u32 slave_addr; 182 182 + u32 target_addr; 183 183 u32 wvalue = *(u32 *)p_data; 184 184 185 185 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) { ··· 210 210 211 211 i2c_edid->gmbus.total_byte_count = 212 212 gmbus1_total_byte_count(wvalue); 213 213 - slave_addr = gmbus1_slave_addr(wvalue); 213 213 + target_addr = gmbus1_target_addr(wvalue); 214 214 215 215 /* vgpu gmbus only support EDID */ 216 216 - if (slave_addr == EDID_ADDR) { 217 217 - i2c_edid->slave_selected = true; 218 218 - } else if (slave_addr != 0) { 216 216 + if (target_addr == EDID_ADDR) { 217 217 + i2c_edid->target_selected = true; 218 218 + } else if (target_addr != 0) { 219 219 gvt_dbg_dpy( 220 220 - "vgpu%d: unsupported gmbus slave addr(0x%x)\n" 220 220 + "vgpu%d: unsupported gmbus target addr(0x%x)\n" 221 221 " gmbus operations will be ignored.\n", 222 222 - vgpu->id, slave_addr); 222 222 + vgpu->id, target_addr); 223 223 } 224 224 225 225 if (wvalue & GMBUS_CYCLE_INDEX) 226 226 i2c_edid->current_edid_read = 227 227 - gmbus1_slave_index(wvalue); 227 227 + gmbus1_target_index(wvalue); 228 228 229 229 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue); 230 230 switch (gmbus1_bus_cycle(wvalue)) { ··· 523 523 } else if (addr == EDID_ADDR) { 524 524 i2c_edid->state = I2C_AUX_CH; 525 525 i2c_edid->port = port_idx; 526 526 - i2c_edid->slave_selected = true; 526 526 + i2c_edid->target_selected = true; 527 527 if (intel_vgpu_has_monitor_on_port(vgpu, 528 528 port_idx) && 529 529 intel_vgpu_port_is_dp(vgpu, port_idx)) ··· 542 542 return; 543 543 if (drm_WARN_ON(&i915->drm, msg_length != 4)) 544 544 return; 545 545 - if (i2c_edid->edid_available && i2c_edid->slave_selected) { 545 545 + if (i2c_edid->edid_available && i2c_edid->target_selected) { 546 546 unsigned char val = edid_get_byte(vgpu); 547 547 548 548 aux_data_for_write = (val << 16); ··· 571 571 edid->state = I2C_NOT_SPECIFIED; 572 572 573 573 edid->port = -1; 574 574 - edid->slave_selected = false; 574 574 + edid->target_selected = false; 575 575 edid->edid_available = false; 576 576 edid->current_edid_read = 0; 577 577

+2 -2

drivers/gpu/drm/i915/gvt/edid.h

reviewed

··· 80 80 * R/W Protect 81 81 * Command and Status. 82 82 * bit0 is the direction bit: 1 is read; 0 is write. 83 83 - * bit1 - bit7 is slave 7-bit address. 83 83 + * bit1 - bit7 is target 7-bit address. 84 84 * bit16 - bit24 total byte count (ignore?) 85 85 * 86 86 * GMBUS2: ··· 130 130 enum i2c_state state; 131 131 132 132 unsigned int port; 133 133 - bool slave_selected; 133 133 + bool target_selected; 134 134 bool edid_available; 135 135 unsigned int current_edid_read; 136 136

+1 -1

drivers/gpu/drm/i915/gvt/opregion.c

reviewed

··· 86 86 u8 skip2; 87 87 u8 dvo_port; 88 88 u8 i2c_pin; /* for add-in card */ 89 89 - u8 slave_addr; /* for add-in card */ 89 89 + u8 target_addr; /* for add-in card */ 90 90 u8 ddc_pin; 91 91 u16 edid_ptr; 92 92 u8 dvo_config;

+1 -1

drivers/gpu/drm/i915/gvt/trace.h

reviewed

··· 227 227 #define GVT_CMD_STR_LEN 40 228 228 TRACE_EVENT(gvt_command, 229 229 TP_PROTO(u8 vgpu_id, u8 ring_id, u32 ip_gma, u32 *cmd_va, 230 230 - u32 cmd_len, u32 buf_type, u32 buf_addr_type, 230 230 + u32 cmd_len, u32 buf_type, u32 buf_addr_type, 231 231 void *workload, const char *cmd_name), 232 232 233 233 TP_ARGS(vgpu_id, ring_id, ip_gma, cmd_va, cmd_len, buf_type,

+21 -15

drivers/gpu/drm/i915/i915_driver.c

reviewed

··· 442 442 */ 443 443 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 444 444 { 445 445 + struct intel_display *display = &dev_priv->display; 445 446 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 446 447 int ret; 447 448 ··· 452 451 if (HAS_PPGTT(dev_priv)) { 453 452 if (intel_vgpu_active(dev_priv) && 454 453 !intel_vgpu_has_full_ppgtt(dev_priv)) { 455 455 - i915_report_error(dev_priv, 456 456 - "incompatible vGPU found, support for isolated ppGTT required\n"); 454 454 + drm_err(&dev_priv->drm, 455 455 + "incompatible vGPU found, support for isolated ppGTT required\n"); 457 456 return -ENXIO; 458 457 } 459 458 } ··· 466 465 */ 467 466 if (intel_vgpu_active(dev_priv) && 468 467 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 469 469 - i915_report_error(dev_priv, 470 470 - "old vGPU host found, support for HWSP emulation required\n"); 468 468 + drm_err(&dev_priv->drm, 469 469 + "old vGPU host found, support for HWSP emulation required\n"); 471 470 return -ENXIO; 472 471 } 473 472 } ··· 543 542 if (ret) 544 543 goto err_msi; 545 544 546 546 - intel_opregion_setup(dev_priv); 545 545 + intel_opregion_setup(display); 547 546 548 547 ret = i915_pcode_init(dev_priv); 549 548 if (ret) ··· 560 559 return 0; 561 560 562 561 err_opregion: 563 563 - intel_opregion_cleanup(dev_priv); 562 562 + intel_opregion_cleanup(display); 564 563 err_msi: 565 564 if (pdev->msi_enabled) 566 565 pci_disable_msi(pdev); ··· 581 580 */ 582 581 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 583 582 { 583 583 + struct intel_display *display = &dev_priv->display; 584 584 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 585 585 586 586 i915_perf_fini(dev_priv); 587 587 588 588 - intel_opregion_cleanup(dev_priv); 588 588 + intel_opregion_cleanup(display); 589 589 590 590 if (pdev->msi_enabled) 591 591 pci_disable_msi(pdev); ··· 1016 1014 static int i915_drm_suspend(struct drm_device *dev) 1017 1015 { 1018 1016 struct drm_i915_private *dev_priv = to_i915(dev); 1017 1017 + struct intel_display *display = &dev_priv->display; 1019 1018 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1020 1019 pci_power_t opregion_target_state; 1021 1020 ··· 1052 1049 i915_save_display(dev_priv); 1053 1050 1054 1051 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1055 1055 - intel_opregion_suspend(dev_priv, opregion_target_state); 1052 1052 + intel_opregion_suspend(display, opregion_target_state); 1056 1053 1057 1054 dev_priv->suspend_count++; 1058 1055 ··· 1141 1138 static int i915_drm_resume(struct drm_device *dev) 1142 1139 { 1143 1140 struct drm_i915_private *dev_priv = to_i915(dev); 1141 1141 + struct intel_display *display = &dev_priv->display; 1144 1142 struct intel_gt *gt; 1145 1143 int ret, i; 1146 1144 ··· 1209 1205 } 1210 1206 intel_hpd_poll_disable(dev_priv); 1211 1207 1212 1212 - intel_opregion_resume(dev_priv); 1208 1208 + intel_opregion_resume(display); 1213 1209 1214 1210 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1215 1211 ··· 1458 1454 static int intel_runtime_suspend(struct device *kdev) 1459 1455 { 1460 1456 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1457 1457 + struct intel_display *display = &dev_priv->display; 1461 1458 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1462 1459 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1463 1460 struct pci_dev *root_pdev; ··· 1533 1528 * won't be able to restore them. Since PCI_D3hot matches the 1534 1529 * actual specification and appears to be working, use it. 1535 1530 */ 1536 1536 - intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1531 1531 + intel_opregion_notify_adapter(display, PCI_D3hot); 1537 1532 } else { 1538 1533 /* 1539 1534 * current versions of firmware which depend on this opregion ··· 1542 1537 * to distinguish it from notifications that might be sent via 1543 1538 * the suspend path. 1544 1539 */ 1545 1545 - intel_opregion_notify_adapter(dev_priv, PCI_D1); 1540 1540 + intel_opregion_notify_adapter(display, PCI_D1); 1546 1541 } 1547 1542 1548 1543 assert_forcewakes_inactive(&dev_priv->uncore); ··· 1557 1552 static int intel_runtime_resume(struct device *kdev) 1558 1553 { 1559 1554 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1555 1555 + struct intel_display *display = &dev_priv->display; 1560 1556 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1561 1557 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1562 1558 struct pci_dev *root_pdev; ··· 1572 1566 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1573 1567 disable_rpm_wakeref_asserts(rpm); 1574 1568 1575 1575 - intel_opregion_notify_adapter(dev_priv, PCI_D0); 1569 1569 + intel_opregion_notify_adapter(display, PCI_D0); 1576 1570 1577 1571 root_pdev = pcie_find_root_port(pdev); 1578 1572 if (root_pdev) ··· 1699 1693 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1700 1694 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1701 1695 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1702 1702 - DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1703 1703 - DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1704 1704 - DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1696 1696 + DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1697 1697 + DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1698 1698 + DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1705 1699 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1706 1700 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1707 1701 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),

-3

drivers/gpu/drm/i915/i915_drv.h

reviewed

··· 678 678 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ 679 679 }) 680 680 681 681 - /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 682 682 - #define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915)) 683 683 - 684 681 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ 685 682 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) 686 683

+3 -3

drivers/gpu/drm/i915/i915_pci.c

reviewed

··· 880 880 { 881 881 struct drm_i915_private *i915; 882 882 883 883 - i915 = pci_get_drvdata(pdev); 883 883 + i915 = pdev_to_i915(pdev); 884 884 if (!i915) /* driver load aborted, nothing to cleanup */ 885 885 return; 886 886 ··· 1003 1003 if (err) 1004 1004 return err; 1005 1005 1006 1006 - if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1006 1006 + if (i915_inject_probe_failure(pdev_to_i915(pdev))) { 1007 1007 i915_pci_remove(pdev); 1008 1008 return -ENODEV; 1009 1009 } ··· 1025 1025 1026 1026 static void i915_pci_shutdown(struct pci_dev *pdev) 1027 1027 { 1028 1028 - struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1028 1028 + struct drm_i915_private *i915 = pdev_to_i915(pdev); 1029 1029 1030 1030 i915_driver_shutdown(i915); 1031 1031 }

+2

drivers/gpu/drm/i915/i915_reg.h

reviewed

··· 2396 2396 2397 2397 /* Display Internal Timeout Register */ 2398 2398 #define RM_TIMEOUT _MMIO(0x42060) 2399 2399 + #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0) 2399 2400 #define MMIO_TIMEOUT_US(us) ((us) << 0) 2400 2401 2401 2402 /* interrupts */ ··· 2575 2574 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 2576 2575 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 2577 2576 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 2577 2577 + #define XELPDP_RM_TIMEOUT REG_BIT(29) 2578 2578 #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27) 2579 2579 #define GEN8_DE_MISC_GSE REG_BIT(27) 2580 2580 #define GEN8_DE_EDP_PSR REG_BIT(19)

+2 -2

drivers/gpu/drm/i915/i915_sysfs.c

reviewed

··· 191 191 192 192 i915_gpu_error_sysfs_teardown(dev_priv); 193 193 194 194 - device_remove_bin_file(kdev, &dpf_attrs_1); 195 195 - device_remove_bin_file(kdev, &dpf_attrs); 194 194 + device_remove_bin_file(kdev, &dpf_attrs_1); 195 195 + device_remove_bin_file(kdev, &dpf_attrs); 196 196 197 197 kobject_put(dev_priv->sysfs_gt); 198 198 }

+5 -46

drivers/gpu/drm/i915/i915_utils.c

reviewed

··· 11 11 #include "i915_reg.h" 12 12 #include "i915_utils.h" 13 13 14 14 - #define FDO_BUG_MSG "Please file a bug on drm/i915; see " FDO_BUG_URL " for details." 15 15 - 16 16 - void 17 17 - __i915_printk(struct drm_i915_private *dev_priv, const char *level, 18 18 - const char *fmt, ...) 19 19 - { 20 20 - static bool shown_bug_once; 21 21 - struct device *kdev = dev_priv->drm.dev; 22 22 - bool is_error = level[1] <= KERN_ERR[1]; 23 23 - bool is_debug = level[1] == KERN_DEBUG[1]; 24 24 - struct va_format vaf; 25 25 - va_list args; 26 26 - 27 27 - if (is_debug && !drm_debug_enabled(DRM_UT_DRIVER)) 28 28 - return; 29 29 - 30 30 - va_start(args, fmt); 31 31 - 32 32 - vaf.fmt = fmt; 33 33 - vaf.va = &args; 34 34 - 35 35 - if (is_error) 36 36 - dev_printk(level, kdev, "%pV", &vaf); 37 37 - else 38 38 - dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV", 39 39 - __builtin_return_address(0), &vaf); 40 40 - 41 41 - va_end(args); 42 42 - 43 43 - if (is_error && !shown_bug_once) { 44 44 - /* 45 45 - * Ask the user to file a bug report for the error, except 46 46 - * if they may have caused the bug by fiddling with unsafe 47 47 - * module parameters. 48 48 - */ 49 49 - if (!test_taint(TAINT_USER)) 50 50 - dev_notice(kdev, "%s", FDO_BUG_MSG); 51 51 - shown_bug_once = true; 52 52 - } 53 53 - } 54 54 - 55 14 void add_taint_for_CI(struct drm_i915_private *i915, unsigned int taint) 56 15 { 57 57 - __i915_printk(i915, KERN_NOTICE, "CI tainted:%#x by %pS\n", 58 58 - taint, (void *)_RET_IP_); 16 16 + drm_notice(&i915->drm, "CI tainted: %#x by %pS\n", 17 17 + taint, __builtin_return_address(0)); 59 18 60 19 /* Failures that occur during fault injection testing are expected */ 61 20 if (!i915_error_injected()) ··· 33 74 if (++i915_probe_fail_count < i915_modparams.inject_probe_failure) 34 75 return 0; 35 76 36 36 - __i915_printk(i915, KERN_INFO, 37 37 - "Injecting failure %d at checkpoint %u [%s:%d]\n", 38 38 - err, i915_modparams.inject_probe_failure, func, line); 77 77 + drm_info(&i915->drm, "Injecting failure %d at checkpoint %u [%s:%d]\n", 78 78 + err, i915_modparams.inject_probe_failure, func, line); 79 79 + 39 80 i915_modparams.inject_probe_failure = 0; 40 81 return err; 41 82 }

+6 -10

drivers/gpu/drm/i915/i915_utils.h

reviewed

··· 45 45 #define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ 46 46 __stringify(x), (long)(x)) 47 47 48 48 - void __printf(3, 4) 49 49 - __i915_printk(struct drm_i915_private *dev_priv, const char *level, 50 50 - const char *fmt, ...); 51 51 - 52 52 - #define i915_report_error(dev_priv, fmt, ...) \ 53 53 - __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) 54 54 - 55 48 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) 56 49 57 50 int __i915_inject_probe_error(struct drm_i915_private *i915, int err, ··· 62 69 63 70 #define i915_inject_probe_failure(i915) i915_inject_probe_error((i915), -ENODEV) 64 71 65 65 - #define i915_probe_error(i915, fmt, ...) \ 66 66 - __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \ 67 67 - fmt, ##__VA_ARGS__) 72 72 + #define i915_probe_error(i915, fmt, ...) ({ \ 73 73 + if (i915_error_injected()) \ 74 74 + drm_dbg(&(i915)->drm, fmt, ##__VA_ARGS__); \ 75 75 + else \ 76 76 + drm_err(&(i915)->drm, fmt, ##__VA_ARGS__); \ 77 77 + }) 68 78 69 79 #define range_overflows(start, size, max) ({ \ 70 80 typeof(start) start__ = (start); \

+15 -5

drivers/gpu/drm/xe/display/xe_display.c

reviewed

··· 127 127 static void xe_display_fini_noirq(void *arg) 128 128 { 129 129 struct xe_device *xe = arg; 130 130 + struct intel_display *display = &xe->display; 130 131 131 132 if (!xe->info.enable_display) 132 133 return; 133 134 134 135 intel_display_driver_remove_noirq(xe); 136 136 + intel_opregion_cleanup(display); 135 137 } 136 138 137 139 int xe_display_init_noirq(struct xe_device *xe) 138 140 { 141 141 + struct intel_display *display = &xe->display; 139 142 int err; 140 143 141 144 if (!xe->info.enable_display) ··· 147 144 intel_display_driver_early_probe(xe); 148 145 149 146 /* Early display init.. */ 150 150 - intel_opregion_setup(xe); 147 147 + intel_opregion_setup(display); 151 148 152 149 /* 153 150 * Fill the dram structure to get the system dram info. This will be ··· 160 157 intel_display_device_info_runtime_init(xe); 161 158 162 159 err = intel_display_driver_probe_noirq(xe); 163 163 - if (err) 160 160 + if (err) { 161 161 + intel_opregion_cleanup(display); 164 162 return err; 163 163 + } 165 164 166 165 return devm_add_action_or_reset(xe->drm.dev, xe_display_fini_noirq, xe); 167 166 } ··· 252 247 253 248 void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir) 254 249 { 250 250 + struct intel_display *display = &xe->display; 251 251 + 255 252 if (!xe->info.enable_display) 256 253 return; 257 254 258 255 if (gu_misc_iir & GU_MISC_GSE) 259 259 - intel_opregion_asle_intr(xe); 256 256 + intel_opregion_asle_intr(display); 260 257 } 261 258 262 259 void xe_display_irq_reset(struct xe_device *xe) ··· 289 282 290 283 void xe_display_pm_suspend(struct xe_device *xe, bool runtime) 291 284 { 285 285 + struct intel_display *display = &xe->display; 292 286 bool s2idle = suspend_to_idle(); 293 287 if (!xe->info.enable_display) 294 288 return; ··· 311 303 312 304 intel_encoder_suspend_all(&xe->display); 313 305 314 314 - intel_opregion_suspend(xe, s2idle ? PCI_D1 : PCI_D3cold); 306 306 + intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold); 315 307 316 308 intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true); 317 309 ··· 341 333 342 334 void xe_display_pm_resume(struct xe_device *xe, bool runtime) 343 335 { 336 336 + struct intel_display *display = &xe->display; 337 337 + 344 338 if (!xe->info.enable_display) 345 339 return; 346 340 ··· 363 353 if (has_display(xe)) 364 354 drm_kms_helper_poll_enable(&xe->drm); 365 355 366 366 - intel_opregion_resume(xe); 356 356 + intel_opregion_resume(display); 367 357 368 358 intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_RUNNING, false); 369 359

+6 -2

drivers/gpu/drm/xe/display/xe_hdcp_gsc.c

reviewed

··· 40 40 { 41 41 struct xe_tile *tile = xe_device_get_root_tile(xe); 42 42 struct xe_gt *gt = tile->media_gt; 43 43 + struct xe_gsc *gsc = &gt->uc.gsc; 43 44 bool ret = true; 44 45 45 45 - if (!xe_uc_fw_is_enabled(&gt->uc.gsc.fw)) 46 46 + if (!gsc && !xe_uc_fw_is_enabled(&gsc->fw)) { 47 47 + drm_dbg_kms(&xe->drm, 48 48 + "GSC Components not ready for HDCP2.x\n"); 46 49 return false; 50 50 + } 47 51 48 52 xe_pm_runtime_get(xe); 49 53 if (xe_force_wake_get(gt_to_fw(gt), XE_FW_GSC)) { ··· 57 53 goto out; 58 54 } 59 55 60 60 - if (!xe_gsc_proxy_init_done(&gt->uc.gsc)) 56 56 + if (!xe_gsc_proxy_init_done(gsc)) 61 57 ret = false; 62 58 63 59 xe_force_wake_put(gt_to_fw(gt), XE_FW_GSC);

+2

include/drm/display/drm_dp_mst_helper.h

reviewed

··· 885 885 void drm_dp_mst_dump_topology(struct seq_file *m, 886 886 struct drm_dp_mst_topology_mgr *mgr); 887 887 888 888 + void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr); 889 889 + 888 890 void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr); 889 891 int __must_check 890 892 drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr,