Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2021-02-12' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Regular fixes for final, there is a ttm regression fix, dp-mst fix,
one amdgpu revert, two i915 fixes, and some misc fixes for sun4i,
xlnx, and vc4.
All pretty quiet and don't think we have any known outstanding
regressions.
ttm:
- page pool regression fix.
dp_mst:
- don't report un-attached ports as connected
amdgpu:
- blank screen fix
i915:
- ensure Type-C FIA is powered when initializing
- fix overlay frontbuffer tracking
sun4i:
- tcon1 sync polarity fix
- always set HDMI clock rate
- fix H6 HDMI PHY config
- fix H6 max frequency
vc4:
- fix buffer overflow
xlnx:
- fix memory leak"
* tag 'drm-fixes-2021-02-12' of git://anongit.freedesktop.org/drm/drm:
drm/ttm: make sure pool pages are cleared
drm/sun4i: dw-hdmi: Fix max. frequency for H6
drm/sun4i: Fix H6 HDMI PHY configuration
drm/sun4i: dw-hdmi: always set clock rate
drm/sun4i: tcon: set sync polarity for tcon1 channel
drm/i915: Fix overlay frontbuffer tracking
Revert "drm/amd/display: Update NV1x SR latency values"
drm/i915/tgl+: Make sure TypeC FIA is powered up when initializing it
drm/dp_mst: Don't report ports connected if nothing is attached to them
drm/xlnx: fix kmemleak by sending vblank_event in atomic_disable
drm/vc4: hvs: Fix buffer overflow with the dlist handling
+122
-78
+2
-2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+2
-2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
···
297
297
},
298
298
},
299
299
.num_states = 5,
300
-
.sr_exit_time_us = 11.6,
301
-
.sr_enter_plus_exit_time_us = 13.9,
300
+
.sr_exit_time_us = 8.6,
301
+
.sr_enter_plus_exit_time_us = 10.9,
302
302
.urgent_latency_us = 4.0,
303
303
.urgent_latency_pixel_data_only_us = 4.0,
304
304
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+1
drivers/gpu/drm/drm_dp_mst_topology.c
+1
drivers/gpu/drm/drm_dp_mst_topology.c
+8
-9
drivers/gpu/drm/i915/display/intel_overlay.c
+8
-9
drivers/gpu/drm/i915/display/intel_overlay.c
···
182
182
struct intel_crtc *crtc;
183
183
struct i915_vma *vma;
184
184
struct i915_vma *old_vma;
185
+
struct intel_frontbuffer *frontbuffer;
185
186
bool active;
186
187
bool pfit_active;
187
188
u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
···
283
282
struct i915_vma *vma)
284
283
{
285
284
enum pipe pipe = overlay->crtc->pipe;
286
-
struct intel_frontbuffer *from = NULL, *to = NULL;
285
+
struct intel_frontbuffer *frontbuffer = NULL;
287
286
288
287
drm_WARN_ON(&overlay->i915->drm, overlay->old_vma);
289
288
290
-
if (overlay->vma)
291
-
from = intel_frontbuffer_get(overlay->vma->obj);
292
289
if (vma)
293
-
to = intel_frontbuffer_get(vma->obj);
290
+
frontbuffer = intel_frontbuffer_get(vma->obj);
294
291
295
-
intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe));
292
+
intel_frontbuffer_track(overlay->frontbuffer, frontbuffer,
293
+
INTEL_FRONTBUFFER_OVERLAY(pipe));
296
294
297
-
if (to)
298
-
intel_frontbuffer_put(to);
299
-
if (from)
300
-
intel_frontbuffer_put(from);
295
+
if (overlay->frontbuffer)
296
+
intel_frontbuffer_put(overlay->frontbuffer);
297
+
overlay->frontbuffer = frontbuffer;
301
298
302
299
intel_frontbuffer_flip_prepare(overlay->i915,
303
300
INTEL_FRONTBUFFER_OVERLAY(pipe));
+37
-30
drivers/gpu/drm/i915/display/intel_tc.c
+37
-30
drivers/gpu/drm/i915/display/intel_tc.c
···
23
23
return names[mode];
24
24
}
25
25
26
-
static void
27
-
tc_port_load_fia_params(struct drm_i915_private *i915,
28
-
struct intel_digital_port *dig_port)
29
-
{
30
-
enum port port = dig_port->base.port;
31
-
enum tc_port tc_port = intel_port_to_tc(i915, port);
32
-
u32 modular_fia;
33
-
34
-
if (INTEL_INFO(i915)->display.has_modular_fia) {
35
-
modular_fia = intel_uncore_read(&i915->uncore,
36
-
PORT_TX_DFLEXDPSP(FIA1));
37
-
drm_WARN_ON(&i915->drm, modular_fia == 0xffffffff);
38
-
modular_fia &= MODULAR_FIA_MASK;
39
-
} else {
40
-
modular_fia = 0;
41
-
}
42
-
43
-
/*
44
-
* Each Modular FIA instance houses 2 TC ports. In SOC that has more
45
-
* than two TC ports, there are multiple instances of Modular FIA.
46
-
*/
47
-
if (modular_fia) {
48
-
dig_port->tc_phy_fia = tc_port / 2;
49
-
dig_port->tc_phy_fia_idx = tc_port % 2;
50
-
} else {
51
-
dig_port->tc_phy_fia = FIA1;
52
-
dig_port->tc_phy_fia_idx = tc_port;
53
-
}
54
-
}
55
-
56
26
static enum intel_display_power_domain
57
27
tc_cold_get_power_domain(struct intel_digital_port *dig_port)
58
28
{
···
614
644
mutex_lock(&dig_port->tc_lock);
615
645
dig_port->tc_link_refcount--;
616
646
mutex_unlock(&dig_port->tc_lock);
647
+
}
648
+
649
+
static bool
650
+
tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
651
+
{
652
+
intel_wakeref_t wakeref;
653
+
u32 val;
654
+
655
+
if (!INTEL_INFO(i915)->display.has_modular_fia)
656
+
return false;
657
+
658
+
wakeref = tc_cold_block(dig_port);
659
+
val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1));
660
+
tc_cold_unblock(dig_port, wakeref);
661
+
662
+
drm_WARN_ON(&i915->drm, val == 0xffffffff);
663
+
664
+
return val & MODULAR_FIA_MASK;
665
+
}
666
+
667
+
static void
668
+
tc_port_load_fia_params(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
669
+
{
670
+
enum port port = dig_port->base.port;
671
+
enum tc_port tc_port = intel_port_to_tc(i915, port);
672
+
673
+
/*
674
+
* Each Modular FIA instance houses 2 TC ports. In SOC that has more
675
+
* than two TC ports, there are multiple instances of Modular FIA.
676
+
*/
677
+
if (tc_has_modular_fia(i915, dig_port)) {
678
+
dig_port->tc_phy_fia = tc_port / 2;
679
+
dig_port->tc_phy_fia_idx = tc_port % 2;
680
+
} else {
681
+
dig_port->tc_phy_fia = FIA1;
682
+
dig_port->tc_phy_fia_idx = tc_port;
683
+
}
617
684
}
618
685
619
686
void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
+25
drivers/gpu/drm/sun4i/sun4i_tcon.c
+25
drivers/gpu/drm/sun4i/sun4i_tcon.c
···
689
689
SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
690
690
SUN4I_TCON1_BASIC5_H_SYNC(hsync));
691
691
692
+
/* Setup the polarity of multiple signals */
693
+
if (tcon->quirks->polarity_in_ch0) {
694
+
val = 0;
695
+
696
+
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
697
+
val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
698
+
699
+
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
700
+
val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
701
+
702
+
regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
703
+
} else {
704
+
/* according to vendor driver, this bit must be always set */
705
+
val = SUN4I_TCON1_IO_POL_UNKNOWN;
706
+
707
+
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
708
+
val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;
709
+
710
+
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
711
+
val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;
712
+
713
+
regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);
714
+
}
715
+
692
716
/* Map output pins to channel 1 */
693
717
regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
694
718
SUN4I_TCON_GCTL_IOMAP_MASK,
···
1541
1517
1542
1518
static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
1543
1519
.has_channel_1 = true,
1520
+
.polarity_in_ch0 = true,
1544
1521
.set_mux = sun8i_r40_tcon_tv_set_mux,
1545
1522
};
1546
1523
+6
drivers/gpu/drm/sun4i/sun4i_tcon.h
+6
drivers/gpu/drm/sun4i/sun4i_tcon.h
···
153
153
#define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff)
154
154
155
155
#define SUN4I_TCON1_IO_POL_REG 0xf0
156
+
/* there is no documentation about this bit */
157
+
#define SUN4I_TCON1_IO_POL_UNKNOWN BIT(26)
158
+
#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE BIT(25)
159
+
#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE BIT(24)
160
+
156
161
#define SUN4I_TCON1_IO_TRI_REG 0xf4
157
162
158
163
#define SUN4I_TCON_ECC_FIFO_REG 0xf8
···
240
235
bool needs_de_be_mux; /* sun6i needs mux to select backend */
241
236
bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
242
237
bool supports_lvds; /* Does the TCON support an LVDS output? */
238
+
bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
243
239
u8 dclk_min_div; /* minimum divider for TCON0 DCLK */
244
240
245
241
/* callback to handle tcon muxing options */
+3
-7
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+3
-7
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
···
21
21
{
22
22
struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder);
23
23
24
-
if (hdmi->quirks->set_rate)
25
-
clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
24
+
clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
26
25
}
27
26
28
27
static const struct drm_encoder_helper_funcs
···
47
48
{
48
49
/*
49
50
* Controller support maximum of 594 MHz, which correlates to
50
-
* 4K@60Hz 4:4:4 or RGB. However, for frequencies greater than
51
-
* 340 MHz scrambling has to be enabled. Because scrambling is
52
-
* not yet implemented, just limit to 340 MHz for now.
51
+
* 4K@60Hz 4:4:4 or RGB.
53
52
*/
54
-
if (mode->clock > 340000)
53
+
if (mode->clock > 594000)
55
54
return MODE_CLOCK_HIGH;
56
55
57
56
return MODE_OK;
···
292
295
293
296
static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
294
297
.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
295
-
.set_rate = true,
296
298
};
297
299
298
300
static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
-1
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-1
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+9
-17
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+9
-17
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
···
104
104
105
105
static const struct dw_hdmi_curr_ctrl sun50i_h6_cur_ctr[] = {
106
106
/* pixelclk bpp8 bpp10 bpp12 */
107
-
{ 25175000, { 0x0000, 0x0000, 0x0000 }, },
108
107
{ 27000000, { 0x0012, 0x0000, 0x0000 }, },
109
-
{ 59400000, { 0x0008, 0x0008, 0x0008 }, },
110
-
{ 72000000, { 0x0008, 0x0008, 0x001b }, },
111
-
{ 74250000, { 0x0013, 0x0013, 0x0013 }, },
112
-
{ 90000000, { 0x0008, 0x001a, 0x001b }, },
113
-
{ 118800000, { 0x001b, 0x001a, 0x001b }, },
114
-
{ 144000000, { 0x001b, 0x001a, 0x0034 }, },
115
-
{ 180000000, { 0x001b, 0x0033, 0x0034 }, },
116
-
{ 216000000, { 0x0036, 0x0033, 0x0034 }, },
117
-
{ 237600000, { 0x0036, 0x0033, 0x001b }, },
118
-
{ 288000000, { 0x0036, 0x001b, 0x001b }, },
119
-
{ 297000000, { 0x0019, 0x001b, 0x0019 }, },
120
-
{ 330000000, { 0x0036, 0x001b, 0x001b }, },
121
-
{ 594000000, { 0x003f, 0x001b, 0x001b }, },
108
+
{ 74250000, { 0x0013, 0x001a, 0x001b }, },
109
+
{ 148500000, { 0x0019, 0x0033, 0x0034 }, },
110
+
{ 297000000, { 0x0019, 0x001b, 0x001b }, },
111
+
{ 594000000, { 0x0010, 0x001b, 0x001b }, },
122
112
{ ~0UL, { 0x0000, 0x0000, 0x0000 }, }
123
113
};
124
114
125
115
static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = {
126
116
/*pixelclk symbol term vlev*/
127
-
{ 74250000, 0x8009, 0x0004, 0x0232},
128
-
{ 148500000, 0x8029, 0x0004, 0x0273},
129
-
{ 594000000, 0x8039, 0x0004, 0x014a},
117
+
{ 27000000, 0x8009, 0x0007, 0x02b0 },
118
+
{ 74250000, 0x8009, 0x0006, 0x022d },
119
+
{ 148500000, 0x8029, 0x0006, 0x0270 },
120
+
{ 297000000, 0x8039, 0x0005, 0x01ab },
121
+
{ 594000000, 0x8029, 0x0000, 0x008a },
130
122
{ ~0UL, 0x0000, 0x0000, 0x0000}
131
123
};
132
124
+10
drivers/gpu/drm/ttm/ttm_pool.c
+10
drivers/gpu/drm/ttm/ttm_pool.c
···
33
33
34
34
#include <linux/module.h>
35
35
#include <linux/dma-mapping.h>
36
+
#include <linux/highmem.h>
36
37
37
38
#ifdef CONFIG_X86
38
39
#include <asm/set_memory.h>
···
219
218
/* Give pages into a specific pool_type */
220
219
static void ttm_pool_type_give(struct ttm_pool_type *pt, struct page *p)
221
220
{
221
+
unsigned int i, num_pages = 1 << pt->order;
222
+
223
+
for (i = 0; i < num_pages; ++i) {
224
+
if (PageHighMem(p))
225
+
clear_highpage(p + i);
226
+
else
227
+
clear_page(page_address(p + i));
228
+
}
229
+
222
230
spin_lock(&pt->lock);
223
231
list_add(&p->lru, &pt->pages);
224
232
spin_unlock(&pt->lock);
+14
-4
drivers/gpu/drm/vc4/vc4_plane.c
+14
-4
drivers/gpu/drm/vc4/vc4_plane.c
···
220
220
__drm_atomic_helper_plane_reset(plane, &vc4_state->base);
221
221
}
222
222
223
-
static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
223
+
static void vc4_dlist_counter_increment(struct vc4_plane_state *vc4_state)
224
224
{
225
225
if (vc4_state->dlist_count == vc4_state->dlist_size) {
226
226
u32 new_size = max(4u, vc4_state->dlist_count * 2);
···
235
235
vc4_state->dlist_size = new_size;
236
236
}
237
237
238
-
vc4_state->dlist[vc4_state->dlist_count++] = val;
238
+
vc4_state->dlist_count++;
239
+
}
240
+
241
+
static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
242
+
{
243
+
unsigned int idx = vc4_state->dlist_count;
244
+
245
+
vc4_dlist_counter_increment(vc4_state);
246
+
vc4_state->dlist[idx] = val;
239
247
}
240
248
241
249
/* Returns the scl0/scl1 field based on whether the dimensions need to
···
986
978
* be set when calling vc4_plane_allocate_lbm().
987
979
*/
988
980
if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
989
-
vc4_state->y_scaling[1] != VC4_SCALING_NONE)
990
-
vc4_state->lbm_offset = vc4_state->dlist_count++;
981
+
vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
982
+
vc4_state->lbm_offset = vc4_state->dlist_count;
983
+
vc4_dlist_counter_increment(vc4_state);
984
+
}
991
985
992
986
if (num_planes > 1) {
993
987
/* Emit Cb/Cr as channel 0 and Y as channel
+7
-8
drivers/gpu/drm/xlnx/zynqmp_disp.c
+7
-8
drivers/gpu/drm/xlnx/zynqmp_disp.c
···
1396
1396
*/
1397
1397
static void zynqmp_disp_disable(struct zynqmp_disp *disp)
1398
1398
{
1399
-
struct drm_crtc *crtc = &disp->crtc;
1400
-
1401
1399
zynqmp_disp_audio_disable(&disp->audio);
1402
1400
1403
1401
zynqmp_disp_avbuf_disable_audio(&disp->avbuf);
1404
1402
zynqmp_disp_avbuf_disable_channels(&disp->avbuf);
1405
1403
zynqmp_disp_avbuf_disable(&disp->avbuf);
1406
-
1407
-
/* Mark the flip is done as crtc is disabled anyway */
1408
-
if (crtc->state->event) {
1409
-
complete_all(crtc->state->event->base.completion);
1410
-
crtc->state->event = NULL;
1411
-
}
1412
1404
}
1413
1405
1414
1406
static inline struct zynqmp_disp *crtc_to_disp(struct drm_crtc *crtc)
···
1490
1498
zynqmp_disp_disable(disp);
1491
1499
1492
1500
drm_crtc_vblank_off(&disp->crtc);
1501
+
1502
+
spin_lock_irq(&crtc->dev->event_lock);
1503
+
if (crtc->state->event) {
1504
+
drm_crtc_send_vblank_event(crtc, crtc->state->event);
1505
+
crtc->state->event = NULL;
1506
+
}
1507
+
spin_unlock_irq(&crtc->dev->event_lock);
1493
1508
1494
1509
clk_disable_unprepare(disp->pclk);
1495
1510
pm_runtime_put_sync(disp->dev);