tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'powerpc-5.2-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc fixes from Michael Ellerman:
"This is a frustratingly large batch at rc5. Some of these were sent
earlier but were missed by me due to being distracted by other things,
and some took a while to track down due to needing manual bisection on
old hardware. But still we clearly need to improve our testing of KVM,
and of 32-bit, so that we catch these earlier.

Summary: seven fixes, all for bugs introduced this cycle.

- The commit to add KASAN support broke booting on 32-bit SMP
machines, due to a refactoring that moved some setup out of the
secondary CPU path.

- A fix for another 32-bit SMP bug introduced by the fast syscall
entry implementation for 32-bit BOOKE. And a build fix for the same
commit.

- Our change to allow the DAWR to be force enabled on Power9
introduced a bug in KVM, where we clobber r3 leading to a host
crash.

- The same commit also exposed a previously unreachable bug in the
nested KVM handling of DAWR, which could lead to an oops in a
nested host.

- One of the DMA reworks broke the b43legacy WiFi driver on some
people's powermacs, fix it by enabling a 30-bit ZONE_DMA on 32-bit.

- A fix for TLB flushing in KVM introduced a new bug, as it neglected
to also flush the ERAT, this could lead to memory corruption in the
guest.

Thanks to: Aaro Koskinen, Christoph Hellwig, Christophe Leroy, Larry
Finger, Michael Neuling, Suraj Jitindar Singh"

* tag 'powerpc-5.2-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
KVM: PPC: Book3S HV: Invalidate ERAT when flushing guest TLB entries
powerpc: enable a 30-bit ZONE_DMA for 32-bit pmac
KVM: PPC: Book3S HV: Only write DAWR[X] when handling h_set_dawr in real mode
KVM: PPC: Book3S HV: Fix r3 corruption in h_set_dabr()
powerpc/32: fix build failure on book3e with KVM
powerpc/booke: fix fast syscall entry on SMP
powerpc/32s: fix initial setup of segment registers on secondary CPU

Linus Torvalds a8282bf0 693cd8ce

+31 -9
+7
arch/powerpc/include/asm/page.h
··· 319 319 #endif /* __ASSEMBLY__ */ 320 320 #include <asm/slice.h> 321 321 322 + /* 323 + * Allow 30-bit DMA for very limited Broadcom wifi chips on many powerbooks. 324 + */ 325 + #ifdef CONFIG_PPC32 326 + #define ARCH_ZONE_DMA_BITS 30 327 + #else 322 328 #define ARCH_ZONE_DMA_BITS 31 329 + #endif 323 330 324 331 #endif /* _ASM_POWERPC_PAGE_H */
+1
arch/powerpc/kernel/head_32.S
··· 752 752 stw r0,0(r3) 753 753 754 754 /* load up the MMU */ 755 + bl load_segment_registers 755 756 bl load_up_mmu 756 757 757 758 /* ptr to phys current thread */
+5 -5
arch/powerpc/kernel/head_booke.h
··· 83 83 SAVE_4GPRS(3, r11); \ 84 84 SAVE_2GPRS(7, r11) 85 85 86 - .macro SYSCALL_ENTRY trapno intno 86 + .macro SYSCALL_ENTRY trapno intno srr1 87 87 mfspr r10, SPRN_SPRG_THREAD 88 88 #ifdef CONFIG_KVM_BOOKE_HV 89 89 BEGIN_FTR_SECTION ··· 94 94 mfspr r11, SPRN_SRR1 95 95 mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */ 96 96 bf 3, 1975f 97 - b kvmppc_handler_BOOKE_INTERRUPT_\intno\()_SPRN_SRR1 97 + b kvmppc_handler_\intno\()_\srr1 98 98 1975: 99 99 mr r12, r13 100 100 lwz r13, THREAD_NORMSAVE(2)(r10) ··· 145 145 tophys(r11,r11) 146 146 addi r11,r11,global_dbcr0@l 147 147 #ifdef CONFIG_SMP 148 - lwz r9,TASK_CPU(r2) 149 - slwi r9,r9,3 150 - add r11,r11,r9 148 + lwz r10, TASK_CPU(r2) 149 + slwi r10, r10, 3 150 + add r11, r11, r10 151 151 #endif 152 152 lwz r12,0(r11) 153 153 mtspr SPRN_DBCR0,r12
+1 -1
arch/powerpc/kernel/head_fsl_booke.S
··· 409 409 410 410 /* System Call Interrupt */ 411 411 START_EXCEPTION(SystemCall) 412 - SYSCALL_ENTRY 0xc00 SYSCALL 412 + SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1 413 413 414 414 /* Auxiliary Processor Unavailable Interrupt */ 415 415 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
+1
arch/powerpc/kvm/book3s_hv_builtin.c
··· 830 830 } 831 831 } 832 832 asm volatile("ptesync": : :"memory"); 833 + asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); 833 834 } 834 835 835 836 void kvmppc_check_need_tlb_flush(struct kvm *kvm, int pcpu,
+13 -2
arch/powerpc/kvm/book3s_hv_rmhandlers.S
··· 2500 2500 LOAD_REG_ADDR(r11, dawr_force_enable) 2501 2501 lbz r11, 0(r11) 2502 2502 cmpdi r11, 0 2503 + bne 3f 2503 2504 li r3, H_HARDWARE 2504 - beqlr 2505 + blr 2506 + 3: 2505 2507 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */ 2506 2508 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW 2507 2509 rlwimi r5, r4, 2, DAWRX_WT 2508 2510 clrrdi r4, r4, 3 2509 2511 std r4, VCPU_DAWR(r3) 2510 2512 std r5, VCPU_DAWRX(r3) 2513 + /* 2514 + * If came in through the real mode hcall handler then it is necessary 2515 + * to write the registers since the return path won't. Otherwise it is 2516 + * sufficient to store then in the vcpu struct as they will be loaded 2517 + * next time the vcpu is run. 2518 + */ 2519 + mfmsr r6 2520 + andi. r6, r6, MSR_DR /* in real mode? */ 2521 + bne 4f 2511 2522 mtspr SPRN_DAWR, r4 2512 2523 mtspr SPRN_DAWRX, r5 2513 - li r3, 0 2524 + 4: li r3, 0 2514 2525 blr 2515 2526 2516 2527 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
+2 -1
arch/powerpc/mm/mem.c
··· 248 248 (long int)((top_of_ram - total_ram) >> 20)); 249 249 250 250 #ifdef CONFIG_ZONE_DMA 251 - max_zone_pfns[ZONE_DMA] = min(max_low_pfn, 0x7fffffffUL >> PAGE_SHIFT); 251 + max_zone_pfns[ZONE_DMA] = min(max_low_pfn, 252 + ((1UL << ARCH_ZONE_DMA_BITS) - 1) >> PAGE_SHIFT); 252 253 #endif 253 254 max_zone_pfns[ZONE_NORMAL] = max_low_pfn; 254 255 #ifdef CONFIG_HIGHMEM
+1
arch/powerpc/platforms/powermac/Kconfig
··· 7 7 select PPC_INDIRECT_PCI if PPC32 8 8 select PPC_MPC106 if PPC32 9 9 select PPC_NATIVE 10 + select ZONE_DMA if PPC32 10 11 default y 11 12 12 13 config PPC_PMAC64