tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2021-04-10' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Was relatively quiet this week, but still a few pulls came in, pretty
much small fixes across the board, a couple of regression fixes in the
amdgpu/radeon code, msm has a few minor fixes across the board, a
panel regression fix also.

amdgpu:
- DCN3 fix
- Fix CAC setting regression for TOPAZ
- Fix ttm regression

radeon:
- Fix ttm regression

msm:
- a5xx/a6xx timestamp fix
- microcode version check
- fail path fix
- block programming fix
- error removal fix

i915:
- Fix invalid access to ACPI _DSM objects

xen:
- Fix use-after-free in xen
- minor duplicate defintion cleanup

vc4:
- Reduce fifo threshold on hvs4 to fix a fifo full error
- minor redunantant assignment cleanup

panel:
- Disable TE support for Droid4 and N950"

* tag 'drm-fixes-2021-04-10' of git://anongit.freedesktop.org/drm/drm:
drm/vc4: crtc: Reduce PV fifo threshold on hvs4
drm/vc4: plane: Remove redundant assignment
drm/amdgpu/smu7: fix CAC setting on TOPAZ
drm/radeon: Fix size overflow
drm/amdgpu: Fix size overflow
drm/i915: Fix invalid access to ACPI _DSM objects
drm/amd/display: Add missing mask for DCN3
drm/panel: panel-dsi-cm: disable TE for now
drm/msm/disp/dpu1: program 3d_merge only if block is attached
drm/msm: a6xx: fix version check for the A650 SQE microcode
drm/msm: Fix a5xx/a6xx timestamps
drm/msm: Fix removal of valid error case when checking speed_bin
drm/msm: Set drvdata to NULL when msm_drm_init() fails
drivers: gpu: drm: xen_drm_front_drm_info is declared twice
gpu/xen: Fix a use after free in xen_drm_drv_init

Linus Torvalds a85f165e 60144b23

+74 -22
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 906 906 907 907 /* Allocate an SG array and squash pages into it */ 908 908 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 909 - ttm->num_pages << PAGE_SHIFT, 909 + (u64)ttm->num_pages << PAGE_SHIFT, 910 910 GFP_KERNEL); 911 911 if (r) 912 912 goto release_sg;
+1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
··· 134 134 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\ 135 135 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK, mask_sh),\ 136 136 HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK_C, mask_sh),\ 137 + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\ 137 138 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ 138 139 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ 139 140 HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
+2 -1
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
··· 1224 1224 (hwmgr->chip_id == CHIP_POLARIS10) || 1225 1225 (hwmgr->chip_id == CHIP_POLARIS11) || 1226 1226 (hwmgr->chip_id == CHIP_POLARIS12) || 1227 - (hwmgr->chip_id == CHIP_TONGA)) 1227 + (hwmgr->chip_id == CHIP_TONGA) || 1228 + (hwmgr->chip_id == CHIP_TOPAZ)) 1228 1229 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); 1229 1230 1230 1231
+20 -2
drivers/gpu/drm/i915/display/intel_acpi.c
··· 84 84 return; 85 85 } 86 86 87 + if (!pkg->package.count) { 88 + DRM_DEBUG_DRIVER("no connection in _DSM\n"); 89 + return; 90 + } 91 + 87 92 connector_count = &pkg->package.elements[0]; 88 93 DRM_DEBUG_DRIVER("MUX info connectors: %lld\n", 89 94 (unsigned long long)connector_count->integer.value); 90 95 for (i = 1; i < pkg->package.count; i++) { 91 96 union acpi_object *obj = &pkg->package.elements[i]; 92 - union acpi_object *connector_id = &obj->package.elements[0]; 93 - union acpi_object *info = &obj->package.elements[1]; 97 + union acpi_object *connector_id; 98 + union acpi_object *info; 99 + 100 + if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count < 2) { 101 + DRM_DEBUG_DRIVER("Invalid object for MUX #%d\n", i); 102 + continue; 103 + } 104 + 105 + connector_id = &obj->package.elements[0]; 106 + info = &obj->package.elements[1]; 107 + if (info->type != ACPI_TYPE_BUFFER || info->buffer.length < 4) { 108 + DRM_DEBUG_DRIVER("Invalid info for MUX obj #%d\n", i); 109 + continue; 110 + } 111 + 94 112 DRM_DEBUG_DRIVER("Connector id: 0x%016llx\n", 95 113 (unsigned long long)connector_id->integer.value); 96 114 DRM_DEBUG_DRIVER(" port id: %s\n",
+2 -2
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
··· 1386 1386 1387 1387 static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 1388 1388 { 1389 - *value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO, 1390 - REG_A5XX_RBBM_PERFCTR_CP_0_HI); 1389 + *value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO, 1390 + REG_A5XX_RBBM_ALWAYSON_COUNTER_HI); 1391 1391 1392 1392 return 0; 1393 1393 }
+12 -6
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 567 567 } else { 568 568 /* 569 569 * a650 tier targets don't need whereami but still need to be 570 - * equal to or newer than 1.95 for other security fixes 570 + * equal to or newer than 0.95 for other security fixes 571 571 */ 572 572 if (adreno_is_a650(adreno_gpu)) { 573 - if ((buf[0] & 0xfff) >= 0x195) { 573 + if ((buf[0] & 0xfff) >= 0x095) { 574 574 ret = true; 575 575 goto out; 576 576 } 577 577 578 578 DRM_DEV_ERROR(&gpu->pdev->dev, 579 579 "a650 SQE ucode is too old. Have version %x need at least %x\n", 580 - buf[0] & 0xfff, 0x195); 580 + buf[0] & 0xfff, 0x095); 581 581 } 582 582 583 583 /* ··· 1228 1228 /* Force the GPU power on so we can read this register */ 1229 1229 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1230 1230 1231 - *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 1232 - REG_A6XX_RBBM_PERFCTR_CP_0_HI); 1231 + *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, 1232 + REG_A6XX_CP_ALWAYS_ON_COUNTER_HI); 1233 1233 1234 1234 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1235 1235 mutex_unlock(&perfcounter_oob); ··· 1406 1406 int ret; 1407 1407 1408 1408 ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin); 1409 - if (ret) { 1409 + /* 1410 + * -ENOENT means that the platform doesn't support speedbin which is 1411 + * fine 1412 + */ 1413 + if (ret == -ENOENT) { 1414 + return 0; 1415 + } else if (ret) { 1410 1416 DRM_DEV_ERROR(dev, 1411 1417 "failed to read speed-bin (%d). Some OPPs may not be supported by hardware", 1412 1418 ret);
+3 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
··· 496 496 497 497 DPU_REG_WRITE(c, CTL_TOP, mode_sel); 498 498 DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); 499 - DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); 499 + if (cfg->merge_3d) 500 + DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, 501 + BIT(cfg->merge_3d - MERGE_3D_0)); 500 502 } 501 503 502 504 static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
+1
drivers/gpu/drm/msm/msm_drv.c
··· 570 570 kfree(priv); 571 571 err_put_drm_dev: 572 572 drm_dev_put(ddev); 573 + platform_set_drvdata(pdev, NULL); 573 574 return ret; 574 575 } 575 576
+9 -3
drivers/gpu/drm/panel/panel-dsi-cm.c
··· 37 37 u32 height_mm; 38 38 u32 max_hs_rate; 39 39 u32 max_lp_rate; 40 + bool te_support; 40 41 }; 41 42 42 43 struct panel_drv_data { ··· 335 334 if (r) 336 335 goto err; 337 336 338 - r = mipi_dsi_dcs_set_tear_on(ddata->dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); 339 - if (r) 340 - goto err; 337 + if (ddata->panel_data->te_support) { 338 + r = mipi_dsi_dcs_set_tear_on(ddata->dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); 339 + if (r) 340 + goto err; 341 + } 341 342 342 343 /* possible panel bug */ 343 344 msleep(100); ··· 622 619 .height_mm = 0, 623 620 .max_hs_rate = 300000000, 624 621 .max_lp_rate = 10000000, 622 + .te_support = true, 625 623 }; 626 624 627 625 static const struct dsic_panel_data himalaya_data = { ··· 633 629 .height_mm = 88, 634 630 .max_hs_rate = 300000000, 635 631 .max_lp_rate = 10000000, 632 + .te_support = false, 636 633 }; 637 634 638 635 static const struct dsic_panel_data droid4_data = { ··· 644 639 .height_mm = 89, 645 640 .max_hs_rate = 300000000, 646 641 .max_lp_rate = 10000000, 642 + .te_support = false, 647 643 }; 648 644 649 645 static const struct of_device_id dsicm_of_match[] = {
+2 -2
drivers/gpu/drm/radeon/radeon_ttm.c
··· 364 364 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { 365 365 /* check that we only pin down anonymous memory 366 366 to prevent problems with writeback */ 367 - unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 367 + unsigned long end = gtt->userptr + (u64)ttm->num_pages * PAGE_SIZE; 368 368 struct vm_area_struct *vma; 369 369 vma = find_vma(gtt->usermm, gtt->userptr); 370 370 if (!vma || vma->vm_file || vma->vm_end < end) ··· 386 386 } while (pinned < ttm->num_pages); 387 387 388 388 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 389 - ttm->num_pages << PAGE_SHIFT, 389 + (u64)ttm->num_pages << PAGE_SHIFT, 390 390 GFP_KERNEL); 391 391 if (r) 392 392 goto release_sg;
+17
drivers/gpu/drm/vc4/vc4_crtc.c
··· 210 210 { 211 211 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc); 212 212 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 213 + struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev); 213 214 u32 fifo_len_bytes = pv_data->fifo_depth; 214 215 215 216 /* ··· 238 237 */ 239 238 if (crtc_data->hvs_output == 5) 240 239 return 32; 240 + 241 + /* 242 + * It looks like in some situations, we will overflow 243 + * the PixelValve FIFO (with the bit 10 of PV stat being 244 + * set) and stall the HVS / PV, eventually resulting in 245 + * a page flip timeout. 246 + * 247 + * Displaying the video overlay during a playback with 248 + * Kodi on an RPi3 seems to be a great solution with a 249 + * failure rate around 50%. 250 + * 251 + * Removing 1 from the FIFO full level however 252 + * seems to completely remove that issue. 253 + */ 254 + if (!vc4->hvs->hvs5) 255 + return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1; 241 256 242 257 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX; 243 258 }
-1
drivers/gpu/drm/vc4/vc4_plane.c
··· 1146 1146 plane->state->src_y = state->src_y; 1147 1147 plane->state->src_w = state->src_w; 1148 1148 plane->state->src_h = state->src_h; 1149 - plane->state->src_h = state->src_h; 1150 1149 plane->state->alpha = state->alpha; 1151 1150 plane->state->pixel_blend_mode = state->pixel_blend_mode; 1152 1151 plane->state->rotation = state->rotation;
+4 -2
drivers/gpu/drm/xen/xen_drm_front.c
··· 521 521 drm_dev = drm_dev_alloc(&xen_drm_driver, dev); 522 522 if (IS_ERR(drm_dev)) { 523 523 ret = PTR_ERR(drm_dev); 524 - goto fail; 524 + goto fail_dev; 525 525 } 526 526 527 527 drm_info->drm_dev = drm_dev; ··· 551 551 drm_kms_helper_poll_fini(drm_dev); 552 552 drm_mode_config_cleanup(drm_dev); 553 553 drm_dev_put(drm_dev); 554 - fail: 554 + fail_dev: 555 555 kfree(drm_info); 556 + front_info->drm_info = NULL; 557 + fail: 556 558 return ret; 557 559 } 558 560
-1
drivers/gpu/drm/xen/xen_drm_front_conn.h
··· 16 16 struct drm_connector; 17 17 struct xen_drm_front_drm_info; 18 18 19 - struct xen_drm_front_drm_info; 20 19 21 20 int xen_drm_front_conn_init(struct xen_drm_front_drm_info *drm_info, 22 21 struct drm_connector *connector);