Merge tag 'mmc-v6.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

+43 -35

drivers/mmc/host/moxart-mmc.c

··· 131 131 struct dma_async_tx_descriptor *tx_desc; 132 132 struct mmc_host *mmc; 133 133 struct mmc_request *mrq; 134 + struct scatterlist *cur_sg; 134 135 struct completion dma_complete; 135 136 struct completion pio_complete; 136 137 137 - struct sg_mapping_iter sg_miter; 138 + u32 num_sg; 139 + u32 data_remain; 138 140 u32 data_len; 139 141 u32 fifo_width; 140 142 u32 timeout; ··· 147 145 bool have_dma; 148 146 bool is_removed; 149 147 }; 148 + 149 + static inline void moxart_init_sg(struct moxart_host *host, 150 + struct mmc_data *data) 151 + { 152 + host->cur_sg = data->sg; 153 + host->num_sg = data->sg_len; 154 + host->data_remain = host->cur_sg->length; 155 + 156 + if (host->data_remain > host->data_len) 157 + host->data_remain = host->data_len; 158 + } 159 + 160 + static inline int moxart_next_sg(struct moxart_host *host) 161 + { 162 + int remain; 163 + struct mmc_data *data = host->mrq->cmd->data; 164 + 165 + host->cur_sg++; 166 + host->num_sg--; 167 + 168 + if (host->num_sg > 0) { 169 + host->data_remain = host->cur_sg->length; 170 + remain = host->data_len - data->bytes_xfered; 171 + if (remain > 0 && remain < host->data_remain) 172 + host->data_remain = remain; 173 + } 174 + 175 + return host->num_sg; 176 + } 150 177 151 178 static int moxart_wait_for_status(struct moxart_host *host, 152 179 u32 mask, u32 *status) ··· 309 278 310 279 static void moxart_transfer_pio(struct moxart_host *host) 311 280 { 312 - struct sg_mapping_iter *sgm = &host->sg_miter; 313 281 struct mmc_data *data = host->mrq->cmd->data; 314 282 u32 *sgp, len = 0, remain, status; 315 283 316 284 if (host->data_len == data->bytes_xfered) 317 285 return; 318 286 319 - /* 320 - * By updating sgm->consumes this will get a proper pointer into the 321 - * buffer at any time. 322 - */ 323 - if (!sg_miter_next(sgm)) { 324 - /* This shold not happen */ 325 - dev_err(mmc_dev(host->mmc), "ran out of scatterlist prematurely\n"); 326 - data->error = -EINVAL; 327 - complete(&host->pio_complete); 328 - return; 329 - } 330 - sgp = sgm->addr; 331 - remain = sgm->length; 332 - if (remain > host->data_len) 333 - remain = host->data_len; 334 - sgm->consumed = 0; 287 + sgp = sg_virt(host->cur_sg); 288 + remain = host->data_remain; 335 289 336 290 if (data->flags & MMC_DATA_WRITE) { 337 291 while (remain > 0) { ··· 331 315 sgp++; 332 316 len += 4; 333 317 } 334 - sgm->consumed += len; 335 318 remain -= len; 336 319 } 337 320 ··· 347 332 sgp++; 348 333 len += 4; 349 334 } 350 - sgm->consumed += len; 351 335 remain -= len; 352 336 } 353 337 } 354 338 355 - data->bytes_xfered += sgm->consumed; 356 - if (host->data_len == data->bytes_xfered) { 339 + data->bytes_xfered += host->data_remain - remain; 340 + host->data_remain = remain; 341 + 342 + if (host->data_len != data->bytes_xfered) 343 + moxart_next_sg(host); 344 + else 357 345 complete(&host->pio_complete); 358 - return; 359 - } 360 346 } 361 347 362 348 static void moxart_prepare_data(struct moxart_host *host) 363 349 { 364 350 struct mmc_data *data = host->mrq->cmd->data; 365 - unsigned int flags = SG_MITER_ATOMIC; /* Used from IRQ */ 366 351 u32 datactrl; 367 352 int blksz_bits; 368 353 ··· 373 358 blksz_bits = ffs(data->blksz) - 1; 374 359 BUG_ON(1 << blksz_bits != data->blksz); 375 360 361 + moxart_init_sg(host, data); 362 + 376 363 datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE); 377 364 378 - if (data->flags & MMC_DATA_WRITE) { 379 - flags |= SG_MITER_FROM_SG; 365 + if (data->flags & MMC_DATA_WRITE) 380 366 datactrl |= DCR_DATA_WRITE; 381 - } else { 382 - flags |= SG_MITER_TO_SG; 383 - } 384 367 385 368 if (moxart_use_dma(host)) 386 369 datactrl |= DCR_DMA_EN; 387 - else 388 - sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 389 370 390 371 writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL); 391 372 writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR); ··· 454 443 } 455 444 456 445 request_done: 457 - if (!moxart_use_dma(host)) 458 - sg_miter_stop(&host->sg_miter); 459 - 460 446 spin_unlock_irqrestore(&host->lock, flags); 461 447 mmc_request_done(host->mmc, mrq); 462 448 }

+4

drivers/mmc/host/sdhci-brcmstb.c

··· 24 24 #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) 25 25 #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) 26 26 #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2) 27 + #define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(4) 27 28 28 29 #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) 29 30 #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1) ··· 384 383 385 384 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) 386 385 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 386 + 387 + if (!(match_priv->flags & BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY)) 388 + host->mmc_host_ops.card_busy = NULL; 387 389 388 390 /* Change the base clock frequency if the DT property exists */ 389 391 if (device_property_read_u32(&pdev->dev, "clock-frequency",

+7 -4

drivers/mmc/host/sdhci-pci-core.c

··· 1326 1326 1327 1327 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1328 1328 if (ret) 1329 - return ret; 1329 + goto fail; 1330 1330 1331 1331 /* 1332 1332 * Turn PMOS on [bit 0], set over current detection to 2.4 V ··· 1337 1337 else 1338 1338 scratch &= ~0x47; 1339 1339 1340 - return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1340 + ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); 1341 + 1342 + fail: 1343 + return pcibios_err_to_errno(ret); 1341 1344 } 1342 1345 1343 1346 static int jmicron_probe(struct sdhci_pci_chip *chip) ··· 2205 2202 2206 2203 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2207 2204 if (ret) 2208 - return ret; 2205 + return pcibios_err_to_errno(ret); 2209 2206 2210 2207 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2211 2208 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); ··· 2214 2211 2215 2212 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2216 2213 if (ret) 2217 - return ret; 2214 + return pcibios_err_to_errno(ret); 2218 2215 2219 2216 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2220 2217

+22 -19

drivers/mmc/host/sdhci-pci-o2micro.c

··· 823 823 ret = pci_read_config_byte(chip->pdev, 824 824 O2_SD_LOCK_WP, &scratch); 825 825 if (ret) 826 - return ret; 826 + goto read_fail; 827 827 scratch &= 0x7f; 828 828 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 829 829 ··· 834 834 ret = pci_read_config_byte(chip->pdev, 835 835 O2_SD_CLKREQ, &scratch); 836 836 if (ret) 837 - return ret; 837 + goto read_fail; 838 838 scratch |= 0x20; 839 839 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); 840 840 ··· 843 843 */ 844 844 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); 845 845 if (ret) 846 - return ret; 846 + goto read_fail; 847 847 scratch |= 0x01; 848 848 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); 849 849 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); ··· 856 856 ret = pci_read_config_byte(chip->pdev, 857 857 O2_SD_INF_MOD, &scratch); 858 858 if (ret) 859 - return ret; 859 + goto read_fail; 860 860 scratch |= 0x08; 861 861 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); 862 862 ··· 864 864 ret = pci_read_config_byte(chip->pdev, 865 865 O2_SD_LOCK_WP, &scratch); 866 866 if (ret) 867 - return ret; 867 + goto read_fail; 868 868 scratch |= 0x80; 869 869 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 870 870 break; ··· 875 875 ret = pci_read_config_byte(chip->pdev, 876 876 O2_SD_LOCK_WP, &scratch); 877 877 if (ret) 878 - return ret; 878 + goto read_fail; 879 879 880 880 scratch &= 0x7f; 881 881 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); ··· 886 886 O2_SD_FUNC_REG0, 887 887 &scratch_32); 888 888 if (ret) 889 - return ret; 889 + goto read_fail; 890 890 scratch_32 = ((scratch_32 & 0xFF000000) >> 24); 891 891 892 892 /* Check Whether subId is 0x11 or 0x12 */ ··· 898 898 O2_SD_FUNC_REG4, 899 899 &scratch_32); 900 900 if (ret) 901 - return ret; 901 + goto read_fail; 902 902 903 903 /* Enable Base Clk setting change */ 904 904 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; ··· 921 921 ret = pci_read_config_dword(chip->pdev, 922 922 O2_SD_CLK_SETTING, &scratch_32); 923 923 if (ret) 924 - return ret; 924 + goto read_fail; 925 925 926 926 scratch_32 &= ~(0xFF00); 927 927 scratch_32 |= 0x07E0C800; ··· 931 931 ret = pci_read_config_dword(chip->pdev, 932 932 O2_SD_CLKREQ, &scratch_32); 933 933 if (ret) 934 - return ret; 934 + goto read_fail; 935 935 scratch_32 |= 0x3; 936 936 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); 937 937 938 938 ret = pci_read_config_dword(chip->pdev, 939 939 O2_SD_PLL_SETTING, &scratch_32); 940 940 if (ret) 941 - return ret; 941 + goto read_fail; 942 942 943 943 scratch_32 &= ~(0x1F3F070E); 944 944 scratch_32 |= 0x18270106; ··· 949 949 ret = pci_read_config_dword(chip->pdev, 950 950 O2_SD_CAP_REG2, &scratch_32); 951 951 if (ret) 952 - return ret; 952 + goto read_fail; 953 953 scratch_32 &= ~(0xE0); 954 954 pci_write_config_dword(chip->pdev, 955 955 O2_SD_CAP_REG2, scratch_32); ··· 961 961 ret = pci_read_config_byte(chip->pdev, 962 962 O2_SD_LOCK_WP, &scratch); 963 963 if (ret) 964 - return ret; 964 + goto read_fail; 965 965 scratch |= 0x80; 966 966 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 967 967 break; ··· 971 971 ret = pci_read_config_byte(chip->pdev, 972 972 O2_SD_LOCK_WP, &scratch); 973 973 if (ret) 974 - return ret; 974 + goto read_fail; 975 975 976 976 scratch &= 0x7f; 977 977 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); ··· 979 979 ret = pci_read_config_dword(chip->pdev, 980 980 O2_SD_PLL_SETTING, &scratch_32); 981 981 if (ret) 982 - return ret; 982 + goto read_fail; 983 983 984 984 if ((scratch_32 & 0xff000000) == 0x01000000) { 985 985 scratch_32 &= 0x0000FFFF; ··· 998 998 O2_SD_FUNC_REG4, 999 999 &scratch_32); 1000 1000 if (ret) 1001 - return ret; 1001 + goto read_fail; 1002 1002 scratch_32 |= (1 << 22); 1003 1003 pci_write_config_dword(chip->pdev, 1004 1004 O2_SD_FUNC_REG4, scratch_32); ··· 1017 1017 ret = pci_read_config_byte(chip->pdev, 1018 1018 O2_SD_LOCK_WP, &scratch); 1019 1019 if (ret) 1020 - return ret; 1020 + goto read_fail; 1021 1021 scratch |= 0x80; 1022 1022 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 1023 1023 break; ··· 1028 1028 /* UnLock WP */ 1029 1029 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 1030 1030 if (ret) 1031 - return ret; 1031 + goto read_fail; 1032 1032 scratch &= 0x7f; 1033 1033 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 1034 1034 ··· 1057 1057 /* Lock WP */ 1058 1058 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); 1059 1059 if (ret) 1060 - return ret; 1060 + goto read_fail; 1061 1061 scratch |= 0x80; 1062 1062 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); 1063 1063 break; 1064 1064 } 1065 1065 1066 1066 return 0; 1067 + 1068 + read_fail: 1069 + return pcibios_err_to_errno(ret); 1067 1070 } 1068 1071 1069 1072 #ifdef CONFIG_PM_SLEEP

+14 -11

drivers/mmc/host/sdhci.c

··· 2515 2515 2516 2516 static int sdhci_check_ro(struct sdhci_host *host) 2517 2517 { 2518 - unsigned long flags; 2518 + bool allow_invert = false; 2519 2519 int is_readonly; 2520 2520 2521 - spin_lock_irqsave(&host->lock, flags); 2522 - 2523 - if (host->flags & SDHCI_DEVICE_DEAD) 2521 + if (host->flags & SDHCI_DEVICE_DEAD) { 2524 2522 is_readonly = 0; 2525 - else if (host->ops->get_ro) 2523 + } else if (host->ops->get_ro) { 2526 2524 is_readonly = host->ops->get_ro(host); 2527 - else if (mmc_can_gpio_ro(host->mmc)) 2525 + } else if (mmc_can_gpio_ro(host->mmc)) { 2528 2526 is_readonly = mmc_gpio_get_ro(host->mmc); 2529 - else 2527 + /* Do not invert twice */ 2528 + allow_invert = !(host->mmc->caps2 & MMC_CAP2_RO_ACTIVE_HIGH); 2529 + } else { 2530 2530 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 2531 2531 & SDHCI_WRITE_PROTECT); 2532 + allow_invert = true; 2533 + } 2532 2534 2533 - spin_unlock_irqrestore(&host->lock, flags); 2535 + if (is_readonly >= 0 && 2536 + allow_invert && 2537 + (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)) 2538 + is_readonly = !is_readonly; 2534 2539 2535 - /* This quirk needs to be replaced by a callback-function later */ 2536 - return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 2537 - !is_readonly : is_readonly; 2540 + return is_readonly; 2538 2541 } 2539 2542 2540 2543 #define SAMPLE_COUNT 5

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