+1 -1

Documentation/ABI/testing/sysfs-bus-iio

reviewed

··· 1428 1428 Contact: linux-iio@vger.kernel.org 1429 1429 Description: 1430 1430 The name of the trigger source being used, as per string given 1431 1431 - in /sys/class/iio/triggerY/name. 1431 1431 + in /sys/bus/iio/devices/triggerY/name. 1432 1432 1433 1433 What: /sys/bus/iio/devices/iio:deviceX/bufferY/length 1434 1434 KernelVersion: 5.11

+6 -3

Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/iio/accel/adi,adxl372.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer 7 7 + title: Analog Devices ADXL371/ADXL372 3-Axis, +/-(200g) Digital Accelerometer 8 8 9 9 maintainers: 10 10 - Marcelo Schmitt <marcelo.schmitt@analog.com> 11 11 - Nuno Sá <nuno.sa@analog.com> 12 12 + - Antoniu Miclaus <antoniu.miclaus@analog.com> 12 13 13 14 description: | 14 14 - Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer that supports 15 15 - both I2C & SPI interfaces 15 15 + Analog Devices ADXL371/ADXL372 3-Axis, +/-(200g) Digital Accelerometer that 16 16 + supports both I2C & SPI interfaces 17 17 + https://www.analog.com/en/products/adxl371.html 16 18 https://www.analog.com/en/products/adxl372.html 17 19 18 20 properties: 19 21 compatible: 20 22 enum: 23 23 + - adi,adxl371 21 24 - adi,adxl372 22 25 23 26 reg:

+20 -18

Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml

reviewed

··· 16 16 17 17 properties: 18 18 compatible: 19 19 - enum: 20 20 - # bmc150-accel driver in Linux 21 21 - - bosch,bma222 22 22 - - bosch,bma222e 23 23 - - bosch,bma250e 24 24 - - bosch,bma253 25 25 - - bosch,bma254 26 26 - - bosch,bma255 27 27 - - bosch,bma280 28 28 - - bosch,bmc150_accel 29 29 - - bosch,bmc156_accel 30 30 - - bosch,bmi055_accel 19 19 + oneOf: 20 20 + - enum: 21 21 + - bosch,bma222 22 22 + - bosch,bma222e 23 23 + - bosch,bma250e 24 24 + - bosch,bma253 25 25 + - bosch,bma254 26 26 + - bosch,bma255 27 27 + - bosch,bma280 28 28 + - bosch,bmc150_accel 29 29 + - bosch,bmc156_accel 30 30 + - bosch,bmi055_accel 31 31 32 32 - # bma180 driver in Linux 33 33 - - bosch,bma023 34 34 - - bosch,bma150 35 35 - - bosch,bma180 36 36 - - bosch,bma250 37 37 - - bosch,smb380 32 32 + - bosch,bma023 33 33 + - bosch,bma150 34 34 + - bosch,bma180 35 35 + - bosch,bma250 36 36 + - bosch,smb380 37 37 + - items: 38 38 + - const: bosch,bmx055-accel 39 39 + - const: bosch,bmc150_accel 38 40 39 41 reg: 40 42 maxItems: 1

+64

Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml

reviewed

··· 19 19 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24-4032-24.pdf 20 20 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-24_ad4632-24.pdf 21 21 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-16-4632-16.pdf 22 22 + * https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4216.pdf 23 23 + * https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4224.pdf 24 24 + 25 25 + $ref: /schemas/spi/spi-peripheral-props.yaml# 22 26 23 27 properties: 24 28 compatible: ··· 33 29 - adi,ad4630-24 34 30 - adi,ad4632-16 35 31 - adi,ad4632-24 32 32 + - adi,adaq4216 33 33 + - adi,adaq4224 36 34 37 35 reg: 38 36 maxItems: 1 ··· 66 60 description: 67 61 Internal buffered Reference. Used when ref-supply is not connected. 68 62 63 63 + vddh-supply: 64 64 + description: 65 65 + PGIA Positive Power Supply. 66 66 + 67 67 + vdd-fda-supply: 68 68 + description: 69 69 + FDA Positive Power Supply. 70 70 + 69 71 cnv-gpios: 70 72 description: 71 73 The Convert Input (CNV). It initiates the sampling conversions. ··· 82 68 reset-gpios: 83 69 description: 84 70 The Reset Input (/RST). Used for asynchronous device reset. 71 71 + maxItems: 1 72 72 + 73 73 + pga-gpios: 74 74 + description: 75 75 + A0 and A1 pins for gain selection. For devices that have PGA configuration 76 76 + input pins, pga-gpios should be defined. 77 77 + minItems: 2 78 78 + maxItems: 2 79 79 + 80 80 + pwms: 81 81 + description: PWM signal connected to the CNV pin. 85 82 maxItems: 1 86 83 87 84 interrupts: ··· 132 107 properties: 133 108 spi-rx-bus-width: 134 109 maxItems: 1 110 110 + # ADAQ devices require a gain property to indicate how hardware PGA is set 111 111 + - if: 112 112 + properties: 113 113 + compatible: 114 114 + contains: 115 115 + pattern: ^adi,adaq 116 116 + then: 117 117 + required: 118 118 + - vddh-supply 119 119 + - vdd-fda-supply 120 120 + - pga-gpios 121 121 + properties: 122 122 + ref-supply: false 123 123 + else: 124 124 + properties: 125 125 + pga-gpios: false 135 126 136 127 examples: 137 128 - | ··· 187 146 ref-supply = <&supply_5V>; 188 147 cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; 189 148 reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; 149 149 + }; 150 150 + }; 151 151 + - | 152 152 + #include <dt-bindings/gpio/gpio.h> 153 153 + 154 154 + spi { 155 155 + #address-cells = <1>; 156 156 + #size-cells = <0>; 157 157 + 158 158 + adc@0 { 159 159 + compatible = "adi,adaq4216"; 160 160 + reg = <0>; 161 161 + spi-max-frequency = <80000000>; 162 162 + vdd-5v-supply = <&supply_5V>; 163 163 + vdd-1v8-supply = <&supply_1_8V>; 164 164 + vio-supply = <&supply_1_8V>; 165 165 + refin-supply = <&refin_sup>; 166 166 + vddh-supply = <&vddh>; 167 167 + vdd-fda-supply = <&vdd_fda>; 168 168 + cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; 169 169 + reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; 170 170 + pga-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>, 171 171 + <&gpio0 3 GPIO_ACTIVE_HIGH>; 190 172 }; 191 173 };

+3

Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml

reviewed

··· 27 27 enum: 28 28 - adi,ad4080 29 29 - adi,ad4081 30 30 + - adi,ad4082 30 31 - adi,ad4083 31 32 - adi,ad4084 33 33 + - adi,ad4085 32 34 - adi,ad4086 33 35 - adi,ad4087 36 36 + - adi,ad4088 34 37 35 38 reg: 36 39 maxItems: 1

+23

Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml

reviewed

··· 62 62 spi-cpol: true 63 63 spi-cpha: true 64 64 65 65 + spi-rx-bus-width: 66 66 + maxItems: 4 67 67 + items: 68 68 + maximum: 1 69 69 + 65 70 vcc-supply: 66 71 description: A 3V to 3.6V supply that powers the chip. 67 72 ··· 165 160 unevaluatedProperties: false 166 161 167 162 allOf: 163 163 + # 2-channel chips only have two SDO lines 164 164 + - if: 165 165 + properties: 166 166 + compatible: 167 167 + enum: 168 168 + - adi,ad7380 169 169 + - adi,ad7381 170 170 + - adi,ad7383 171 171 + - adi,ad7384 172 172 + - adi,ad7386 173 173 + - adi,ad7387 174 174 + - adi,ad7388 175 175 + then: 176 176 + properties: 177 177 + spi-rx-bus-width: 178 178 + maxItems: 2 179 179 + 168 180 # pseudo-differential chips require common mode voltage supplies, 169 181 # true differential chips don't use them 170 182 - if: ··· 306 284 spi-cpol; 307 285 spi-cpha; 308 286 spi-max-frequency = <80000000>; 287 287 + spi-rx-bus-width = <1>, <1>, <1>, <1>; 309 288 310 289 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 311 290 interrupt-parent = <&gpio0>;

+4

Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml

reviewed

··· 27 27 - amlogic,meson-gxm-saradc 28 28 - amlogic,meson-axg-saradc 29 29 - amlogic,meson-g12a-saradc 30 30 + # Usage of this generic fallback is not allowed for new devices 30 31 - const: amlogic,meson-saradc 32 32 + - items: 33 33 + - const: amlogic,meson-s4-saradc 34 34 + - const: amlogic,meson-g12a-saradc 31 35 32 36 reg: 33 37 maxItems: 1

+7

Documentation/devicetree/bindings/iio/adc/lltc,ltc2497.yaml

reviewed

··· 11 11 - Liam Beguin <liambeguin@gmail.com> 12 12 13 13 description: | 14 14 + LTC2305: 15 15 + low noise, low power, 2-channel, 12-bit successive approximation ADC with an 16 16 + I2C compatible serial interface. 17 17 + 18 18 + https://www.analog.com/media/en/technical-documentation/data-sheets/23015fb.pdf 19 19 + 14 20 LTC2309: 15 21 low noise, low power, 8-channel, 12-bit successive approximation ADC with an 16 22 I2C compatible serial interface. ··· 34 28 properties: 35 29 compatible: 36 30 enum: 31 31 + - lltc,ltc2305 37 32 - lltc,ltc2309 38 33 - lltc,ltc2497 39 34 - lltc,ltc2499

+1

Documentation/devicetree/bindings/iio/adc/motorola,cpcap-adc.yaml

reviewed

··· 19 19 enum: 20 20 - motorola,cpcap-adc 21 21 - motorola,mapphone-cpcap-adc 22 22 + - motorola,mot-cpcap-adc 22 23 23 24 interrupts: 24 25 maxItems: 1

+151

Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm's SPMI PMIC ADC5 Gen3 8 8 + 9 9 + maintainers: 10 10 + - Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> 11 11 + 12 12 + description: | 13 13 + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to clients to read 14 14 + voltage. It is a 16-bit sigma-delta ADC. It also performs the same thermal 15 15 + monitoring function as the existing ADC_TM devices. 16 16 + 17 17 + The interface is implemented on SDAM (Shared Direct Access Memory) peripherals 18 18 + on the master PMIC rather than a dedicated ADC peripheral. The number of PMIC 19 19 + SDAM peripherals allocated for ADC is not correlated with the PMIC used, it is 20 20 + programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements. 21 21 + All boards using a particular (SOC + master PMIC) combination will have the 22 22 + same number of ADC SDAMs supported on that PMIC. 23 23 + 24 24 + properties: 25 25 + compatible: 26 26 + const: qcom,spmi-adc5-gen3 27 27 + 28 28 + reg: 29 29 + items: 30 30 + - description: SDAM0 base address in the SPMI PMIC register map 31 31 + - description: SDAM1 base address 32 32 + minItems: 1 33 33 + 34 34 + "#address-cells": 35 35 + const: 1 36 36 + 37 37 + "#size-cells": 38 38 + const: 0 39 39 + 40 40 + "#io-channel-cells": 41 41 + const: 1 42 42 + 43 43 + "#thermal-sensor-cells": 44 44 + const: 1 45 45 + 46 46 + interrupts: 47 47 + items: 48 48 + - description: SDAM0 end of conversion (EOC) interrupt 49 49 + - description: SDAM1 EOC interrupt 50 50 + minItems: 1 51 51 + 52 52 + patternProperties: 53 53 + "^channel@[0-9a-f]+$": 54 54 + type: object 55 55 + unevaluatedProperties: false 56 56 + $ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml 57 57 + description: 58 58 + Represents the external channels which are connected to the ADC. 59 59 + 60 60 + properties: 61 61 + qcom,decimation: 62 62 + enum: [ 85, 340, 1360 ] 63 63 + default: 1360 64 64 + 65 65 + qcom,hw-settle-time: 66 66 + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 67 67 + 1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000 ] 68 68 + default: 15 69 69 + 70 70 + qcom,avg-samples: 71 71 + enum: [ 1, 2, 4, 8, 16 ] 72 72 + default: 1 73 73 + 74 74 + qcom,adc-tm: 75 75 + description: 76 76 + ADC_TM is a threshold monitoring feature in HW which can be enabled 77 77 + on any ADC channel, to trigger an IRQ for threshold violation. In 78 78 + earlier ADC generations, it was implemented in a separate device 79 79 + (documented in Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.) 80 80 + In Gen3, this feature can be enabled in the same ADC device for any 81 81 + channel and threshold monitoring and IRQ triggering are handled in FW 82 82 + (PBS) instead of another dedicated HW block. 83 83 + This property indicates ADC_TM monitoring is done on this channel. 84 84 + type: boolean 85 85 + 86 86 + required: 87 87 + - compatible 88 88 + - reg 89 89 + - "#address-cells" 90 90 + - "#size-cells" 91 91 + - "#io-channel-cells" 92 92 + - interrupts 93 93 + 94 94 + additionalProperties: false 95 95 + 96 96 + examples: 97 97 + - | 98 98 + #include <dt-bindings/interrupt-controller/irq.h> 99 99 + 100 100 + pmic { 101 101 + #address-cells = <1>; 102 102 + #size-cells = <0>; 103 103 + 104 104 + adc@9000 { 105 105 + compatible = "qcom,spmi-adc5-gen3"; 106 106 + reg = <0x9000>, <0x9100>; 107 107 + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, 108 108 + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; 109 109 + #address-cells = <1>; 110 110 + #size-cells = <0>; 111 111 + #io-channel-cells = <1>; 112 112 + #thermal-sensor-cells = <1>; 113 113 + 114 114 + /* PMK8550 Channel nodes */ 115 115 + channel@3 { 116 116 + reg = <0x3>; 117 117 + label = "pmk8550_die_temp"; 118 118 + qcom,pre-scaling = <1 1>; 119 119 + }; 120 120 + 121 121 + channel@44 { 122 122 + reg = <0x44>; 123 123 + label = "pmk8550_xo_therm"; 124 124 + qcom,pre-scaling = <1 1>; 125 125 + qcom,ratiometric; 126 126 + qcom,hw-settle-time = <200>; 127 127 + qcom,adc-tm; 128 128 + }; 129 129 + 130 130 + /* PM8550 Channel nodes */ 131 131 + channel@103 { 132 132 + reg = <0x103>; 133 133 + label = "pm8550_die_temp"; 134 134 + qcom,pre-scaling = <1 1>; 135 135 + }; 136 136 + 137 137 + /* PM8550B Channel nodes */ 138 138 + channel@78f { 139 139 + reg = <0x78f>; 140 140 + label = "pm8550b_vbat_sns_qbg"; 141 141 + qcom,pre-scaling = <1 3>; 142 142 + }; 143 143 + 144 144 + /* PM8550VS_C Channel nodes */ 145 145 + channel@203 { 146 146 + reg = <0x203>; 147 147 + label = "pm8550vs_c_die_temp"; 148 148 + qcom,pre-scaling = <1 1>; 149 149 + }; 150 150 + }; 151 151 + };

+84

Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc-common.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm Technologies, Inc. SPMI PMIC ADC channels 8 8 + 9 9 + maintainers: 10 10 + - Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> 11 11 + 12 12 + description: 13 13 + This defines the common properties used to define Qualcomm VADC channels. 14 14 + 15 15 + properties: 16 16 + reg: 17 17 + description: 18 18 + ADC channel number (PMIC-specific for versions after PMIC5 ADC). 19 19 + maxItems: 1 20 20 + 21 21 + label: 22 22 + description: 23 23 + ADC input of the platform as seen in the schematics. 24 24 + For thermistor inputs connected to generic AMUX or GPIO inputs 25 25 + these can vary across platform for the same pins. Hence select 26 26 + the platform schematics name for this channel. 27 27 + 28 28 + qcom,decimation: 29 29 + $ref: /schemas/types.yaml#/definitions/uint32 30 30 + description: 31 31 + This parameter is used to decrease ADC sampling rate. 32 32 + Quicker measurements can be made by reducing decimation ratio. 33 33 + 34 34 + qcom,pre-scaling: 35 35 + $ref: /schemas/types.yaml#/definitions/uint32-array 36 36 + description: 37 37 + Used for scaling the channel input signal before the signal is 38 38 + fed to VADC. The configuration for this node is to know the 39 39 + pre-determined ratio and use it for post scaling. It is a pair of 40 40 + integers, denoting the numerator and denominator of the fraction by which 41 41 + input signal is multiplied. For example, <1 3> indicates the signal is scaled 42 42 + down to 1/3 of its value before ADC measurement. 43 43 + If property is not found default value depending on chip will be used. 44 44 + oneOf: 45 45 + - items: 46 46 + - const: 1 47 47 + - enum: [ 1, 3, 4, 6, 20, 8, 10, 16 ] 48 48 + - items: 49 49 + - const: 10 50 50 + - const: 81 51 51 + 52 52 + qcom,ratiometric: 53 53 + type: boolean 54 54 + description: | 55 55 + Channel calibration type. 56 56 + - For compatible property "qcom,spmi-vadc", if this property is 57 57 + specified VADC will use the VDD reference (1.8V) and GND for 58 58 + channel calibration. If property is not found, channel will be 59 59 + calibrated with 0.625V and 1.25V reference channels, also 60 60 + known as absolute calibration. 61 61 + - For other compatible properties, if this property is specified 62 62 + VADC will use the VDD reference (1.875V) and GND for channel 63 63 + calibration. If property is not found, channel will be calibrated 64 64 + with 0V and 1.25V reference channels, also known as absolute calibration. 65 65 + 66 66 + qcom,hw-settle-time: 67 67 + $ref: /schemas/types.yaml#/definitions/uint32 68 68 + description: | 69 69 + Time between AMUX getting configured and the ADC starting 70 70 + conversion. The 'hw_settle_time' is an index used from valid values 71 71 + and programmed in hardware to achieve the hardware settling delay. 72 72 + 73 73 + qcom,avg-samples: 74 74 + $ref: /schemas/types.yaml#/definitions/uint32 75 75 + description: | 76 76 + Number of samples to be used for measurement. 77 77 + Averaging provides the option to obtain a single measurement 78 78 + from the ADC that is an average of multiple samples. The value 79 79 + selected is 2^(value). 80 80 + 81 81 + required: 82 82 + - reg 83 83 + 84 84 + additionalProperties: true

+4 -74

Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml

reviewed

··· 15 15 voltage. The VADC is a 15-bit sigma-delta ADC. 16 16 SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read 17 17 voltage. The VADC is a 16-bit sigma-delta ADC. 18 18 + Note that PMIC7 ADC is the generation between PMIC5 and PMIC5 Gen3 ADC, 19 19 + it can be considered like PMIC5 Gen2. 18 20 19 21 properties: 20 22 compatible: ··· 58 56 patternProperties: 59 57 "^channel@[0-9a-f]+$": 60 58 type: object 61 61 - additionalProperties: false 59 59 + unevaluatedProperties: false 62 60 description: | 63 61 Represents the external channels which are connected to the ADC. 64 62 For compatible property "qcom,spmi-vadc" following channels, also known as ··· 66 64 configuration nodes should be defined: 67 65 VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV, 68 66 VADC_GND_REF and VADC_VDD_VADC. 69 69 - 70 70 - properties: 71 71 - reg: 72 72 - maxItems: 1 73 73 - description: | 74 74 - ADC channel number. 75 75 - See include/dt-bindings/iio/qcom,spmi-vadc.h 76 76 - For PMIC7 ADC, the channel numbers are specified separately per PMIC 77 77 - in the PMIC-specific files in include/dt-bindings/iio/. 78 78 - 79 79 - label: 80 80 - description: | 81 81 - ADC input of the platform as seen in the schematics. 82 82 - For thermistor inputs connected to generic AMUX or GPIO inputs 83 83 - these can vary across platform for the same pins. Hence select 84 84 - the platform schematics name for this channel. 85 85 - 86 86 - qcom,decimation: 87 87 - $ref: /schemas/types.yaml#/definitions/uint32 88 88 - description: | 89 89 - This parameter is used to decrease ADC sampling rate. 90 90 - Quicker measurements can be made by reducing decimation ratio. 91 91 - 92 92 - qcom,pre-scaling: 93 93 - description: | 94 94 - Used for scaling the channel input signal before the signal is 95 95 - fed to VADC. The configuration for this node is to know the 96 96 - pre-determined ratio and use it for post scaling. It is a pair of 97 97 - integers, denoting the numerator and denominator of the fraction by which 98 98 - input signal is multiplied. For example, <1 3> indicates the signal is scaled 99 99 - down to 1/3 of its value before ADC measurement. 100 100 - If property is not found default value depending on chip will be used. 101 101 - $ref: /schemas/types.yaml#/definitions/uint32-array 102 102 - oneOf: 103 103 - - items: 104 104 - - const: 1 105 105 - - enum: [ 1, 3, 4, 6, 20, 8, 10, 16 ] 106 106 - - items: 107 107 - - const: 10 108 108 - - const: 81 109 109 - 110 110 - qcom,ratiometric: 111 111 - description: | 112 112 - Channel calibration type. 113 113 - - For compatible property "qcom,spmi-vadc", if this property is 114 114 - specified VADC will use the VDD reference (1.8V) and GND for 115 115 - channel calibration. If property is not found, channel will be 116 116 - calibrated with 0.625V and 1.25V reference channels, also 117 117 - known as absolute calibration. 118 118 - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and 119 119 - "qcom,spmi-adc-rev2", if this property is specified VADC will use 120 120 - the VDD reference (1.875V) and GND for channel calibration. If 121 121 - property is not found, channel will be calibrated with 0V and 1.25V 122 122 - reference channels, also known as absolute calibration. 123 123 - type: boolean 124 124 - 125 125 - qcom,hw-settle-time: 126 126 - $ref: /schemas/types.yaml#/definitions/uint32 127 127 - description: | 128 128 - Time between AMUX getting configured and the ADC starting 129 129 - conversion. The 'hw_settle_time' is an index used from valid values 130 130 - and programmed in hardware to achieve the hardware settling delay. 131 131 - 132 132 - qcom,avg-samples: 133 133 - $ref: /schemas/types.yaml#/definitions/uint32 134 134 - description: | 135 135 - Number of samples to be used for measurement. 136 136 - Averaging provides the option to obtain a single measurement 137 137 - from the ADC that is an average of multiple samples. The value 138 138 - selected is 2^(value). 139 139 - 140 140 - required: 141 141 - - reg 67 67 + $ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml 142 68 143 69 allOf: 144 70 - if:

+101

Documentation/devicetree/bindings/iio/amplifiers/adi,ad8366.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/iio/amplifiers/adi,ad8366.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: AD8366 and similar Gain Amplifiers and Digital Attenuators 8 8 + 9 9 + maintainers: 10 10 + - Michael Hennerich <michael.hennerich@analog.com> 11 11 + - Rodrigo Alencar <rodrigo.alencar@analog.com> 12 12 + 13 13 + description: 14 14 + Digital Variable Gain Amplifiers (VGAs) and Digital Attenuators with 15 15 + SPI interface. 16 16 + 17 17 + properties: 18 18 + compatible: 19 19 + enum: 20 20 + - adi,ad8366 21 21 + - adi,ada4961 22 22 + - adi,adl5240 23 23 + - adi,adrf5702 24 24 + - adi,adrf5703 25 25 + - adi,adrf5720 26 26 + - adi,adrf5730 27 27 + - adi,adrf5731 28 28 + - adi,hmc271a 29 29 + - adi,hmc792a 30 30 + - adi,hmc1018a 31 31 + - adi,hmc1019a 32 32 + - adi,hmc1119 33 33 + 34 34 + reg: 35 35 + maxItems: 1 36 36 + 37 37 + vcc-supply: 38 38 + description: Regulator that provides power to the device. 39 39 + 40 40 + reset-gpios: 41 41 + maxItems: 1 42 42 + 43 43 + enable-gpios: 44 44 + maxItems: 1 45 45 + description: Power-up or Serial Mode Enable GPIO. 46 46 + 47 47 + required: 48 48 + - compatible 49 49 + - reg 50 50 + - vcc-supply 51 51 + 52 52 + allOf: 53 53 + - $ref: /schemas/spi/spi-peripheral-props.yaml# 54 54 + - if: 55 55 + not: 56 56 + properties: 57 57 + compatible: 58 58 + contains: 59 59 + const: adi,hmc271a 60 60 + then: 61 61 + properties: 62 62 + reset-gpios: false 63 63 + - if: 64 64 + not: 65 65 + properties: 66 66 + compatible: 67 67 + contains: 68 68 + anyOf: 69 69 + - const: adi,ad8366 70 70 + - const: adi,ada4961 71 71 + - const: adi,adrf5702 72 72 + - const: adi,adrf5703 73 73 + - const: adi,adrf5720 74 74 + - const: adi,adrf5730 75 75 + - const: adi,adrf5731 76 76 + - const: adi,hmc792a 77 77 + - const: adi,hmc1018a 78 78 + - const: adi,hmc1019a 79 79 + - const: adi,hmc1119 80 80 + then: 81 81 + properties: 82 82 + enable-gpios: false 83 83 + 84 84 + unevaluatedProperties: false 85 85 + 86 86 + examples: 87 87 + - | 88 88 + #include <dt-bindings/gpio/gpio.h> 89 89 + spi { 90 90 + #address-cells = <1>; 91 91 + #size-cells = <0>; 92 92 + 93 93 + amplifier@0 { 94 94 + compatible = "adi,ad8366"; 95 95 + reg = <0>; 96 96 + spi-max-frequency = <1000000>; 97 97 + vcc-supply = <&vcc_3v3>; 98 98 + enable-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; 99 99 + }; 100 100 + }; 101 101 + ...

+35 -22

Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/iio/dac/lltc,ltc2632.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Linear Technology LTC263x 12-/10-/8-Bit Rail-to-Rail DAC 7 7 + title: Linear Technology LTC263x and LTC2654 Rail-to-Rail DAC 8 8 9 9 maintainers: 10 10 - Michael Hennerich <michael.hennerich@analog.com> 11 11 12 12 description: | 13 13 - Bindings for the Linear Technology LTC2632/2634/2636 DAC 14 14 - Datasheet can be found here: https://www.analog.com/media/en/technical-documentation/data-sheets/LTC263[246].pdf 13 13 + Bindings for the Linear Technology LTC2632/2634/2636/2654 DAC 14 14 + Datasheet can be found here: 15 15 + https://www.analog.com/media/en/technical-documentation/data-sheets/LTC263[246].pdf 16 16 + https://www.analog.com/media/en/technical-documentation/data-sheets/2654f.pdf 15 17 16 18 properties: 17 19 compatible: 18 18 - enum: 19 19 - - lltc,ltc2632-l12 20 20 - - lltc,ltc2632-l10 21 21 - - lltc,ltc2632-l8 22 22 - - lltc,ltc2632-h12 23 23 - - lltc,ltc2632-h10 24 24 - - lltc,ltc2632-h8 25 25 - - lltc,ltc2634-l12 26 26 - - lltc,ltc2634-l10 27 27 - - lltc,ltc2634-l8 28 28 - - lltc,ltc2634-h12 29 29 - - lltc,ltc2634-h10 30 30 - - lltc,ltc2634-h8 31 31 - - lltc,ltc2636-l12 32 32 - - lltc,ltc2636-l10 33 33 - - lltc,ltc2636-l8 34 34 - - lltc,ltc2636-h12 35 35 - - lltc,ltc2636-h10 36 36 - - lltc,ltc2636-h8 20 20 + oneOf: 21 21 + - enum: 22 22 + - lltc,ltc2632-l12 23 23 + - lltc,ltc2632-l10 24 24 + - lltc,ltc2632-l8 25 25 + - lltc,ltc2632-h12 26 26 + - lltc,ltc2632-h10 27 27 + - lltc,ltc2632-h8 28 28 + - lltc,ltc2634-l12 29 29 + - lltc,ltc2634-l10 30 30 + - lltc,ltc2634-l8 31 31 + - lltc,ltc2634-h12 32 32 + - lltc,ltc2634-h10 33 33 + - lltc,ltc2634-h8 34 34 + - lltc,ltc2636-l12 35 35 + - lltc,ltc2636-l10 36 36 + - lltc,ltc2636-l8 37 37 + - lltc,ltc2636-h12 38 38 + - lltc,ltc2636-h10 39 39 + - lltc,ltc2636-h8 40 40 + - lltc,ltc2654-l16 41 41 + - lltc,ltc2654-h16 42 42 + - items: 43 43 + - enum: 44 44 + - lltc,ltc2654-l12 45 45 + - const: lltc,ltc2634-l12 46 46 + - items: 47 47 + - enum: 48 48 + - lltc,ltc2654-h12 49 49 + - const: lltc,ltc2634-h12 37 50 38 51 reg: 39 52 maxItems: 1

+40 -2

Documentation/devicetree/bindings/iio/dac/maxim,ds4424.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/iio/dac/maxim,ds4424.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Maxim Integrated DS4422/DS4424 7-bit Sink/Source Current DAC 7 7 + title: Maxim Integrated DS4402/DS4404 and DS4422/DS4424 Current DACs 8 8 9 9 maintainers: 10 10 - Ismail Kose <ihkose@gmail.com> 11 11 12 12 description: | 13 13 - Datasheet publicly available at: 13 13 + Datasheets publicly available at: 14 14 + https://datasheets.maximintegrated.com/en/ds/DS4402-DS4404.pdf 14 15 https://datasheets.maximintegrated.com/en/ds/DS4422-DS4424.pdf 15 16 16 17 properties: 17 18 compatible: 18 19 enum: 20 20 + - maxim,ds4402 21 21 + - maxim,ds4404 19 22 - maxim,ds4422 20 23 - maxim,ds4424 21 24 ··· 27 24 28 25 vcc-supply: true 29 26 27 27 + maxim,rfs-ohms: 28 28 + description: | 29 29 + Array of resistance values in Ohms for the external Rfs resistors 30 30 + connected to the FS pins. These values determine the full-scale 31 31 + output current. The actual resistance depends on the chip variant 32 32 + and specific hardware design requirements. 33 33 + minItems: 2 34 34 + maxItems: 4 35 35 + 30 36 required: 31 37 - compatible 32 38 - reg 39 39 + - maxim,rfs-ohms 40 40 + 41 41 + allOf: 42 42 + - if: 43 43 + properties: 44 44 + compatible: 45 45 + contains: 46 46 + enum: 47 47 + - maxim,ds4402 48 48 + - maxim,ds4422 49 49 + then: 50 50 + properties: 51 51 + maxim,rfs-ohms: 52 52 + maxItems: 2 53 53 + - if: 54 54 + properties: 55 55 + compatible: 56 56 + contains: 57 57 + enum: 58 58 + - maxim,ds4404 59 59 + - maxim,ds4424 60 60 + then: 61 61 + properties: 62 62 + maxim,rfs-ohms: 63 63 + minItems: 4 33 64 34 65 additionalProperties: false 35 66 ··· 77 40 compatible = "maxim,ds4424"; 78 41 reg = <0x10>; /* When A0, A1 pins are ground */ 79 42 vcc-supply = <&vcc_3v3>; 43 43 + maxim,rfs-ohms = <40000>, <40000>, <40000>, <40000>; 80 44 }; 81 45 }; 82 46 ...

+1 -1

Documentation/devicetree/bindings/iio/dac/ti,dac7612.yaml

reviewed

··· 9 9 description: 10 10 The DAC7612 is a dual, 12-bit digital-to-analog converter (DAC) with 11 11 guaranteed 12-bit monotonicity performance over the industrial temperature 12 12 - range. Is is programmable through an SPI interface. 12 12 + range. It is programmable through an SPI interface. 13 13 14 14 maintainers: 15 15 - Ricardo Ribalda Delgado <ricardo@ribalda.com>

+8 -4

Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml

reviewed

··· 11 11 12 12 properties: 13 13 compatible: 14 14 - enum: 15 15 - - bosch,bmg160 16 16 - - bosch,bmi055_gyro 17 17 - - bosch,bmi088_gyro 14 14 + oneOf: 15 15 + - enum: 16 16 + - bosch,bmg160 17 17 + - bosch,bmi055_gyro 18 18 + - bosch,bmi088_gyro 19 19 + - items: 20 20 + - const: bosch,bmx055-gyro 21 21 + - const: bosch,bmg160 18 22 19 23 reg: 20 24 maxItems: 1

+25 -6

Documentation/devicetree/bindings/iio/light/vishay,vcnl4000.yaml

reviewed

··· 18 18 19 19 properties: 20 20 compatible: 21 21 - enum: 22 22 - - vishay,vcnl4000 23 23 - - vishay,vcnl4010 24 24 - - vishay,vcnl4020 25 25 - - vishay,vcnl4040 26 26 - - vishay,vcnl4200 21 21 + oneOf: 22 22 + - enum: 23 23 + - capella,cm36672p 24 24 + - vishay,vcnl4000 25 25 + - vishay,vcnl4010 26 26 + - vishay,vcnl4020 27 27 + - vishay,vcnl4040 28 28 + - vishay,vcnl4200 29 29 + - items: 30 30 + - const: capella,cm36686 31 31 + - const: vishay,vcnl4040 27 32 28 33 interrupts: 29 34 maxItems: 1 35 35 + 36 36 + vdd-supply: 37 37 + description: Regulator providing power to the "VDD" pin. 38 38 + 39 39 + vio-supply: 40 40 + description: Regulator providing power for pull-up of the I/O lines. 41 41 + Does not connect to the sensor directly, but is needed for the 42 42 + correct operation of the I2C and interrupt lines. 43 43 + 44 44 + vled-supply: 45 45 + description: Regulator providing power to the IR anode pin. 30 46 31 47 reg: 32 48 maxItems: 1 ··· 65 49 compatible = "vishay,vcnl4200"; 66 50 reg = <0x51>; 67 51 proximity-near-level = <220>; 52 52 + vdd-supply = <&reg_vdd>; 53 53 + vio-supply = <&reg_vio>; 54 54 + vled-supply = <&reg_vled>; 68 55 }; 69 56 }; 70 57 ...

+9 -5

Documentation/devicetree/bindings/iio/magnetometer/bosch,bmc150_magn.yaml

reviewed

··· 21 21 description: 22 22 Note the bmm150_magn is a deprecated compatible as this part contains only 23 23 a magnetometer. 24 24 - enum: 25 25 - - bosch,bmc150_magn 26 26 - - bosch,bmc156_magn 27 27 - - bosch,bmm150 28 28 - - bosch,bmm150_magn 24 24 + oneOf: 25 25 + - enum: 26 26 + - bosch,bmc150_magn 27 27 + - bosch,bmc156_magn 28 28 + - bosch,bmm150 29 29 + - bosch,bmm150_magn 30 30 + - items: 31 31 + - const: bosch,bmx055-magn 32 32 + - const: bosch,bmc150_magn 29 33 30 34 reg: 31 35 maxItems: 1

+19 -3

Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/iio/proximity/st,vl53l0x.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: ST VL53L0X ToF ranging sensor 7 7 + title: ST VL53L0X/VL53L1X ToF ranging sensor 8 8 9 9 maintainers: 10 10 - Song Qiang <songqiang1304521@gmail.com> 11 11 + - Siratul Islam <email@sirat.me> 11 12 12 13 properties: 13 14 compatible: 14 14 - const: st,vl53l0x 15 15 + enum: 16 16 + - st,vl53l0x 17 17 + - st,vl53l1x 15 18 16 19 reg: 17 20 maxItems: 1 ··· 24 21 25 22 reset-gpios: 26 23 maxItems: 1 24 24 + description: 25 25 + Phandle to the XSHUT GPIO. Used for hardware reset. 27 26 28 27 vdd-supply: true 29 28 30 29 required: 31 30 - compatible 32 31 - reg 32 32 + 33 33 + allOf: 34 34 + - if: 35 35 + properties: 36 36 + compatible: 37 37 + contains: 38 38 + const: st,vl53l1x 39 39 + then: 40 40 + required: 41 41 + - vdd-supply 33 42 34 43 additionalProperties: false 35 44 ··· 53 38 #size-cells = <0>; 54 39 55 40 proximity@29 { 56 56 - compatible = "st,vl53l0x"; 41 41 + compatible = "st,vl53l1x"; 57 42 reg = <0x29>; 43 43 + vdd-supply = <&reg_3v3>; 58 44 interrupt-parent = <&gpio>; 59 45 interrupts = <23 IRQ_TYPE_EDGE_FALLING>; 60 46 };

+4

Documentation/devicetree/bindings/iio/proximity/tyhx,hx9023s.yaml

reviewed

··· 28 28 29 29 vdd-supply: true 30 30 31 31 + firmware-name: 32 32 + maxItems: 1 33 33 + 31 34 "#address-cells": 32 35 const: 1 33 36 ··· 68 65 interrupt-parent = <&pio>; 69 66 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 70 67 vdd-supply = <&pp1800_prox>; 68 68 + firmware-name = "hx9023s.bin"; 71 69 72 70 #address-cells = <1>; 73 71 #size-cells = <0>;

+1

Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml

reviewed

··· 135 135 "^adc@[0-9a-f]+$": 136 136 type: object 137 137 oneOf: 138 138 + - $ref: /schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# 138 139 - $ref: /schemas/iio/adc/qcom,spmi-iadc.yaml# 139 140 - $ref: /schemas/iio/adc/qcom,spmi-rradc.yaml# 140 141 - $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml#

+39

Documentation/iio/ad4030.rst

reviewed

··· 92 92 In this mode, both channels conversion results are bit interleaved one SDO line. 93 93 As such the wiring is the same as `One lane mode`_. 94 94 95 95 + SPI offload wiring 96 96 + ^^^^^^^^^^^^^^^^^^ 97 97 + 98 98 + .. code-block:: 99 99 + 100 100 + +-------------+ +-------------+ 101 101 + | CNV |<-----+--| GPIO | 102 102 + | | +--| PWM0 | 103 103 + | | | | 104 104 + | | +--| PWM1 | 105 105 + | | | +-------------+ 106 106 + | | +->| TRIGGER | 107 107 + | CS |<--------| CS | 108 108 + | | | | 109 109 + | ADC | | SPI | 110 110 + | | | | 111 111 + | SDI |<--------| SDO | 112 112 + | SDO |-------->| SDI | 113 113 + | SCLK |<--------| SCLK | 114 114 + +-------------+ +-------------+ 115 115 + 116 116 + In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are required. 117 117 + The ``pwms`` property specifies the PWM that is connected to the ADC CNV pin. 118 118 + The SPI offload will have a ``trigger-sources`` property to indicate the SPI 119 119 + offload (PWM) trigger source. For AD4030 and similar ADCs, there are two 120 120 + possible data transfer zones for sample N. One of them (zone 1) starts after the 121 121 + data conversion for sample N is complete while the other one (zone 2) starts 9.8 122 122 + nanoseconds after the rising edge of CNV for sample N + 1. 123 123 + 124 124 + The configuration depicted in the above diagram is intended to perform data 125 125 + transfer in zone 2. To achieve high sample rates while meeting ADC timing 126 126 + requirements, an offset is added between the rising edges of PWM0 and PWM1 to 127 127 + delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This 128 128 + requires a specialized PWM controller that can provide such an offset. 129 129 + The `AD4630-FMC HDL project`_, for example, can be configured to sample AD4030 130 130 + data during zone 2 data read window. 131 131 + 132 132 + .. _AD4630-FMC HDL project: https://analogdevicesinc.github.io/hdl/projects/ad4630_fmc/index.html 133 133 + 95 134 SPI Clock mode 96 135 -------------- 97 136

+3 -3

Documentation/iio/ad7191.rst

reviewed

··· 63 63 64 64 The AD7191 supports both internal and external clock sources: 65 65 66 66 - - When CLKSEL pin is tied LOW: Uses internal 4.92MHz clock (no clock property 66 66 + - When CLKSEL pin is ACTIVE: Uses internal 4.92MHz clock (no clock property 67 67 needed) 68 68 - - When CLKSEL pin is tied HIGH: Requires external clock source 68 68 + - When CLKSEL pin is INACTIVE: Requires external clock source 69 69 - Can be a crystal between MCLK1 and MCLK2 pins 70 70 - - Or a CMOS-compatible clock driving MCLK2 pin 70 70 + - Or a CMOS-compatible clock driving MCLK1 pin and MCLK2 left unconnected 71 71 - Must specify the "clocks" property in device tree when using external clock 72 72 73 73 SPI Interface Requirements

+56 -33

Documentation/iio/adxl345.rst

reviewed

··· 12 12 * `ADXL345 <https://www.analog.com/ADXL345>`_ 13 13 * `ADXL375 <https://www.analog.com/ADXL375>`_ 14 14 15 15 - The ADXL345 is a generic purpose low power, 3-axis accelerometer with selectable 16 16 - measurement ranges. The ADXL345 supports the ±2 g, ±4 g, ±8 g, and ±16 g ranges. 15 15 + The ADXL345 is a general-purpose, low-power, 3-axis accelerometer with selectable 16 16 + measurement ranges. The ADXL345 supports the following ranges: 17 17 + 18 18 + - ±2g (approx. ±19.61 m/s^2) 19 19 + - ±4g (approx. ±39.23 m/s^2) 20 20 + - ±8g (approx. ±78.45 m/s^2) 21 21 + - ±16g (approx. ±156.91 m/s^2) 17 22 18 23 2. Device Attributes 19 24 ==================== 20 25 21 21 - Each IIO device, has a device folder under ``/sys/bus/iio/devices/iio:deviceX``, 26 26 + Each IIO device has a device folder under ``/sys/bus/iio/devices/iio:deviceX``, 22 27 where X is the IIO index of the device. Under these folders reside a set of 23 28 device files, depending on the characteristics and features of the hardware 24 24 - device in questions. These files are consistently generalized and documented in 29 29 + device in question. These files are consistently generalized and documented in 25 30 the IIO ABI documentation. 26 31 27 32 The following table shows the ADXL345 related device files, found in the ··· 47 42 +-------------------------------------------+----------------------------------------------------------+ 48 43 | in_accel_x_raw | Raw X-axis accelerometer channel value. | 49 44 +-------------------------------------------+----------------------------------------------------------+ 50 50 - | in_accel_y_calibbias | y-axis acceleration offset correction | 45 45 + | in_accel_y_calibbias | Y-axis acceleration offset correction | 51 46 +-------------------------------------------+----------------------------------------------------------+ 52 47 | in_accel_y_raw | Raw Y-axis accelerometer channel value. | 53 48 +-------------------------------------------+----------------------------------------------------------+ ··· 73 68 +-------------------------------------+---------------------------+ 74 69 | Channel type | Measurement unit | 75 70 +-------------------------------------+---------------------------+ 76 76 - | Acceleration on X, Y, and Z axis | Meters per second squared | 71 71 + | Acceleration on X, Y, and Z axes | Meters per second squared | 77 72 +-------------------------------------+---------------------------+ 78 73 79 74 Sensor Events ··· 83 78 driver supports either none or a single active interrupt (INT) line, selectable 84 79 from the two available options: INT1 or INT2. The active INT line should be 85 80 specified in the device tree. If no INT line is configured, the sensor defaults 86 86 - to FIFO bypass mode, where event detection is disabled and only X, Y, and Z axis 87 87 - measurements are available. 81 81 + to FIFO bypass mode, where event detection is disabled and only individual 82 82 + X, Y, and Z axis measurements are available. 88 83 89 84 The table below lists the ADXL345-related device files located in the 90 85 device-specific path: ``/sys/bus/iio/devices/iio:deviceX/events``. ··· 95 90 +---------------------------------------------+---------------------------------------------+ 96 91 | Event handle | Description | 97 92 +---------------------------------------------+---------------------------------------------+ 98 98 - | in_accel_gesture_doubletap_en | Enable double tap detection on all axis | 93 93 + | in_accel_gesture_doubletap_en | Enable double tap detection on all axes | 99 94 +---------------------------------------------+---------------------------------------------+ 100 95 | in_accel_gesture_doubletap_reset_timeout | Double tap window in [us] | 101 96 +---------------------------------------------+---------------------------------------------+ 102 102 - | in_accel_gesture_doubletap_tap2_min_delay | Double tap latent in [us] | 97 97 + | in_accel_gesture_doubletap_scale | Double tap gesture threshold scale. | 98 98 + +---------------------------------------------+---------------------------------------------+ 99 99 + | in_accel_gesture_doubletap_tap2_min_delay | Double tap latency in [us] | 100 100 + +---------------------------------------------+---------------------------------------------+ 101 101 + | in_accel_gesture_doubletap_value | Double tap threshold value | 102 102 + +---------------------------------------------+---------------------------------------------+ 103 103 + | in_accel_gesture_singletap_scale | Single tap gesture threshold scale. | 103 104 +---------------------------------------------+---------------------------------------------+ 104 105 | in_accel_gesture_singletap_timeout | Single tap duration in [us] | 105 106 +---------------------------------------------+---------------------------------------------+ 106 106 - | in_accel_gesture_singletap_value | Single tap threshold value in 62.5/LSB | 107 107 - +---------------------------------------------+---------------------------------------------+ 108 108 - | in_accel_mag_falling_period | Inactivity time in seconds | 109 109 - +---------------------------------------------+---------------------------------------------+ 110 110 - | in_accel_mag_falling_value | Inactivity threshold value in 62.5/LSB | 111 111 - +---------------------------------------------+---------------------------------------------+ 112 112 - | in_accel_mag_adaptive_rising_en | Enable AC coupled activity on X axis | 107 107 + | in_accel_gesture_singletap_value | Single tap threshold value | 113 108 +---------------------------------------------+---------------------------------------------+ 114 109 | in_accel_mag_adaptive_falling_period | AC coupled inactivity time in seconds | 115 110 +---------------------------------------------+---------------------------------------------+ 116 116 - | in_accel_mag_adaptive_falling_value | AC coupled inactivity threshold in 62.5/LSB | 111 111 + | in_accel_mag_adaptive_falling_scale | AC coupled inactivity threshold scale. | 117 112 +---------------------------------------------+---------------------------------------------+ 118 118 - | in_accel_mag_adaptive_rising_value | AC coupled activity threshold in 62.5/LSB | 113 113 + | in_accel_mag_adaptive_falling_value | AC coupled inactivity threshold | 114 114 + +---------------------------------------------+---------------------------------------------+ 115 115 + | in_accel_mag_adaptive_rising_en | Enable AC coupled activity on X axis | 116 116 + +---------------------------------------------+---------------------------------------------+ 117 117 + | in_accel_mag_adaptive_rising_scale | AC coupled activity threshold scale. | 118 118 + +---------------------------------------------+---------------------------------------------+ 119 119 + | in_accel_mag_adaptive_rising_value | AC coupled activity threshold | 120 120 + +---------------------------------------------+---------------------------------------------+ 121 121 + | in_accel_mag_falling_period | Inactivity time in seconds | 122 122 + +---------------------------------------------+---------------------------------------------+ 123 123 + | in_accel_mag_falling_scale | DC coupled inactivity threshold scale. | 124 124 + +---------------------------------------------+---------------------------------------------+ 125 125 + | in_accel_mag_falling_value | Inactivity threshold value | 119 126 +---------------------------------------------+---------------------------------------------+ 120 127 | in_accel_mag_rising_en | Enable activity detection on X axis | 121 128 +---------------------------------------------+---------------------------------------------+ 122 122 - | in_accel_mag_rising_value | Activity threshold value in 62.5/LSB | 129 129 + | in_accel_mag_rising_scale | DC coupled activity threshold scale. | 130 130 + +---------------------------------------------+---------------------------------------------+ 131 131 + | in_accel_mag_rising_value | Activity threshold value | 132 132 + +---------------------------------------------+---------------------------------------------+ 133 133 + | in_accel_x&y&z_mag_adaptive_falling_en | Enable AC coupled inactivity on all axes | 134 134 + +---------------------------------------------+---------------------------------------------+ 135 135 + | in_accel_x&y&z_mag_falling_en | Enable inactivity detection on all axes | 123 136 +---------------------------------------------+---------------------------------------------+ 124 137 | in_accel_x_gesture_singletap_en | Enable single tap detection on X axis | 125 125 - +---------------------------------------------+---------------------------------------------+ 126 126 - | in_accel_x&y&z_mag_falling_en | Enable inactivity detection on all axis | 127 127 - +---------------------------------------------+---------------------------------------------+ 128 128 - | in_accel_x&y&z_mag_adaptive_falling_en | Enable AC coupled inactivity on all axis | 129 138 +---------------------------------------------+---------------------------------------------+ 130 139 | in_accel_y_gesture_singletap_en | Enable single tap detection on Y axis | 131 140 +---------------------------------------------+---------------------------------------------+ ··· 159 140 appropriate activity and inactivity thresholds by scaling the default values 160 141 based on the ratio of the previous range to the new one. The resulting threshold 161 142 will never be zero and will always fall between 1 and 255, corresponding to up 162 162 - to 62.5 g/LSB as specified in the datasheet. However, you can override these 163 163 - estimated thresholds by setting explicit values. 143 143 + to 62.5 mg/LSB (0.612915 m/s^2/LSB) as specified in the datasheet. However, 144 144 + you can override these estimated thresholds by setting explicit values. 164 145 165 146 When **activity** and **inactivity** events are enabled, the driver 166 147 automatically manages hysteresis behavior by setting the **link** and ··· 289 270 .. code-block:: bash 290 271 291 272 root:/sys/bus/iio/devices/iio:device0> cat ./in_accel_scale 292 292 - 0.478899 273 273 + 0.004789 293 274 root:/sys/bus/iio/devices/iio:device0> cat ./in_accel_scale_available 294 294 - 0.478899 0.957798 1.915595 3.831190 275 275 + 0.004789 0.009578 0.019156 0.038312 295 276 296 296 - root:/sys/bus/iio/devices/iio:device0> echo 1.915595 > ./in_accel_scale 277 277 + root:/sys/bus/iio/devices/iio:device0> echo 0.019156 > ./in_accel_scale 297 278 root:/sys/bus/iio/devices/iio:device0> cat ./in_accel_scale 298 298 - 1.915595 279 279 + 0.019156 299 280 300 281 Set output data rate (ODR): 301 282 ··· 331 312 332 313 root:/sys/bus/iio/devices/iio:device0> echo 24 > ./buffer0/length 333 314 334 334 - ## AC coupled activity, threshold [62.5/LSB] 315 315 + ## Check the event scale factor (0.0625 * 9.80665) 316 316 + root:/sys/bus/iio/devices/iio:device0> cat ./events/in_accel_gesture_doubletap_scale 317 317 + 0.612915 318 318 + 319 319 + ## AC coupled activity, threshold [0.612915 m/s^2/LSB] 335 320 root:/sys/bus/iio/devices/iio:device0> echo 6 > ./events/in_accel_mag_adaptive_rising_value 336 321 337 337 - ## AC coupled inactivity, threshold, [62.5/LSB] 322 322 + ## AC coupled inactivity, threshold, [0.612915 m/s^2/LSB] 338 323 root:/sys/bus/iio/devices/iio:device0> echo 4 > ./events/in_accel_mag_adaptive_falling_value 339 324 340 325 ## AC coupled inactivity, time [s] ··· 353 330 ## doubletap, window [us] 354 331 root:/sys/bus/iio/devices/iio:device0> echo 0.025 > ./events/in_accel_gesture_doubletap_reset_timeout 355 332 356 356 - ## doubletap, latent [us] 333 333 + ## doubletap, latency [us] 357 334 root:/sys/bus/iio/devices/iio:device0> echo 0.025 > ./events/in_accel_gesture_doubletap_tap2_min_delay 358 335 359 336 ## AC coupled activity, enable

+28 -1

MAINTAINERS

reviewed

··· 651 651 F: Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml 652 652 F: drivers/iio/accel/adxl367* 653 653 654 654 - ADXL372 THREE-AXIS DIGITAL ACCELEROMETER DRIVER 654 654 + ADXL371/ADXL372 THREE-AXIS DIGITAL ACCELEROMETER DRIVER 655 655 M: Michael Hennerich <michael.hennerich@analog.com> 656 656 + M: Marcelo Schmitt <marcelo.schmitt@analog.com> 657 657 + M: Nuno Sá <nuno.sa@analog.com> 658 658 + M: Antoniu Miclaus <antoniu.miclaus@analog.com> 656 659 S: Supported 657 660 W: https://ez.analog.com/linux-software-drivers 658 661 F: Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml ··· 1594 1591 F: Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml 1595 1592 F: drivers/iio/adc/ad7780.c 1596 1593 1594 1594 + ANALOG DEVICES INC AD8366 DRIVER 1595 1595 + M: Michael Hennerich <Michael.Hennerich@analog.com> 1596 1596 + M: Rodrigo Alencar <rodrigo.alencar@analog.com> 1597 1597 + L: linux-iio@vger.kernel.org 1598 1598 + S: Supported 1599 1599 + W: https://ez.analog.com/linux-software-drivers 1600 1600 + F: Documentation/devicetree/bindings/iio/amplifiers/adi,ad8366.yaml 1601 1601 + F: drivers/iio/amplifiers/ad8366.c 1602 1602 + 1597 1603 ANALOG DEVICES INC AD9467 DRIVER 1598 1604 M: Michael Hennerich <Michael.Hennerich@analog.com> 1599 1605 M: Nuno Sa <nuno.sa@analog.com> ··· 1710 1698 S: Supported 1711 1699 W: https://ez.analog.com/linux-software-drivers 1712 1700 F: Documentation/devicetree/bindings/iio/imu/adi,adis16550.yaml 1701 1701 + 1702 1702 + ANALOG DEVICES INC ADL8113 DRIVER 1703 1703 + M: Antoniu Miclaus <antoniu.miclaus@analog.com> 1704 1704 + L: linux-iio@vger.kernel.org 1705 1705 + S: Supported 1706 1706 + W: https://ez.analog.com/linux-software-drivers 1707 1707 + F: Documentation/devicetree/bindings/iio/amplifiers/adi,adl8113.yaml 1708 1708 + F: drivers/iio/amplifiers/adl8113.c 1713 1709 1714 1710 ANALOG DEVICES INC ADM1177 DRIVER 1715 1711 M: Michael Hennerich <Michael.Hennerich@analog.com> ··· 25104 25084 S: Maintained 25105 25085 F: Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml 25106 25086 F: drivers/iio/proximity/vl53l0x-i2c.c 25087 25087 + 25088 25088 + ST VL53L1X ToF RANGER(I2C) IIO DRIVER 25089 25089 + M: Siratul Islam <email@sirat.me> 25090 25090 + L: linux-iio@vger.kernel.org 25091 25091 + S: Maintained 25092 25092 + F: Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml 25093 25093 + F: drivers/iio/proximity/vl53l1x-i2c.c 25107 25094 25108 25095 STABLE BRANCH 25109 25096 M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

+6 -6

drivers/iio/accel/Kconfig

reviewed

··· 158 158 select IIO_TRIGGERED_BUFFER 159 159 160 160 config ADXL372_SPI 161 161 - tristate "Analog Devices ADXL372 3-Axis Accelerometer SPI Driver" 161 161 + tristate "Analog Devices ADXL371/ADXL372 3-Axis Accelerometer SPI Driver" 162 162 depends on SPI 163 163 select ADXL372 164 164 select REGMAP_SPI 165 165 help 166 166 - Say yes here to add support for the Analog Devices ADXL372 triaxial 167 167 - acceleration sensor. 166 166 + Say yes here to add support for the Analog Devices ADXL371/ADXL372 167 167 + triaxial acceleration sensor. 168 168 To compile this driver as a module, choose M here: the 169 169 module will be called adxl372_spi. 170 170 171 171 config ADXL372_I2C 172 172 - tristate "Analog Devices ADXL372 3-Axis Accelerometer I2C Driver" 172 172 + tristate "Analog Devices ADXL371/ADXL372 3-Axis Accelerometer I2C Driver" 173 173 depends on I2C 174 174 select ADXL372 175 175 select REGMAP_I2C 176 176 help 177 177 - Say yes here to add support for the Analog Devices ADXL372 triaxial 178 178 - acceleration sensor. 177 177 + Say yes here to add support for the Analog Devices ADXL371/ADXL372 178 178 + triaxial acceleration sensor. 179 179 To compile this driver as a module, choose M here: the 180 180 module will be called adxl372_i2c. 181 181

+1 -1

drivers/iio/accel/adis16201.c

reviewed

··· 147 147 /* 148 148 * The raw ADC value is 1278 when the temperature 149 149 * is 25 degrees and the scale factor per milli 150 150 - * degree celcius is -470. 150 150 + * degree Celsius is -470. 151 151 */ 152 152 *val = 25000 / -470 - 1278; 153 153 return IIO_VAL_INT;

+1 -1

drivers/iio/accel/adis16209.c

reviewed

··· 186 186 /* 187 187 * The raw ADC value is 0x4FE when the temperature 188 188 * is 45 degrees and the scale factor per milli 189 189 - * degree celcius is -470. 189 189 + * degree Celsius is -470. 190 190 */ 191 191 *val = 25000 / -470 - 0x4FE; 192 192 return IIO_VAL_INT;

+4 -7

drivers/iio/accel/adxl313_core.c

reviewed

··· 8 8 */ 9 9 10 10 #include <linux/bitfield.h> 11 11 + #include <linux/cleanup.h> 11 12 #include <linux/interrupt.h> 12 13 #include <linux/module.h> 13 14 #include <linux/overflow.h> ··· 357 356 { 358 357 int ret; 359 358 360 360 - mutex_lock(&data->lock); 359 359 + guard(mutex)(&data->lock); 361 360 362 361 ret = regmap_bulk_read(data->regmap, 363 362 ADXL313_REG_DATA_AXIS(chan->address), 364 363 &data->transf_buf, sizeof(data->transf_buf)); 365 364 if (ret) 366 366 - goto unlock_ret; 365 365 + return ret; 367 366 368 368 - ret = le16_to_cpu(data->transf_buf); 369 369 - 370 370 - unlock_ret: 371 371 - mutex_unlock(&data->lock); 372 372 - return ret; 367 367 + return le16_to_cpu(data->transf_buf); 373 368 } 374 369 375 370 static int adxl313_read_freq_avail(struct iio_dev *indio_dev,

+24 -8

drivers/iio/accel/adxl345_core.c

reviewed

··· 213 213 .dir = IIO_EV_DIR_RISING, 214 214 .mask_shared_by_type = 215 215 BIT(IIO_EV_INFO_ENABLE) | 216 216 + BIT(IIO_EV_INFO_SCALE) | 216 217 BIT(IIO_EV_INFO_VALUE), 217 218 }, 218 219 { ··· 222 221 .dir = IIO_EV_DIR_RISING, 223 222 .mask_shared_by_type = 224 223 BIT(IIO_EV_INFO_ENABLE) | 224 224 + BIT(IIO_EV_INFO_SCALE) | 225 225 BIT(IIO_EV_INFO_VALUE), 226 226 }, 227 227 { ··· 230 228 .type = IIO_EV_TYPE_GESTURE, 231 229 .dir = IIO_EV_DIR_SINGLETAP, 232 230 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 233 233 - .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 231 231 + .mask_shared_by_type = 232 232 + BIT(IIO_EV_INFO_SCALE) | 233 233 + BIT(IIO_EV_INFO_VALUE) | 234 234 BIT(IIO_EV_INFO_TIMEOUT), 235 235 }, 236 236 { 237 237 /* double tap */ 238 238 .type = IIO_EV_TYPE_GESTURE, 239 239 .dir = IIO_EV_DIR_DOUBLETAP, 240 240 - .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) | 240 240 + .mask_shared_by_type = 241 241 + BIT(IIO_EV_INFO_ENABLE) | 242 242 + BIT(IIO_EV_INFO_SCALE) | 243 243 + BIT(IIO_EV_INFO_VALUE) | 241 244 BIT(IIO_EV_INFO_RESET_TIMEOUT) | 242 245 BIT(IIO_EV_INFO_TAP2_MIN_DELAY), 243 246 }, ··· 281 274 .dir = IIO_EV_DIR_FALLING, 282 275 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 283 276 .mask_shared_by_type = 277 277 + BIT(IIO_EV_INFO_SCALE) | 284 278 BIT(IIO_EV_INFO_VALUE) | 285 279 BIT(IIO_EV_INFO_PERIOD), 286 280 }, ··· 291 283 .dir = IIO_EV_DIR_FALLING, 292 284 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 293 285 .mask_shared_by_type = 286 286 + BIT(IIO_EV_INFO_SCALE) | 294 287 BIT(IIO_EV_INFO_VALUE) | 295 288 BIT(IIO_EV_INFO_PERIOD), 296 289 }, ··· 1350 1341 unsigned int tap_threshold; 1351 1342 int ret; 1352 1343 1344 1344 + /* 1345 1345 + * The event threshold LSB is fixed at 62.5 mg/LSB 1346 1346 + * 0.0625 * 9.80665 = 0.612915625 m/s^2 1347 1347 + */ 1348 1348 + if (info == IIO_EV_INFO_SCALE) { 1349 1349 + *val = 0; 1350 1350 + *val2 = 612915; 1351 1351 + return IIO_VAL_INT_PLUS_MICRO; 1352 1352 + } 1353 1353 + 1353 1354 switch (type) { 1354 1355 case IIO_EV_TYPE_MAG: 1355 1356 return adxl345_read_mag_value(st, dir, info, ··· 1374 1355 case IIO_EV_TYPE_GESTURE: 1375 1356 switch (info) { 1376 1357 case IIO_EV_INFO_VALUE: 1377 1377 - /* 1378 1378 - * The scale factor would be 62.5mg/LSB (i.e. 0xFF = 16g) but 1379 1379 - * not applied here. In context of this general purpose sensor, 1380 1380 - * what imports is rather signal intensity than the absolute 1381 1381 - * measured g value. 1382 1382 - */ 1383 1358 ret = regmap_read(st->regmap, ADXL345_REG_THRESH_TAP, 1384 1359 &tap_threshold); 1385 1360 if (ret) ··· 1413 1400 ret = adxl345_set_measure_en(st, false); 1414 1401 if (ret) 1415 1402 return ret; 1403 1403 + 1404 1404 + if (info == IIO_EV_INFO_SCALE) 1405 1405 + return -EINVAL; 1416 1406 1417 1407 switch (type) { 1418 1408 case IIO_EV_TYPE_MAG:

+193 -121

drivers/iio/accel/adxl372.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0+ 2 2 /* 3 3 - * ADXL372 3-Axis Digital Accelerometer core driver 3 3 + * ADXL371/ADXL372 3-Axis Digital Accelerometer core driver 4 4 * 5 5 * Copyright 2018 Analog Devices Inc. 6 6 */ 7 7 8 8 #include <linux/bitfield.h> 9 9 #include <linux/bitops.h> 10 10 + #include <linux/cleanup.h> 10 11 #include <linux/interrupt.h> 11 12 #include <linux/irq.h> 12 13 #include <linux/module.h> ··· 181 180 ADXL372_ODR_1600HZ, 182 181 ADXL372_ODR_3200HZ, 183 182 ADXL372_ODR_6400HZ, 183 183 + ADXL372_ODR_NUM 184 184 + }; 185 185 + 186 186 + enum adxl371_odr { 187 187 + ADXL371_ODR_320HZ, 188 188 + ADXL371_ODR_640HZ, 189 189 + ADXL371_ODR_1280HZ, 190 190 + ADXL371_ODR_2560HZ, 191 191 + ADXL371_ODR_5120HZ, 192 192 + ADXL371_ODR_NUM 184 193 }; 185 194 186 195 enum adxl372_bandwidth { ··· 225 214 ADXL372_FIFO_OLD_SAVED 226 215 }; 227 216 228 228 - static const int adxl372_samp_freq_tbl[5] = { 229 229 - 400, 800, 1600, 3200, 6400, 217 217 + static const int adxl372_samp_freq_tbl[ADXL372_ODR_NUM] = { 218 218 + [ADXL372_ODR_400HZ] = 400, 219 219 + [ADXL372_ODR_800HZ] = 800, 220 220 + [ADXL372_ODR_1600HZ] = 1600, 221 221 + [ADXL372_ODR_3200HZ] = 3200, 222 222 + [ADXL372_ODR_6400HZ] = 6400, 230 223 }; 231 224 232 232 - static const int adxl372_bw_freq_tbl[5] = { 233 233 - 200, 400, 800, 1600, 3200, 225 225 + static const int adxl372_bw_freq_tbl[ADXL372_ODR_NUM] = { 226 226 + [ADXL372_BW_200HZ] = 200, 227 227 + [ADXL372_BW_400HZ] = 400, 228 228 + [ADXL372_BW_800HZ] = 800, 229 229 + [ADXL372_BW_1600HZ] = 1600, 230 230 + [ADXL372_BW_3200HZ] = 3200, 234 231 }; 232 232 + 233 233 + static const int adxl371_samp_freq_tbl[ADXL371_ODR_NUM] = { 234 234 + [ADXL371_ODR_320HZ] = 320, 235 235 + [ADXL371_ODR_640HZ] = 640, 236 236 + [ADXL371_ODR_1280HZ] = 1280, 237 237 + [ADXL371_ODR_2560HZ] = 2560, 238 238 + [ADXL371_ODR_5120HZ] = 5120, 239 239 + }; 240 240 + 241 241 + static const int adxl371_bw_freq_tbl[ADXL371_ODR_NUM] = { 242 242 + [ADXL371_ODR_320HZ] = 160, 243 243 + [ADXL371_ODR_640HZ] = 320, 244 244 + [ADXL371_ODR_1280HZ] = 640, 245 245 + [ADXL371_ODR_2560HZ] = 1280, 246 246 + [ADXL371_ODR_5120HZ] = 2560, 247 247 + }; 248 248 + 249 249 + const struct adxl372_chip_info adxl371_chip_info = { 250 250 + .name = "adxl371", 251 251 + .samp_freq_tbl = adxl371_samp_freq_tbl, 252 252 + .bw_freq_tbl = adxl371_bw_freq_tbl, 253 253 + .num_freqs = ARRAY_SIZE(adxl371_samp_freq_tbl), 254 254 + .act_time_scale_us = 4125, 255 255 + .act_time_scale_low_us = 8250, 256 256 + .inact_time_scale_ms = 16, 257 257 + .inact_time_scale_low_ms = 32, 258 258 + .max_odr = ADXL371_ODR_5120HZ, 259 259 + /* Silicon erratum (er001) causes FIFO data misalignment on ADXL371 */ 260 260 + .fifo_supported = false, 261 261 + }; 262 262 + EXPORT_SYMBOL_NS_GPL(adxl371_chip_info, "IIO_ADXL372"); 263 263 + 264 264 + const struct adxl372_chip_info adxl372_chip_info = { 265 265 + .name = "adxl372", 266 266 + .samp_freq_tbl = adxl372_samp_freq_tbl, 267 267 + .bw_freq_tbl = adxl372_bw_freq_tbl, 268 268 + .num_freqs = ARRAY_SIZE(adxl372_samp_freq_tbl), 269 269 + .act_time_scale_us = 3300, 270 270 + .act_time_scale_low_us = 6600, 271 271 + .inact_time_scale_ms = 13, 272 272 + .inact_time_scale_low_ms = 26, 273 273 + .max_odr = ADXL372_ODR_6400HZ, 274 274 + .fifo_supported = true, 275 275 + }; 276 276 + EXPORT_SYMBOL_NS_GPL(adxl372_chip_info, "IIO_ADXL372"); 235 277 236 278 struct adxl372_axis_lookup { 237 279 unsigned int bits; ··· 321 257 .modified = 1, \ 322 258 .channel2 = IIO_MOD_##axis, \ 323 259 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 324 324 - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 325 325 - BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 260 260 + .info_mask_shared_by_type = \ 261 261 + BIT(IIO_CHAN_INFO_SCALE) | \ 262 262 + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 263 263 + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 264 264 + .info_mask_shared_by_type_available = \ 265 265 + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 326 266 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 327 267 .scan_index = index, \ 328 268 .scan_type = { \ ··· 347 279 }; 348 280 349 281 struct adxl372_state { 282 282 + const struct adxl372_chip_info *chip_info; 350 283 int irq; 351 284 struct device *dev; 352 285 struct regmap *regmap; ··· 405 336 struct adxl372_state *st = iio_priv(indio_dev); 406 337 int ret; 407 338 408 408 - mutex_lock(&st->threshold_m); 339 339 + guard(mutex)(&st->threshold_m); 340 340 + 409 341 ret = regmap_write(st->regmap, addr, ADXL372_THRESH_VAL_H_SEL(threshold)); 410 342 if (ret < 0) 411 411 - goto unlock; 343 343 + return ret; 412 344 413 413 - ret = regmap_update_bits(st->regmap, addr + 1, GENMASK(7, 5), 414 414 - ADXL372_THRESH_VAL_L_SEL(threshold) << 5); 415 415 - 416 416 - unlock: 417 417 - mutex_unlock(&st->threshold_m); 418 418 - 419 419 - return ret; 345 345 + return regmap_update_bits(st->regmap, addr + 1, GENMASK(7, 5), 346 346 + ADXL372_THRESH_VAL_L_SEL(threshold) << 5); 420 347 } 421 348 422 349 static int adxl372_read_axis(struct adxl372_state *st, u8 addr) ··· 536 471 int ret; 537 472 538 473 /* 539 539 - * 3.3 ms per code is the scale factor of the TIME_ACT register for 540 540 - * ODR = 6400 Hz. It is 6.6 ms per code for ODR = 3200 Hz and below. 474 474 + * The scale factor of the TIME_ACT register depends on the ODR. 475 475 + * A higher scale factor is used at the maximum ODR and a lower 476 476 + * one at all other rates. 541 477 */ 542 542 - if (st->odr == ADXL372_ODR_6400HZ) 543 543 - scale_factor = 3300; 478 478 + if (st->odr == st->chip_info->max_odr) 479 479 + scale_factor = st->chip_info->act_time_scale_us; 544 480 else 545 545 - scale_factor = 6600; 481 481 + scale_factor = st->chip_info->act_time_scale_low_us; 546 482 547 483 reg_val = DIV_ROUND_CLOSEST(act_time_ms * 1000, scale_factor); 548 484 ··· 567 501 int ret; 568 502 569 503 /* 570 570 - * 13 ms per code is the scale factor of the TIME_INACT register for 571 571 - * ODR = 6400 Hz. It is 26 ms per code for ODR = 3200 Hz and below. 504 504 + * The scale factor of the TIME_INACT register depends on the ODR. 505 505 + * A higher scale factor is used at the maximum ODR and a lower 506 506 + * one at all other rates. 572 507 */ 573 573 - if (st->odr == ADXL372_ODR_6400HZ) 574 574 - scale_factor = 13; 508 508 + if (st->odr == st->chip_info->max_odr) 509 509 + scale_factor = st->chip_info->inact_time_scale_ms; 575 510 else 576 576 - scale_factor = 26; 511 511 + scale_factor = st->chip_info->inact_time_scale_low_ms; 577 512 578 513 res = DIV_ROUND_CLOSEST(inact_time_ms, scale_factor); 579 514 reg_val_h = (res >> 8) & 0xFF; ··· 784 717 if (ret < 0) 785 718 return ret; 786 719 787 787 - ret = adxl372_set_odr(st, ADXL372_ODR_6400HZ); 720 720 + ret = adxl372_set_odr(st, st->chip_info->max_odr); 788 721 if (ret < 0) 789 722 return ret; 790 723 ··· 844 777 *val2 = ADXL372_USCALE; 845 778 return IIO_VAL_INT_PLUS_MICRO; 846 779 case IIO_CHAN_INFO_SAMP_FREQ: 847 847 - *val = adxl372_samp_freq_tbl[st->odr]; 780 780 + *val = st->chip_info->samp_freq_tbl[st->odr]; 848 781 return IIO_VAL_INT; 849 782 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 850 850 - *val = adxl372_bw_freq_tbl[st->bw]; 783 783 + *val = st->chip_info->bw_freq_tbl[st->bw]; 851 784 return IIO_VAL_INT; 852 785 } 853 786 ··· 863 796 864 797 switch (info) { 865 798 case IIO_CHAN_INFO_SAMP_FREQ: 866 866 - odr_index = adxl372_find_closest_match(adxl372_samp_freq_tbl, 867 867 - ARRAY_SIZE(adxl372_samp_freq_tbl), 868 868 - val); 799 799 + odr_index = adxl372_find_closest_match(st->chip_info->samp_freq_tbl, 800 800 + st->chip_info->num_freqs, 801 801 + val); 869 802 ret = adxl372_set_odr(st, odr_index); 870 803 if (ret < 0) 871 804 return ret; 872 872 - /* 873 873 - * The timer period depends on the ODR selected. 874 874 - * At 3200 Hz and below, it is 6.6 ms; at 6400 Hz, it is 3.3 ms 875 875 - */ 805 805 + /* Recalculate activity time as the timer period depends on ODR */ 876 806 ret = adxl372_set_activity_time_ms(st, st->act_time_ms); 877 807 if (ret < 0) 878 808 return ret; 879 879 - /* 880 880 - * The timer period depends on the ODR selected. 881 881 - * At 3200 Hz and below, it is 26 ms; at 6400 Hz, it is 13 ms 882 882 - */ 809 809 + /* Recalculate inactivity time as the timer period depends on ODR */ 883 810 ret = adxl372_set_inactivity_time_ms(st, st->inact_time_ms); 884 811 if (ret < 0) 885 812 return ret; ··· 886 825 887 826 return ret; 888 827 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 889 889 - bw_index = adxl372_find_closest_match(adxl372_bw_freq_tbl, 890 890 - ARRAY_SIZE(adxl372_bw_freq_tbl), 891 891 - val); 828 828 + bw_index = adxl372_find_closest_match(st->chip_info->bw_freq_tbl, 829 829 + st->chip_info->num_freqs, 830 830 + val); 892 831 return adxl372_set_bandwidth(st, bw_index); 893 832 default: 894 833 return -EINVAL; ··· 1016 955 } 1017 956 1018 957 return adxl372_set_interrupts(st, st->int1_bitmask, 0); 1019 1019 - } 1020 1020 - 1021 1021 - static ssize_t adxl372_show_filter_freq_avail(struct device *dev, 1022 1022 - struct device_attribute *attr, 1023 1023 - char *buf) 1024 1024 - { 1025 1025 - struct iio_dev *indio_dev = dev_to_iio_dev(dev); 1026 1026 - struct adxl372_state *st = iio_priv(indio_dev); 1027 1027 - int i; 1028 1028 - size_t len = 0; 1029 1029 - 1030 1030 - for (i = 0; i <= st->odr; i++) 1031 1031 - len += scnprintf(buf + len, PAGE_SIZE - len, 1032 1032 - "%d ", adxl372_bw_freq_tbl[i]); 1033 1033 - 1034 1034 - buf[len - 1] = '\n'; 1035 1035 - 1036 1036 - return len; 1037 958 } 1038 959 1039 960 static ssize_t adxl372_get_fifo_enabled(struct device *dev, ··· 1185 1142 .set_trigger_state = adxl372_peak_dready_trig_set_state, 1186 1143 }; 1187 1144 1188 1188 - static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("400 800 1600 3200 6400"); 1189 1189 - static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available, 1190 1190 - 0444, adxl372_show_filter_freq_avail, NULL, 0); 1145 1145 + static int adxl372_read_avail(struct iio_dev *indio_dev, 1146 1146 + struct iio_chan_spec const *chan, 1147 1147 + const int **vals, int *type, int *length, 1148 1148 + long mask) 1149 1149 + { 1150 1150 + struct adxl372_state *st = iio_priv(indio_dev); 1191 1151 1192 1192 - static struct attribute *adxl372_attributes[] = { 1193 1193 - &iio_const_attr_sampling_frequency_available.dev_attr.attr, 1194 1194 - &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr, 1195 1195 - NULL, 1196 1196 - }; 1197 1197 - 1198 1198 - static const struct attribute_group adxl372_attrs_group = { 1199 1199 - .attrs = adxl372_attributes, 1200 1200 - }; 1152 1152 + switch (mask) { 1153 1153 + case IIO_CHAN_INFO_SAMP_FREQ: 1154 1154 + *vals = st->chip_info->samp_freq_tbl; 1155 1155 + *type = IIO_VAL_INT; 1156 1156 + *length = st->chip_info->num_freqs; 1157 1157 + return IIO_AVAIL_LIST; 1158 1158 + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1159 1159 + *vals = st->chip_info->bw_freq_tbl; 1160 1160 + *type = IIO_VAL_INT; 1161 1161 + /* 1162 1162 + * Bandwidth cannot exceed half the sampling frequency 1163 1163 + * (Nyquist), so limit available values based on current ODR. 1164 1164 + */ 1165 1165 + *length = st->odr + 1; 1166 1166 + return IIO_AVAIL_LIST; 1167 1167 + default: 1168 1168 + return -EINVAL; 1169 1169 + } 1170 1170 + } 1201 1171 1202 1172 static const struct iio_info adxl372_info = { 1203 1173 .validate_trigger = &adxl372_validate_trigger, 1204 1204 - .attrs = &adxl372_attrs_group, 1205 1174 .read_raw = adxl372_read_raw, 1206 1175 .write_raw = adxl372_write_raw, 1176 1176 + .read_avail = adxl372_read_avail, 1207 1177 .read_event_config = adxl372_read_event_config, 1208 1178 .write_event_config = adxl372_write_event_config, 1209 1179 .read_event_value = adxl372_read_event_value, ··· 1231 1175 } 1232 1176 EXPORT_SYMBOL_NS_GPL(adxl372_readable_noinc_reg, "IIO_ADXL372"); 1233 1177 1178 1178 + static int adxl372_buffer_setup(struct iio_dev *indio_dev) 1179 1179 + { 1180 1180 + struct adxl372_state *st = iio_priv(indio_dev); 1181 1181 + struct device *dev = st->dev; 1182 1182 + int ret; 1183 1183 + 1184 1184 + ret = devm_iio_triggered_buffer_setup_ext(dev, indio_dev, NULL, 1185 1185 + adxl372_trigger_handler, 1186 1186 + IIO_BUFFER_DIRECTION_IN, 1187 1187 + &adxl372_buffer_ops, 1188 1188 + adxl372_fifo_attributes); 1189 1189 + if (ret) 1190 1190 + return ret; 1191 1191 + 1192 1192 + if (!st->irq) 1193 1193 + return 0; 1194 1194 + 1195 1195 + st->dready_trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 1196 1196 + indio_dev->name, 1197 1197 + iio_device_id(indio_dev)); 1198 1198 + if (!st->dready_trig) 1199 1199 + return -ENOMEM; 1200 1200 + 1201 1201 + st->peak_datardy_trig = devm_iio_trigger_alloc(dev, "%s-dev%d-peak", 1202 1202 + indio_dev->name, 1203 1203 + iio_device_id(indio_dev)); 1204 1204 + if (!st->peak_datardy_trig) 1205 1205 + return -ENOMEM; 1206 1206 + 1207 1207 + st->dready_trig->ops = &adxl372_trigger_ops; 1208 1208 + st->peak_datardy_trig->ops = &adxl372_peak_data_trigger_ops; 1209 1209 + iio_trigger_set_drvdata(st->dready_trig, indio_dev); 1210 1210 + iio_trigger_set_drvdata(st->peak_datardy_trig, indio_dev); 1211 1211 + ret = devm_iio_trigger_register(dev, st->dready_trig); 1212 1212 + if (ret) 1213 1213 + return ret; 1214 1214 + 1215 1215 + ret = devm_iio_trigger_register(dev, st->peak_datardy_trig); 1216 1216 + if (ret) 1217 1217 + return ret; 1218 1218 + 1219 1219 + indio_dev->trig = iio_trigger_get(st->dready_trig); 1220 1220 + 1221 1221 + return devm_request_irq(dev, st->irq, 1222 1222 + iio_trigger_generic_data_rdy_poll, 1223 1223 + IRQF_TRIGGER_RISING | IRQF_NO_THREAD, 1224 1224 + indio_dev->name, st->dready_trig); 1225 1225 + } 1226 1226 + 1234 1227 int adxl372_probe(struct device *dev, struct regmap *regmap, 1235 1235 - int irq, const char *name) 1228 1228 + int irq, const struct adxl372_chip_info *chip_info) 1236 1229 { 1237 1230 struct iio_dev *indio_dev; 1238 1231 struct adxl372_state *st; ··· 1297 1192 st->dev = dev; 1298 1193 st->regmap = regmap; 1299 1194 st->irq = irq; 1195 1195 + st->chip_info = chip_info; 1300 1196 1301 1197 mutex_init(&st->threshold_m); 1302 1198 1303 1199 indio_dev->channels = adxl372_channels; 1304 1200 indio_dev->num_channels = ARRAY_SIZE(adxl372_channels); 1305 1305 - indio_dev->available_scan_masks = adxl372_channel_masks; 1306 1306 - indio_dev->name = name; 1201 1201 + indio_dev->name = chip_info->name; 1307 1202 indio_dev->info = &adxl372_info; 1308 1308 - indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1203 1203 + 1204 1204 + if (chip_info->fifo_supported) { 1205 1205 + indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1206 1206 + indio_dev->available_scan_masks = adxl372_channel_masks; 1207 1207 + } else { 1208 1208 + indio_dev->modes = INDIO_DIRECT_MODE; 1209 1209 + } 1309 1210 1310 1211 ret = adxl372_setup(st); 1311 1212 if (ret < 0) { ··· 1319 1208 return ret; 1320 1209 } 1321 1210 1322 1322 - ret = devm_iio_triggered_buffer_setup_ext(dev, 1323 1323 - indio_dev, NULL, 1324 1324 - adxl372_trigger_handler, 1325 1325 - IIO_BUFFER_DIRECTION_IN, 1326 1326 - &adxl372_buffer_ops, 1327 1327 - adxl372_fifo_attributes); 1328 1328 - if (ret < 0) 1329 1329 - return ret; 1330 1330 - 1331 1331 - if (st->irq) { 1332 1332 - st->dready_trig = devm_iio_trigger_alloc(dev, 1333 1333 - "%s-dev%d", 1334 1334 - indio_dev->name, 1335 1335 - iio_device_id(indio_dev)); 1336 1336 - if (st->dready_trig == NULL) 1337 1337 - return -ENOMEM; 1338 1338 - 1339 1339 - st->peak_datardy_trig = devm_iio_trigger_alloc(dev, 1340 1340 - "%s-dev%d-peak", 1341 1341 - indio_dev->name, 1342 1342 - iio_device_id(indio_dev)); 1343 1343 - if (!st->peak_datardy_trig) 1344 1344 - return -ENOMEM; 1345 1345 - 1346 1346 - st->dready_trig->ops = &adxl372_trigger_ops; 1347 1347 - st->peak_datardy_trig->ops = &adxl372_peak_data_trigger_ops; 1348 1348 - iio_trigger_set_drvdata(st->dready_trig, indio_dev); 1349 1349 - iio_trigger_set_drvdata(st->peak_datardy_trig, indio_dev); 1350 1350 - ret = devm_iio_trigger_register(dev, st->dready_trig); 1351 1351 - if (ret < 0) 1352 1352 - return ret; 1353 1353 - 1354 1354 - ret = devm_iio_trigger_register(dev, st->peak_datardy_trig); 1355 1355 - if (ret < 0) 1356 1356 - return ret; 1357 1357 - 1358 1358 - indio_dev->trig = iio_trigger_get(st->dready_trig); 1359 1359 - 1360 1360 - ret = devm_request_irq(dev, st->irq, 1361 1361 - iio_trigger_generic_data_rdy_poll, 1362 1362 - IRQF_TRIGGER_RISING | IRQF_NO_THREAD, 1363 1363 - indio_dev->name, st->dready_trig); 1211 1211 + if (chip_info->fifo_supported) { 1212 1212 + ret = adxl372_buffer_setup(indio_dev); 1364 1213 if (ret < 0) 1365 1214 return ret; 1366 1215 } ··· 1330 1259 EXPORT_SYMBOL_NS_GPL(adxl372_probe, "IIO_ADXL372"); 1331 1260 1332 1261 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1333 1333 - MODULE_DESCRIPTION("Analog Devices ADXL372 3-axis accelerometer driver"); 1262 1262 + MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>"); 1263 1263 + MODULE_DESCRIPTION("Analog Devices ADXL371/ADXL372 3-axis accelerometer driver"); 1334 1264 MODULE_LICENSE("GPL");

+18 -2

drivers/iio/accel/adxl372.h

reviewed

··· 1 1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 2 /* 3 3 - * ADXL372 3-Axis Digital Accelerometer 3 3 + * ADXL371/ADXL372 3-Axis Digital Accelerometer 4 4 * 5 5 * Copyright 2018 Analog Devices Inc. 6 6 */ ··· 10 10 11 11 #define ADXL372_REVID 0x03 12 12 13 13 + struct adxl372_chip_info { 14 14 + const char *name; 15 15 + const int *samp_freq_tbl; 16 16 + const int *bw_freq_tbl; 17 17 + unsigned int num_freqs; 18 18 + unsigned int act_time_scale_us; 19 19 + unsigned int act_time_scale_low_us; 20 20 + unsigned int inact_time_scale_ms; 21 21 + unsigned int inact_time_scale_low_ms; 22 22 + unsigned int max_odr; 23 23 + bool fifo_supported; 24 24 + }; 25 25 + 26 26 + extern const struct adxl372_chip_info adxl371_chip_info; 27 27 + extern const struct adxl372_chip_info adxl372_chip_info; 28 28 + 13 29 int adxl372_probe(struct device *dev, struct regmap *regmap, 14 14 - int irq, const char *name); 30 30 + int irq, const struct adxl372_chip_info *chip_info); 15 31 bool adxl372_readable_noinc_reg(struct device *dev, unsigned int reg); 16 32 17 33 #endif /* _ADXL372_H_ */

+11 -6

drivers/iio/accel/adxl372_i2c.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0+ 2 2 /* 3 3 - * ADXL372 3-Axis Digital Accelerometer I2C driver 3 3 + * ADXL371/ADXL372 3-Axis Digital Accelerometer I2C driver 4 4 * 5 5 * Copyright 2018 Analog Devices Inc. 6 6 */ ··· 20 20 21 21 static int adxl372_i2c_probe(struct i2c_client *client) 22 22 { 23 23 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 23 23 + const struct adxl372_chip_info *chip_info; 24 24 struct regmap *regmap; 25 25 unsigned int regval; 26 26 int ret; 27 27 + 28 28 + chip_info = i2c_get_match_data(client); 27 29 28 30 regmap = devm_regmap_init_i2c(client, &adxl372_regmap_config); 29 31 if (IS_ERR(regmap)) ··· 40 38 dev_warn(&client->dev, 41 39 "I2C might not work properly with other devices on the bus"); 42 40 43 43 - return adxl372_probe(&client->dev, regmap, client->irq, id->name); 41 41 + return adxl372_probe(&client->dev, regmap, client->irq, chip_info); 44 42 } 45 43 46 44 static const struct i2c_device_id adxl372_i2c_id[] = { 47 47 - { "adxl372" }, 45 45 + { "adxl371", (kernel_ulong_t)&adxl371_chip_info }, 46 46 + { "adxl372", (kernel_ulong_t)&adxl372_chip_info }, 48 47 { } 49 48 }; 50 49 MODULE_DEVICE_TABLE(i2c, adxl372_i2c_id); 51 50 52 51 static const struct of_device_id adxl372_of_match[] = { 53 53 - { .compatible = "adi,adxl372" }, 52 52 + { .compatible = "adi,adxl371", .data = &adxl371_chip_info }, 53 53 + { .compatible = "adi,adxl372", .data = &adxl372_chip_info }, 54 54 { } 55 55 }; 56 56 MODULE_DEVICE_TABLE(of, adxl372_of_match); ··· 69 65 module_i2c_driver(adxl372_i2c_driver); 70 66 71 67 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 72 72 - MODULE_DESCRIPTION("Analog Devices ADXL372 3-axis accelerometer I2C driver"); 68 68 + MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>"); 69 69 + MODULE_DESCRIPTION("Analog Devices ADXL371/ADXL372 3-axis accelerometer I2C driver"); 73 70 MODULE_LICENSE("GPL"); 74 71 MODULE_IMPORT_NS("IIO_ADXL372");

+11 -6

drivers/iio/accel/adxl372_spi.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0+ 2 2 /* 3 3 - * ADXL372 3-Axis Digital Accelerometer SPI driver 3 3 + * ADXL371/ADXL372 3-Axis Digital Accelerometer SPI driver 4 4 * 5 5 * Copyright 2018 Analog Devices Inc. 6 6 */ ··· 22 22 23 23 static int adxl372_spi_probe(struct spi_device *spi) 24 24 { 25 25 - const struct spi_device_id *id = spi_get_device_id(spi); 25 25 + const struct adxl372_chip_info *chip_info; 26 26 struct regmap *regmap; 27 27 + 28 28 + chip_info = spi_get_device_match_data(spi); 27 29 28 30 regmap = devm_regmap_init_spi(spi, &adxl372_spi_regmap_config); 29 31 if (IS_ERR(regmap)) 30 32 return PTR_ERR(regmap); 31 33 32 32 - return adxl372_probe(&spi->dev, regmap, spi->irq, id->name); 34 34 + return adxl372_probe(&spi->dev, regmap, spi->irq, chip_info); 33 35 } 34 36 35 37 static const struct spi_device_id adxl372_spi_id[] = { 36 36 - { "adxl372", 0 }, 38 38 + { "adxl371", (kernel_ulong_t)&adxl371_chip_info }, 39 39 + { "adxl372", (kernel_ulong_t)&adxl372_chip_info }, 37 40 { } 38 41 }; 39 42 MODULE_DEVICE_TABLE(spi, adxl372_spi_id); 40 43 41 44 static const struct of_device_id adxl372_of_match[] = { 42 42 - { .compatible = "adi,adxl372" }, 45 45 + { .compatible = "adi,adxl371", .data = &adxl371_chip_info }, 46 46 + { .compatible = "adi,adxl372", .data = &adxl372_chip_info }, 43 47 { } 44 48 }; 45 49 MODULE_DEVICE_TABLE(of, adxl372_of_match); ··· 60 56 module_spi_driver(adxl372_spi_driver); 61 57 62 58 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 63 63 - MODULE_DESCRIPTION("Analog Devices ADXL372 3-axis accelerometer SPI driver"); 59 59 + MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>"); 60 60 + MODULE_DESCRIPTION("Analog Devices ADXL371/ADXL372 3-axis accelerometer SPI driver"); 64 61 MODULE_LICENSE("GPL"); 65 62 MODULE_IMPORT_NS("IIO_ADXL372");

+2 -2

drivers/iio/accel/adxl380.c

reviewed

··· 31 31 #define ADXL319_ID_VAL 382 32 32 33 33 #define ADXL380_DEVID_AD_REG 0x00 34 34 - #define ADLX380_PART_ID_REG 0x02 34 34 + #define ADXL380_PART_ID_REG 0x02 35 35 36 36 #define ADXL380_X_DATA_H_REG 0x15 37 37 #define ADXL380_Y_DATA_H_REG 0x17 ··· 1878 1878 if (reg_val != ADXL380_DEVID_AD_VAL) 1879 1879 dev_warn(st->dev, "Unknown chip id %x\n", reg_val); 1880 1880 1881 1881 - ret = regmap_bulk_read(st->regmap, ADLX380_PART_ID_REG, 1881 1881 + ret = regmap_bulk_read(st->regmap, ADXL380_PART_ID_REG, 1882 1882 &st->transf_buf, 2); 1883 1883 if (ret) 1884 1884 return ret;

+2 -2

drivers/iio/accel/bmc150-accel-core.c

reviewed

··· 851 851 wm = data->watermark; 852 852 mutex_unlock(&data->mutex); 853 853 854 854 - return sprintf(buf, "%d\n", wm); 854 854 + return sysfs_emit(buf, "%d\n", wm); 855 855 } 856 856 857 857 static ssize_t bmc150_accel_get_fifo_state(struct device *dev, ··· 866 866 state = data->fifo_mode; 867 867 mutex_unlock(&data->mutex); 868 868 869 869 - return sprintf(buf, "%d\n", state); 869 869 + return sysfs_emit(buf, "%d\n", state); 870 870 } 871 871 872 872 static const struct iio_mount_matrix *

+93 -122

drivers/iio/accel/sca3000.c

reviewed

··· 7 7 * See industrialio/accels/sca3000.h for comments. 8 8 */ 9 9 10 10 + #include <linux/cleanup.h> 10 11 #include <linux/interrupt.h> 11 12 #include <linux/fs.h> 12 13 #include <linux/device.h> ··· 172 171 173 172 /** 174 173 * struct sca3000_chip_info - model dependent parameters 174 174 + * @name: name of the chip 175 175 * @scale: scale * 10^-6 176 176 * @temp_output: some devices have temperature sensors. 177 177 * @measurement_mode_freq: normal mode sampling frequency ··· 195 193 * sca3000 variant. 196 194 **/ 197 195 struct sca3000_chip_info { 196 196 + const char *name; 198 197 unsigned int scale; 199 198 bool temp_output; 200 199 int measurement_mode_freq; ··· 210 207 int mot_det_mult_y[7]; 211 208 }; 212 209 213 213 - enum sca3000_variant { 214 214 - d01, 215 215 - e02, 216 216 - e04, 217 217 - e05, 210 210 + static const struct sca3000_chip_info sca3000_chip_info_d01 = { 211 211 + .name = "sca3000_d01", 212 212 + .scale = 7357, 213 213 + .temp_output = true, 214 214 + .measurement_mode_freq = 250, 215 215 + .measurement_mode_3db_freq = 45, 216 216 + .option_mode_1 = SCA3000_OP_MODE_BYPASS, 217 217 + .option_mode_1_freq = 250, 218 218 + .option_mode_1_3db_freq = 70, 219 219 + .mot_det_mult_xz = { 50, 100, 200, 350, 650, 1300 }, 220 220 + .mot_det_mult_y = { 50, 100, 150, 250, 450, 850, 1750 }, 218 221 }; 219 222 220 220 - /* 221 221 - * Note where option modes are not defined, the chip simply does not 222 222 - * support any. 223 223 - * Other chips in the sca3000 series use i2c and are not included here. 224 224 - * 225 225 - * Some of these devices are only listed in the family data sheet and 226 226 - * do not actually appear to be available. 227 227 - */ 228 228 - static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = { 229 229 - [d01] = { 230 230 - .scale = 7357, 231 231 - .temp_output = true, 232 232 - .measurement_mode_freq = 250, 233 233 - .measurement_mode_3db_freq = 45, 234 234 - .option_mode_1 = SCA3000_OP_MODE_BYPASS, 235 235 - .option_mode_1_freq = 250, 236 236 - .option_mode_1_3db_freq = 70, 237 237 - .mot_det_mult_xz = {50, 100, 200, 350, 650, 1300}, 238 238 - .mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750}, 239 239 - }, 240 240 - [e02] = { 241 241 - .scale = 9810, 242 242 - .measurement_mode_freq = 125, 243 243 - .measurement_mode_3db_freq = 40, 244 244 - .option_mode_1 = SCA3000_OP_MODE_NARROW, 245 245 - .option_mode_1_freq = 63, 246 246 - .option_mode_1_3db_freq = 11, 247 247 - .mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050}, 248 248 - .mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700}, 249 249 - }, 250 250 - [e04] = { 251 251 - .scale = 19620, 252 252 - .measurement_mode_freq = 100, 253 253 - .measurement_mode_3db_freq = 38, 254 254 - .option_mode_1 = SCA3000_OP_MODE_NARROW, 255 255 - .option_mode_1_freq = 50, 256 256 - .option_mode_1_3db_freq = 9, 257 257 - .option_mode_2 = SCA3000_OP_MODE_WIDE, 258 258 - .option_mode_2_freq = 400, 259 259 - .option_mode_2_3db_freq = 70, 260 260 - .mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100}, 261 261 - .mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000}, 262 262 - }, 263 263 - [e05] = { 264 264 - .scale = 61313, 265 265 - .measurement_mode_freq = 200, 266 266 - .measurement_mode_3db_freq = 60, 267 267 - .option_mode_1 = SCA3000_OP_MODE_NARROW, 268 268 - .option_mode_1_freq = 50, 269 269 - .option_mode_1_3db_freq = 9, 270 270 - .option_mode_2 = SCA3000_OP_MODE_WIDE, 271 271 - .option_mode_2_freq = 400, 272 272 - .option_mode_2_3db_freq = 75, 273 273 - .mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900}, 274 274 - .mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600}, 275 275 - }, 223 223 + static const struct sca3000_chip_info sca3000_chip_info_e02 = { 224 224 + .name = "sca3000_e02", 225 225 + .scale = 9810, 226 226 + .measurement_mode_freq = 125, 227 227 + .measurement_mode_3db_freq = 40, 228 228 + .option_mode_1 = SCA3000_OP_MODE_NARROW, 229 229 + .option_mode_1_freq = 63, 230 230 + .option_mode_1_3db_freq = 11, 231 231 + .mot_det_mult_xz = { 100, 150, 300, 550, 1050, 2050 }, 232 232 + .mot_det_mult_y = { 50, 100, 200, 350, 700, 1350, 2700 }, 233 233 + }; 234 234 + 235 235 + static const struct sca3000_chip_info sca3000_chip_info_e04 = { 236 236 + .name = "sca3000_e04", 237 237 + .scale = 19620, 238 238 + .measurement_mode_freq = 100, 239 239 + .measurement_mode_3db_freq = 38, 240 240 + .option_mode_1 = SCA3000_OP_MODE_NARROW, 241 241 + .option_mode_1_freq = 50, 242 242 + .option_mode_1_3db_freq = 9, 243 243 + .option_mode_2 = SCA3000_OP_MODE_WIDE, 244 244 + .option_mode_2_freq = 400, 245 245 + .option_mode_2_3db_freq = 70, 246 246 + .mot_det_mult_xz = { 200, 300, 600, 1100, 2100, 4100 }, 247 247 + .mot_det_mult_y = { 100, 200, 400, 7000, 1400, 2700, 54000 }, 248 248 + }; 249 249 + 250 250 + static const struct sca3000_chip_info sca3000_chip_info_e05 = { 251 251 + .name = "sca3000_e05", 252 252 + .scale = 61313, 253 253 + .measurement_mode_freq = 200, 254 254 + .measurement_mode_3db_freq = 60, 255 255 + .option_mode_1 = SCA3000_OP_MODE_NARROW, 256 256 + .option_mode_1_freq = 50, 257 257 + .option_mode_1_3db_freq = 9, 258 258 + .option_mode_2 = SCA3000_OP_MODE_WIDE, 259 259 + .option_mode_2_freq = 400, 260 260 + .option_mode_2_3db_freq = 75, 261 261 + .mot_det_mult_xz = { 600, 900, 1700, 3200, 6100, 11900 }, 262 262 + .mot_det_mult_y = { 300, 600, 1200, 2000, 4100, 7800, 15600 }, 276 263 }; 277 264 278 265 static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val) ··· 1428 1435 .write_event_config = &sca3000_write_event_config, 1429 1436 }; 1430 1437 1438 1438 + static void sca3000_stop_all_interrupts(void *data) 1439 1439 + { 1440 1440 + struct iio_dev *indio_dev = data; 1441 1441 + struct sca3000_state *st = iio_priv(indio_dev); 1442 1442 + int ret; 1443 1443 + 1444 1444 + guard(mutex)(&st->lock); 1445 1445 + 1446 1446 + ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1); 1447 1447 + if (ret) 1448 1448 + return; 1449 1449 + 1450 1450 + sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR, 1451 1451 + (st->rx[0] & 1452 1452 + ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER | 1453 1453 + SCA3000_REG_INT_MASK_RING_HALF | 1454 1454 + SCA3000_REG_INT_MASK_ALL_INTS))); 1455 1455 + } 1456 1456 + 1431 1457 static int sca3000_probe(struct spi_device *spi) 1432 1458 { 1433 1433 - int ret; 1459 1459 + struct device *dev = &spi->dev; 1434 1460 struct sca3000_state *st; 1435 1461 struct iio_dev *indio_dev; 1462 1462 + int ret; 1436 1463 1437 1437 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1464 1464 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1438 1465 if (!indio_dev) 1439 1466 return -ENOMEM; 1440 1467 1441 1468 st = iio_priv(indio_dev); 1442 1442 - spi_set_drvdata(spi, indio_dev); 1443 1469 st->us = spi; 1444 1470 mutex_init(&st->lock); 1445 1445 - st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi) 1446 1446 - ->driver_data]; 1471 1471 + st->info = spi_get_device_match_data(spi); 1447 1472 1448 1448 - indio_dev->name = spi_get_device_id(spi)->name; 1473 1473 + indio_dev->name = st->info->name; 1449 1474 indio_dev->info = &sca3000_info; 1450 1475 if (st->info->temp_output) { 1451 1476 indio_dev->channels = sca3000_channels_with_temp; ··· 1475 1464 } 1476 1465 indio_dev->modes = INDIO_DIRECT_MODE; 1477 1466 1478 1478 - ret = devm_iio_kfifo_buffer_setup(&spi->dev, indio_dev, 1479 1479 - &sca3000_ring_setup_ops); 1467 1467 + ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, &sca3000_ring_setup_ops); 1480 1468 if (ret) 1481 1469 return ret; 1482 1470 1483 1471 if (spi->irq) { 1484 1484 - ret = request_threaded_irq(spi->irq, 1485 1485 - NULL, 1486 1486 - &sca3000_event_handler, 1487 1487 - IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1488 1488 - "sca3000", 1489 1489 - indio_dev); 1472 1472 + ret = devm_request_threaded_irq(dev, spi->irq, NULL, 1473 1473 + &sca3000_event_handler, 1474 1474 + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1475 1475 + "sca3000", 1476 1476 + indio_dev); 1490 1477 if (ret) 1491 1478 return ret; 1492 1479 } 1493 1480 ret = sca3000_clean_setup(st); 1494 1481 if (ret) 1495 1495 - goto error_free_irq; 1482 1482 + return ret; 1496 1483 1497 1484 ret = sca3000_print_rev(indio_dev); 1498 1485 if (ret) 1499 1499 - goto error_free_irq; 1486 1486 + return ret; 1500 1487 1501 1501 - ret = iio_device_register(indio_dev); 1488 1488 + ret = devm_add_action_or_reset(dev, sca3000_stop_all_interrupts, indio_dev); 1502 1489 if (ret) 1503 1503 - goto error_free_irq; 1490 1490 + return ret; 1504 1491 1505 1505 - return 0; 1506 1506 - 1507 1507 - error_free_irq: 1508 1508 - if (spi->irq) 1509 1509 - free_irq(spi->irq, indio_dev); 1510 1510 - 1511 1511 - return ret; 1512 1512 - } 1513 1513 - 1514 1514 - static int sca3000_stop_all_interrupts(struct sca3000_state *st) 1515 1515 - { 1516 1516 - int ret; 1517 1517 - 1518 1518 - mutex_lock(&st->lock); 1519 1519 - ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1); 1520 1520 - if (ret) 1521 1521 - goto error_ret; 1522 1522 - ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR, 1523 1523 - (st->rx[0] & 1524 1524 - ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER | 1525 1525 - SCA3000_REG_INT_MASK_RING_HALF | 1526 1526 - SCA3000_REG_INT_MASK_ALL_INTS))); 1527 1527 - error_ret: 1528 1528 - mutex_unlock(&st->lock); 1529 1529 - return ret; 1530 1530 - } 1531 1531 - 1532 1532 - static void sca3000_remove(struct spi_device *spi) 1533 1533 - { 1534 1534 - struct iio_dev *indio_dev = spi_get_drvdata(spi); 1535 1535 - struct sca3000_state *st = iio_priv(indio_dev); 1536 1536 - 1537 1537 - iio_device_unregister(indio_dev); 1538 1538 - 1539 1539 - /* Must ensure no interrupts can be generated after this! */ 1540 1540 - sca3000_stop_all_interrupts(st); 1541 1541 - if (spi->irq) 1542 1542 - free_irq(spi->irq, indio_dev); 1492 1492 + return devm_iio_device_register(dev, indio_dev); 1543 1493 } 1544 1494 1545 1495 static const struct spi_device_id sca3000_id[] = { 1546 1546 - {"sca3000_d01", d01}, 1547 1547 - {"sca3000_e02", e02}, 1548 1548 - {"sca3000_e04", e04}, 1549 1549 - {"sca3000_e05", e05}, 1496 1496 + { "sca3000_d01", (kernel_ulong_t)&sca3000_chip_info_d01 }, 1497 1497 + { "sca3000_e02", (kernel_ulong_t)&sca3000_chip_info_e02 }, 1498 1498 + { "sca3000_e04", (kernel_ulong_t)&sca3000_chip_info_e04 }, 1499 1499 + { "sca3000_e05", (kernel_ulong_t)&sca3000_chip_info_e05 }, 1550 1500 { } 1551 1501 }; 1552 1502 MODULE_DEVICE_TABLE(spi, sca3000_id); ··· 1517 1545 .name = "sca3000", 1518 1546 }, 1519 1547 .probe = sca3000_probe, 1520 1520 - .remove = sca3000_remove, 1521 1548 .id_table = sca3000_id, 1522 1549 }; 1523 1550 module_spi_driver(sca3000_driver);

+33

drivers/iio/adc/Kconfig

reviewed

··· 60 60 tristate "Analog Devices AD4030 ADC Driver" 61 61 depends on SPI 62 62 depends on GPIOLIB 63 63 + depends on PWM 63 64 select REGMAP 64 65 select IIO_BUFFER 66 66 + select IIO_BUFFER_DMA 67 67 + select IIO_BUFFER_DMAENGINE 65 68 select IIO_TRIGGERED_BUFFER 69 69 + select SPI_OFFLOAD 70 70 + select SPI_OFFLOAD_TRIGGER_PWM 66 71 help 67 72 Say yes here to build support for Analog Devices AD4030 and AD4630 high speed 68 73 SPI analog to digital converters (ADC). ··· 418 413 select REGMAP_SPI 419 414 select RATIONAL 420 415 select IIO_BUFFER 416 416 + select IIO_BUFFER_DMAENGINE 421 417 select IIO_TRIGGER 422 418 select IIO_TRIGGERED_BUFFER 419 419 + select SPI_OFFLOAD 423 420 help 424 421 Say yes here to build support for Analog Devices AD7768-1 SPI 425 422 simultaneously sampling sigma-delta analog to digital converter (ADC). ··· 1372 1365 1373 1366 To compile this driver as a module, choose M here: the module will 1374 1367 be called qcom-spmi-adc5. 1368 1368 + 1369 1369 + config QCOM_SPMI_ADC5_GEN3 1370 1370 + tristate "Qualcomm Technologies Inc. SPMI PMIC5 GEN3 ADC" 1371 1371 + depends on SPMI && THERMAL 1372 1372 + select REGMAP_SPMI 1373 1373 + select QCOM_VADC_COMMON 1374 1374 + select AUXILIARY_BUS 1375 1375 + help 1376 1376 + IIO Voltage PMIC5 Gen3 ADC driver for Qualcomm Technologies Inc. 1377 1377 + 1378 1378 + The driver supports reading multiple channels. The ADC is a 16-bit 1379 1379 + sigma-delta ADC. The hardware supports calibrated results for 1380 1380 + conversion requests and clients include reading phone power supply 1381 1381 + voltage, on board system thermistors connected to the PMIC ADC, 1382 1382 + PMIC die temperature, charger temperature, battery current, USB 1383 1383 + voltage input and voltage signals connected to supported PMIC GPIO 1384 1384 + pins. The hardware supports internal pull-up for thermistors and can 1385 1385 + choose between a 30k, 100k or 400k ohm pull up using the ADC channels. 1386 1386 + 1387 1387 + In addition, the same driver supports ADC thermal monitoring devices 1388 1388 + too. They appear as thermal zones with multiple trip points. A thermal 1389 1389 + client sets threshold temperature for both warm and cool trips and 1390 1390 + gets updated when a threshold is reached. 1391 1391 + 1392 1392 + To compile this driver as a module, choose M here: the module will 1393 1393 + be called qcom-spmi-adc5-gen3. 1375 1394 1376 1395 config RCAR_GYRO_ADC 1377 1396 tristate "Renesas R-Car GyroADC driver"

+1

drivers/iio/adc/Makefile

reviewed

··· 116 116 obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o 117 117 obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o 118 118 obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o 119 119 + obj-$(CONFIG_QCOM_SPMI_ADC5_GEN3) += qcom-spmi-adc5-gen3.o 119 120 obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o 120 121 obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o 121 122 obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o

+596 -22

drivers/iio/adc/ad4030.c

reviewed

··· 14 14 */ 15 15 16 16 #include <linux/bitfield.h> 17 17 + #include <linux/cleanup.h> 17 18 #include <linux/clk.h> 18 18 - #include <linux/iio/iio.h> 19 19 - #include <linux/iio/trigger_consumer.h> 20 20 - #include <linux/iio/triggered_buffer.h> 19 19 + #include <linux/dmaengine.h> 20 20 + #include <linux/limits.h> 21 21 + #include <linux/log2.h> 22 22 + #include <linux/math64.h> 23 23 + #include <linux/minmax.h> 24 24 + #include <linux/pwm.h> 21 25 #include <linux/regmap.h> 22 26 #include <linux/regulator/consumer.h> 27 27 + #include <linux/spi/offload/consumer.h> 23 28 #include <linux/spi/spi.h> 24 29 #include <linux/unaligned.h> 25 30 #include <linux/units.h> 31 31 + #include <linux/types.h> 32 32 + 33 33 + #include <linux/iio/buffer-dmaengine.h> 34 34 + #include <linux/iio/iio.h> 35 35 + #include <linux/iio/trigger_consumer.h> 36 36 + #include <linux/iio/triggered_buffer.h> 26 37 27 38 #define AD4030_REG_INTERFACE_CONFIG_A 0x00 28 39 #define AD4030_REG_INTERFACE_CONFIG_A_SW_RESET (BIT(0) | BIT(7)) ··· 48 37 #define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00 49 38 #define AD4030_REG_CHIP_GRADE_AD4632_16_GRADE 0x05 50 39 #define AD4030_REG_CHIP_GRADE_AD4632_24_GRADE 0x02 40 40 + #define AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE 0x1E 41 41 + #define AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE 0x1C 51 42 #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) 52 43 #define AD4030_REG_SCRATCH_PAD 0x0A 53 44 #define AD4030_REG_SPI_REVISION 0x0B ··· 124 111 #define AD4632_TCYC_NS 2000 125 112 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS) 126 113 #define AD4030_TRESET_COM_DELAY_MS 750 114 114 + /* Datasheet says 9.8ns, so use the closest integer value */ 115 115 + #define AD4030_TQUIET_CNV_DELAY_NS 10 116 116 + 117 117 + /* HARDWARE_GAIN */ 118 118 + #define ADAQ4616_PGA_PINS 2 119 119 + #define ADAQ4616_PGA_GAIN_MAX_NANO (NANO * 2 / 3) 127 120 128 121 enum ad4030_out_mode { 129 122 AD4030_OUT_DATA_MD_DIFF, ··· 151 132 AD4030_SCAN_TYPE_AVG, 152 133 }; 153 134 135 135 + /* 136 136 + * Gains computed as fractions of 1000 so they can be expressed by integers. 137 137 + */ 138 138 + static const int adaq4216_hw_gains_vpv[] = { 139 139 + 1 * MILLI / 3, /* 0.333 */ 140 140 + 5 * MILLI / 9, /* 0.555 */ 141 141 + 20 * MILLI / 9, /* 0.2222 */ 142 142 + 20 * MILLI / 3, /* 0.6666 */ 143 143 + }; 144 144 + 145 145 + static const int adaq4216_hw_gains_frac[][2] = { 146 146 + { 1, 3 }, /* 1/3 V/V gain */ 147 147 + { 5, 9 }, /* 5/9 V/V gain */ 148 148 + { 20, 9 }, /* 20/9 V/V gain */ 149 149 + { 20, 3 }, /* 20/3 V/V gain */ 150 150 + }; 151 151 + 154 152 struct ad4030_chip_info { 155 153 const char *name; 156 154 const unsigned long *available_masks; 157 155 const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB]; 156 156 + const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; 158 157 u8 grade; 159 158 u8 precision_bits; 159 159 + bool has_pga; 160 160 /* Number of hardware channels */ 161 161 int num_voltage_inputs; 162 162 unsigned int tcyc_ns; 163 163 + unsigned int max_sample_rate_hz; 163 164 }; 164 165 165 166 struct ad4030_state { ··· 192 153 int offset_avail[3]; 193 154 unsigned int avg_log2; 194 155 enum ad4030_out_mode mode; 156 156 + /* Offload sampling */ 157 157 + struct spi_transfer offload_xfer; 158 158 + struct spi_message offload_msg; 159 159 + struct spi_offload *offload; 160 160 + struct spi_offload_trigger *offload_trigger; 161 161 + struct spi_offload_trigger_config offload_trigger_config; 162 162 + struct pwm_device *cnv_trigger; 163 163 + size_t scale_avail_size; 164 164 + struct pwm_waveform cnv_wf; 165 165 + unsigned int scale_avail[ARRAY_SIZE(adaq4216_hw_gains_vpv)][2]; 166 166 + struct gpio_descs *pga_gpios; 167 167 + unsigned int pga_index; 195 168 196 169 /* 197 170 * DMA (thus cache coherency maintenance) requires the transfer buffers ··· 260 209 * - voltage0-voltage1 261 210 * - voltage2-voltage3 262 211 */ 263 263 - #define AD4030_CHAN_DIFF(_idx, _scan_type) { \ 212 212 + #define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload, _pga) { \ 264 213 .info_mask_shared_by_all = \ 214 214 + (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ 265 215 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 266 216 .info_mask_shared_by_all_available = \ 267 217 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ ··· 271 219 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 272 220 BIT(IIO_CHAN_INFO_RAW), \ 273 221 .info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 222 222 + (_pga ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ 274 223 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 275 224 .type = IIO_VOLTAGE, \ 276 225 .indexed = 1, \ ··· 285 232 .num_ext_scan_type = ARRAY_SIZE(_scan_type), \ 286 233 } 287 234 235 235 + #define AD4030_CHAN_DIFF(_idx, _scan_type) \ 236 236 + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 0) 237 237 + 238 238 + #define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ 239 239 + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 0) 240 240 + 241 241 + #define ADAQ4216_CHAN_DIFF(_idx, _scan_type) \ 242 242 + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 1) 243 243 + 244 244 + #define ADAQ4216_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ 245 245 + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 1) 246 246 + 247 247 + /* 248 248 + * AD4030 can average over 2^N samples, where N = 1, 2, 3, ..., 16. 249 249 + * We use N = 0 to mean no sample averaging. 250 250 + */ 288 251 static const int ad4030_average_modes[] = { 289 289 - 1, 2, 4, 8, 16, 32, 64, 128, 290 290 - 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 291 291 - 65536, 252 252 + BIT(0), /* No sampling average */ 253 253 + BIT(1), BIT(2), BIT(3), BIT(4), 254 254 + BIT(5), BIT(6), BIT(7), BIT(8), 255 255 + BIT(9), BIT(10), BIT(11), BIT(12), 256 256 + BIT(13), BIT(14), BIT(15), BIT(16), 257 257 + }; 258 258 + 259 259 + static const struct spi_offload_config ad4030_offload_config = { 260 260 + .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 261 261 + SPI_OFFLOAD_CAP_RX_STREAM_DMA, 292 262 }; 293 263 294 264 static int ad4030_enter_config_mode(struct ad4030_state *st) ··· 453 377 .max_register = AD4030_REG_DIG_ERR, 454 378 }; 455 379 380 380 + static void ad4030_fill_scale_avail(struct ad4030_state *st) 381 381 + { 382 382 + unsigned int mag_bits, int_part, fract_part; 383 383 + u64 range; 384 384 + 385 385 + /* 386 386 + * The maximum precision of differential channels is retrieved from the 387 387 + * chip properties. The output code of differential channels is in two's 388 388 + * complement format (i.e. signed), so the MSB is the sign bit and only 389 389 + * (precision_bits - 1) bits express voltage magnitude. 390 390 + */ 391 391 + mag_bits = st->chip->precision_bits - 1; 392 392 + 393 393 + for (unsigned int i = 0; i < ARRAY_SIZE(adaq4216_hw_gains_frac); i++) { 394 394 + range = mult_frac(st->vref_uv, adaq4216_hw_gains_frac[i][1], 395 395 + adaq4216_hw_gains_frac[i][0]); 396 396 + /* 397 397 + * If range were in mV, we would multiply it by NANO below. 398 398 + * Though, range is in µV so multiply it by MICRO only so the 399 399 + * result after right shift and division scales output codes to 400 400 + * millivolts. 401 401 + */ 402 402 + int_part = div_u64_rem((range * MICRO) >> mag_bits, NANO, &fract_part); 403 403 + st->scale_avail[i][0] = int_part; 404 404 + st->scale_avail[i][1] = fract_part; 405 405 + } 406 406 + } 407 407 + 408 408 + static int ad4030_set_pga_gain(struct ad4030_state *st) 409 409 + { 410 410 + DECLARE_BITMAP(bitmap, ADAQ4616_PGA_PINS) = { }; 411 411 + 412 412 + bitmap_write(bitmap, st->pga_index, 0, ADAQ4616_PGA_PINS); 413 413 + 414 414 + return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); 415 415 + } 416 416 + 417 417 + static int ad4030_set_pga(struct iio_dev *indio_dev, int gain_int, int gain_fract) 418 418 + { 419 419 + struct ad4030_state *st = iio_priv(indio_dev); 420 420 + unsigned int mag_bits = st->chip->precision_bits - 1; 421 421 + unsigned int tmp; 422 422 + u64 gain_nano; 423 423 + 424 424 + if (!st->pga_gpios) 425 425 + return -EINVAL; 426 426 + 427 427 + gain_nano = gain_int * NANO + gain_fract; 428 428 + if (!in_range(gain_nano, 1, ADAQ4616_PGA_GAIN_MAX_NANO)) 429 429 + return -EINVAL; 430 430 + 431 431 + tmp = DIV_ROUND_CLOSEST_ULL(gain_nano << mag_bits, NANO); 432 432 + gain_nano = DIV_ROUND_CLOSEST(st->vref_uv, tmp); 433 433 + st->pga_index = find_closest(gain_nano, adaq4216_hw_gains_vpv, 434 434 + ARRAY_SIZE(adaq4216_hw_gains_vpv)); 435 435 + 436 436 + return ad4030_set_pga_gain(st); 437 437 + } 438 438 + 456 439 static int ad4030_get_chan_scale(struct iio_dev *indio_dev, 457 440 struct iio_chan_spec const *chan, 458 441 int *val, ··· 523 388 scan_type = iio_get_current_scan_type(indio_dev, chan); 524 389 if (IS_ERR(scan_type)) 525 390 return PTR_ERR(scan_type); 391 391 + 392 392 + /* The LSB of the 8-bit common-mode data is always vref/256. */ 393 393 + if (st->chip->has_pga && scan_type->realbits != 8) { 394 394 + *val = st->scale_avail[st->pga_index][0]; 395 395 + *val2 = st->scale_avail[st->pga_index][1]; 396 396 + return IIO_VAL_INT_PLUS_NANO; 397 397 + } 526 398 527 399 if (chan->differential) 528 400 *val = (st->vref_uv * 2) / MILLI; ··· 593 451 } 594 452 } 595 453 454 454 + static void ad4030_get_sampling_freq(struct ad4030_state *st, int *freq) 455 455 + { 456 456 + struct spi_offload_trigger_config *config = &st->offload_trigger_config; 457 457 + 458 458 + /* 459 459 + * Conversion data is fetched from the device when the offload transfer 460 460 + * is triggered. Thus, provide the SPI offload trigger frequency as the 461 461 + * sampling frequency. 462 462 + */ 463 463 + *freq = config->periodic.frequency_hz; 464 464 + } 465 465 + 466 466 + static int ad4030_update_conversion_rate(struct ad4030_state *st, 467 467 + unsigned int freq_hz, unsigned int avg_log2) 468 468 + { 469 469 + struct spi_offload_trigger_config *config = &st->offload_trigger_config; 470 470 + unsigned int offload_period_ns, cnv_rate_hz; 471 471 + struct pwm_waveform cnv_wf = { }; 472 472 + u64 target = AD4030_TCNVH_NS; 473 473 + u64 offload_offset_ns; 474 474 + int ret; 475 475 + 476 476 + /* 477 477 + * When averaging/oversampling over N samples, we fire the offload 478 478 + * trigger once at every N pulses of the CNV signal. Conversely, the CNV 479 479 + * signal needs to be N times faster than the offload trigger. Take that 480 480 + * into account to correctly re-evaluate both the PWM waveform connected 481 481 + * to CNV and the SPI offload trigger. 482 482 + */ 483 483 + cnv_rate_hz = freq_hz << avg_log2; 484 484 + 485 485 + cnv_wf.period_length_ns = DIV_ROUND_CLOSEST(NSEC_PER_SEC, cnv_rate_hz); 486 486 + /* 487 487 + * The datasheet lists a minimum time of 9.8 ns, but no maximum. If the 488 488 + * rounded PWM's value is less than 10, increase the target value by 10 489 489 + * and attempt to round the waveform again, until the value is at least 490 490 + * 10 ns. Use a separate variable to represent the target in case the 491 491 + * rounding is severe enough to keep putting the first few results under 492 492 + * the minimum 10ns condition checked by the while loop. 493 493 + */ 494 494 + do { 495 495 + cnv_wf.duty_length_ns = target; 496 496 + ret = pwm_round_waveform_might_sleep(st->cnv_trigger, &cnv_wf); 497 497 + if (ret) 498 498 + return ret; 499 499 + target += AD4030_TCNVH_NS; 500 500 + } while (cnv_wf.duty_length_ns < AD4030_TCNVH_NS); 501 501 + 502 502 + /* 503 503 + * The CNV waveform period (period_length_ns) might get rounded down by 504 504 + * pwm_round_waveform_might_sleep(). Check the resultant PWM period 505 505 + * is not smaller than the minimum data conversion cycle time. 506 506 + */ 507 507 + if (!in_range(cnv_wf.period_length_ns, AD4030_TCYC_NS, INT_MAX)) 508 508 + return -EINVAL; 509 509 + 510 510 + offload_period_ns = DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq_hz); 511 511 + 512 512 + config->periodic.frequency_hz = DIV_ROUND_UP(HZ_PER_GHZ, offload_period_ns); 513 513 + 514 514 + /* 515 515 + * The hardware does the capture on zone 2 (when SPI trigger PWM 516 516 + * is used). This means that the SPI trigger signal should happen at 517 517 + * tsync + tquiet_con_delay being tsync the conversion signal period 518 518 + * and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly. 519 519 + * 520 520 + * The PWM waveform API only supports nanosecond resolution right now, 521 521 + * so round this setting to the closest available value. 522 522 + */ 523 523 + offload_offset_ns = AD4030_TQUIET_CNV_DELAY_NS; 524 524 + do { 525 525 + config->periodic.offset_ns = offload_offset_ns; 526 526 + ret = spi_offload_trigger_validate(st->offload_trigger, config); 527 527 + if (ret) 528 528 + return ret; 529 529 + offload_offset_ns += AD4030_TQUIET_CNV_DELAY_NS; 530 530 + } while (config->periodic.offset_ns < AD4030_TQUIET_CNV_DELAY_NS); 531 531 + 532 532 + st->cnv_wf = cnv_wf; 533 533 + 534 534 + return 0; 535 535 + } 536 536 + 537 537 + static int ad4030_set_sampling_freq(struct iio_dev *indio_dev, int freq_hz) 538 538 + { 539 539 + struct ad4030_state *st = iio_priv(indio_dev); 540 540 + 541 541 + if (freq_hz == 0) 542 542 + return -EINVAL; 543 543 + 544 544 + if (!in_range(freq_hz, 0, st->chip->max_sample_rate_hz)) 545 545 + return -ERANGE; 546 546 + 547 547 + return ad4030_update_conversion_rate(st, freq_hz, st->avg_log2); 548 548 + } 549 549 + 596 550 static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev, 597 551 struct iio_chan_spec const *chan, 598 552 int gain_int, ··· 748 510 struct ad4030_state *st = iio_priv(dev); 749 511 unsigned int avg_log2 = ilog2(avg_val); 750 512 unsigned int last_avg_idx = ARRAY_SIZE(ad4030_average_modes) - 1; 513 513 + int freq_hz; 751 514 int ret; 752 515 753 516 if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx]) 754 517 return -EINVAL; 518 518 + 519 519 + if (st->offload_trigger) { 520 520 + /* 521 521 + * The sample averaging and sampling frequency configurations 522 522 + * are mutually dependent on each other. That's because the 523 523 + * effective data sample rate is fCNV / 2^N, where N is the 524 524 + * number of samples being averaged. 525 525 + * 526 526 + * When SPI offload is supported and we have control over the 527 527 + * sample rate, the conversion start signal (CNV) and the SPI 528 528 + * offload trigger frequencies must be re-evaluated so data is 529 529 + * fetched only after 'avg_val' conversions. 530 530 + */ 531 531 + ad4030_get_sampling_freq(st, &freq_hz); 532 532 + ret = ad4030_update_conversion_rate(st, freq_hz, avg_log2); 533 533 + if (ret) 534 534 + return ret; 535 535 + } 755 536 756 537 ret = regmap_write(st->regmap, AD4030_REG_AVG, 757 538 AD4030_REG_AVG_MASK_AVG_SYNC | ··· 880 623 /* Add one byte if we are using a differential + common byte mode */ 881 624 bytes_to_read += (st->mode == AD4030_OUT_DATA_MD_24_DIFF_8_COM || 882 625 st->mode == AD4030_OUT_DATA_MD_16_DIFF_8_COM) ? 1 : 0; 883 883 - /* Mulitiply by the number of hardware channels */ 626 626 + /* Multiply by the number of hardware channels */ 884 627 bytes_to_read *= st->chip->num_voltage_inputs; 885 628 886 629 for (i = 0; i < cnv_nb; i++) { ··· 999 742 *length = ARRAY_SIZE(ad4030_average_modes); 1000 743 return IIO_AVAIL_LIST; 1001 744 745 745 + case IIO_CHAN_INFO_SCALE: 746 746 + if (st->scale_avail_size == 1) 747 747 + *vals = (int *)st->scale_avail[st->pga_index]; 748 748 + else 749 749 + *vals = (int *)st->scale_avail; 750 750 + *length = st->scale_avail_size * 2; /* print int and nano part */ 751 751 + *type = IIO_VAL_INT_PLUS_NANO; 752 752 + return IIO_AVAIL_LIST; 753 753 + 1002 754 default: 1003 755 return -EINVAL; 1004 756 } ··· 1031 765 1032 766 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1033 767 *val = BIT(st->avg_log2); 768 768 + return IIO_VAL_INT; 769 769 + 770 770 + case IIO_CHAN_INFO_SAMP_FREQ: 771 771 + ad4030_get_sampling_freq(st, val); 1034 772 return IIO_VAL_INT; 1035 773 1036 774 default: ··· 1077 807 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1078 808 return ad4030_set_avg_frame_len(indio_dev, val); 1079 809 810 810 + case IIO_CHAN_INFO_SAMP_FREQ: 811 811 + return ad4030_set_sampling_freq(indio_dev, val); 812 812 + 813 813 + case IIO_CHAN_INFO_SCALE: 814 814 + return ad4030_set_pga(indio_dev, val, val2); 815 815 + 1080 816 default: 1081 817 return -EINVAL; 1082 818 } ··· 1102 826 iio_device_release_direct(indio_dev); 1103 827 1104 828 return ret; 829 829 + } 830 830 + 831 831 + static int ad4030_write_raw_get_fmt(struct iio_dev *indio_dev, 832 832 + struct iio_chan_spec const *chan, long mask) 833 833 + { 834 834 + switch (mask) { 835 835 + case IIO_CHAN_INFO_SCALE: 836 836 + return IIO_VAL_INT_PLUS_NANO; 837 837 + default: 838 838 + return IIO_VAL_INT_PLUS_MICRO; 839 839 + } 1105 840 } 1106 841 1107 842 static int ad4030_reg_access(struct iio_dev *indio_dev, unsigned int reg, ··· 1161 874 .read_avail = ad4030_read_avail, 1162 875 .read_raw = ad4030_read_raw, 1163 876 .write_raw = ad4030_write_raw, 877 877 + .write_raw_get_fmt = &ad4030_write_raw_get_fmt, 1164 878 .debugfs_reg_access = ad4030_reg_access, 1165 879 .read_label = ad4030_read_label, 1166 880 .get_current_scan_type = ad4030_get_current_scan_type, ··· 1182 894 1183 895 static const struct iio_buffer_setup_ops ad4030_buffer_setup_ops = { 1184 896 .validate_scan_mask = ad4030_validate_scan_mask, 897 897 + }; 898 898 + 899 899 + static void ad4030_prepare_offload_msg(struct iio_dev *indio_dev) 900 900 + { 901 901 + struct ad4030_state *st = iio_priv(indio_dev); 902 902 + u8 offload_bpw; 903 903 + 904 904 + if (st->mode == AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) 905 905 + offload_bpw = 32; 906 906 + else 907 907 + offload_bpw = st->chip->precision_bits; 908 908 + 909 909 + st->offload_xfer.bits_per_word = offload_bpw; 910 910 + st->offload_xfer.len = spi_bpw_to_bytes(offload_bpw); 911 911 + st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 912 912 + spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); 913 913 + } 914 914 + 915 915 + static int ad4030_offload_buffer_postenable(struct iio_dev *indio_dev) 916 916 + { 917 917 + struct ad4030_state *st = iio_priv(indio_dev); 918 918 + unsigned int reg_modes; 919 919 + int ret; 920 920 + 921 921 + /* 922 922 + * When data from 2 analog input channels is output through a single 923 923 + * bus line (interleaved mode (LANE_MD == 0b11)) and gets pushed through 924 924 + * DMA, extra hardware is required to do the de-interleaving. While we 925 925 + * don't support such hardware configurations, disallow interleaved mode 926 926 + * when using SPI offload. 927 927 + */ 928 928 + ret = regmap_read(st->regmap, AD4030_REG_MODES, &reg_modes); 929 929 + if (ret) 930 930 + return ret; 931 931 + 932 932 + if (st->chip->num_voltage_inputs > 1 && 933 933 + FIELD_GET(AD4030_REG_MODES_MASK_LANE_MODE, reg_modes) == AD4030_LANE_MD_INTERLEAVED) 934 934 + return -EINVAL; 935 935 + 936 936 + ad4030_prepare_offload_msg(indio_dev); 937 937 + st->offload_msg.offload = st->offload; 938 938 + ret = spi_optimize_message(st->spi, &st->offload_msg); 939 939 + if (ret) 940 940 + return ret; 941 941 + 942 942 + ret = pwm_set_waveform_might_sleep(st->cnv_trigger, &st->cnv_wf, false); 943 943 + if (ret) 944 944 + goto out_unoptimize; 945 945 + 946 946 + ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, 947 947 + &st->offload_trigger_config); 948 948 + if (ret) 949 949 + goto out_pwm_disable; 950 950 + 951 951 + return 0; 952 952 + 953 953 + out_pwm_disable: 954 954 + pwm_disable(st->cnv_trigger); 955 955 + out_unoptimize: 956 956 + spi_unoptimize_message(&st->offload_msg); 957 957 + 958 958 + return ret; 959 959 + } 960 960 + 961 961 + static int ad4030_offload_buffer_predisable(struct iio_dev *indio_dev) 962 962 + { 963 963 + struct ad4030_state *st = iio_priv(indio_dev); 964 964 + 965 965 + spi_offload_trigger_disable(st->offload, st->offload_trigger); 966 966 + 967 967 + pwm_disable(st->cnv_trigger); 968 968 + 969 969 + spi_unoptimize_message(&st->offload_msg); 970 970 + 971 971 + return 0; 972 972 + } 973 973 + 974 974 + static const struct iio_buffer_setup_ops ad4030_offload_buffer_setup_ops = { 975 975 + .postenable = &ad4030_offload_buffer_postenable, 976 976 + .predisable = &ad4030_offload_buffer_predisable, 1185 977 }; 1186 978 1187 979 static int ad4030_regulators_get(struct ad4030_state *st) ··· 1333 965 return 0; 1334 966 } 1335 967 968 968 + static int ad4030_pwm_get(struct ad4030_state *st) 969 969 + { 970 970 + struct device *dev = &st->spi->dev; 971 971 + 972 972 + st->cnv_trigger = devm_pwm_get(dev, NULL); 973 973 + if (IS_ERR(st->cnv_trigger)) 974 974 + return dev_err_probe(dev, PTR_ERR(st->cnv_trigger), 975 975 + "Failed to get CNV PWM\n"); 976 976 + 977 977 + /* 978 978 + * Preemptively disable the PWM, since we only want to enable it with 979 979 + * the buffer. 980 980 + */ 981 981 + pwm_disable(st->cnv_trigger); 982 982 + 983 983 + return 0; 984 984 + } 985 985 + 1336 986 static int ad4030_config(struct ad4030_state *st) 1337 987 { 1338 988 int ret; ··· 1374 988 if (st->vio_uv < AD4030_VIO_THRESHOLD_UV) 1375 989 return regmap_write(st->regmap, AD4030_REG_IO, 1376 990 AD4030_REG_IO_MASK_IO2X); 991 991 + 992 992 + return 0; 993 993 + } 994 994 + 995 995 + static int ad4030_spi_offload_setup(struct iio_dev *indio_dev, 996 996 + struct ad4030_state *st) 997 997 + { 998 998 + struct device *dev = &st->spi->dev; 999 999 + struct dma_chan *rx_dma; 1000 1000 + 1001 1001 + indio_dev->setup_ops = &ad4030_offload_buffer_setup_ops; 1002 1002 + 1003 1003 + st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 1004 1004 + SPI_OFFLOAD_TRIGGER_PERIODIC); 1005 1005 + if (IS_ERR(st->offload_trigger)) 1006 1006 + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1007 1007 + "failed to get offload trigger\n"); 1008 1008 + 1009 1009 + st->offload_trigger_config.type = SPI_OFFLOAD_TRIGGER_PERIODIC; 1010 1010 + 1011 1011 + rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 1012 1012 + if (IS_ERR(rx_dma)) 1013 1013 + return dev_err_probe(dev, PTR_ERR(rx_dma), 1014 1014 + "failed to get offload RX DMA\n"); 1015 1015 + 1016 1016 + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, 1017 1017 + IIO_BUFFER_DIRECTION_IN); 1018 1018 + } 1019 1019 + 1020 1020 + static int ad4030_setup_pga(struct device *dev, struct iio_dev *indio_dev, 1021 1021 + struct ad4030_state *st) 1022 1022 + { 1023 1023 + /* Setup GPIOs for PGA control */ 1024 1024 + st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); 1025 1025 + if (IS_ERR(st->pga_gpios)) 1026 1026 + return dev_err_probe(dev, PTR_ERR(st->pga_gpios), 1027 1027 + "Failed to get PGA gpios.\n"); 1028 1028 + 1029 1029 + if (st->pga_gpios->ndescs != ADAQ4616_PGA_PINS) 1030 1030 + return dev_err_probe(dev, -EINVAL, 1031 1031 + "Expected %d GPIOs for PGA control.\n", 1032 1032 + ADAQ4616_PGA_PINS); 1033 1033 + 1034 1034 + st->scale_avail_size = ARRAY_SIZE(adaq4216_hw_gains_vpv); 1035 1035 + st->pga_index = 0; 1377 1036 1378 1037 return 0; 1379 1038 } ··· 1465 1034 if (ret) 1466 1035 return ret; 1467 1036 1037 1037 + if (st->chip->has_pga) { 1038 1038 + ret = ad4030_setup_pga(dev, indio_dev, st); 1039 1039 + if (ret) 1040 1040 + return ret; 1041 1041 + 1042 1042 + ad4030_fill_scale_avail(st); 1043 1043 + } 1044 1044 + 1468 1045 ret = ad4030_config(st); 1469 1046 if (ret) 1470 1047 return ret; ··· 1482 1043 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), 1483 1044 "Failed to get cnv gpio\n"); 1484 1045 1485 1485 - /* 1486 1486 - * One hardware channel is split in two software channels when using 1487 1487 - * common byte mode. Add one more channel for the timestamp. 1488 1488 - */ 1489 1489 - indio_dev->num_channels = 2 * st->chip->num_voltage_inputs + 1; 1490 1046 indio_dev->name = st->chip->name; 1491 1047 indio_dev->modes = INDIO_DIRECT_MODE; 1492 1048 indio_dev->info = &ad4030_iio_info; 1493 1493 - indio_dev->channels = st->chip->channels; 1494 1049 indio_dev->available_scan_masks = st->chip->available_masks; 1495 1050 1496 1496 - ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1497 1497 - iio_pollfunc_store_time, 1498 1498 - ad4030_trigger_handler, 1499 1499 - &ad4030_buffer_setup_ops); 1500 1500 - if (ret) 1501 1501 - return dev_err_probe(dev, ret, 1502 1502 - "Failed to setup triggered buffer\n"); 1051 1051 + st->offload = devm_spi_offload_get(dev, spi, &ad4030_offload_config); 1052 1052 + ret = PTR_ERR_OR_ZERO(st->offload); 1053 1053 + /* Fall back to low speed usage when no SPI offload is available. */ 1054 1054 + if (ret == -ENODEV) { 1055 1055 + /* 1056 1056 + * One hardware channel is split in two software channels when 1057 1057 + * using common byte mode. Add one more channel for the timestamp. 1058 1058 + */ 1059 1059 + indio_dev->num_channels = 2 * st->chip->num_voltage_inputs + 1; 1060 1060 + indio_dev->channels = st->chip->channels; 1061 1061 + 1062 1062 + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1063 1063 + iio_pollfunc_store_time, 1064 1064 + ad4030_trigger_handler, 1065 1065 + &ad4030_buffer_setup_ops); 1066 1066 + if (ret) 1067 1067 + return dev_err_probe(dev, ret, 1068 1068 + "Failed to setup triggered buffer\n"); 1069 1069 + } else if (ret) { 1070 1070 + return dev_err_probe(dev, ret, "failed to get offload\n"); 1071 1071 + } else { 1072 1072 + /* 1073 1073 + * Offloaded SPI transfers can't support software timestamp so 1074 1074 + * no additional timestamp channel is added. 1075 1075 + */ 1076 1076 + indio_dev->num_channels = st->chip->num_voltage_inputs; 1077 1077 + indio_dev->channels = st->chip->offload_channels; 1078 1078 + ret = ad4030_spi_offload_setup(indio_dev, st); 1079 1079 + if (ret) 1080 1080 + return dev_err_probe(dev, ret, 1081 1081 + "Failed to setup SPI offload\n"); 1082 1082 + 1083 1083 + ret = ad4030_pwm_get(st); 1084 1084 + if (ret) 1085 1085 + return dev_err_probe(dev, ret, "Failed to get PWM\n"); 1086 1086 + 1087 1087 + /* 1088 1088 + * Start with a slower sampling rate so there is some room for 1089 1089 + * adjusting the sample averaging and the sampling frequency 1090 1090 + * without hitting the maximum conversion rate. 1091 1091 + */ 1092 1092 + ret = ad4030_update_conversion_rate(st, st->chip->max_sample_rate_hz >> 4, 1093 1093 + st->avg_log2); 1094 1094 + if (ret) 1095 1095 + return dev_err_probe(dev, ret, 1096 1096 + "Failed to set offload samp freq\n"); 1097 1097 + } 1503 1098 1504 1099 return devm_iio_device_register(dev, indio_dev); 1505 1100 } ··· 1571 1098 }, 1572 1099 }; 1573 1100 1101 1101 + static const struct iio_scan_type ad4030_24_offload_scan_types[] = { 1102 1102 + [AD4030_SCAN_TYPE_NORMAL] = { 1103 1103 + .sign = 's', 1104 1104 + .realbits = 24, 1105 1105 + .storagebits = 32, 1106 1106 + .shift = 0, 1107 1107 + .endianness = IIO_CPU, 1108 1108 + }, 1109 1109 + [AD4030_SCAN_TYPE_AVG] = { 1110 1110 + .sign = 's', 1111 1111 + .realbits = 30, 1112 1112 + .storagebits = 32, 1113 1113 + .shift = 2, 1114 1114 + .endianness = IIO_CPU, 1115 1115 + }, 1116 1116 + }; 1117 1117 + 1574 1118 static const struct iio_scan_type ad4030_16_scan_types[] = { 1575 1119 [AD4030_SCAN_TYPE_NORMAL] = { 1576 1120 .sign = 's', 1577 1577 - .storagebits = 32, 1578 1121 .realbits = 16, 1122 1122 + .storagebits = 32, 1579 1123 .shift = 16, 1580 1124 .endianness = IIO_BE, 1581 1125 }, ··· 1605 1115 } 1606 1116 }; 1607 1117 1118 1118 + static const struct iio_scan_type ad4030_16_offload_scan_types[] = { 1119 1119 + [AD4030_SCAN_TYPE_NORMAL] = { 1120 1120 + .sign = 's', 1121 1121 + .realbits = 16, 1122 1122 + .storagebits = 32, 1123 1123 + .shift = 0, 1124 1124 + .endianness = IIO_CPU, 1125 1125 + }, 1126 1126 + [AD4030_SCAN_TYPE_AVG] = { 1127 1127 + .sign = 's', 1128 1128 + .realbits = 30, 1129 1129 + .storagebits = 32, 1130 1130 + .shift = 2, 1131 1131 + .endianness = IIO_CPU, 1132 1132 + }, 1133 1133 + }; 1134 1134 + 1608 1135 static const struct ad4030_chip_info ad4030_24_chip_info = { 1609 1136 .name = "ad4030-24", 1610 1137 .available_masks = ad4030_channel_masks, ··· 1630 1123 AD4030_CHAN_CMO(1, 0), 1631 1124 IIO_CHAN_SOFT_TIMESTAMP(2), 1632 1125 }, 1126 1126 + .offload_channels = { 1127 1127 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1128 1128 + }, 1633 1129 .grade = AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, 1634 1130 .precision_bits = 24, 1635 1131 .num_voltage_inputs = 1, 1636 1132 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1133 1133 + .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1637 1134 }; 1638 1135 1639 1136 static const struct ad4030_chip_info ad4630_16_chip_info = { ··· 1650 1139 AD4030_CHAN_CMO(3, 1), 1651 1140 IIO_CHAN_SOFT_TIMESTAMP(4), 1652 1141 }, 1142 1142 + .offload_channels = { 1143 1143 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), 1144 1144 + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), 1145 1145 + }, 1653 1146 .grade = AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, 1654 1147 .precision_bits = 16, 1655 1148 .num_voltage_inputs = 2, 1656 1149 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1150 1150 + .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1657 1151 }; 1658 1152 1659 1153 static const struct ad4030_chip_info ad4630_24_chip_info = { ··· 1671 1155 AD4030_CHAN_CMO(3, 1), 1672 1156 IIO_CHAN_SOFT_TIMESTAMP(4), 1673 1157 }, 1158 1158 + .offload_channels = { 1159 1159 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1160 1160 + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), 1161 1161 + }, 1674 1162 .grade = AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, 1675 1163 .precision_bits = 24, 1676 1164 .num_voltage_inputs = 2, 1677 1165 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1166 1166 + .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1678 1167 }; 1679 1168 1680 1169 static const struct ad4030_chip_info ad4632_16_chip_info = { ··· 1692 1171 AD4030_CHAN_CMO(3, 1), 1693 1172 IIO_CHAN_SOFT_TIMESTAMP(4), 1694 1173 }, 1174 1174 + .offload_channels = { 1175 1175 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), 1176 1176 + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), 1177 1177 + }, 1695 1178 .grade = AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, 1696 1179 .precision_bits = 16, 1697 1180 .num_voltage_inputs = 2, 1698 1181 .tcyc_ns = AD4632_TCYC_ADJUSTED_NS, 1182 1182 + .max_sample_rate_hz = 500 * HZ_PER_KHZ, 1699 1183 }; 1700 1184 1701 1185 static const struct ad4030_chip_info ad4632_24_chip_info = { ··· 1713 1187 AD4030_CHAN_CMO(3, 1), 1714 1188 IIO_CHAN_SOFT_TIMESTAMP(4), 1715 1189 }, 1190 1190 + .offload_channels = { 1191 1191 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1192 1192 + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), 1193 1193 + }, 1716 1194 .grade = AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, 1717 1195 .precision_bits = 24, 1718 1196 .num_voltage_inputs = 2, 1719 1197 .tcyc_ns = AD4632_TCYC_ADJUSTED_NS, 1198 1198 + .max_sample_rate_hz = 500 * HZ_PER_KHZ, 1199 1199 + }; 1200 1200 + 1201 1201 + static const struct ad4030_chip_info adaq4216_chip_info = { 1202 1202 + .name = "adaq4216", 1203 1203 + .available_masks = ad4030_channel_masks, 1204 1204 + .channels = { 1205 1205 + ADAQ4216_CHAN_DIFF(0, ad4030_16_scan_types), 1206 1206 + AD4030_CHAN_CMO(1, 0), 1207 1207 + IIO_CHAN_SOFT_TIMESTAMP(2), 1208 1208 + }, 1209 1209 + .offload_channels = { 1210 1210 + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), 1211 1211 + }, 1212 1212 + .grade = AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE, 1213 1213 + .precision_bits = 16, 1214 1214 + .has_pga = true, 1215 1215 + .num_voltage_inputs = 1, 1216 1216 + .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1217 1217 + .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1218 1218 + }; 1219 1219 + 1220 1220 + static const struct ad4030_chip_info adaq4224_chip_info = { 1221 1221 + .name = "adaq4224", 1222 1222 + .available_masks = ad4030_channel_masks, 1223 1223 + .channels = { 1224 1224 + ADAQ4216_CHAN_DIFF(0, ad4030_24_scan_types), 1225 1225 + AD4030_CHAN_CMO(1, 0), 1226 1226 + IIO_CHAN_SOFT_TIMESTAMP(2), 1227 1227 + }, 1228 1228 + .offload_channels = { 1229 1229 + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1230 1230 + }, 1231 1231 + .grade = AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE, 1232 1232 + .precision_bits = 24, 1233 1233 + .has_pga = true, 1234 1234 + .num_voltage_inputs = 1, 1235 1235 + .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1236 1236 + .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1720 1237 }; 1721 1238 1722 1239 static const struct spi_device_id ad4030_id_table[] = { ··· 1768 1199 { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info }, 1769 1200 { "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info }, 1770 1201 { "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info }, 1202 1202 + { "adaq4216", (kernel_ulong_t)&adaq4216_chip_info }, 1203 1203 + { "adaq4224", (kernel_ulong_t)&adaq4224_chip_info }, 1771 1204 { } 1772 1205 }; 1773 1206 MODULE_DEVICE_TABLE(spi, ad4030_id_table); ··· 1780 1209 { .compatible = "adi,ad4630-24", .data = &ad4630_24_chip_info }, 1781 1210 { .compatible = "adi,ad4632-16", .data = &ad4632_16_chip_info }, 1782 1211 { .compatible = "adi,ad4632-24", .data = &ad4632_24_chip_info }, 1212 1212 + { .compatible = "adi,adaq4216", .data = &adaq4216_chip_info }, 1213 1213 + { .compatible = "adi,adaq4224", .data = &adaq4224_chip_info }, 1783 1214 { } 1784 1215 }; 1785 1216 MODULE_DEVICE_TABLE(of, ad4030_of_match); ··· 1799 1226 MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>"); 1800 1227 MODULE_DESCRIPTION("Analog Devices AD4630 ADC family driver"); 1801 1228 MODULE_LICENSE("GPL"); 1229 1229 + MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");

+10 -2

drivers/iio/adc/ad4062.c

reviewed

··· 1199 1199 * The AD4062 in burst averaging mode increases realbits from 16-bits to 1200 1200 * 20-bits, increasing the storagebits from 16-bits to 32-bits. 1201 1201 */ 1202 1202 - static inline size_t ad4062_sizeof_storagebits(struct ad4062_state *st) 1202 1202 + static inline int ad4062_sizeof_storagebits(struct ad4062_state *st) 1203 1203 { 1204 1204 const struct iio_scan_type *scan_type = 1205 1205 iio_get_current_scan_type(st->indio_dev, st->chip->channels); 1206 1206 + 1207 1207 + if (IS_ERR(scan_type)) 1208 1208 + return PTR_ERR(scan_type); 1206 1209 1207 1210 return BITS_TO_BYTES(scan_type->storagebits); 1208 1211 } ··· 1236 1233 if (ret) 1237 1234 return ret; 1238 1235 1239 1239 - st->conv_sizeof = ad4062_sizeof_storagebits(st); 1236 1236 + ret = ad4062_sizeof_storagebits(st); 1237 1237 + if (ret < 0) 1238 1238 + return ret; 1239 1239 + 1240 1240 + st->conv_sizeof = ret; 1241 1241 + 1240 1242 st->conv_addr = ad4062_get_conv_addr(st, st->conv_sizeof); 1241 1243 /* CONV_READ requires read to trigger first sample. */ 1242 1244 struct i3c_xfer xfer_sample[2] = {

+45 -1

drivers/iio/adc/ad4080.c

reviewed

··· 127 127 #define AD4080_SPI_READ BIT(7) 128 128 #define AD4080_CHIP_ID 0x0050 129 129 #define AD4081_CHIP_ID 0x0051 130 130 + #define AD4082_CHIP_ID 0x0052 130 131 #define AD4083_CHIP_ID 0x0053 131 132 #define AD4084_CHIP_ID 0x0054 133 133 + #define AD4085_CHIP_ID 0x0055 132 134 #define AD4086_CHIP_ID 0x0056 133 135 #define AD4087_CHIP_ID 0x0057 136 136 + #define AD4088_CHIP_ID 0x0058 134 137 135 138 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 136 139 ··· 188 185 */ 189 186 struct mutex lock; 190 187 unsigned int num_lanes; 191 191 - unsigned int dec_rate; 192 188 unsigned long clk_rate; 193 189 enum ad4080_filter_type filter_type; 194 190 bool lvds_cnv_en; ··· 444 442 445 443 static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20, 32); 446 444 445 445 + static const struct iio_chan_spec ad4082_channel = AD4080_CHANNEL_DEFINE(20, 32); 446 446 + 447 447 static const struct iio_chan_spec ad4083_channel = AD4080_CHANNEL_DEFINE(16, 16); 448 448 449 449 static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16); 450 450 451 451 + static const struct iio_chan_spec ad4085_channel = AD4080_CHANNEL_DEFINE(16, 16); 452 452 + 451 453 static const struct iio_chan_spec ad4086_channel = AD4080_CHANNEL_DEFINE(14, 16); 452 454 453 455 static const struct iio_chan_spec ad4087_channel = AD4080_CHANNEL_DEFINE(14, 16); 456 456 + 457 457 + static const struct iio_chan_spec ad4088_channel = AD4080_CHANNEL_DEFINE(14, 16); 454 458 455 459 static const struct ad4080_chip_info ad4080_chip_info = { 456 460 .name = "ad4080", ··· 476 468 .num_channels = 1, 477 469 .channels = &ad4081_channel, 478 470 .lvds_cnv_clk_cnt_max = 2, 471 471 + }; 472 472 + 473 473 + static const struct ad4080_chip_info ad4082_chip_info = { 474 474 + .name = "ad4082", 475 475 + .product_id = AD4082_CHIP_ID, 476 476 + .scale_table = ad4080_scale_table, 477 477 + .num_scales = ARRAY_SIZE(ad4080_scale_table), 478 478 + .num_channels = 1, 479 479 + .channels = &ad4082_channel, 480 480 + .lvds_cnv_clk_cnt_max = 8, 479 481 }; 480 482 481 483 static const struct ad4080_chip_info ad4083_chip_info = { ··· 508 490 .lvds_cnv_clk_cnt_max = 2, 509 491 }; 510 492 493 493 + static const struct ad4080_chip_info ad4085_chip_info = { 494 494 + .name = "ad4085", 495 495 + .product_id = AD4085_CHIP_ID, 496 496 + .scale_table = ad4080_scale_table, 497 497 + .num_scales = ARRAY_SIZE(ad4080_scale_table), 498 498 + .num_channels = 1, 499 499 + .channels = &ad4085_channel, 500 500 + .lvds_cnv_clk_cnt_max = 8, 501 501 + }; 502 502 + 511 503 static const struct ad4080_chip_info ad4086_chip_info = { 512 504 .name = "ad4086", 513 505 .product_id = AD4086_CHIP_ID, ··· 536 508 .num_channels = 1, 537 509 .channels = &ad4087_channel, 538 510 .lvds_cnv_clk_cnt_max = 1, 511 511 + }; 512 512 + 513 513 + static const struct ad4080_chip_info ad4088_chip_info = { 514 514 + .name = "ad4088", 515 515 + .product_id = AD4088_CHIP_ID, 516 516 + .scale_table = ad4080_scale_table, 517 517 + .num_scales = ARRAY_SIZE(ad4080_scale_table), 518 518 + .num_channels = 1, 519 519 + .channels = &ad4088_channel, 520 520 + .lvds_cnv_clk_cnt_max = 8, 539 521 }; 540 522 541 523 static int ad4080_setup(struct iio_dev *indio_dev) ··· 704 666 static const struct spi_device_id ad4080_id[] = { 705 667 { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, 706 668 { "ad4081", (kernel_ulong_t)&ad4081_chip_info }, 669 669 + { "ad4082", (kernel_ulong_t)&ad4082_chip_info }, 707 670 { "ad4083", (kernel_ulong_t)&ad4083_chip_info }, 708 671 { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, 672 672 + { "ad4085", (kernel_ulong_t)&ad4085_chip_info }, 709 673 { "ad4086", (kernel_ulong_t)&ad4086_chip_info }, 710 674 { "ad4087", (kernel_ulong_t)&ad4087_chip_info }, 675 675 + { "ad4088", (kernel_ulong_t)&ad4088_chip_info }, 711 676 { } 712 677 }; 713 678 MODULE_DEVICE_TABLE(spi, ad4080_id); ··· 718 677 static const struct of_device_id ad4080_of_match[] = { 719 678 { .compatible = "adi,ad4080", &ad4080_chip_info }, 720 679 { .compatible = "adi,ad4081", &ad4081_chip_info }, 680 680 + { .compatible = "adi,ad4082", &ad4082_chip_info }, 721 681 { .compatible = "adi,ad4083", &ad4083_chip_info }, 722 682 { .compatible = "adi,ad4084", &ad4084_chip_info }, 683 683 + { .compatible = "adi,ad4085", &ad4085_chip_info }, 723 684 { .compatible = "adi,ad4086", &ad4086_chip_info }, 724 685 { .compatible = "adi,ad4087", &ad4087_chip_info }, 686 686 + { .compatible = "adi,ad4088", &ad4088_chip_info }, 725 687 { } 726 688 }; 727 689 MODULE_DEVICE_TABLE(of, ad4080_of_match);

+3 -3

drivers/iio/adc/ad4170-4.c

reviewed

··· 275 275 }; 276 276 277 277 enum ad4170_ref_buf { 278 278 - AD4170_REF_BUF_PRE, /* Pre-charge referrence buffer */ 279 279 - AD4170_REF_BUF_FULL, /* Full referrence buffering */ 280 280 - AD4170_REF_BUF_BYPASS, /* Bypass referrence buffering */ 278 278 + AD4170_REF_BUF_PRE, /* Pre-charge reference buffer */ 279 279 + AD4170_REF_BUF_FULL, /* Full reference buffering */ 280 280 + AD4170_REF_BUF_BYPASS, /* Bypass reference buffering */ 281 281 }; 282 282 283 283 /* maps adi,positive/negative-reference-buffer property values to enum */

+2 -1

drivers/iio/adc/ad7173.c

reviewed

··· 1763 1763 static unsigned int ad7173_calc_openwire_thrsh_raw(struct ad7173_state *st, 1764 1764 struct iio_chan_spec *chan, 1765 1765 struct ad7173_channel *chan_st_priv, 1766 1766 - unsigned int thrsh_mv) { 1766 1766 + unsigned int thrsh_mv) 1767 1767 + { 1767 1768 unsigned int thrsh_raw; 1768 1769 1769 1770 thrsh_raw =

-3

drivers/iio/adc/ad7192.c

reviewed

··· 1402 1402 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI; 1403 1403 1404 1404 st->chip_info = spi_get_device_match_data(spi); 1405 1405 - if (!st->chip_info) 1406 1406 - return -ENODEV; 1407 1407 - 1408 1405 indio_dev->name = st->chip_info->name; 1409 1406 indio_dev->modes = INDIO_DIRECT_MODE; 1410 1407 indio_dev->info = st->chip_info->info;

+2 -4

drivers/iio/adc/ad7266.c

reviewed

··· 409 409 st->gpios[i] = devm_gpiod_get(&spi->dev, 410 410 ad7266_gpio_labels[i], 411 411 GPIOD_OUT_LOW); 412 412 - if (IS_ERR(st->gpios[i])) { 413 413 - ret = PTR_ERR(st->gpios[i]); 414 414 - return ret; 415 415 - } 412 412 + if (IS_ERR(st->gpios[i])) 413 413 + return PTR_ERR(st->gpios[i]); 416 414 } 417 415 } 418 416 } else {

+39 -14

drivers/iio/adc/ad7380.c

reviewed

··· 77 77 #define AD7380_CONFIG1_REFSEL BIT(1) 78 78 #define AD7380_CONFIG1_PMODE BIT(0) 79 79 80 80 - #define AD7380_CONFIG2_SDO2 GENMASK(9, 8) 81 81 - #define AD7380_CONFIG2_SDO BIT(8) 80 80 + #define AD7380_CONFIG2_SDO GENMASK(9, 8) 82 81 #define AD7380_CONFIG2_RESET GENMASK(7, 0) 83 82 84 83 #define AD7380_CONFIG2_RESET_SOFT 0x3C ··· 91 92 #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ 92 93 #define T_POWERUP_US 5000 /* Power up */ 93 94 94 94 - /* 95 95 - * AD738x support several SDO lines to increase throughput, but driver currently 96 96 - * supports only 1 SDO line (standard SPI transaction) 97 97 - */ 98 98 - #define AD7380_NUM_SDO_LINES 1 99 95 #define AD7380_DEFAULT_GAIN_MILLI 1000 100 96 101 97 /* ··· 882 888 bool resolution_boost_enabled; 883 889 unsigned int ch; 884 890 bool seq; 891 891 + /* How many SDO lines are wired up. */ 892 892 + u8 num_sdo_lines; 885 893 unsigned int vref_mv; 886 894 unsigned int vcm_mv[MAX_NUM_CHANNELS]; 887 895 unsigned int gain_milli[MAX_NUM_CHANNELS]; ··· 1080 1084 if (oversampling_ratio > 1) 1081 1085 xfer.delay.value = T_CONVERT_0_NS + 1082 1086 T_CONVERT_X_NS * (oversampling_ratio - 1) * 1083 1083 - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; 1087 1087 + st->chip_info->num_simult_channels / st->num_sdo_lines; 1084 1088 1085 1089 return spi_sync_transfer(st->spi, &xfer, 1); 1086 1090 } ··· 1109 1113 if (oversampling_ratio > 1) 1110 1114 t_convert = T_CONVERT_0_NS + T_CONVERT_X_NS * 1111 1115 (oversampling_ratio - 1) * 1112 1112 - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; 1116 1116 + st->chip_info->num_simult_channels / st->num_sdo_lines; 1113 1117 1114 1118 if (st->seq) { 1115 1119 xfer[0].delay.value = xfer[1].delay.value = t_convert; ··· 1194 1198 xfer->bits_per_word = scan_type->realbits; 1195 1199 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1196 1200 xfer->len = AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_channels; 1201 1201 + if (st->num_sdo_lines > 1) 1202 1202 + xfer->multi_lane_mode = SPI_MULTI_LANE_MODE_STRIPE; 1197 1203 1198 1204 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); 1199 1205 st->offload_msg.offload = st->offload; ··· 1791 1793 1792 1794 static int ad7380_init(struct ad7380_state *st, bool external_ref_en) 1793 1795 { 1796 1796 + u32 sdo; 1794 1797 int ret; 1795 1798 1796 1799 /* perform hard reset */ ··· 1814 1815 st->ch = 0; 1815 1816 st->seq = false; 1816 1817 1817 1817 - /* SPI 1-wire mode */ 1818 1818 + /* SDO field has an irregular mapping. */ 1819 1819 + switch (st->num_sdo_lines) { 1820 1820 + case 1: 1821 1821 + sdo = 1; 1822 1822 + break; 1823 1823 + case 2: 1824 1824 + sdo = 0; 1825 1825 + break; 1826 1826 + case 4: 1827 1827 + sdo = 2; 1828 1828 + break; 1829 1829 + default: 1830 1830 + return -EINVAL; 1831 1831 + } 1832 1832 + 1818 1833 return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, 1819 1834 AD7380_CONFIG2_SDO, 1820 1820 - FIELD_PREP(AD7380_CONFIG2_SDO, 1821 1821 - AD7380_NUM_SDO_LINES)); 1835 1835 + FIELD_PREP(AD7380_CONFIG2_SDO, sdo)); 1822 1836 } 1823 1837 1824 1838 static int ad7380_probe_spi_offload(struct iio_dev *indio_dev, ··· 1854 1842 "failed to get offload trigger\n"); 1855 1843 1856 1844 sample_rate = st->chip_info->max_conversion_rate_hz * 1857 1857 - AD7380_NUM_SDO_LINES / st->chip_info->num_simult_channels; 1845 1845 + st->num_sdo_lines / st->chip_info->num_simult_channels; 1858 1846 1859 1847 st->sample_freq_range[0] = 1; /* min */ 1860 1848 st->sample_freq_range[1] = 1; /* step */ ··· 1862 1850 1863 1851 /* 1864 1852 * Starting with a quite low frequency, to allow oversampling x32, 1865 1865 - * user is then reponsible to adjust the frequency for the specific case. 1853 1853 + * user is then responsible to adjust the frequency for the specific case. 1866 1854 */ 1867 1855 ret = ad7380_set_sample_freq(st, sample_rate / 32); 1868 1856 if (ret) ··· 1898 1886 st->chip_info = spi_get_device_match_data(spi); 1899 1887 if (!st->chip_info) 1900 1888 return dev_err_probe(dev, -EINVAL, "missing match data\n"); 1889 1889 + 1890 1890 + st->num_sdo_lines = spi->num_rx_lanes; 1891 1891 + 1892 1892 + if (st->num_sdo_lines < 1 || st->num_sdo_lines > st->chip_info->num_simult_channels) 1893 1893 + return dev_err_probe(dev, -EINVAL, 1894 1894 + "invalid number of SDO lines (%d)\n", 1895 1895 + st->num_sdo_lines); 1901 1896 1902 1897 ret = devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies, 1903 1898 st->chip_info->supplies); ··· 2029 2010 st->normal_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2030 2011 st->normal_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2031 2012 st->normal_xfer[1].rx_buf = st->scan_data; 2013 2013 + if (st->num_sdo_lines > 1) 2014 2014 + st->normal_xfer[1].multi_lane_mode = SPI_MULTI_LANE_MODE_STRIPE; 2032 2015 2033 2016 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, 2034 2017 ARRAY_SIZE(st->normal_xfer)); ··· 2052 2031 st->seq_xfer[2].cs_change = 1; 2053 2032 st->seq_xfer[2].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; 2054 2033 st->seq_xfer[2].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 2034 2034 + if (st->num_sdo_lines > 1) { 2035 2035 + st->seq_xfer[2].multi_lane_mode = SPI_MULTI_LANE_MODE_STRIPE; 2036 2036 + st->seq_xfer[3].multi_lane_mode = SPI_MULTI_LANE_MODE_STRIPE; 2037 2037 + } 2055 2038 2056 2039 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, 2057 2040 ARRAY_SIZE(st->seq_xfer));

+204 -17

drivers/iio/adc/ad7768-1.c

reviewed

··· 25 25 #include <linux/regulator/consumer.h> 26 26 #include <linux/regulator/driver.h> 27 27 #include <linux/sysfs.h> 28 28 + #include <linux/spi/offload/consumer.h> 29 29 + #include <linux/spi/offload/provider.h> 28 30 #include <linux/spi/spi.h> 29 31 #include <linux/unaligned.h> 30 32 #include <linux/units.h> 31 33 #include <linux/util_macros.h> 32 34 33 35 #include <linux/iio/buffer.h> 36 36 + #include <linux/iio/buffer-dmaengine.h> 34 37 #include <linux/iio/iio.h> 35 38 #include <linux/iio/sysfs.h> 36 39 #include <linux/iio/trigger.h> ··· 164 161 enum ad7768_scan_type { 165 162 AD7768_SCAN_TYPE_NORMAL, 166 163 AD7768_SCAN_TYPE_HIGH_SPEED, 164 164 + AD7768_SCAN_TYPE_OFFLOAD_NORMAL, 165 165 + AD7768_SCAN_TYPE_OFFLOAD_HIGH_SPEED, 167 166 }; 168 167 169 168 enum { ··· 271 266 .storagebits = 16, 272 267 .endianness = IIO_BE, 273 268 }, 269 269 + [AD7768_SCAN_TYPE_OFFLOAD_NORMAL] = { 270 270 + .sign = 's', 271 271 + .realbits = 24, 272 272 + .storagebits = 32, 273 273 + .endianness = IIO_CPU, 274 274 + }, 275 275 + [AD7768_SCAN_TYPE_OFFLOAD_HIGH_SPEED] = { 276 276 + .sign = 's', 277 277 + .realbits = 16, 278 278 + .storagebits = 32, 279 279 + .endianness = IIO_CPU, 280 280 + }, 274 281 }; 275 282 276 283 struct ad7768_chip_info { ··· 300 283 301 284 struct ad7768_state { 302 285 struct spi_device *spi; 286 286 + struct spi_offload *offload; 287 287 + struct spi_offload_trigger *offload_trigger; 303 288 struct regmap *regmap; 304 289 struct regmap *regmap24; 305 290 int vref_uv; ··· 309 290 unsigned int vcm_output_sel; 310 291 struct clk *mclk; 311 292 unsigned int mclk_freq; 312 312 - unsigned int mclk_div; 313 293 unsigned int oversampling_ratio; 314 294 enum ad7768_filter_type filter_type; 315 295 unsigned int samp_freq; ··· 324 306 struct gpio_desc *gpio_reset; 325 307 const char *labels[AD7768_MAX_CHANNELS]; 326 308 struct gpio_chip gpiochip; 309 309 + struct spi_transfer offload_xfer; 310 310 + struct spi_message offload_msg; 327 311 const struct ad7768_chip_info *chip; 328 312 bool en_spi_sync; 329 313 struct mutex pga_lock; /* protect device internal state (PGA) */ ··· 484 464 int readval, ret; 485 465 486 466 reinit_completion(&st->completion); 487 487 - 488 488 - ret = ad7768_set_mode(st, AD7768_ONE_SHOT); 489 489 - if (ret < 0) 490 490 - return ret; 467 467 + enable_irq(st->spi->irq); 491 468 492 469 ret = wait_for_completion_timeout(&st->completion, 493 470 msecs_to_jiffies(1000)); 471 471 + disable_irq(st->spi->irq); 494 472 if (!ret) 495 473 return -ETIMEDOUT; 496 474 ··· 504 486 */ 505 487 if (st->oversampling_ratio == 8) 506 488 readval >>= 8; 507 507 - 508 508 - /* 509 509 - * Any SPI configuration of the AD7768-1 can only be 510 510 - * performed in continuous conversion mode. 511 511 - */ 512 512 - ret = ad7768_set_mode(st, AD7768_CONTINUOUS); 513 513 - if (ret < 0) 514 514 - return ret; 515 489 516 490 return readval; 517 491 } ··· 1148 1138 { 1149 1139 struct ad7768_state *st = iio_priv(indio_dev); 1150 1140 1141 1141 + if (st->offload) 1142 1142 + return st->oversampling_ratio == 8 ? 1143 1143 + AD7768_SCAN_TYPE_OFFLOAD_HIGH_SPEED : AD7768_SCAN_TYPE_OFFLOAD_NORMAL; 1144 1144 + 1151 1145 return st->oversampling_ratio == 8 ? 1152 1146 AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL; 1153 1147 } ··· 1266 1252 return ret; 1267 1253 } 1268 1254 1255 1255 + ret = ad7768_set_mode(st, AD7768_CONTINUOUS); 1256 1256 + if (ret) 1257 1257 + return ret; 1258 1258 + 1269 1259 /* For backwards compatibility, try the adi,sync-in-gpios property */ 1270 1260 st->gpio_sync_in = devm_gpiod_get_optional(&st->spi->dev, "adi,sync-in", 1271 1261 GPIOD_OUT_LOW); ··· 1374 1356 .predisable = &ad7768_buffer_predisable, 1375 1357 }; 1376 1358 1359 1359 + static int ad7768_offload_buffer_postenable(struct iio_dev *indio_dev) 1360 1360 + { 1361 1361 + struct ad7768_state *st = iio_priv(indio_dev); 1362 1362 + struct spi_offload_trigger_config config = { 1363 1363 + .type = SPI_OFFLOAD_TRIGGER_DATA_READY, 1364 1364 + }; 1365 1365 + const struct iio_scan_type *scan_type; 1366 1366 + unsigned int unused; 1367 1367 + int ret; 1368 1368 + 1369 1369 + scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); 1370 1370 + if (IS_ERR(scan_type)) 1371 1371 + return PTR_ERR(scan_type); 1372 1372 + 1373 1373 + st->offload_xfer.len = spi_bpw_to_bytes(scan_type->realbits); 1374 1374 + st->offload_xfer.bits_per_word = scan_type->realbits; 1375 1375 + st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1376 1376 + 1377 1377 + spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); 1378 1378 + st->offload_msg.offload = st->offload; 1379 1379 + 1380 1380 + ret = spi_optimize_message(st->spi, &st->offload_msg); 1381 1381 + if (ret) { 1382 1382 + dev_err(&st->spi->dev, "failed to prepare offload, err: %d\n", ret); 1383 1383 + return ret; 1384 1384 + } 1385 1385 + 1386 1386 + /* 1387 1387 + * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter 1388 1388 + * continuous read mode. Subsequent data reads do not require an 1389 1389 + * initial 8-bit write to query the ADC_DATA register. 1390 1390 + */ 1391 1391 + ret = regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01); 1392 1392 + if (ret) 1393 1393 + goto err_unoptimize_message; 1394 1394 + 1395 1395 + ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, 1396 1396 + &config); 1397 1397 + if (ret) 1398 1398 + goto err_exit_continuous_read_mode; 1399 1399 + 1400 1400 + return 0; 1401 1401 + 1402 1402 + err_exit_continuous_read_mode: 1403 1403 + regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused); 1404 1404 + 1405 1405 + err_unoptimize_message: 1406 1406 + spi_unoptimize_message(&st->offload_msg); 1407 1407 + 1408 1408 + return ret; 1409 1409 + } 1410 1410 + 1411 1411 + static int ad7768_offload_buffer_predisable(struct iio_dev *indio_dev) 1412 1412 + { 1413 1413 + struct ad7768_state *st = iio_priv(indio_dev); 1414 1414 + unsigned int unused; 1415 1415 + 1416 1416 + spi_offload_trigger_disable(st->offload, st->offload_trigger); 1417 1417 + spi_unoptimize_message(&st->offload_msg); 1418 1418 + 1419 1419 + /* 1420 1420 + * To exit continuous read mode, perform a single read of the ADC_DATA 1421 1421 + * reg (0x2C), which allows further configuration of the device. 1422 1422 + */ 1423 1423 + return regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused); 1424 1424 + } 1425 1425 + 1426 1426 + static const struct iio_buffer_setup_ops ad7768_offload_buffer_ops = { 1427 1427 + .postenable = ad7768_offload_buffer_postenable, 1428 1428 + .predisable = ad7768_offload_buffer_predisable, 1429 1429 + }; 1430 1430 + 1431 1431 + static int ad7768_set_trigger_state(struct iio_trigger *trig, bool enable) 1432 1432 + { 1433 1433 + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1434 1434 + struct ad7768_state *st = iio_priv(indio_dev); 1435 1435 + 1436 1436 + if (enable) 1437 1437 + enable_irq(st->spi->irq); 1438 1438 + else 1439 1439 + disable_irq(st->spi->irq); 1440 1440 + 1441 1441 + return 0; 1442 1442 + } 1443 1443 + 1377 1444 static const struct iio_trigger_ops ad7768_trigger_ops = { 1378 1445 .validate_device = iio_trigger_validate_own_device, 1446 1446 + .set_trigger_state = ad7768_set_trigger_state, 1379 1447 }; 1380 1448 1381 1449 static int ad7768_set_channel_label(struct iio_dev *indio_dev, ··· 1694 1590 return 0; 1695 1591 } 1696 1592 1593 1593 + static bool ad7768_offload_trigger_match(struct spi_offload_trigger *trigger, 1594 1594 + enum spi_offload_trigger_type type, 1595 1595 + u64 *args, u32 nargs) 1596 1596 + { 1597 1597 + if (type != SPI_OFFLOAD_TRIGGER_DATA_READY) 1598 1598 + return false; 1599 1599 + 1600 1600 + /* Up to 2 args are allowed, but only 1 is used */ 1601 1601 + if (nargs == 0 || nargs > 2 || args[0] != AD7768_TRIGGER_SOURCE_DRDY) 1602 1602 + return false; 1603 1603 + 1604 1604 + return true; 1605 1605 + } 1606 1606 + 1607 1607 + static int ad7768_offload_trigger_request(struct spi_offload_trigger *trigger, 1608 1608 + enum spi_offload_trigger_type type, 1609 1609 + u64 *args, u32 nargs) 1610 1610 + { 1611 1611 + /* Should already be validated by match, but just in case */ 1612 1612 + if (nargs == 0 || nargs > 2) 1613 1613 + return -EINVAL; 1614 1614 + 1615 1615 + return 0; 1616 1616 + } 1617 1617 + 1618 1618 + static const struct spi_offload_trigger_ops ad7768_offload_trigger_ops = { 1619 1619 + .match = ad7768_offload_trigger_match, 1620 1620 + .request = ad7768_offload_trigger_request, 1621 1621 + }; 1622 1622 + 1697 1623 static const struct ad7768_chip_info ad7768_chip_info = { 1698 1624 .name = "ad7768-1", 1699 1625 .channel_spec = ad7768_channels, ··· 1761 1627 .has_variable_aaf = true, 1762 1628 }; 1763 1629 1630 1630 + static const struct spi_offload_config ad7768_spi_offload_config = { 1631 1631 + .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | SPI_OFFLOAD_CAP_RX_STREAM_DMA, 1632 1632 + }; 1633 1633 + 1634 1634 + static int ad7768_spi_offload_probe(struct iio_dev *indio_dev, 1635 1635 + struct ad7768_state *st) 1636 1636 + { 1637 1637 + struct device *dev = &st->spi->dev; 1638 1638 + struct spi_offload_trigger_info trigger_info = { 1639 1639 + .fwnode = dev_fwnode(dev), 1640 1640 + .ops = &ad7768_offload_trigger_ops, 1641 1641 + .priv = st, 1642 1642 + }; 1643 1643 + struct dma_chan *rx_dma; 1644 1644 + int ret; 1645 1645 + 1646 1646 + ret = devm_spi_offload_trigger_register(dev, &trigger_info); 1647 1647 + if (ret) 1648 1648 + return dev_err_probe(dev, ret, "failed to register offload trigger\n"); 1649 1649 + 1650 1650 + st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 1651 1651 + SPI_OFFLOAD_TRIGGER_DATA_READY); 1652 1652 + if (IS_ERR(st->offload_trigger)) 1653 1653 + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1654 1654 + "failed to get offload trigger\n"); 1655 1655 + 1656 1656 + rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 1657 1657 + if (IS_ERR(rx_dma)) 1658 1658 + return dev_err_probe(dev, PTR_ERR(rx_dma), "failed to get offload RX DMA\n"); 1659 1659 + 1660 1660 + ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, 1661 1661 + IIO_BUFFER_DIRECTION_IN); 1662 1662 + if (ret) 1663 1663 + return dev_err_probe(dev, ret, "failed to setup offload RX DMA\n"); 1664 1664 + 1665 1665 + indio_dev->setup_ops = &ad7768_offload_buffer_ops; 1666 1666 + 1667 1667 + return 0; 1668 1668 + } 1669 1669 + 1764 1670 static int ad7768_probe(struct spi_device *spi) 1765 1671 { 1766 1672 struct ad7768_state *st; 1767 1673 struct iio_dev *indio_dev; 1674 1674 + struct device *dev = &spi->dev; 1768 1675 int ret; 1769 1676 1770 1677 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); ··· 1896 1721 return ret; 1897 1722 1898 1723 ret = devm_request_irq(&spi->dev, spi->irq, &ad7768_interrupt, 1899 1899 - IRQF_TRIGGER_RISING | IRQF_NO_THREAD, 1724 1724 + IRQF_TRIGGER_RISING | IRQF_NO_THREAD | IRQF_NO_AUTOEN, 1900 1725 indio_dev->name, indio_dev); 1901 1726 if (ret) 1902 1727 return ret; 1903 1728 1904 1904 - ret = ad7768_triggered_buffer_alloc(indio_dev); 1905 1905 - if (ret) 1906 1906 - return ret; 1729 1729 + st->offload = devm_spi_offload_get(dev, spi, &ad7768_spi_offload_config); 1730 1730 + ret = PTR_ERR_OR_ZERO(st->offload); 1731 1731 + if (ret == -ENODEV) { 1732 1732 + /* If not using SPI offload, fall back to low speed usage */ 1733 1733 + ret = ad7768_triggered_buffer_alloc(indio_dev); 1734 1734 + if (ret) 1735 1735 + return ret; 1736 1736 + } else if (ret) { 1737 1737 + return dev_err_probe(dev, ret, "failed to get SPI offload\n"); 1738 1738 + } else { 1739 1739 + ret = ad7768_spi_offload_probe(indio_dev, st); 1740 1740 + if (ret) 1741 1741 + return ret; 1742 1742 + } 1907 1743 1908 1744 return devm_iio_device_register(&spi->dev, indio_dev); 1909 1745 } ··· 1950 1764 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1951 1765 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); 1952 1766 MODULE_LICENSE("GPL v2"); 1767 1767 + MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");

+1 -2

drivers/iio/adc/ad7793.c

reviewed

··· 152 152 153 153 struct ad7793_state { 154 154 const struct ad7793_chip_info *chip_info; 155 155 - u16 int_vref_mv; 156 155 u16 mode; 157 156 u16 conf; 158 157 u32 scale_avail[8][2]; ··· 804 805 805 806 vref_mv = ret / 1000; 806 807 } else { 807 807 - vref_mv = 1170; /* Build-in ref */ 808 808 + vref_mv = 1170; /* Built-in ref */ 808 809 } 809 810 810 811 st->chip_info =

+1 -1

drivers/iio/adc/ad7887.c

reviewed

··· 104 104 { 105 105 struct ad7887_state *st = iio_priv(indio_dev); 106 106 107 107 - /* dummy read: restore default CH0 settin */ 107 107 + /* dummy read: restore default CH0 settings */ 108 108 return spi_sync(st->spi, &st->msg[AD7887_CH0]); 109 109 } 110 110

+2 -2

drivers/iio/adc/ad7923.c

reviewed

··· 30 30 #define AD7923_PM_MODE_AS (1) /* auto shutdown */ 31 31 #define AD7923_PM_MODE_FS (2) /* full shutdown */ 32 32 #define AD7923_PM_MODE_OPS (3) /* normal operation */ 33 33 - #define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */ 33 33 + #define AD7923_SEQUENCE_OFF (0) /* no sequence function */ 34 34 #define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */ 35 35 #define AD7923_SEQUENCE_ON (3) /* continuous sequence */ 36 36 ··· 39 39 #define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */ 40 40 #define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \ 41 41 + (((sequence) & 2) << 9)) 42 42 - /* write sequence fonction */ 42 42 + /* write sequence function */ 43 43 /* left shift for CR : bit 11 transmit in first */ 44 44 #define AD7923_SHIFT_REGISTER 4 45 45

+56 -39

drivers/iio/adc/ad9467.c

reviewed

··· 176 176 struct clk *clk; 177 177 /* used for debugfs */ 178 178 struct ad9467_chan_test_mode *chan_test; 179 179 - unsigned int output_mode; 180 179 unsigned int (*scales)[2]; 181 180 /* 182 181 * Times 2 because we may also invert the signal polarity and run the ··· 924 925 return ret; 925 926 926 927 guard(mutex)(&st->lock); 927 927 - return ad9467_calibrate(st); 928 928 + 929 929 + if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) 930 930 + return ad9467_calibrate(st); 931 931 + 932 932 + return 0; 928 933 } 929 934 930 935 static int ad9467_write_raw(struct iio_dev *indio_dev, ··· 1134 1131 len = scnprintf(buf, sizeof(buf), "Running \"%s\" Test:\n\t", 1135 1132 ad9467_test_modes[chan->mode]); 1136 1133 1137 1137 - ret = iio_backend_debugfs_print_chan_status(st->back, chan->idx, 1138 1138 - buf + len, 1139 1139 - sizeof(buf) - len); 1140 1140 - if (ret < 0) 1141 1141 - return ret; 1142 1142 - len += ret; 1134 1134 + if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) { 1135 1135 + ret = iio_backend_debugfs_print_chan_status(st->back, 1136 1136 + chan->idx, 1137 1137 + buf + len, 1138 1138 + sizeof(buf) - len); 1139 1139 + if (ret < 0) 1140 1140 + return ret; 1141 1141 + len += ret; 1142 1142 + } 1143 1143 } else if (chan->mode == AN877_ADC_TESTMODE_OFF) { 1144 1144 len = scnprintf(buf, sizeof(buf), "No test Running...\n"); 1145 1145 } else { ··· 1181 1175 if (mode == AN877_ADC_TESTMODE_OFF) { 1182 1176 unsigned int out_mode; 1183 1177 1184 1184 - if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ || 1185 1185 - chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1186 1186 - ret = ad9467_backend_testmode_off(st, chan->idx); 1187 1187 - if (ret) 1188 1188 - return ret; 1178 1178 + if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) { 1179 1179 + if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ || 1180 1180 + chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1181 1181 + ret = ad9467_backend_testmode_off(st, chan->idx); 1182 1182 + if (ret) 1183 1183 + return ret; 1184 1184 + } 1189 1185 } 1190 1186 1191 1187 ret = ad9467_testmode_set(st, chan->idx, mode); ··· 1213 1205 return ret; 1214 1206 1215 1207 /* some patterns have a backend matching monitoring block */ 1216 1216 - if (mode == AN877_ADC_TESTMODE_PN9_SEQ) { 1217 1217 - ret = ad9467_backend_testmode_on(st, chan->idx, 1208 1208 + if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) { 1209 1209 + if (mode == AN877_ADC_TESTMODE_PN9_SEQ) { 1210 1210 + ret = ad9467_backend_testmode_on(st, chan->idx, 1218 1211 IIO_BACKEND_ADI_PRBS_9A); 1219 1219 - if (ret) 1220 1220 - return ret; 1221 1221 - } else if (mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1222 1222 - ret = ad9467_backend_testmode_on(st, chan->idx, 1212 1212 + if (ret) 1213 1213 + return ret; 1214 1214 + } else if (mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1215 1215 + ret = ad9467_backend_testmode_on(st, chan->idx, 1223 1216 IIO_BACKEND_ADI_PRBS_23A); 1224 1224 - if (ret) 1225 1225 - return ret; 1217 1217 + if (ret) 1218 1218 + return ret; 1219 1219 + } 1226 1220 } 1227 1221 } 1228 1222 ··· 1290 1280 if (!st->chan_test) 1291 1281 return; 1292 1282 1293 1293 - debugfs_create_file("calibration_table_dump", 0400, d, st, 1294 1294 - &ad9467_calib_table_fops); 1283 1283 + if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) 1284 1284 + debugfs_create_file("calibration_table_dump", 0400, d, st, 1285 1285 + &ad9467_calib_table_fops); 1295 1286 1296 1287 for (chan = 0; chan < st->info->num_channels; chan++) { 1297 1288 snprintf(attr_name, sizeof(attr_name), "in_voltage%u_test_mode", ··· 1311 1300 1312 1301 static int ad9467_probe(struct spi_device *spi) 1313 1302 { 1303 1303 + struct device *dev = &spi->dev; 1314 1304 struct iio_dev *indio_dev; 1315 1305 struct ad9467_state *st; 1316 1306 unsigned int id; 1317 1307 int ret; 1318 1308 1319 1319 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1309 1309 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1320 1310 if (!indio_dev) 1321 1311 return -ENOMEM; 1322 1312 ··· 1332 1320 if (AD9467_CAN_INVERT(st)) 1333 1321 st->calib_map_size *= 2; 1334 1322 1335 1335 - st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk"); 1323 1323 + st->clk = devm_clk_get_enabled(dev, "adc-clk"); 1336 1324 if (IS_ERR(st->clk)) 1337 1325 return PTR_ERR(st->clk); 1338 1326 1339 1339 - st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 1340 1340 - GPIOD_OUT_LOW); 1327 1327 + st->pwrdown_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_LOW); 1341 1328 if (IS_ERR(st->pwrdown_gpio)) 1342 1329 return PTR_ERR(st->pwrdown_gpio); 1343 1330 1344 1344 - ret = ad9467_reset(&spi->dev); 1331 1331 + ret = ad9467_reset(dev); 1345 1332 if (ret) 1346 1333 return ret; 1347 1334 ··· 1350 1339 1351 1340 id = ad9467_spi_read(st, AN877_ADC_REG_CHIP_ID); 1352 1341 if (id != st->info->id) { 1353 1353 - dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 1342 1342 + dev_err(dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 1354 1343 id, st->info->id); 1355 1344 return -ENODEV; 1356 1345 } ··· 1367 1356 if (ret) 1368 1357 return ret; 1369 1358 1370 1370 - ret = devm_iio_backend_request_buffer(&spi->dev, st->back, indio_dev); 1371 1371 - if (ret) 1372 1372 - return ret; 1359 1359 + if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_BUFFER)) { 1360 1360 + ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); 1361 1361 + if (ret) 1362 1362 + return ret; 1363 1363 + } 1373 1364 1374 1374 - ret = devm_iio_backend_enable(&spi->dev, st->back); 1375 1375 - if (ret) 1376 1376 - return ret; 1365 1365 + if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_ENABLE)) { 1366 1366 + ret = devm_iio_backend_enable(dev, st->back); 1367 1367 + if (ret) 1368 1368 + return ret; 1369 1369 + } 1377 1370 1378 1378 - ret = ad9467_calibrate(st); 1379 1379 - if (ret) 1380 1380 - return ret; 1371 1371 + if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) { 1372 1372 + ret = ad9467_calibrate(st); 1373 1373 + if (ret) 1374 1374 + return ret; 1375 1375 + } 1381 1376 1382 1382 - ret = devm_iio_device_register(&spi->dev, indio_dev); 1377 1377 + ret = devm_iio_device_register(dev, indio_dev); 1383 1378 if (ret) 1384 1379 return ret; 1385 1380

+4 -2

drivers/iio/adc/ad_sigma_delta.c

reviewed

··· 51 51 */ 52 52 void ad_sd_set_comm(struct ad_sigma_delta *sigma_delta, u8 comm) 53 53 { 54 54 - /* Some variants use the lower two bits of the communications register 55 55 - * to select the channel */ 54 54 + /* 55 55 + * Some variants use the lower two bits of the communications register 56 56 + * to select the channel. 57 57 + */ 56 58 sigma_delta->comm = comm & AD_SD_COMM_CHAN_MASK; 57 59 } 58 60 EXPORT_SYMBOL_NS_GPL(ad_sd_set_comm, "IIO_AD_SIGMA_DELTA");

+4 -9

drivers/iio/adc/ade9000.c

reviewed

··· 218 218 #define ADE9000_ST1_ERROR1_BIT BIT(29) 219 219 #define ADE9000_ST1_ERROR2_BIT BIT(30) 220 220 #define ADE9000_ST1_ERROR3_BIT BIT(31) 221 221 - #define ADE9000_ST_ERROR \ 222 222 - (ADE9000_ST1_ERROR0 | ADE9000_ST1_ERROR1 | \ 223 223 - ADE9000_ST1_ERROR2 | ADE9000_ST1_ERROR3) 224 221 #define ADE9000_ST1_CROSSING_FIRST 6 225 222 #define ADE9000_ST1_CROSSING_DEPTH 25 226 223 ··· 280 283 #define ADE9000_PHASE_C_POS_BIT BIT(6) 281 284 282 285 #define ADE9000_MAX_PHASE_NR 3 283 283 - #define AD9000_CHANNELS_PER_PHASE 10 284 286 285 287 /* 286 288 * Calculate register address for multi-phase device. ··· 1545 1549 1546 1550 ret = regmap_clear_bits(st->regmap, ADE9000_REG_MASK0, interrupts); 1547 1551 if (ret) { 1548 1548 - dev_err(dev, "Post-disable update maks0 fail\n"); 1552 1552 + dev_err(dev, "Post-disable update mask0 fail\n"); 1549 1553 return ret; 1550 1554 } 1551 1555 ··· 1585 1589 /* Only wait for completion if IRQ1 is available to signal reset done */ 1586 1590 if (fwnode_irq_get_byname(dev_fwnode(dev), "irq1") >= 0) { 1587 1591 if (!wait_for_completion_timeout(&st->reset_completion, 1588 1588 - msecs_to_jiffies(1000))) { 1589 1589 - dev_err(dev, "Reset timeout after 1s\n"); 1590 1590 - return -ETIMEDOUT; 1591 1591 - } 1592 1592 + msecs_to_jiffies(1000))) 1593 1593 + return dev_err_probe(dev, -ETIMEDOUT, 1594 1594 + "Reset timeout after 1s\n"); 1592 1595 } 1593 1596 /* If no IRQ available, reset is already complete after the 50ms delay above */ 1594 1597

+5

drivers/iio/adc/adi-axi-adc.c

reviewed

··· 621 621 static const struct iio_backend_info adi_axi_adc_generic = { 622 622 .name = "axi-adc", 623 623 .ops = &adi_axi_adc_ops, 624 624 + .caps = IIO_BACKEND_CAP_CALIBRATION | IIO_BACKEND_CAP_BUFFER | 625 625 + IIO_BACKEND_CAP_ENABLE, 624 626 }; 625 627 626 628 static const struct iio_backend_ops adi_ad485x_ops = { ··· 647 645 static const struct iio_backend_info axi_ad485x = { 648 646 .name = "axi-ad485x", 649 647 .ops = &adi_ad485x_ops, 648 648 + .caps = IIO_BACKEND_CAP_CALIBRATION | IIO_BACKEND_CAP_BUFFER | 649 649 + IIO_BACKEND_CAP_ENABLE, 650 650 }; 651 651 652 652 static const struct iio_backend_ops adi_ad408x_ops = { ··· 669 665 static const struct iio_backend_info axi_ad408x = { 670 666 .name = "axi-ad408x", 671 667 .ops = &adi_ad408x_ops, 668 668 + .caps = IIO_BACKEND_CAP_BUFFER | IIO_BACKEND_CAP_ENABLE, 672 669 }; 673 670 674 671 static int adi_axi_adc_probe(struct platform_device *pdev)

+59 -13

drivers/iio/adc/aspeed_adc.c

reviewed

··· 75 75 76 76 #define ASPEED_ADC_INIT_POLLING_TIME 500 77 77 #define ASPEED_ADC_INIT_TIMEOUT 500000 78 78 + /* Battery sensing is typically on the last channel */ 79 79 + #define ASPEED_ADC_BATTERY_CHANNEL 7 78 80 /* 79 81 * When the sampling rate is too high, the ADC may not have enough charging 80 82 * time, resulting in a low voltage value. Thus, the default uses a slow ··· 122 120 bool battery_sensing; 123 121 struct adc_gain battery_mode_gain; 124 122 }; 123 123 + 124 124 + /* 125 125 + * Enable multiple consecutive channels starting from channel 0. 126 126 + * This creates a bitmask for channels 0 to (num_channels - 1). 127 127 + * For example: num_channels=3 creates mask 0x0007 (channels 0,1,2) 128 128 + */ 129 129 + static inline u32 aspeed_adc_channels_mask(unsigned int num_channels) 130 130 + { 131 131 + if (num_channels > 16) 132 132 + return GENMASK(15, 0); 133 133 + 134 134 + return BIT(num_channels) - 1; 135 135 + } 136 136 + 137 137 + static inline unsigned int aspeed_adc_get_active_channels(const struct aspeed_adc_data *data) 138 138 + { 139 139 + /* 140 140 + * For controllers with battery sensing capability, the last channel 141 141 + * is reserved for battery sensing and should not be included in 142 142 + * normal channel operations. 143 143 + */ 144 144 + if (data->model_data->bat_sense_sup) 145 145 + return data->model_data->num_channels - 1; 146 146 + return data->model_data->num_channels; 147 147 + } 125 148 126 149 #define ASPEED_CHAN(_idx, _data_reg_addr) { \ 127 150 .type = IIO_VOLTAGE, \ ··· 263 236 ASPEED_ADC_CTRL_CHANNEL_ENABLE(0), 264 237 data->base + ASPEED_REG_ENGINE_CONTROL); 265 238 /* 266 266 - * After enable compensating sensing mode need to wait some time for ADC stable 267 267 - * Experiment result is 1ms. 239 239 + * After enable compensating sensing mode need to wait some time for the 240 240 + * ADC stablize. Experiment result is 1ms. 268 241 */ 269 269 - mdelay(1); 242 242 + fsleep(1000); 270 243 271 244 for (index = 0; index < 16; index++) { 272 245 /* ··· 312 285 313 286 switch (mask) { 314 287 case IIO_CHAN_INFO_RAW: 315 315 - if (data->battery_sensing && chan->channel == 7) { 316 316 - adc_engine_control_reg_val = 317 317 - readl(data->base + ASPEED_REG_ENGINE_CONTROL); 288 288 + adc_engine_control_reg_val = readl(data->base + ASPEED_REG_ENGINE_CONTROL); 289 289 + /* 290 290 + * For battery sensing capable controllers, we need to enable 291 291 + * the specific channel before reading. This is required because 292 292 + * the battery channel may not be enabled by default. 293 293 + */ 294 294 + if (data->model_data->bat_sense_sup && 295 295 + chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { 296 296 + u32 ctrl_reg = adc_engine_control_reg_val & ~ASPEED_ADC_CTRL_CHANNEL; 297 297 + 298 298 + ctrl_reg |= ASPEED_ADC_CTRL_CHANNEL_ENABLE(chan->channel); 299 299 + writel(ctrl_reg, data->base + ASPEED_REG_ENGINE_CONTROL); 300 300 + /* 301 301 + * After enable a new channel need to wait some time for ADC stable 302 302 + * Experiment result is 1ms. 303 303 + */ 304 304 + fsleep(1000); 305 305 + } 306 306 + 307 307 + if (data->battery_sensing && chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { 318 308 writel(adc_engine_control_reg_val | 319 309 FIELD_PREP(ASPEED_ADC_CH7_MODE, 320 310 ASPEED_ADC_CH7_BAT) | 321 311 ASPEED_ADC_BAT_SENSING_ENABLE, 322 312 data->base + ASPEED_REG_ENGINE_CONTROL); 323 313 /* 324 324 - * After enable battery sensing mode need to wait some time for adc stable 314 314 + * After enable battery sensing mode need to wait some time for ADC stable 325 315 * Experiment result is 1ms. 326 316 */ 327 327 - mdelay(1); 317 317 + fsleep(1000); 328 318 *val = readw(data->base + chan->address); 329 319 *val = (*val * data->battery_mode_gain.mult) / 330 320 data->battery_mode_gain.div; 331 331 - /* Restore control register value */ 332 332 - writel(adc_engine_control_reg_val, 333 333 - data->base + ASPEED_REG_ENGINE_CONTROL); 334 321 } else 335 322 *val = readw(data->base + chan->address); 323 323 + /* Restore control register value */ 324 324 + writel(adc_engine_control_reg_val, 325 325 + data->base + ASPEED_REG_ENGINE_CONTROL); 336 326 return IIO_VAL_INT; 337 327 338 328 case IIO_CHAN_INFO_OFFSET: 339 339 - if (data->battery_sensing && chan->channel == 7) 329 329 + if (data->battery_sensing && chan->channel == ASPEED_ADC_BATTERY_CHANNEL) 340 330 *val = (data->cv * data->battery_mode_gain.mult) / 341 331 data->battery_mode_gain.div; 342 332 else ··· 654 610 /* Start all channels in normal mode. */ 655 611 adc_engine_control_reg_val = 656 612 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 657 657 - adc_engine_control_reg_val |= ASPEED_ADC_CTRL_CHANNEL; 613 613 + FIELD_MODIFY(ASPEED_ADC_CTRL_CHANNEL, &adc_engine_control_reg_val, 614 614 + aspeed_adc_channels_mask(aspeed_adc_get_active_channels(data))); 615 615 + 658 616 writel(adc_engine_control_reg_val, 659 617 data->base + ASPEED_REG_ENGINE_CONTROL); 660 618

+3 -2

drivers/iio/adc/at91-sama5d2_adc.c

reviewed

··· 2259 2259 return 0; 2260 2260 2261 2261 /* Get the calibration data from NVMEM. */ 2262 2262 - temp_calib = devm_nvmem_cell_get(dev, "temperature_calib"); 2262 2262 + temp_calib = nvmem_cell_get(dev, "temperature_calib"); 2263 2263 if (IS_ERR(temp_calib)) { 2264 2264 ret = PTR_ERR(temp_calib); 2265 2265 if (ret != -ENOENT) ··· 2268 2268 } 2269 2269 2270 2270 buf = nvmem_cell_read(temp_calib, &len); 2271 2271 + nvmem_cell_put(temp_calib); 2271 2272 if (IS_ERR(buf)) { 2272 2273 dev_err(dev, "Failed to read calibration data!\n"); 2273 2274 return PTR_ERR(buf); ··· 2508 2507 at91_adc_buffer_postdisable(indio_dev); 2509 2508 2510 2509 /* 2511 2511 - * Do a sofware reset of the ADC before we go to suspend. 2510 2510 + * Do a software reset of the ADC before we go to suspend. 2512 2511 * this will ensure that all pins are free from being muxed by the ADC 2513 2512 * and can be used by for other devices. 2514 2513 * Otherwise, ADC will hog them and we can't go to suspend mode.

+5 -7

drivers/iio/adc/at91_adc.c

reviewed

··· 171 171 }; 172 172 173 173 /** 174 174 - * struct at91_adc_reg_desc - Various informations relative to registers 174 174 + * struct at91_adc_reg_desc - Various information relative to registers 175 175 * @channel_base: Base offset for the channel data registers 176 176 * @drdy_mask: Mask of the DRDY field in the relevant registers 177 177 * (Interruptions registers mostly) ··· 231 231 struct iio_trigger **trig; 232 232 bool use_external; 233 233 u32 vref_mv; 234 234 - u32 res; /* resolution used for convertions */ 234 234 + u32 res; /* resolution used for conversions */ 235 235 wait_queue_head_t wq_data_avail; 236 236 const struct at91_adc_caps *caps; 237 237 ··· 304 304 } 305 305 } 306 306 307 307 - static int at91_ts_sample(struct iio_dev *idev) 307 307 + static void at91_ts_sample(struct iio_dev *idev) 308 308 { 309 309 struct at91_adc_state *st = iio_priv(idev); 310 310 unsigned int xscale, yscale, reg, z1, z2; ··· 323 323 xscale = (reg >> 16) & xyz_mask; 324 324 if (xscale == 0) { 325 325 dev_err(&idev->dev, "Error: xscale == 0!\n"); 326 326 - return -1; 326 326 + return; 327 327 } 328 328 x /= xscale; 329 329 ··· 334 334 yscale = (reg >> 16) & xyz_mask; 335 335 if (yscale == 0) { 336 336 dev_err(&idev->dev, "Error: yscale == 0!\n"); 337 337 - return -1; 337 337 + return; 338 338 } 339 339 y /= yscale; 340 340 ··· 363 363 } else { 364 364 dev_dbg(&idev->dev, "pressure too low: not reporting\n"); 365 365 } 366 366 - 367 367 - return 0; 368 366 } 369 367 370 368 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)

+15

drivers/iio/adc/cpcap-adc.c

reviewed

··· 934 934 .atox_ps_factor_out = 0, 935 935 }; 936 936 937 937 + static const struct cpcap_adc_ato mot_adc = { 938 938 + .ato_in = 0x0300, 939 939 + .atox_in = 0, 940 940 + .adc_ps_factor_in = 0x0200, 941 941 + .atox_ps_factor_in = 0, 942 942 + .ato_out = 0x0780, 943 943 + .atox_out = 0, 944 944 + .adc_ps_factor_out = 0x0600, 945 945 + .atox_ps_factor_out = 0, 946 946 + }; 947 947 + 937 948 static const struct of_device_id cpcap_adc_id_table[] = { 938 949 { 939 950 .compatible = "motorola,cpcap-adc", ··· 952 941 { 953 942 .compatible = "motorola,mapphone-cpcap-adc", 954 943 .data = &mapphone_adc, 944 944 + }, 945 945 + { 946 946 + .compatible = "motorola,mot-cpcap-adc", 947 947 + .data = &mot_adc, 955 948 }, 956 949 { } 957 950 };

+1 -1

drivers/iio/adc/fsl-imx25-gcq.c

reviewed

··· 47 47 * of register writes, then a wait for a completion callback, 48 48 * and finally a register read, during which userspace could issue 49 49 * another read request. This lock protects a read access from 50 50 - * ocurring before another one has finished. 50 50 + * occurring before another one has finished. 51 51 */ 52 52 struct mutex lock; 53 53 };

+53 -12

drivers/iio/adc/ina2xx-adc.c

reviewed

··· 121 121 .volatile_reg = ina2xx_is_volatile_reg, 122 122 }; 123 123 124 124 - enum ina2xx_ids { ina219, ina226 }; 124 124 + enum ina2xx_ids { ina219, ina226, ina236 }; 125 125 126 126 struct ina2xx_config { 127 127 const char *name; ··· 174 174 .bus_voltage_lsb = 1250, 175 175 .power_lsb_factor = 25, 176 176 .chip_id = ina226, 177 177 + }, 178 178 + [ina236] = { 179 179 + .name = "ina236", 180 180 + .config_default = INA226_CONFIG_DEFAULT, 181 181 + .calibration_value = 2048, 182 182 + .shunt_voltage_lsb = 2500, 183 183 + .bus_voltage_shift = 0, 184 184 + .bus_voltage_lsb = 1600, 185 185 + .power_lsb_factor = 32, 186 186 + .chip_id = ina236, 177 187 }, 178 188 }; 179 189 ··· 509 499 break; 510 500 511 501 case IIO_CHAN_INFO_INT_TIME: 512 512 - if (chip->config->chip_id == ina226) { 502 502 + switch (chip->config->chip_id) { 503 503 + case ina226: 504 504 + case ina236: 513 505 if (chan->address == INA2XX_SHUNT_VOLTAGE) 514 506 ret = ina226_set_int_time_vshunt(chip, val2, 515 507 &tmp); 516 508 else 517 509 ret = ina226_set_int_time_vbus(chip, val2, 518 510 &tmp); 519 519 - } else { 511 511 + break; 512 512 + case ina219: 520 513 if (chan->address == INA2XX_SHUNT_VOLTAGE) 521 514 ret = ina219_set_int_time_vshunt(chip, val2, 522 515 &tmp); 523 516 else 524 517 ret = ina219_set_int_time_vbus(chip, val2, 525 518 &tmp); 519 519 + break; 520 520 + default: 521 521 + ret = -EINVAL; 526 522 } 527 523 break; 528 524 ··· 743 727 * For now, we do an extra read of the MASK_ENABLE register (INA226) 744 728 * resp. the BUS_VOLTAGE register (INA219). 745 729 */ 746 746 - if (chip->config->chip_id == ina226) { 730 730 + switch (chip->config->chip_id) { 731 731 + case ina226: 732 732 + case ina236: 747 733 ret = regmap_read(chip->regmap, 748 734 INA226_MASK_ENABLE, &alert); 735 735 + if (ret < 0) 736 736 + return ret; 737 737 + 749 738 alert &= INA226_CVRF; 750 750 - } else { 739 739 + break; 740 740 + case ina219: 751 741 ret = regmap_read(chip->regmap, 752 742 INA2XX_BUS_VOLTAGE, &alert); 743 743 + if (ret < 0) 744 744 + return ret; 753 745 alert &= INA219_CNVR; 746 746 + break; 747 747 + default: 748 748 + return -EINVAL; 754 749 } 755 755 - 756 756 - if (ret < 0) 757 757 - return ret; 758 750 759 751 return !!alert; 760 752 } ··· 1022 998 /* Patch the current config register with default. */ 1023 999 val = chip->config->config_default; 1024 1000 1025 1025 - if (type == ina226) { 1001 1001 + switch (type) { 1002 1002 + case ina226: 1003 1003 + case ina236: 1026 1004 ina226_set_average(chip, INA226_DEFAULT_AVG, &val); 1027 1005 ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val); 1028 1006 ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val); 1029 1029 - } else { 1007 1007 + break; 1008 1008 + case ina219: 1030 1009 chip->avg = 1; 1031 1010 ina219_set_int_time_vbus(chip, INA219_DEFAULT_IT, &val); 1032 1011 ina219_set_int_time_vshunt(chip, INA219_DEFAULT_IT, &val); 1033 1012 ina219_set_vbus_range_denom(chip, INA219_DEFAULT_BRNG, &val); 1034 1013 ina219_set_vshunt_pga_gain(chip, INA219_DEFAULT_PGA, &val); 1014 1014 + break; 1015 1015 + default: 1016 1016 + return -EINVAL; 1035 1017 } 1036 1018 1037 1019 ret = ina2xx_init(chip, val); ··· 1047 1017 } 1048 1018 1049 1019 indio_dev->modes = INDIO_DIRECT_MODE; 1050 1050 - if (type == ina226) { 1020 1020 + switch (type) { 1021 1021 + case ina226: 1022 1022 + case ina236: 1051 1023 indio_dev->channels = ina226_channels; 1052 1024 indio_dev->num_channels = ARRAY_SIZE(ina226_channels); 1053 1025 indio_dev->info = &ina226_info; 1054 1054 - } else { 1026 1026 + break; 1027 1027 + case ina219: 1055 1028 indio_dev->channels = ina219_channels; 1056 1029 indio_dev->num_channels = ARRAY_SIZE(ina219_channels); 1057 1030 indio_dev->info = &ina219_info; 1031 1031 + break; 1032 1032 + default: 1033 1033 + return -EINVAL; 1058 1034 } 1059 1035 indio_dev->name = id ? id->name : chip->config->name; 1060 1036 ··· 1093 1057 { "ina226", ina226 }, 1094 1058 { "ina230", ina226 }, 1095 1059 { "ina231", ina226 }, 1060 1060 + { "ina236", ina236 }, 1096 1061 { } 1097 1062 }; 1098 1063 MODULE_DEVICE_TABLE(i2c, ina2xx_id); ··· 1118 1081 { 1119 1082 .compatible = "ti,ina231", 1120 1083 .data = (void *)ina226 1084 1084 + }, 1085 1085 + { 1086 1086 + .compatible = "ti,ina236", 1087 1087 + .data = (void *)ina236 1121 1088 }, 1122 1089 { } 1123 1090 };

+60 -21

drivers/iio/adc/ltc2309.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* 3 3 + * The LTC2305 is a 2-Channel, 12-Bit SAR ADC with an I2C Interface. 3 4 * The LTC2309 is an 8-Channel, 12-Bit SAR ADC with an I2C Interface. 4 5 * 5 6 * Datasheet: 7 7 + * https://www.analog.com/media/en/technical-documentation/data-sheets/23015fb.pdf 6 8 * https://www.analog.com/media/en/technical-documentation/data-sheets/2309fd.pdf 7 9 * 8 10 * Copyright (c) 2023, Liam Beguin <liambeguin@gmail.com> ··· 43 41 }; 44 42 45 43 /* Order matches expected channel address, See datasheet Table 1. */ 44 44 + enum ltc2305_channels { 45 45 + LTC2305_CH0_CH1 = 0x0, 46 46 + LTC2305_CH1_CH0 = 0x4, 47 47 + LTC2305_CH0 = 0x8, 48 48 + LTC2305_CH1 = 0xc, 49 49 + }; 50 50 + 46 51 enum ltc2309_channels { 47 47 - LTC2309_CH0_CH1 = 0, 48 48 - LTC2309_CH2_CH3, 49 49 - LTC2309_CH4_CH5, 50 50 - LTC2309_CH6_CH7, 51 51 - LTC2309_CH1_CH0, 52 52 - LTC2309_CH3_CH2, 53 53 - LTC2309_CH5_CH4, 54 54 - LTC2309_CH7_CH6, 55 55 - LTC2309_CH0, 56 56 - LTC2309_CH2, 57 57 - LTC2309_CH4, 58 58 - LTC2309_CH6, 59 59 - LTC2309_CH1, 60 60 - LTC2309_CH3, 61 61 - LTC2309_CH5, 62 62 - LTC2309_CH7, 52 52 + LTC2309_CH0_CH1 = 0x0, 53 53 + LTC2309_CH2_CH3 = 0x1, 54 54 + LTC2309_CH4_CH5 = 0x2, 55 55 + LTC2309_CH6_CH7 = 0x3, 56 56 + LTC2309_CH1_CH0 = 0x4, 57 57 + LTC2309_CH3_CH2 = 0x5, 58 58 + LTC2309_CH5_CH4 = 0x6, 59 59 + LTC2309_CH7_CH6 = 0x7, 60 60 + LTC2309_CH0 = 0x8, 61 61 + LTC2309_CH2 = 0x9, 62 62 + LTC2309_CH4 = 0xa, 63 63 + LTC2309_CH6 = 0xb, 64 64 + LTC2309_CH1 = 0xc, 65 65 + LTC2309_CH3 = 0xd, 66 66 + LTC2309_CH5 = 0xe, 67 67 + LTC2309_CH7 = 0xf, 63 68 }; 64 69 65 70 #define LTC2309_CHAN(_chan, _addr) { \ ··· 89 80 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 90 81 } 91 82 83 83 + static const struct iio_chan_spec ltc2305_channels[] = { 84 84 + LTC2309_CHAN(0, LTC2305_CH0), 85 85 + LTC2309_CHAN(1, LTC2305_CH1), 86 86 + LTC2309_DIFF_CHAN(0, 1, LTC2305_CH0_CH1), 87 87 + LTC2309_DIFF_CHAN(1, 0, LTC2305_CH1_CH0), 88 88 + }; 89 89 + 92 90 static const struct iio_chan_spec ltc2309_channels[] = { 93 91 LTC2309_CHAN(0, LTC2309_CH0), 94 92 LTC2309_CHAN(1, LTC2309_CH1), ··· 113 97 LTC2309_DIFF_CHAN(3, 2, LTC2309_CH3_CH2), 114 98 LTC2309_DIFF_CHAN(5, 4, LTC2309_CH5_CH4), 115 99 LTC2309_DIFF_CHAN(7, 6, LTC2309_CH7_CH6), 100 100 + }; 101 101 + 102 102 + struct ltc2309_chip_info { 103 103 + const char *name; 104 104 + const struct iio_chan_spec *channels; 105 105 + int num_channels; 106 106 + }; 107 107 + 108 108 + static const struct ltc2309_chip_info ltc2305_chip_info = { 109 109 + .name = "ltc2305", 110 110 + .channels = ltc2305_channels, 111 111 + .num_channels = ARRAY_SIZE(ltc2305_channels), 112 112 + }; 113 113 + 114 114 + static const struct ltc2309_chip_info ltc2309_chip_info = { 115 115 + .name = "ltc2309", 116 116 + .channels = ltc2309_channels, 117 117 + .num_channels = ARRAY_SIZE(ltc2309_channels), 116 118 }; 117 119 118 120 static int ltc2309_read_raw_channel(struct ltc2309 *ltc2309, ··· 192 158 193 159 static int ltc2309_probe(struct i2c_client *client) 194 160 { 161 161 + const struct ltc2309_chip_info *chip_info; 195 162 struct iio_dev *indio_dev; 196 163 struct ltc2309 *ltc2309; 197 164 int ret; ··· 202 167 return -ENOMEM; 203 168 204 169 ltc2309 = iio_priv(indio_dev); 170 170 + chip_info = i2c_get_match_data(client); 171 171 + 205 172 ltc2309->dev = &indio_dev->dev; 206 173 ltc2309->client = client; 207 174 208 208 - indio_dev->name = "ltc2309"; 175 175 + indio_dev->name = chip_info->name; 209 176 indio_dev->modes = INDIO_DIRECT_MODE; 210 210 - indio_dev->channels = ltc2309_channels; 211 211 - indio_dev->num_channels = ARRAY_SIZE(ltc2309_channels); 177 177 + indio_dev->channels = chip_info->channels; 178 178 + indio_dev->num_channels = chip_info->num_channels; 212 179 indio_dev->info = &ltc2309_info; 213 180 214 181 ret = devm_regulator_get_enable_read_voltage(&client->dev, "vref"); ··· 226 189 } 227 190 228 191 static const struct of_device_id ltc2309_of_match[] = { 229 229 - { .compatible = "lltc,ltc2309" }, 192 192 + { .compatible = "lltc,ltc2305", .data = &ltc2305_chip_info }, 193 193 + { .compatible = "lltc,ltc2309", .data = &ltc2309_chip_info }, 230 194 { } 231 195 }; 232 196 MODULE_DEVICE_TABLE(of, ltc2309_of_match); 233 197 234 198 static const struct i2c_device_id ltc2309_id[] = { 235 235 - { "ltc2309" }, 199 199 + { "ltc2305", (kernel_ulong_t)&ltc2305_chip_info }, 200 200 + { "ltc2309", (kernel_ulong_t)&ltc2309_chip_info }, 236 201 { } 237 202 }; 238 203 MODULE_DEVICE_TABLE(i2c, ltc2309_id);

+2 -2

drivers/iio/adc/max11410.c

reviewed

··· 912 912 913 913 static int max11410_probe(struct spi_device *spi) 914 914 { 915 915 - const char *vrefp_regs[] = { "vref0p", "vref1p", "vref2p" }; 916 916 - const char *vrefn_regs[] = { "vref0n", "vref1n", "vref2n" }; 915 915 + static const char * const vrefp_regs[] = { "vref0p", "vref1p", "vref2p" }; 916 916 + static const char * const vrefn_regs[] = { "vref0n", "vref1n", "vref2n" }; 917 917 struct device *dev = &spi->dev; 918 918 struct max11410_state *st; 919 919 struct iio_dev *indio_dev;

+44 -43

drivers/iio/adc/max1363.c

reviewed

··· 121 121 }; 122 122 123 123 /** 124 124 - * struct max1363_chip_info - chip specifc information 124 124 + * struct max1363_chip_info - chip specific information 125 125 * @info: iio core function callbacks structure 126 126 * @channels: channel specification 127 127 * @num_channels: number of channels ··· 149 149 * @configbyte: cache of current device config byte 150 150 * @chip_info: chip model specific constants, available modes, etc. 151 151 * @current_mode: the scan mode of this chip 152 152 - * @requestedmask: a valid requested set of channels 153 152 * @lock: lock to ensure state is consistent 154 153 * @monitor_on: whether monitor mode is enabled 155 154 * @monitor_speed: parameter corresponding to device monitor speed setting ··· 168 169 u8 configbyte; 169 170 const struct max1363_chip_info *chip_info; 170 171 const struct max1363_mode *current_mode; 171 171 - u32 requestedmask; 172 172 struct mutex lock; 173 173 174 174 /* Using monitor modes and buffer at the same time is ··· 635 637 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10); 636 638 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12); 637 639 638 638 - enum { max1361, 639 639 - max1362, 640 640 - max1363, 641 641 - max1364, 642 642 - max1036, 643 643 - max1037, 644 644 - max1038, 645 645 - max1039, 646 646 - max1136, 647 647 - max1137, 648 648 - max1138, 649 649 - max1139, 650 650 - max1236, 651 651 - max1237, 652 652 - max1238, 653 653 - max1239, 654 654 - max11600, 655 655 - max11601, 656 656 - max11602, 657 657 - max11603, 658 658 - max11604, 659 659 - max11605, 660 660 - max11606, 661 661 - max11607, 662 662 - max11608, 663 663 - max11609, 664 664 - max11610, 665 665 - max11611, 666 666 - max11612, 667 667 - max11613, 668 668 - max11614, 669 669 - max11615, 670 670 - max11616, 671 671 - max11617, 672 672 - max11644, 673 673 - max11645, 674 674 - max11646, 675 675 - max11647 640 640 + enum { 641 641 + max1361, 642 642 + max1362, 643 643 + max1363, 644 644 + max1364, 645 645 + max1036, 646 646 + max1037, 647 647 + max1038, 648 648 + max1039, 649 649 + max1136, 650 650 + max1137, 651 651 + max1138, 652 652 + max1139, 653 653 + max1236, 654 654 + max1237, 655 655 + max1238, 656 656 + max1239, 657 657 + max11600, 658 658 + max11601, 659 659 + max11602, 660 660 + max11603, 661 661 + max11604, 662 662 + max11605, 663 663 + max11606, 664 664 + max11607, 665 665 + max11608, 666 666 + max11609, 667 667 + max11610, 668 668 + max11611, 669 669 + max11612, 670 670 + max11613, 671 671 + max11614, 672 672 + max11615, 673 673 + max11616, 674 674 + max11617, 675 675 + max11644, 676 676 + max11645, 677 677 + max11646, 678 678 + max11647, 676 679 }; 677 680 678 678 - static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600, 679 679 - 8300, 4200, 2000, 1000 }; 681 681 + static const int max1363_monitor_speeds[] = { 682 682 + 133000, 665000, 33300, 16600, 683 683 + 8300, 4200, 2000, 1000, 684 684 + }; 680 685 681 686 static ssize_t max1363_monitor_show_freq(struct device *dev, 682 687 struct device_attribute *attr,

+1 -1

drivers/iio/adc/mcp3564.c

reviewed

··· 349 349 * struct mcp3564_state - working data for a ADC device 350 350 * @chip_info: chip specific data 351 351 * @spi: SPI device structure 352 352 - * @vref_mv: voltage reference value in miliVolts 352 352 + * @vref_mv: voltage reference value in millivolts 353 353 * @lock: synchronize access to driver's state members 354 354 * @dev_addr: hardware device address 355 355 * @oversampling: the index inside oversampling list of the ADC

+1 -1

drivers/iio/adc/men_z188_adc.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 - * MEN 16z188 Analog to Digial Converter 3 3 + * MEN 16z188 Analog to Digital Converter 4 4 * 5 5 * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de) 6 6 * Author: Johannes Thumshirn <johannes.thumshirn@men.de>

+15 -6

drivers/iio/adc/meson_saradc.c

reviewed

··· 792 792 size_t read_len; 793 793 int ret; 794 794 795 795 - temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib"); 795 795 + temperature_calib = nvmem_cell_get(dev, "temperature_calib"); 796 796 if (IS_ERR(temperature_calib)) { 797 797 ret = PTR_ERR(temperature_calib); 798 798 ··· 806 806 return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n"); 807 807 } 808 808 809 809 - priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl"); 810 810 - if (IS_ERR(priv->tsc_regmap)) 811 811 - return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap), 812 812 - "failed to get amlogic,hhi-sysctrl regmap\n"); 813 813 - 814 809 read_len = MESON_SAR_ADC_EFUSE_BYTES; 815 810 buf = nvmem_cell_read(temperature_calib, &read_len); 811 811 + nvmem_cell_put(temperature_calib); 816 812 if (IS_ERR(buf)) 817 813 return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n"); 818 814 if (read_len != MESON_SAR_ADC_EFUSE_BYTES) { 819 815 kfree(buf); 820 816 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n"); 821 817 } 818 818 + 819 819 + priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl"); 820 820 + if (IS_ERR(priv->tsc_regmap)) 821 821 + return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap), 822 822 + "failed to get amlogic,hhi-sysctrl regmap\n"); 822 823 823 824 trimming_bits = priv->param->temperature_trimming_bits; 824 825 trimming_mask = BIT(trimming_bits) - 1; ··· 1314 1313 .name = "meson-g12a-saradc", 1315 1314 }; 1316 1315 1316 1316 + static const struct meson_sar_adc_data meson_sar_adc_s4_data = { 1317 1317 + .param = &meson_sar_adc_g12a_param, 1318 1318 + .name = "meson-s4-saradc", 1319 1319 + }; 1320 1320 + 1317 1321 static const struct of_device_id meson_sar_adc_of_match[] = { 1318 1322 { 1319 1323 .compatible = "amlogic,meson8-saradc", ··· 1347 1341 }, { 1348 1342 .compatible = "amlogic,meson-g12a-saradc", 1349 1343 .data = &meson_sar_adc_g12a_data, 1344 1344 + }, { 1345 1345 + .compatible = "amlogic,meson-s4-saradc", 1346 1346 + .data = &meson_sar_adc_s4_data, 1350 1347 }, 1351 1348 { } 1352 1349 };

+1 -1

drivers/iio/adc/mt6359-auxadc.c

reviewed

··· 322 322 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2), 323 323 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP1, 15, 8, 5, 2), 324 324 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 325 325 - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP1, 15 ,8, 1, 1), 325 325 + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP1, 15, 8, 1, 1), 326 326 MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP1, 15, 8, 3, 2), 327 327 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP1, 15, 128, 1, 1), 328 328 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP1, 15, 256, 1, 1),

+1 -2

drivers/iio/adc/nau7802.c

reviewed

··· 55 55 struct mutex data_lock; 56 56 u32 vref_mv; 57 57 u32 conversion_count; 58 58 - u32 min_conversions; 59 58 u8 sample_rate; 60 59 u32 scale_avail[8]; 61 60 struct completion value_ok; ··· 256 257 /* 257 258 * Because there is actually only one ADC for both channels, we have to 258 259 * wait for enough conversions to happen before getting a significant 259 259 - * value when changing channels and the values are far appart. 260 260 + * value when changing channels and the values are far apart. 260 261 */ 261 262 do { 262 263 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);

+1 -1

drivers/iio/adc/npcm_adc.c

reviewed

··· 38 38 * read access from userspace. Reading a raw value requires a sequence 39 39 * of register writes, then a wait for a event and finally a register 40 40 * read, during which userspace could issue another read request. 41 41 - * This lock protects a read access from ocurring before another one 41 41 + * This lock protects a read access from occurring before another one 42 42 * has finished. 43 43 */ 44 44 struct mutex lock;

+2 -1

drivers/iio/adc/nxp-sar-adc.c

reviewed

··· 247 247 248 248 static inline int nxp_sar_adc_calibration_wait(void __iomem *base) 249 249 { 250 250 - u32 msr, ret; 250 250 + u32 msr; 251 251 + int ret; 251 252 252 253 ret = readl_poll_timeout(NXP_SAR_ADC_MSR(base), msr, 253 254 !FIELD_GET(NXP_SAR_ADC_MSR_CALBUSY, msr),

+1 -1

drivers/iio/adc/pac1921.c

reviewed

··· 856 856 /* 857 857 * Read available scales for a specific channel 858 858 * 859 859 - * NOTE: using extended info insted of iio.read_avail() because access to 859 859 + * NOTE: using extended info instead of iio.read_avail() because access to 860 860 * current scales must be locked as they depend on shunt resistor which may 861 861 * change runtime. Caller of iio.read_avail() would access the table unlocked 862 862 * instead.

+1 -1

drivers/iio/adc/pac1934.c

reviewed

··· 1351 1351 1352 1352 dyn_ch_struct = devm_kzalloc(dev, channel_size, GFP_KERNEL); 1353 1353 if (!dyn_ch_struct) 1354 1354 - return -EINVAL; 1354 1354 + return -ENOMEM; 1355 1355 1356 1356 tmp_data = dyn_ch_struct; 1357 1357

+4 -4

drivers/iio/adc/palmas_gpadc.c

reviewed

··· 105 105 * of register writes, then a wait for a completion callback, 106 106 * and finally a register read, during which userspace could issue 107 107 * another read request. This lock protects a read access from 108 108 - * ocurring before another one has finished. 108 108 + * occurring before another one has finished. 109 109 * 110 110 * This is the palmas_gpadc structure to store run-time information 111 111 * and pointers for this driver instance. ··· 521 521 522 522 val = (val * 1000) / adc->adc_info[adc_chan].gain; 523 523 524 524 - if (adc->adc_info[adc_chan].is_uncalibrated) { 524 524 + if (adc->adc_info[adc_chan].is_uncalibrated) { 525 525 /* 2% worse */ 526 526 min_gain_error -= 20; 527 527 min_offset_error = -36; 528 528 - } else { 528 528 + } else { 529 529 val = (val * adc->adc_info[adc_chan].gain_error - 530 530 adc->adc_info[adc_chan].offset) / 531 531 1000; 532 532 min_offset_error = -2; 533 533 - } 533 533 + } 534 534 535 535 return palmas_gpadc_threshold_with_tolerance(val, 536 536 min_INL,

+860

drivers/iio/adc/qcom-spmi-adc5-gen3.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 4 + */ 5 5 + 6 6 + #include <linux/auxiliary_bus.h> 7 7 + #include <linux/bitfield.h> 8 8 + #include <linux/bits.h> 9 9 + #include <linux/cleanup.h> 10 10 + #include <linux/completion.h> 11 11 + #include <linux/container_of.h> 12 12 + #include <linux/delay.h> 13 13 + #include <linux/device.h> 14 14 + #include <linux/device/devres.h> 15 15 + #include <linux/dev_printk.h> 16 16 + #include <linux/err.h> 17 17 + #include <linux/export.h> 18 18 + #include <linux/iio/adc/qcom-adc5-gen3-common.h> 19 19 + #include <linux/iio/iio.h> 20 20 + #include <linux/interrupt.h> 21 21 + #include <linux/kernel.h> 22 22 + #include <linux/module.h> 23 23 + #include <linux/mod_devicetable.h> 24 24 + #include <linux/mutex.h> 25 25 + #include <linux/platform_device.h> 26 26 + #include <linux/property.h> 27 27 + #include <linux/regmap.h> 28 28 + #include <linux/types.h> 29 29 + #include <linux/unaligned.h> 30 30 + 31 31 + #define ADC5_GEN3_VADC_SDAM 0x0 32 32 + 33 33 + struct adc5_chip; 34 34 + 35 35 + /** 36 36 + * struct adc5_channel_prop - ADC channel structure 37 37 + * @common_props: structure with ADC channel properties (common to TM usage). 38 38 + * @adc_tm: indicates TM type if the channel is used for TM measurements. 39 39 + * @chip: pointer to top-level ADC device structure. 40 40 + */ 41 41 + struct adc5_channel_prop { 42 42 + struct adc5_channel_common_prop common_props; 43 43 + int adc_tm; 44 44 + struct adc5_chip *chip; 45 45 + }; 46 46 + 47 47 + /** 48 48 + * struct adc5_chip - ADC private structure. 49 49 + * @dev: SPMI ADC5 Gen3 device. 50 50 + * @dev_data: Top-level ADC device data. 51 51 + * @nchannels: number of ADC channels. 52 52 + * @chan_props: array of ADC channel properties. 53 53 + * @iio_chans: array of IIO channels specification. 54 54 + * @complete: ADC result notification after interrupt is received. 55 55 + * @lock: ADC lock for access to the peripheral, to prevent concurrent 56 56 + * requests from multiple clients. 57 57 + * @data: software configuration data. 58 58 + * @n_tm_channels: number of ADC channels used for TM measurements. 59 59 + * @handler: TM callback to be called for threshold violation interrupt 60 60 + * on first SDAM. 61 61 + * @tm_aux: pointer to auxiliary TM device. 62 62 + */ 63 63 + struct adc5_chip { 64 64 + struct device *dev; 65 65 + struct adc5_device_data dev_data; 66 66 + unsigned int nchannels; 67 67 + struct adc5_channel_prop *chan_props; 68 68 + struct iio_chan_spec *iio_chans; 69 69 + struct completion complete; 70 70 + struct mutex lock; 71 71 + const struct adc5_data *data; 72 72 + unsigned int n_tm_channels; 73 73 + void (*handler)(struct auxiliary_device *tm_aux); 74 74 + struct auxiliary_device *tm_aux; 75 75 + }; 76 76 + 77 77 + int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index, 78 78 + u16 offset, u8 *data, int len) 79 79 + { 80 80 + return regmap_bulk_read(adc->regmap, 81 81 + adc->base[sdam_index].base_addr + offset, 82 82 + data, len); 83 83 + } 84 84 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_read, "QCOM_SPMI_ADC5_GEN3"); 85 85 + 86 86 + int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index, 87 87 + u16 offset, u8 *data, int len) 88 88 + { 89 89 + return regmap_bulk_write(adc->regmap, 90 90 + adc->base[sdam_index].base_addr + offset, 91 91 + data, len); 92 92 + } 93 93 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_write, "QCOM_SPMI_ADC5_GEN3"); 94 94 + 95 95 + static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data) 96 96 + { 97 97 + u8 rslt[2]; 98 98 + int ret; 99 99 + 100 100 + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, 101 101 + ADC5_GEN3_CH_DATA0(0), rslt, sizeof(rslt)); 102 102 + if (ret) 103 103 + return ret; 104 104 + 105 105 + *data = get_unaligned_le16(rslt); 106 106 + 107 107 + if (*data == ADC5_USR_DATA_CHECK) { 108 108 + dev_err(adc->dev, "Invalid data:%#x\n", *data); 109 109 + return -EINVAL; 110 110 + } 111 111 + 112 112 + dev_dbg(adc->dev, "voltage raw code:%#x\n", *data); 113 113 + 114 114 + return 0; 115 115 + } 116 116 + 117 117 + void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, u8 *data) 118 118 + { 119 119 + /* Update calibration select and decimation ratio select */ 120 120 + *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK); 121 121 + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method); 122 122 + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation); 123 123 + } 124 124 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_update_dig_param, "QCOM_SPMI_ADC5_GEN3"); 125 125 + 126 126 + #define ADC5_GEN3_READ_CONFIG_REGS 7 127 127 + 128 128 + static int adc5_gen3_configure(struct adc5_chip *adc, 129 129 + struct adc5_channel_common_prop *prop) 130 130 + { 131 131 + u8 buf[ADC5_GEN3_READ_CONFIG_REGS]; 132 132 + u8 conv_req = 0; 133 133 + int ret; 134 134 + 135 135 + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SID, 136 136 + buf, sizeof(buf)); 137 137 + if (ret) 138 138 + return ret; 139 139 + 140 140 + /* Write SID */ 141 141 + buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid); 142 142 + 143 143 + /* 144 144 + * Use channel 0 by default for immediate conversion and to indicate 145 145 + * there is an actual conversion request 146 146 + */ 147 147 + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | 0; 148 148 + 149 149 + buf[2] = ADC5_GEN3_TIME_IMMEDIATE; 150 150 + 151 151 + /* Digital param selection */ 152 152 + adc5_gen3_update_dig_param(prop, &buf[3]); 153 153 + 154 154 + /* Update fast average sample value */ 155 155 + buf[4] = FIELD_PREP(ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK, 156 156 + prop->avg_samples) | ADC5_GEN3_FAST_AVG_CTL_EN; 157 157 + 158 158 + /* Select ADC channel */ 159 159 + buf[5] = prop->channel; 160 160 + 161 161 + /* Select HW settle delay for channel */ 162 162 + buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, 163 163 + prop->hw_settle_time_us); 164 164 + 165 165 + reinit_completion(&adc->complete); 166 166 + 167 167 + ret = adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SID, 168 168 + buf, sizeof(buf)); 169 169 + if (ret) 170 170 + return ret; 171 171 + 172 172 + conv_req = ADC5_GEN3_CONV_REQ_REQ; 173 173 + return adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM, 174 174 + ADC5_GEN3_CONV_REQ, &conv_req, sizeof(conv_req)); 175 175 + } 176 176 + 177 177 + /* 178 178 + * Worst case delay from PBS in readying handshake bit can be up to 15ms, when 179 179 + * PBS is busy running other simultaneous transactions, while in the best case, 180 180 + * it is already ready at this point. Assigning polling delay and retry count 181 181 + * accordingly. 182 182 + */ 183 183 + 184 184 + #define ADC5_GEN3_HS_DELAY_US 100 185 185 + #define ADC5_GEN3_HS_RETRY_COUNT 150 186 186 + 187 187 + int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc, 188 188 + unsigned int sdam_index) 189 189 + { 190 190 + u8 conv_req = ADC5_GEN3_CONV_REQ_REQ; 191 191 + int ret, count; 192 192 + u8 status = 0; 193 193 + 194 194 + for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) { 195 195 + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, sizeof(status)); 196 196 + if (ret) 197 197 + return ret; 198 198 + 199 199 + if (status == ADC5_GEN3_HS_READY) { 200 200 + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ, 201 201 + &conv_req, sizeof(conv_req)); 202 202 + if (ret) 203 203 + return ret; 204 204 + 205 205 + if (!conv_req) 206 206 + return 0; 207 207 + } 208 208 + 209 209 + fsleep(ADC5_GEN3_HS_DELAY_US); 210 210 + } 211 211 + 212 212 + pr_err("Setting HS ready bit timed out, sdam_index:%d, status:%#x\n", 213 213 + sdam_index, status); 214 214 + return -ETIMEDOUT; 215 215 + } 216 216 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_poll_wait_hs, "QCOM_SPMI_ADC5_GEN3"); 217 217 + 218 218 + int adc5_gen3_status_clear(struct adc5_device_data *adc, 219 219 + int sdam_index, u16 offset, u8 *val, int len) 220 220 + { 221 221 + u8 value; 222 222 + int ret; 223 223 + 224 224 + ret = adc5_gen3_write(adc, sdam_index, offset, val, len); 225 225 + if (ret) 226 226 + return ret; 227 227 + 228 228 + /* To indicate conversion request is only to clear a status */ 229 229 + value = 0; 230 230 + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &value, 231 231 + sizeof(value)); 232 232 + if (ret) 233 233 + return ret; 234 234 + 235 235 + value = ADC5_GEN3_CONV_REQ_REQ; 236 236 + return adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &value, 237 237 + sizeof(value)); 238 238 + } 239 239 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_status_clear, "QCOM_SPMI_ADC5_GEN3"); 240 240 + 241 241 + /* 242 242 + * Worst case delay from PBS for conversion time can be up to 500ms, when PBS 243 243 + * has timed out twice, once for the initial attempt and once for a retry of 244 244 + * the same transaction. 245 245 + */ 246 246 + 247 247 + #define ADC5_GEN3_CONV_TIMEOUT_MS 501 248 248 + 249 249 + static int adc5_gen3_do_conversion(struct adc5_chip *adc, 250 250 + struct adc5_channel_common_prop *prop, 251 251 + u16 *data_volt) 252 252 + { 253 253 + unsigned long rc; 254 254 + int ret; 255 255 + u8 val; 256 256 + 257 257 + guard(mutex)(&adc->lock); 258 258 + ret = adc5_gen3_poll_wait_hs(&adc->dev_data, ADC5_GEN3_VADC_SDAM); 259 259 + if (ret) 260 260 + return ret; 261 261 + 262 262 + ret = adc5_gen3_configure(adc, prop); 263 263 + if (ret) { 264 264 + dev_err(adc->dev, "ADC configure failed with %d\n", ret); 265 265 + return ret; 266 266 + } 267 267 + 268 268 + /* No support for polling mode at present */ 269 269 + rc = wait_for_completion_timeout(&adc->complete, 270 270 + msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS)); 271 271 + if (!rc) { 272 272 + dev_err(adc->dev, "Reading ADC channel %s timed out\n", 273 273 + prop->label); 274 274 + return -ETIMEDOUT; 275 275 + } 276 276 + 277 277 + ret = adc5_gen3_read_voltage_data(adc, data_volt); 278 278 + if (ret) 279 279 + return ret; 280 280 + 281 281 + val = BIT(0); 282 282 + return adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM, 283 283 + ADC5_GEN3_EOC_CLR, &val, 1); 284 284 + } 285 285 + 286 286 + static irqreturn_t adc5_gen3_isr(int irq, void *dev_id) 287 287 + { 288 288 + struct adc5_chip *adc = dev_id; 289 289 + struct device *dev = adc->dev; 290 290 + struct auxiliary_device *adev; 291 291 + u8 status, eoc_status, val; 292 292 + u8 tm_status[2]; 293 293 + int ret; 294 294 + 295 295 + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, 296 296 + ADC5_GEN3_STATUS1, &status, sizeof(status)); 297 297 + if (ret) { 298 298 + dev_err(dev, "adc read status1 failed with %d\n", ret); 299 299 + return IRQ_HANDLED; 300 300 + } 301 301 + 302 302 + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, 303 303 + ADC5_GEN3_EOC_STS, &eoc_status, sizeof(eoc_status)); 304 304 + if (ret) { 305 305 + dev_err(dev, "adc read eoc status failed with %d\n", ret); 306 306 + return IRQ_HANDLED; 307 307 + } 308 308 + 309 309 + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { 310 310 + dev_err_ratelimited(dev, 311 311 + "Unexpected conversion fault, status:%#x, eoc_status:%#x\n", 312 312 + status, eoc_status); 313 313 + val = ADC5_GEN3_CONV_ERR_CLR_REQ; 314 314 + adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM, 315 315 + ADC5_GEN3_CONV_ERR_CLR, &val, 1); 316 316 + return IRQ_HANDLED; 317 317 + } 318 318 + 319 319 + /* CHAN0 is the preconfigured channel for immediate conversion */ 320 320 + if (eoc_status & ADC5_GEN3_EOC_CHAN_0) 321 321 + complete(&adc->complete); 322 322 + 323 323 + ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, 324 324 + ADC5_GEN3_TM_HIGH_STS, tm_status, sizeof(tm_status)); 325 325 + if (ret) { 326 326 + dev_err(dev, "adc read TM status failed with %d\n", ret); 327 327 + return IRQ_HANDLED; 328 328 + } 329 329 + 330 330 + dev_dbg(dev, "Interrupt status:%#x, EOC status:%#x, high:%#x, low:%#x\n", 331 331 + status, eoc_status, tm_status[0], tm_status[1]); 332 332 + 333 333 + if (tm_status[0] || tm_status[1]) { 334 334 + adev = adc->tm_aux; 335 335 + if (!adev || !adev->dev.driver) { 336 336 + dev_err(dev, "adc_tm auxiliary device not initialized\n"); 337 337 + return IRQ_HANDLED; 338 338 + } 339 339 + 340 340 + adc->handler(adev); 341 341 + } 342 342 + 343 343 + return IRQ_HANDLED; 344 344 + } 345 345 + 346 346 + static int adc5_gen3_fwnode_xlate(struct iio_dev *indio_dev, 347 347 + const struct fwnode_reference_args *iiospec) 348 348 + { 349 349 + struct adc5_chip *adc = iio_priv(indio_dev); 350 350 + int i, v_channel; 351 351 + 352 352 + for (i = 0; i < adc->nchannels; i++) { 353 353 + v_channel = ADC5_GEN3_V_CHAN(adc->chan_props[i].common_props); 354 354 + if (v_channel == iiospec->args[0]) 355 355 + return i; 356 356 + } 357 357 + 358 358 + return -ENOENT; 359 359 + } 360 360 + 361 361 + static int adc5_gen3_read_raw(struct iio_dev *indio_dev, 362 362 + struct iio_chan_spec const *chan, int *val, 363 363 + int *val2, long mask) 364 364 + { 365 365 + struct adc5_chip *adc = iio_priv(indio_dev); 366 366 + struct adc5_channel_common_prop *prop; 367 367 + u16 adc_code_volt; 368 368 + int ret; 369 369 + 370 370 + prop = &adc->chan_props[chan->address].common_props; 371 371 + 372 372 + switch (mask) { 373 373 + case IIO_CHAN_INFO_PROCESSED: 374 374 + ret = adc5_gen3_do_conversion(adc, prop, &adc_code_volt); 375 375 + if (ret) 376 376 + return ret; 377 377 + 378 378 + ret = qcom_adc5_hw_scale(prop->scale_fn_type, prop->prescale, 379 379 + adc->data, adc_code_volt, val); 380 380 + if (ret) 381 381 + return ret; 382 382 + 383 383 + return IIO_VAL_INT; 384 384 + default: 385 385 + return -EINVAL; 386 386 + } 387 387 + } 388 388 + 389 389 + static int adc5_gen3_read_label(struct iio_dev *indio_dev, 390 390 + const struct iio_chan_spec *chan, char *label) 391 391 + { 392 392 + struct adc5_chip *adc = iio_priv(indio_dev); 393 393 + struct adc5_channel_prop *prop; 394 394 + 395 395 + prop = &adc->chan_props[chan->address]; 396 396 + return sprintf(label, "%s\n", prop->common_props.label); 397 397 + } 398 398 + 399 399 + static const struct iio_info adc5_gen3_info = { 400 400 + .read_raw = adc5_gen3_read_raw, 401 401 + .read_label = adc5_gen3_read_label, 402 402 + .fwnode_xlate = adc5_gen3_fwnode_xlate, 403 403 + }; 404 404 + 405 405 + struct adc5_channels { 406 406 + unsigned int prescale_index; 407 407 + enum iio_chan_type type; 408 408 + long info_mask; 409 409 + enum vadc_scale_fn_type scale_fn_type; 410 410 + }; 411 411 + 412 412 + /* In these definitions, _pre refers to an index into adc5_prescale_ratios. */ 413 413 + #define ADC5_CHAN(_type, _mask, _pre, _scale) \ 414 414 + { \ 415 415 + .prescale_index = _pre, \ 416 416 + .type = _type, \ 417 417 + .info_mask = _mask, \ 418 418 + .scale_fn_type = _scale, \ 419 419 + }, \ 420 420 + 421 421 + #define ADC5_CHAN_TEMP(_pre, _scale) \ 422 422 + ADC5_CHAN(IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ 423 423 + 424 424 + #define ADC5_CHAN_VOLT(_pre, _scale) \ 425 425 + ADC5_CHAN(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ 426 426 + 427 427 + #define ADC5_CHAN_CUR(_pre, _scale) \ 428 428 + ADC5_CHAN(IIO_CURRENT, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ 429 429 + 430 430 + static const struct adc5_channels adc5_gen3_chans_pmic[ADC5_MAX_CHANNEL] = { 431 431 + [ADC5_GEN3_REF_GND] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT) 432 432 + [ADC5_GEN3_1P25VREF] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT) 433 433 + [ADC5_GEN3_VPH_PWR] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT) 434 434 + [ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT) 435 435 + [ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT) 436 436 + [ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT) 437 437 + [ADC5_GEN3_DIE_TEMP] = ADC5_CHAN_TEMP(0, 438 438 + SCALE_HW_CALIB_PMIC_THERM_PM7) 439 439 + [ADC5_GEN3_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP(0, 440 440 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 441 441 + [ADC5_GEN3_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP(0, 442 442 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 443 443 + [ADC5_GEN3_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP(0, 444 444 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 445 445 + [ADC5_GEN3_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP(0, 446 446 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 447 447 + [ADC5_GEN3_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP(0, 448 448 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 449 449 + [ADC5_GEN3_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP(0, 450 450 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 451 451 + [ADC5_GEN3_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, 452 452 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 453 453 + [ADC5_GEN3_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, 454 454 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 455 455 + [ADC5_GEN3_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, 456 456 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 457 457 + [ADC5_GEN3_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP(0, 458 458 + SCALE_HW_CALIB_THERM_100K_PU_PM7) 459 459 + }; 460 460 + 461 461 + static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc, 462 462 + struct adc5_channel_prop *prop, 463 463 + struct fwnode_handle *fwnode) 464 464 + { 465 465 + const char *name = fwnode_get_name(fwnode); 466 466 + const struct adc5_data *data = adc->data; 467 467 + struct device *dev = adc->dev; 468 468 + const char *channel_name; 469 469 + u32 chan, value, sid; 470 470 + u32 varr[2]; 471 471 + int ret; 472 472 + 473 473 + ret = fwnode_property_read_u32(fwnode, "reg", &chan); 474 474 + if (ret < 0) 475 475 + return dev_err_probe(dev, ret, "invalid channel number %s\n", 476 476 + name); 477 477 + 478 478 + /* 479 479 + * Value read from "reg" is virtual channel number 480 480 + * virtual channel number = sid << 8 | channel number 481 481 + */ 482 482 + sid = FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan); 483 483 + chan = FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan); 484 484 + 485 485 + if (chan > ADC5_MAX_CHANNEL) 486 486 + return dev_err_probe(dev, -EINVAL, 487 487 + "%s invalid channel number %d\n", 488 488 + name, chan); 489 489 + 490 490 + prop->common_props.channel = chan; 491 491 + prop->common_props.sid = sid; 492 492 + 493 493 + if (!adc->data->adc_chans[chan].info_mask) 494 494 + return dev_err_probe(dev, -EINVAL, "Channel %#x not supported\n", chan); 495 495 + 496 496 + channel_name = name; 497 497 + fwnode_property_read_string(fwnode, "label", &channel_name); 498 498 + prop->common_props.label = channel_name; 499 499 + 500 500 + value = data->decimation[ADC5_DECIMATION_DEFAULT]; 501 501 + fwnode_property_read_u32(fwnode, "qcom,decimation", &value); 502 502 + ret = qcom_adc5_decimation_from_dt(value, data->decimation); 503 503 + if (ret < 0) 504 504 + return dev_err_probe(dev, ret, "%#x invalid decimation %d\n", 505 505 + chan, value); 506 506 + prop->common_props.decimation = ret; 507 507 + 508 508 + prop->common_props.prescale = adc->data->adc_chans[chan].prescale_index; 509 509 + ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2); 510 510 + if (!ret) { 511 511 + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); 512 512 + if (ret < 0) 513 513 + return dev_err_probe(dev, ret, 514 514 + "%#x invalid pre-scaling <%d %d>\n", 515 515 + chan, varr[0], varr[1]); 516 516 + prop->common_props.prescale = ret; 517 517 + } 518 518 + 519 519 + value = data->hw_settle_1[VADC_DEF_HW_SETTLE_TIME]; 520 520 + fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value); 521 521 + ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1); 522 522 + if (ret < 0) 523 523 + return dev_err_probe(dev, ret, 524 524 + "%#x invalid hw-settle-time %d us\n", 525 525 + chan, value); 526 526 + prop->common_props.hw_settle_time_us = ret; 527 527 + 528 528 + value = BIT(VADC_DEF_AVG_SAMPLES); 529 529 + fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value); 530 530 + ret = qcom_adc5_avg_samples_from_dt(value); 531 531 + if (ret < 0) 532 532 + return dev_err_probe(dev, ret, "%#x invalid avg-samples %d\n", 533 533 + chan, value); 534 534 + prop->common_props.avg_samples = ret; 535 535 + 536 536 + if (fwnode_property_read_bool(fwnode, "qcom,ratiometric")) 537 537 + prop->common_props.cal_method = ADC5_RATIOMETRIC_CAL; 538 538 + else 539 539 + prop->common_props.cal_method = ADC5_ABSOLUTE_CAL; 540 540 + 541 541 + prop->adc_tm = fwnode_property_read_bool(fwnode, "qcom,adc-tm"); 542 542 + if (prop->adc_tm) { 543 543 + adc->n_tm_channels++; 544 544 + if (adc->n_tm_channels > (adc->dev_data.num_sdams * 8 - 1)) 545 545 + return dev_err_probe(dev, -EINVAL, 546 546 + "Number of TM nodes %u greater than channels supported:%u\n", 547 547 + adc->n_tm_channels, 548 548 + adc->dev_data.num_sdams * 8 - 1); 549 549 + } 550 550 + 551 551 + return 0; 552 552 + } 553 553 + 554 554 + static const struct adc5_data adc5_gen3_data_pmic = { 555 555 + .full_scale_code_volt = 0x70e4, 556 556 + .adc_chans = adc5_gen3_chans_pmic, 557 557 + .info = &adc5_gen3_info, 558 558 + .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) 559 559 + { 85, 340, 1360 }, 560 560 + .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) 561 561 + { 15, 100, 200, 300, 562 562 + 400, 500, 600, 700, 563 563 + 1000, 2000, 4000, 8000, 564 564 + 16000, 32000, 64000, 128000 }, 565 565 + }; 566 566 + 567 567 + static const struct of_device_id adc5_match_table[] = { 568 568 + { 569 569 + .compatible = "qcom,spmi-adc5-gen3", 570 570 + .data = &adc5_gen3_data_pmic, 571 571 + }, 572 572 + { } 573 573 + }; 574 574 + MODULE_DEVICE_TABLE(of, adc5_match_table); 575 575 + 576 576 + static int adc5_get_fw_data(struct adc5_chip *adc) 577 577 + { 578 578 + const struct adc5_channels *adc_chan; 579 579 + struct adc5_channel_prop *chan_props; 580 580 + struct iio_chan_spec *iio_chan; 581 581 + struct device *dev = adc->dev; 582 582 + unsigned int index = 0; 583 583 + int ret; 584 584 + 585 585 + adc->nchannels = device_get_child_node_count(dev); 586 586 + if (!adc->nchannels) 587 587 + return dev_err_probe(dev, -EINVAL, "No ADC channels found\n"); 588 588 + 589 589 + adc->iio_chans = devm_kcalloc(dev, adc->nchannels, 590 590 + sizeof(*adc->iio_chans), GFP_KERNEL); 591 591 + if (!adc->iio_chans) 592 592 + return -ENOMEM; 593 593 + 594 594 + adc->chan_props = devm_kcalloc(dev, adc->nchannels, 595 595 + sizeof(*adc->chan_props), GFP_KERNEL); 596 596 + if (!adc->chan_props) 597 597 + return -ENOMEM; 598 598 + 599 599 + chan_props = adc->chan_props; 600 600 + adc->n_tm_channels = 0; 601 601 + iio_chan = adc->iio_chans; 602 602 + adc->data = device_get_match_data(dev); 603 603 + 604 604 + device_for_each_child_node_scoped(dev, child) { 605 605 + ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child); 606 606 + if (ret) 607 607 + return ret; 608 608 + 609 609 + chan_props->chip = adc; 610 610 + adc_chan = &adc->data->adc_chans[chan_props->common_props.channel]; 611 611 + chan_props->common_props.scale_fn_type = adc_chan->scale_fn_type; 612 612 + 613 613 + iio_chan->channel = ADC5_GEN3_V_CHAN(chan_props->common_props); 614 614 + iio_chan->info_mask_separate = adc_chan->info_mask; 615 615 + iio_chan->type = adc_chan->type; 616 616 + iio_chan->address = index; 617 617 + iio_chan->indexed = 1; 618 618 + iio_chan++; 619 619 + chan_props++; 620 620 + index++; 621 621 + } 622 622 + 623 623 + return 0; 624 624 + } 625 625 + 626 626 + static void adc5_gen3_uninit_aux(void *data) 627 627 + { 628 628 + auxiliary_device_uninit(data); 629 629 + } 630 630 + 631 631 + static void adc5_gen3_delete_aux(void *data) 632 632 + { 633 633 + auxiliary_device_delete(data); 634 634 + } 635 635 + 636 636 + static void adc5_gen3_aux_device_release(struct device *dev) {} 637 637 + 638 638 + static int adc5_gen3_add_aux_tm_device(struct adc5_chip *adc) 639 639 + { 640 640 + struct tm5_aux_dev_wrapper *aux_device; 641 641 + int i, ret, i_tm = 0; 642 642 + 643 643 + aux_device = devm_kzalloc(adc->dev, sizeof(*aux_device), GFP_KERNEL); 644 644 + if (!aux_device) 645 645 + return -ENOMEM; 646 646 + 647 647 + aux_device->aux_dev.name = "adc5_tm_gen3"; 648 648 + aux_device->aux_dev.dev.parent = adc->dev; 649 649 + aux_device->aux_dev.dev.release = adc5_gen3_aux_device_release; 650 650 + 651 651 + aux_device->tm_props = devm_kcalloc(adc->dev, adc->n_tm_channels, 652 652 + sizeof(*aux_device->tm_props), 653 653 + GFP_KERNEL); 654 654 + if (!aux_device->tm_props) 655 655 + return -ENOMEM; 656 656 + 657 657 + aux_device->dev_data = &adc->dev_data; 658 658 + 659 659 + for (i = 0; i < adc->nchannels; i++) { 660 660 + if (!adc->chan_props[i].adc_tm) 661 661 + continue; 662 662 + aux_device->tm_props[i_tm] = adc->chan_props[i].common_props; 663 663 + i_tm++; 664 664 + } 665 665 + 666 666 + device_set_of_node_from_dev(&aux_device->aux_dev.dev, adc->dev); 667 667 + 668 668 + aux_device->n_tm_channels = adc->n_tm_channels; 669 669 + 670 670 + ret = auxiliary_device_init(&aux_device->aux_dev); 671 671 + if (ret) 672 672 + return ret; 673 673 + 674 674 + ret = devm_add_action_or_reset(adc->dev, adc5_gen3_uninit_aux, 675 675 + &aux_device->aux_dev); 676 676 + if (ret) 677 677 + return ret; 678 678 + 679 679 + ret = auxiliary_device_add(&aux_device->aux_dev); 680 680 + if (ret) 681 681 + return ret; 682 682 + ret = devm_add_action_or_reset(adc->dev, adc5_gen3_delete_aux, 683 683 + &aux_device->aux_dev); 684 684 + if (ret) 685 685 + return ret; 686 686 + 687 687 + adc->tm_aux = &aux_device->aux_dev; 688 688 + 689 689 + return 0; 690 690 + } 691 691 + 692 692 + void adc5_gen3_mutex_lock(struct device *dev) 693 693 + __acquires(&adc->lock) 694 694 + { 695 695 + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); 696 696 + struct adc5_chip *adc = iio_priv(indio_dev); 697 697 + 698 698 + mutex_lock(&adc->lock); 699 699 + } 700 700 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_mutex_lock, "QCOM_SPMI_ADC5_GEN3"); 701 701 + 702 702 + void adc5_gen3_mutex_unlock(struct device *dev) 703 703 + __releases(&adc->lock) 704 704 + { 705 705 + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); 706 706 + struct adc5_chip *adc = iio_priv(indio_dev); 707 707 + 708 708 + mutex_unlock(&adc->lock); 709 709 + } 710 710 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_mutex_unlock, "QCOM_SPMI_ADC5_GEN3"); 711 711 + 712 712 + int adc5_gen3_get_scaled_reading(struct device *dev, 713 713 + struct adc5_channel_common_prop *common_props, 714 714 + int *val) 715 715 + { 716 716 + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); 717 717 + struct adc5_chip *adc = iio_priv(indio_dev); 718 718 + u16 adc_code_volt; 719 719 + int ret; 720 720 + 721 721 + ret = adc5_gen3_do_conversion(adc, common_props, &adc_code_volt); 722 722 + if (ret) 723 723 + return ret; 724 724 + 725 725 + return qcom_adc5_hw_scale(common_props->scale_fn_type, 726 726 + common_props->prescale, 727 727 + adc->data, adc_code_volt, val); 728 728 + } 729 729 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_get_scaled_reading, "QCOM_SPMI_ADC5_GEN3"); 730 730 + 731 731 + int adc5_gen3_therm_code_to_temp(struct device *dev, 732 732 + struct adc5_channel_common_prop *common_props, 733 733 + u16 code, int *val) 734 734 + { 735 735 + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); 736 736 + struct adc5_chip *adc = iio_priv(indio_dev); 737 737 + 738 738 + return qcom_adc5_hw_scale(common_props->scale_fn_type, 739 739 + common_props->prescale, 740 740 + adc->data, code, val); 741 741 + } 742 742 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_therm_code_to_temp, "QCOM_SPMI_ADC5_GEN3"); 743 743 + 744 744 + void adc5_gen3_register_tm_event_notifier(struct device *dev, 745 745 + void (*handler)(struct auxiliary_device *)) 746 746 + { 747 747 + struct iio_dev *indio_dev = dev_get_drvdata(dev->parent); 748 748 + struct adc5_chip *adc = iio_priv(indio_dev); 749 749 + 750 750 + adc->handler = handler; 751 751 + } 752 752 + EXPORT_SYMBOL_NS_GPL(adc5_gen3_register_tm_event_notifier, "QCOM_SPMI_ADC5_GEN3"); 753 753 + 754 754 + static int adc5_gen3_probe(struct platform_device *pdev) 755 755 + { 756 756 + struct device *dev = &pdev->dev; 757 757 + struct iio_dev *indio_dev; 758 758 + struct adc5_chip *adc; 759 759 + struct regmap *regmap; 760 760 + int ret, i; 761 761 + u32 *reg; 762 762 + 763 763 + regmap = dev_get_regmap(dev->parent, NULL); 764 764 + if (!regmap) 765 765 + return -ENODEV; 766 766 + 767 767 + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 768 768 + if (!indio_dev) 769 769 + return -ENOMEM; 770 770 + 771 771 + adc = iio_priv(indio_dev); 772 772 + adc->dev_data.regmap = regmap; 773 773 + adc->dev = dev; 774 774 + 775 775 + ret = device_property_count_u32(dev, "reg"); 776 776 + if (ret < 0) 777 777 + return ret; 778 778 + 779 779 + adc->dev_data.num_sdams = ret; 780 780 + 781 781 + reg = devm_kcalloc(dev, adc->dev_data.num_sdams, sizeof(u32), 782 782 + GFP_KERNEL); 783 783 + if (!reg) 784 784 + return -ENOMEM; 785 785 + 786 786 + ret = device_property_read_u32_array(dev, "reg", reg, 787 787 + adc->dev_data.num_sdams); 788 788 + if (ret) 789 789 + return dev_err_probe(dev, ret, 790 790 + "Failed to read reg property\n"); 791 791 + 792 792 + adc->dev_data.base = devm_kcalloc(dev, adc->dev_data.num_sdams, 793 793 + sizeof(*adc->dev_data.base), 794 794 + GFP_KERNEL); 795 795 + if (!adc->dev_data.base) 796 796 + return -ENOMEM; 797 797 + 798 798 + platform_set_drvdata(pdev, indio_dev); 799 799 + init_completion(&adc->complete); 800 800 + ret = devm_mutex_init(dev, &adc->lock); 801 801 + if (ret) 802 802 + return ret; 803 803 + 804 804 + for (i = 0; i < adc->dev_data.num_sdams; i++) { 805 805 + adc->dev_data.base[i].base_addr = reg[i]; 806 806 + 807 807 + ret = platform_get_irq(pdev, i); 808 808 + if (ret < 0) 809 809 + return dev_err_probe(dev, ret, 810 810 + "Getting IRQ %d failed\n", i); 811 811 + 812 812 + adc->dev_data.base[i].irq = ret; 813 813 + 814 814 + adc->dev_data.base[i].irq_name = devm_kasprintf(dev, GFP_KERNEL, 815 815 + "sdam%d", i); 816 816 + if (!adc->dev_data.base[i].irq_name) 817 817 + return -ENOMEM; 818 818 + } 819 819 + 820 820 + ret = devm_request_irq(dev, adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq, 821 821 + adc5_gen3_isr, 0, 822 822 + adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq_name, 823 823 + adc); 824 824 + if (ret) 825 825 + return dev_err_probe(dev, ret, 826 826 + "Failed to request SDAM%d irq\n", 827 827 + ADC5_GEN3_VADC_SDAM); 828 828 + 829 829 + ret = adc5_get_fw_data(adc); 830 830 + if (ret) 831 831 + return ret; 832 832 + 833 833 + if (adc->n_tm_channels > 0) { 834 834 + ret = adc5_gen3_add_aux_tm_device(adc); 835 835 + if (ret) 836 836 + dev_err_probe(dev, ret, 837 837 + "Failed to add auxiliary TM device\n"); 838 838 + } 839 839 + 840 840 + indio_dev->name = "spmi-adc5-gen3"; 841 841 + indio_dev->modes = INDIO_DIRECT_MODE; 842 842 + indio_dev->info = &adc5_gen3_info; 843 843 + indio_dev->channels = adc->iio_chans; 844 844 + indio_dev->num_channels = adc->nchannels; 845 845 + 846 846 + return devm_iio_device_register(dev, indio_dev); 847 847 + } 848 848 + 849 849 + static struct platform_driver adc5_gen3_driver = { 850 850 + .driver = { 851 851 + .name = "qcom-spmi-adc5-gen3", 852 852 + .of_match_table = adc5_match_table, 853 853 + }, 854 854 + .probe = adc5_gen3_probe, 855 855 + }; 856 856 + module_platform_driver(adc5_gen3_driver); 857 857 + 858 858 + MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 Gen3 ADC driver"); 859 859 + MODULE_LICENSE("GPL"); 860 860 + MODULE_IMPORT_NS("QCOM_SPMI_ADC5_GEN3");

+2 -2

drivers/iio/adc/rohm-bd79124.c

reviewed

··· 75 75 76 76 /* 77 77 * The high limit, low limit and last measurement result are each stored in 78 78 - * 2 consequtive registers. 4 bits are in the high bits of the first register 78 78 + * 2 consecutive registers. 4 bits are in the high bits of the first register 79 79 * and 8 bits in the next register. 80 80 * 81 81 * These macros return the address of the first reg for the given channel. ··· 962 962 if (ret) 963 963 return ret; 964 964 965 965 - /* Enable writing the measured values to the regsters */ 965 965 + /* Enable writing the measured values to the registers */ 966 966 ret = regmap_set_bits(data->map, BD79124_REG_GEN_CFG, 967 967 BD79124_MSK_STATS_EN); 968 968 if (ret)

+1

drivers/iio/adc/sd_adc_modulator.c

reviewed

··· 77 77 static const struct iio_backend_info sd_backend_info = { 78 78 .name = "sd-modulator", 79 79 .ops = &sd_backend_ops, 80 80 + .caps = IIO_BACKEND_CAP_ENABLE, 80 81 }; 81 82 82 83 static int iio_sd_mod_register(struct platform_device *pdev)

+1 -1

drivers/iio/adc/spear_adc.c

reviewed

··· 82 82 * of register writes, then a wait for a completion callback, 83 83 * and finally a register read, during which userspace could issue 84 84 * another read request. This lock protects a read access from 85 85 - * ocurring before another one has finished. 85 85 + * occurring before another one has finished. 86 86 */ 87 87 struct mutex lock; 88 88 u32 current_clk;

+1 -1

drivers/iio/adc/stm32-adc-core.c

reviewed

··· 227 227 if (priv->aclk) { 228 228 /* 229 229 * Asynchronous clock modes (e.g. ckmode == 0) 230 230 - * From spec: PLL output musn't exceed max rate 230 230 + * From spec: PLL output mustn't exceed max rate 231 231 */ 232 232 rate = clk_get_rate(priv->aclk); 233 233 if (!rate) {

+1 -1

drivers/iio/adc/stm32-adc.c

reviewed

··· 1662 1662 /* 1663 1663 * Clear ovr bit to avoid subsequent calls to IRQ handler. 1664 1664 * This requires to stop ADC first. OVR bit state in ISR, 1665 1665 - * is propaged to CSR register by hardware. 1665 1665 + * is propagated to CSR register by hardware. 1666 1666 */ 1667 1667 adc->cfg->stop_conv(indio_dev); 1668 1668 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask);

+1 -1

drivers/iio/adc/sun20i-gpadc-iio.c

reviewed

··· 55 55 * of register writes, then a wait for a completion callback, 56 56 * and finally a register read, during which userspace could issue 57 57 * another read request. This lock protects a read access from 58 58 - * ocurring before another one has finished. 58 58 + * occurring before another one has finished. 59 59 */ 60 60 struct mutex lock; 61 61 };

-1

drivers/iio/adc/ti-ads1015.c

reviewed

··· 231 231 } 232 232 233 233 struct ads1015_channel_data { 234 234 - bool enabled; 235 234 unsigned int pga; 236 235 unsigned int data_rate; 237 236 };

+1 -2

drivers/iio/adc/ti-ads1119.c

reviewed

··· 740 740 NULL, IRQF_ONESHOT, 741 741 "ads1119", indio_dev); 742 742 if (ret) 743 743 - return dev_err_probe(dev, ret, 744 744 - "Failed to allocate irq\n"); 743 743 + return ret; 745 744 746 745 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 747 746 indio_dev->name,

+88 -95

drivers/iio/adc/ti-ads7950.c

reviewed

··· 47 47 #define TI_ADS7950_MAX_CHAN 16 48 48 #define TI_ADS7950_NUM_GPIOS 4 49 49 50 50 - #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16)) 51 51 - 52 50 /* val = value, dec = left shift, bits = number of bits of the mask */ 53 51 #define TI_ADS7950_EXTRACT(val, dec, bits) \ 54 52 (((val) >> (dec)) & ((1 << (bits)) - 1)) ··· 103 105 * DMA (thus cache coherency maintenance) may require the 104 106 * transfer buffers to live in their own cache lines. 105 107 */ 106 106 - u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE] 107 107 - __aligned(IIO_DMA_MINALIGN); 108 108 + u16 rx_buf[TI_ADS7950_MAX_CHAN + 2] __aligned(IIO_DMA_MINALIGN); 108 109 u16 tx_buf[TI_ADS7950_MAX_CHAN + 2]; 109 110 u16 single_tx; 110 111 u16 single_rx; ··· 113 116 struct ti_ads7950_chip_info { 114 117 const struct iio_chan_spec *channels; 115 118 unsigned int num_channels; 116 116 - }; 117 117 - 118 118 - enum ti_ads7950_id { 119 119 - TI_ADS7950, 120 120 - TI_ADS7951, 121 121 - TI_ADS7952, 122 122 - TI_ADS7953, 123 123 - TI_ADS7954, 124 124 - TI_ADS7955, 125 125 - TI_ADS7956, 126 126 - TI_ADS7957, 127 127 - TI_ADS7958, 128 128 - TI_ADS7959, 129 129 - TI_ADS7960, 130 130 - TI_ADS7961, 131 119 }; 132 120 133 121 #define TI_ADS7950_V_CHAN(index, bits) \ ··· 207 225 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8); 208 226 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8); 209 227 210 210 - static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = { 211 211 - [TI_ADS7950] = { 212 212 - .channels = ti_ads7950_channels, 213 213 - .num_channels = ARRAY_SIZE(ti_ads7950_channels), 214 214 - }, 215 215 - [TI_ADS7951] = { 216 216 - .channels = ti_ads7951_channels, 217 217 - .num_channels = ARRAY_SIZE(ti_ads7951_channels), 218 218 - }, 219 219 - [TI_ADS7952] = { 220 220 - .channels = ti_ads7952_channels, 221 221 - .num_channels = ARRAY_SIZE(ti_ads7952_channels), 222 222 - }, 223 223 - [TI_ADS7953] = { 224 224 - .channels = ti_ads7953_channels, 225 225 - .num_channels = ARRAY_SIZE(ti_ads7953_channels), 226 226 - }, 227 227 - [TI_ADS7954] = { 228 228 - .channels = ti_ads7954_channels, 229 229 - .num_channels = ARRAY_SIZE(ti_ads7954_channels), 230 230 - }, 231 231 - [TI_ADS7955] = { 232 232 - .channels = ti_ads7955_channels, 233 233 - .num_channels = ARRAY_SIZE(ti_ads7955_channels), 234 234 - }, 235 235 - [TI_ADS7956] = { 236 236 - .channels = ti_ads7956_channels, 237 237 - .num_channels = ARRAY_SIZE(ti_ads7956_channels), 238 238 - }, 239 239 - [TI_ADS7957] = { 240 240 - .channels = ti_ads7957_channels, 241 241 - .num_channels = ARRAY_SIZE(ti_ads7957_channels), 242 242 - }, 243 243 - [TI_ADS7958] = { 244 244 - .channels = ti_ads7958_channels, 245 245 - .num_channels = ARRAY_SIZE(ti_ads7958_channels), 246 246 - }, 247 247 - [TI_ADS7959] = { 248 248 - .channels = ti_ads7959_channels, 249 249 - .num_channels = ARRAY_SIZE(ti_ads7959_channels), 250 250 - }, 251 251 - [TI_ADS7960] = { 252 252 - .channels = ti_ads7960_channels, 253 253 - .num_channels = ARRAY_SIZE(ti_ads7960_channels), 254 254 - }, 255 255 - [TI_ADS7961] = { 256 256 - .channels = ti_ads7961_channels, 257 257 - .num_channels = ARRAY_SIZE(ti_ads7961_channels), 258 258 - }, 228 228 + static const struct ti_ads7950_chip_info ti_ads7950_chip_info = { 229 229 + .channels = ti_ads7950_channels, 230 230 + .num_channels = ARRAY_SIZE(ti_ads7950_channels), 231 231 + }; 232 232 + 233 233 + static const struct ti_ads7950_chip_info ti_ads7951_chip_info = { 234 234 + .channels = ti_ads7951_channels, 235 235 + .num_channels = ARRAY_SIZE(ti_ads7951_channels), 236 236 + }; 237 237 + 238 238 + static const struct ti_ads7950_chip_info ti_ads7952_chip_info = { 239 239 + .channels = ti_ads7952_channels, 240 240 + .num_channels = ARRAY_SIZE(ti_ads7952_channels), 241 241 + }; 242 242 + 243 243 + static const struct ti_ads7950_chip_info ti_ads7953_chip_info = { 244 244 + .channels = ti_ads7953_channels, 245 245 + .num_channels = ARRAY_SIZE(ti_ads7953_channels), 246 246 + }; 247 247 + 248 248 + static const struct ti_ads7950_chip_info ti_ads7954_chip_info = { 249 249 + .channels = ti_ads7954_channels, 250 250 + .num_channels = ARRAY_SIZE(ti_ads7954_channels), 251 251 + }; 252 252 + 253 253 + static const struct ti_ads7950_chip_info ti_ads7955_chip_info = { 254 254 + .channels = ti_ads7955_channels, 255 255 + .num_channels = ARRAY_SIZE(ti_ads7955_channels), 256 256 + }; 257 257 + 258 258 + static const struct ti_ads7950_chip_info ti_ads7956_chip_info = { 259 259 + .channels = ti_ads7956_channels, 260 260 + .num_channels = ARRAY_SIZE(ti_ads7956_channels), 261 261 + }; 262 262 + 263 263 + static const struct ti_ads7950_chip_info ti_ads7957_chip_info = { 264 264 + .channels = ti_ads7957_channels, 265 265 + .num_channels = ARRAY_SIZE(ti_ads7957_channels), 266 266 + }; 267 267 + 268 268 + static const struct ti_ads7950_chip_info ti_ads7958_chip_info = { 269 269 + .channels = ti_ads7958_channels, 270 270 + .num_channels = ARRAY_SIZE(ti_ads7958_channels), 271 271 + }; 272 272 + 273 273 + static const struct ti_ads7950_chip_info ti_ads7959_chip_info = { 274 274 + .channels = ti_ads7959_channels, 275 275 + .num_channels = ARRAY_SIZE(ti_ads7959_channels), 276 276 + }; 277 277 + 278 278 + static const struct ti_ads7950_chip_info ti_ads7960_chip_info = { 279 279 + .channels = ti_ads7960_channels, 280 280 + .num_channels = ARRAY_SIZE(ti_ads7960_channels), 281 281 + }; 282 282 + 283 283 + static const struct ti_ads7950_chip_info ti_ads7961_chip_info = { 284 284 + .channels = ti_ads7961_channels, 285 285 + .num_channels = ARRAY_SIZE(ti_ads7961_channels), 259 286 }; 260 287 261 288 /* ··· 304 313 if (ret < 0) 305 314 goto out; 306 315 307 307 - iio_push_to_buffers_with_timestamp(indio_dev, &st->rx_buf[2], 308 308 - iio_get_time_ns(indio_dev)); 316 316 + iio_push_to_buffers_with_ts_unaligned(indio_dev, &st->rx_buf[2], 317 317 + sizeof(*st->rx_buf) * 318 318 + TI_ADS7950_MAX_CHAN, 319 319 + iio_get_time_ns(indio_dev)); 309 320 310 321 out: 311 322 mutex_unlock(&st->slock); ··· 554 561 555 562 st->spi = spi; 556 563 557 557 - info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data]; 564 564 + info = spi_get_device_match_data(spi); 558 565 559 566 indio_dev->name = spi_get_device_id(spi)->name; 560 567 indio_dev->modes = INDIO_DIRECT_MODE; ··· 676 683 } 677 684 678 685 static const struct spi_device_id ti_ads7950_id[] = { 679 679 - { "ads7950", TI_ADS7950 }, 680 680 - { "ads7951", TI_ADS7951 }, 681 681 - { "ads7952", TI_ADS7952 }, 682 682 - { "ads7953", TI_ADS7953 }, 683 683 - { "ads7954", TI_ADS7954 }, 684 684 - { "ads7955", TI_ADS7955 }, 685 685 - { "ads7956", TI_ADS7956 }, 686 686 - { "ads7957", TI_ADS7957 }, 687 687 - { "ads7958", TI_ADS7958 }, 688 688 - { "ads7959", TI_ADS7959 }, 689 689 - { "ads7960", TI_ADS7960 }, 690 690 - { "ads7961", TI_ADS7961 }, 686 686 + { "ads7950", (kernel_ulong_t)&ti_ads7950_chip_info }, 687 687 + { "ads7951", (kernel_ulong_t)&ti_ads7951_chip_info }, 688 688 + { "ads7952", (kernel_ulong_t)&ti_ads7952_chip_info }, 689 689 + { "ads7953", (kernel_ulong_t)&ti_ads7953_chip_info }, 690 690 + { "ads7954", (kernel_ulong_t)&ti_ads7954_chip_info }, 691 691 + { "ads7955", (kernel_ulong_t)&ti_ads7955_chip_info }, 692 692 + { "ads7956", (kernel_ulong_t)&ti_ads7956_chip_info }, 693 693 + { "ads7957", (kernel_ulong_t)&ti_ads7957_chip_info }, 694 694 + { "ads7958", (kernel_ulong_t)&ti_ads7958_chip_info }, 695 695 + { "ads7959", (kernel_ulong_t)&ti_ads7959_chip_info }, 696 696 + { "ads7960", (kernel_ulong_t)&ti_ads7960_chip_info }, 697 697 + { "ads7961", (kernel_ulong_t)&ti_ads7961_chip_info }, 691 698 { } 692 699 }; 693 700 MODULE_DEVICE_TABLE(spi, ti_ads7950_id); 694 701 695 702 static const struct of_device_id ads7950_of_table[] = { 696 696 - { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] }, 697 697 - { .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] }, 698 698 - { .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] }, 699 699 - { .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] }, 700 700 - { .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] }, 701 701 - { .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] }, 702 702 - { .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] }, 703 703 - { .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] }, 704 704 - { .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] }, 705 705 - { .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] }, 706 706 - { .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] }, 707 707 - { .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] }, 703 703 + { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info }, 704 704 + { .compatible = "ti,ads7951", .data = &ti_ads7951_chip_info }, 705 705 + { .compatible = "ti,ads7952", .data = &ti_ads7952_chip_info }, 706 706 + { .compatible = "ti,ads7953", .data = &ti_ads7953_chip_info }, 707 707 + { .compatible = "ti,ads7954", .data = &ti_ads7954_chip_info }, 708 708 + { .compatible = "ti,ads7955", .data = &ti_ads7955_chip_info }, 709 709 + { .compatible = "ti,ads7956", .data = &ti_ads7956_chip_info }, 710 710 + { .compatible = "ti,ads7957", .data = &ti_ads7957_chip_info }, 711 711 + { .compatible = "ti,ads7958", .data = &ti_ads7958_chip_info }, 712 712 + { .compatible = "ti,ads7959", .data = &ti_ads7959_chip_info }, 713 713 + { .compatible = "ti,ads7960", .data = &ti_ads7960_chip_info }, 714 714 + { .compatible = "ti,ads7961", .data = &ti_ads7961_chip_info }, 708 715 { } 709 716 }; 710 717 MODULE_DEVICE_TABLE(of, ads7950_of_table);

+3 -3

drivers/iio/adc/ti_am335x_adc.c

reviewed

··· 113 113 * There are 16 configurable steps and 8 analog input 114 114 * lines available which are shared between Touchscreen and ADC. 115 115 * 116 116 - * Steps forwards i.e. from 0 towards 16 are used by ADC 117 117 - * depending on number of input lines needed. 116 116 + * Steps forward, i.e. from 0 towards 16, are used by ADC 117 117 + * depending on the number of input lines needed. 118 118 * Channel would represent which analog input 119 119 - * needs to be given to ADC to digitalize data. 119 119 + * needs to be given to ADC to digitize data. 120 120 */ 121 121 for (i = 0; i < adc_dev->channels; i++) { 122 122 int chan;

+1 -1

drivers/iio/adc/twl4030-madc.c

reviewed

··· 252 252 {5, 11}, /* CHANNEL 15 */ 253 253 }; 254 254 255 255 - /* Conversion table from -3 to 55 degrees Celcius */ 255 255 + /* Conversion table from -3 to 55 degrees Celsius */ 256 256 static int twl4030_therm_tbl[] = { 257 257 30800, 29500, 28300, 27100, 258 258 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700,

+1 -1

drivers/iio/adc/twl6030-gpadc.c

reviewed

··· 416 416 { 417 417 /* 418 418 * for any prior chosen channel, when the conversion is ready 419 419 - * the result is avalable in GPCH0_LSB, GPCH0_MSB. 419 419 + * the result is available in GPCH0_LSB, GPCH0_MSB. 420 420 */ 421 421 422 422 return TWL6032_GPADC_GPCH0_LSB;

+3 -6

drivers/iio/addac/ad74413r.c

reviewed

··· 839 839 if (ret) 840 840 return ret; 841 841 842 842 - ret = wait_for_completion_timeout(&st->adc_data_completion, 843 843 - msecs_to_jiffies(1000)); 844 844 - if (!ret) { 845 845 - ret = -ETIMEDOUT; 846 846 - return ret; 847 847 - } 842 842 + if (!wait_for_completion_timeout(&st->adc_data_completion, 843 843 + msecs_to_jiffies(1000))) 844 844 + return -ETIMEDOUT; 848 845 849 846 ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel), 850 847 &uval);

+8

drivers/iio/amplifiers/Kconfig

reviewed

··· 18 18 AD8366 Dual-Digital Variable Gain Amplifier (VGA) 19 19 ADA4961 BiCMOS RF Digital Gain Amplifier (DGA) 20 20 ADL5240 Digitally controlled variable gain amplifier (VGA) 21 21 + ADRF5702: 0.125 dB LSB, 8-Bit, Silicon Digital Attenuator 22 22 + ADRF5703: 0.25 dB LSB, 7-Bit, Silicon Digital Attenuator 23 23 + ADRF5720: 0.5 dB LSB, 6-Bit, Silicon Digital Attenuator 24 24 + ADRF5730: 0.5 dB LSB, 6-Bit, Silicon Digital Attenuator 25 25 + ADRF5731: 2 dB LSB, 4-Bit, Silicon Digital Attenuator 26 26 + HMC271A: 1dB LSB 5-Bit Digital Attenuator SMT 21 27 HMC792A 0.25 dB LSB GaAs MMIC 6-Bit Digital Attenuator 28 28 + HMC1018A: 1.0 dB LSB GaAs MMIC 5-BIT Digital Attenuator 29 29 + HMC1019A: 0.5 dB LSB GaAs MMIC 5-BIT Digital Attenuator 22 30 HMC1119 0.25 dB LSB, 7-Bit, Silicon Digital Attenuator 23 31 24 32 To compile this driver as a module, choose M here: the

+231 -178

drivers/iio/amplifiers/ad8366.c

reviewed

··· 5 5 * AD8366 Dual-Digital Variable Gain Amplifier (VGA) 6 6 * ADA4961 BiCMOS RF Digital Gain Amplifier (DGA) 7 7 * ADL5240 Digitally controlled variable gain amplifier (VGA) 8 8 + * ADRF5702: 0.125 dB LSB, 8-Bit, Silicon Digital Attenuator, 50 MHz to 20 GHz 9 9 + * ADRF5703: 0.25 dB LSB, 7-Bit, Silicon Digital Attenuator, 9 kHz to 20 GHz 10 10 + * ADRF5720: 0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 9 kHz to 40 GHz 11 11 + * ADRF5730: 0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz 12 12 + * ADRF5731: 2 dB LSB, 4-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz 13 13 + * HMC271A: 1dB LSB 5-Bit Digital Attenuator SMT, 0.7 - 3.7 GHz 8 14 * HMC792A 0.25 dB LSB GaAs MMIC 6-Bit Digital Attenuator 15 15 + * HMC1018A: 1.0 dB LSB GaAs MMIC 5-BIT DIGITAL ATTENUATOR, 0.1 - 30 GHz 16 16 + * HMC1019A: 0.5 dB LSB GaAs MMIC 5-BIT DIGITAL ATTENUATOR, 0.1 - 30 GHz 9 17 * HMC1119 0.25 dB LSB, 7-Bit, Silicon Digital Attenuator 10 18 * 11 11 - * Copyright 2012-2019 Analog Devices Inc. 19 19 + * Copyright 2012-2026 Analog Devices Inc. 12 20 */ 13 21 14 14 - #include <linux/device.h> 15 15 - #include <linux/kernel.h> 16 16 - #include <linux/slab.h> 17 17 - #include <linux/sysfs.h> 18 18 - #include <linux/spi/spi.h> 19 19 - #include <linux/regulator/consumer.h> 20 20 - #include <linux/gpio/consumer.h> 21 21 - #include <linux/err.h> 22 22 - #include <linux/module.h> 23 22 #include <linux/bitrev.h> 23 23 + #include <linux/bits.h> 24 24 + #include <linux/dev_printk.h> 25 25 + #include <linux/err.h> 26 26 + #include <linux/gpio/consumer.h> 27 27 + #include <linux/math.h> 28 28 + #include <linux/minmax.h> 29 29 + #include <linux/mod_devicetable.h> 30 30 + #include <linux/module.h> 31 31 + #include <linux/mutex.h> 32 32 + #include <linux/regulator/consumer.h> 33 33 + #include <linux/reset.h> 34 34 + #include <linux/spi/spi.h> 35 35 + #include <linux/types.h> 36 36 + #include <linux/unaligned.h> 24 37 25 38 #include <linux/iio/iio.h> 26 26 - #include <linux/iio/sysfs.h> 27 27 - 28 28 - enum ad8366_type { 29 29 - ID_AD8366, 30 30 - ID_ADA4961, 31 31 - ID_ADL5240, 32 32 - ID_HMC792, 33 33 - ID_HMC1119, 34 34 - }; 35 39 36 40 struct ad8366_info { 41 41 + const char *name; 37 42 int gain_min; 38 43 int gain_max; 44 44 + int gain_step; 45 45 + size_t num_channels; 46 46 + size_t (*pack_code)(const unsigned char *code, size_t num_channels, 47 47 + unsigned char *data); 39 48 }; 40 49 41 50 struct ad8366_state { 42 51 struct spi_device *spi; 43 43 - struct regulator *reg; 44 52 struct mutex lock; /* protect sensor state */ 45 45 - struct gpio_desc *reset_gpio; 46 53 unsigned char ch[2]; 47 47 - enum ad8366_type type; 48 54 const struct ad8366_info *info; 49 55 /* 50 56 * DMA (thus cache coherency maintenance) may require the ··· 59 53 unsigned char data[2] __aligned(IIO_DMA_MINALIGN); 60 54 }; 61 55 62 62 - static const struct ad8366_info ad8366_infos[] = { 63 63 - [ID_AD8366] = { 64 64 - .gain_min = 4500, 65 65 - .gain_max = 20500, 66 66 - }, 67 67 - [ID_ADA4961] = { 68 68 - .gain_min = -6000, 69 69 - .gain_max = 15000, 70 70 - }, 71 71 - [ID_ADL5240] = { 72 72 - .gain_min = -11500, 73 73 - .gain_max = 20000, 74 74 - }, 75 75 - [ID_HMC792] = { 76 76 - .gain_min = -15750, 77 77 - .gain_max = 0, 78 78 - }, 79 79 - [ID_HMC1119] = { 80 80 - .gain_min = -31750, 81 81 - .gain_max = 0, 82 82 - }, 56 56 + static size_t ad8366_pack_code(const unsigned char *code, size_t num_channels, 57 57 + unsigned char *data) 58 58 + { 59 59 + u8 ch_a = bitrev8(code[0]) >> 2; 60 60 + u8 ch_b = bitrev8(code[1]) >> 2; 61 61 + 62 62 + put_unaligned_be16((ch_b << 6) | ch_a, &data[0]); 63 63 + return sizeof(__be16); 64 64 + } 65 65 + 66 66 + static size_t adrf5731_pack_code(const unsigned char *code, size_t num_channels, 67 67 + unsigned char *data) 68 68 + { 69 69 + data[0] = code[0] << 2; 70 70 + return 1; 71 71 + } 72 72 + 73 73 + static size_t hmc271_pack_code(const unsigned char *code, size_t num_channels, 74 74 + unsigned char *data) 75 75 + { 76 76 + data[0] = bitrev8(code[0]) >> 3; 77 77 + return 1; 78 78 + } 79 79 + 80 80 + static const struct ad8366_info ad8366_chip_info = { 81 81 + .name = "ad8366", 82 82 + .gain_min = 4500, 83 83 + .gain_max = 20500, 84 84 + .gain_step = 253, 85 85 + .num_channels = 2, 86 86 + .pack_code = ad8366_pack_code, 83 87 }; 84 88 85 85 - static int ad8366_write(struct iio_dev *indio_dev, 86 86 - unsigned char ch_a, unsigned char ch_b) 89 89 + static const struct ad8366_info ada4961_chip_info = { 90 90 + .name = "ada4961", 91 91 + .gain_min = -6000, 92 92 + .gain_max = 15000, 93 93 + .gain_step = -1000, 94 94 + .num_channels = 1, 95 95 + }; 96 96 + 97 97 + static const struct ad8366_info adl5240_chip_info = { 98 98 + .name = "adl5240", 99 99 + .gain_min = -11500, 100 100 + .gain_max = 20000, 101 101 + .gain_step = 500, 102 102 + .num_channels = 1, 103 103 + }; 104 104 + 105 105 + static const struct ad8366_info adrf5702_chip_info = { 106 106 + .name = "adrf5702", 107 107 + .gain_min = -31875, 108 108 + .gain_max = 0, 109 109 + .gain_step = -125, 110 110 + .num_channels = 1, 111 111 + }; 112 112 + 113 113 + static const struct ad8366_info adrf5703_chip_info = { 114 114 + .name = "adrf5703", 115 115 + .gain_min = -31750, 116 116 + .gain_max = 0, 117 117 + .gain_step = -250, 118 118 + .num_channels = 1, 119 119 + }; 120 120 + 121 121 + static const struct ad8366_info adrf5720_chip_info = { 122 122 + .name = "adrf5720", 123 123 + .gain_min = -31500, 124 124 + .gain_max = 0, 125 125 + .gain_step = -500, 126 126 + .num_channels = 1, 127 127 + }; 128 128 + 129 129 + static const struct ad8366_info adrf5730_chip_info = { 130 130 + .name = "adrf5730", 131 131 + .gain_min = -31500, 132 132 + .gain_max = 0, 133 133 + .gain_step = -500, 134 134 + .num_channels = 1, 135 135 + }; 136 136 + 137 137 + static const struct ad8366_info adrf5731_chip_info = { 138 138 + .name = "adrf5731", 139 139 + .gain_min = -30000, 140 140 + .gain_max = 0, 141 141 + .gain_step = -2000, 142 142 + .num_channels = 1, 143 143 + .pack_code = adrf5731_pack_code, 144 144 + }; 145 145 + 146 146 + static const struct ad8366_info hmc271_chip_info = { 147 147 + .name = "hmc271a", 148 148 + .gain_min = -31000, 149 149 + .gain_max = 0, 150 150 + .gain_step = 1000, 151 151 + .num_channels = 1, 152 152 + .pack_code = hmc271_pack_code, 153 153 + }; 154 154 + 155 155 + static const struct ad8366_info hmc792_chip_info = { 156 156 + .name = "hmc792a", 157 157 + .gain_min = -15750, 158 158 + .gain_max = 0, 159 159 + .gain_step = 250, 160 160 + .num_channels = 1, 161 161 + }; 162 162 + 163 163 + static const struct ad8366_info hmc1018_chip_info = { 164 164 + .name = "hmc1018a", 165 165 + .gain_min = -31000, 166 166 + .gain_max = 0, 167 167 + .gain_step = 1000, 168 168 + .num_channels = 1, 169 169 + }; 170 170 + 171 171 + static const struct ad8366_info hmc1019_chip_info = { 172 172 + .name = "hmc1019a", 173 173 + .gain_min = -15500, 174 174 + .gain_max = 0, 175 175 + .gain_step = 500, 176 176 + .num_channels = 1, 177 177 + }; 178 178 + 179 179 + static const struct ad8366_info hmc1119_chip_info = { 180 180 + .name = "hmc1119", 181 181 + .gain_min = -31750, 182 182 + .gain_max = 0, 183 183 + .gain_step = -250, 184 184 + .num_channels = 1, 185 185 + }; 186 186 + 187 187 + static int ad8366_write_code(struct ad8366_state *st) 87 188 { 88 88 - struct ad8366_state *st = iio_priv(indio_dev); 89 89 - int ret; 189 189 + const struct ad8366_info *inf = st->info; 190 190 + size_t len = 1; 90 191 91 91 - switch (st->type) { 92 92 - case ID_AD8366: 93 93 - ch_a = bitrev8(ch_a & 0x3F); 94 94 - ch_b = bitrev8(ch_b & 0x3F); 192 192 + if (inf->pack_code) 193 193 + len = inf->pack_code(st->ch, inf->num_channels, st->data); 194 194 + else 195 195 + st->data[0] = st->ch[0]; 95 196 96 96 - st->data[0] = ch_b >> 4; 97 97 - st->data[1] = (ch_b << 4) | (ch_a >> 2); 98 98 - break; 99 99 - case ID_ADA4961: 100 100 - st->data[0] = ch_a & 0x1F; 101 101 - break; 102 102 - case ID_ADL5240: 103 103 - st->data[0] = (ch_a & 0x3F); 104 104 - break; 105 105 - case ID_HMC792: 106 106 - case ID_HMC1119: 107 107 - st->data[0] = ch_a; 108 108 - break; 109 109 - } 110 110 - 111 111 - ret = spi_write(st->spi, st->data, indio_dev->num_channels); 112 112 - if (ret < 0) 113 113 - dev_err(&indio_dev->dev, "write failed (%d)", ret); 114 114 - 115 115 - return ret; 197 197 + return spi_write(st->spi, st->data, len); 116 198 } 117 199 118 200 static int ad8366_read_raw(struct iio_dev *indio_dev, ··· 210 116 long m) 211 117 { 212 118 struct ad8366_state *st = iio_priv(indio_dev); 119 119 + const struct ad8366_info *inf = st->info; 213 120 int ret; 214 121 int code, gain = 0; 215 122 ··· 218 123 switch (m) { 219 124 case IIO_CHAN_INFO_HARDWAREGAIN: 220 125 code = st->ch[chan->channel]; 221 221 - 222 222 - switch (st->type) { 223 223 - case ID_AD8366: 224 224 - gain = code * 253 + 4500; 225 225 - break; 226 226 - case ID_ADA4961: 227 227 - gain = 15000 - code * 1000; 228 228 - break; 229 229 - case ID_ADL5240: 230 230 - gain = 20000 - 31500 + code * 500; 231 231 - break; 232 232 - case ID_HMC792: 233 233 - gain = -1 * code * 500; 234 234 - break; 235 235 - case ID_HMC1119: 236 236 - gain = -1 * code * 250; 237 237 - break; 238 238 - } 239 239 - 126 126 + gain = inf->gain_step > 0 ? inf->gain_min : inf->gain_max; 127 127 + gain += inf->gain_step * code; 240 128 /* Values in dB */ 241 129 *val = gain / 1000; 242 130 *val2 = (gain % 1000) * 1000; ··· 254 176 if (gain > inf->gain_max || gain < inf->gain_min) 255 177 return -EINVAL; 256 178 257 257 - switch (st->type) { 258 258 - case ID_AD8366: 259 259 - code = (gain - 4500) / 253; 260 260 - break; 261 261 - case ID_ADA4961: 262 262 - code = (15000 - gain) / 1000; 263 263 - break; 264 264 - case ID_ADL5240: 265 265 - code = ((gain - 500 - 20000) / 500) & 0x3F; 266 266 - break; 267 267 - case ID_HMC792: 268 268 - code = (abs(gain) / 500) & 0x3F; 269 269 - break; 270 270 - case ID_HMC1119: 271 271 - code = (abs(gain) / 250) & 0x7F; 272 272 - break; 273 273 - } 179 179 + gain -= inf->gain_step > 0 ? inf->gain_min : inf->gain_max; 180 180 + code = DIV_ROUND_CLOSEST(gain, inf->gain_step); 274 181 275 182 mutex_lock(&st->lock); 276 183 switch (mask) { 277 184 case IIO_CHAN_INFO_HARDWAREGAIN: 278 185 st->ch[chan->channel] = code; 279 279 - ret = ad8366_write(indio_dev, st->ch[0], st->ch[1]); 186 186 + ret = ad8366_write_code(st); 280 187 break; 281 188 default: 282 189 ret = -EINVAL; ··· 302 239 AD8366_CHAN(1), 303 240 }; 304 241 305 305 - static const struct iio_chan_spec ada4961_channels[] = { 306 306 - AD8366_CHAN(0), 307 307 - }; 308 308 - 309 242 static int ad8366_probe(struct spi_device *spi) 310 243 { 244 244 + struct device *dev = &spi->dev; 245 245 + struct gpio_desc *enable_gpio; 246 246 + struct reset_control *rstc; 311 247 struct iio_dev *indio_dev; 312 248 struct ad8366_state *st; 313 249 int ret; 314 250 315 315 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 251 251 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 316 252 if (indio_dev == NULL) 317 253 return -ENOMEM; 318 254 319 255 st = iio_priv(indio_dev); 320 256 321 321 - st->reg = devm_regulator_get(&spi->dev, "vcc"); 322 322 - if (!IS_ERR(st->reg)) { 323 323 - ret = regulator_enable(st->reg); 324 324 - if (ret) 325 325 - return ret; 326 326 - } 257 257 + ret = devm_mutex_init(dev, &st->lock); 258 258 + if (ret) 259 259 + return ret; 327 260 328 328 - spi_set_drvdata(spi, indio_dev); 329 329 - mutex_init(&st->lock); 261 261 + ret = devm_regulator_get_enable(dev, "vcc"); 262 262 + if (ret) 263 263 + return dev_err_probe(dev, ret, "Failed to get regulator\n"); 264 264 + 330 265 st->spi = spi; 331 331 - st->type = spi_get_device_id(spi)->driver_data; 266 266 + st->info = spi_get_device_match_data(spi); 332 267 333 333 - switch (st->type) { 334 334 - case ID_AD8366: 335 335 - indio_dev->channels = ad8366_channels; 336 336 - indio_dev->num_channels = ARRAY_SIZE(ad8366_channels); 337 337 - break; 338 338 - case ID_ADA4961: 339 339 - case ID_ADL5240: 340 340 - case ID_HMC792: 341 341 - case ID_HMC1119: 342 342 - st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_HIGH); 343 343 - if (IS_ERR(st->reset_gpio)) { 344 344 - ret = PTR_ERR(st->reset_gpio); 345 345 - goto error_disable_reg; 346 346 - } 347 347 - indio_dev->channels = ada4961_channels; 348 348 - indio_dev->num_channels = ARRAY_SIZE(ada4961_channels); 349 349 - break; 350 350 - default: 351 351 - dev_err(&spi->dev, "Invalid device ID\n"); 352 352 - ret = -EINVAL; 353 353 - goto error_disable_reg; 354 354 - } 268 268 + enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); 269 269 + if (IS_ERR(enable_gpio)) 270 270 + return dev_err_probe(dev, PTR_ERR(enable_gpio), 271 271 + "Failed to get enable GPIO\n"); 355 272 356 356 - st->info = &ad8366_infos[st->type]; 357 357 - indio_dev->name = spi_get_device_id(spi)->name; 273 273 + rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); 274 274 + if (IS_ERR(rstc)) 275 275 + return dev_err_probe(dev, PTR_ERR(rstc), 276 276 + "Failed to get reset controller\n"); 277 277 + 278 278 + indio_dev->name = st->info->name; 358 279 indio_dev->info = &ad8366_info; 359 280 indio_dev->modes = INDIO_DIRECT_MODE; 281 281 + indio_dev->channels = ad8366_channels; 282 282 + indio_dev->num_channels = st->info->num_channels; 360 283 361 361 - ret = ad8366_write(indio_dev, 0, 0); 284 284 + ret = ad8366_write_code(st); 362 285 if (ret < 0) 363 363 - goto error_disable_reg; 286 286 + return dev_err_probe(dev, ret, "failed to write initial gain\n"); 364 287 365 365 - ret = iio_device_register(indio_dev); 366 366 - if (ret) 367 367 - goto error_disable_reg; 368 368 - 369 369 - return 0; 370 370 - 371 371 - error_disable_reg: 372 372 - if (!IS_ERR(st->reg)) 373 373 - regulator_disable(st->reg); 374 374 - 375 375 - return ret; 376 376 - } 377 377 - 378 378 - static void ad8366_remove(struct spi_device *spi) 379 379 - { 380 380 - struct iio_dev *indio_dev = spi_get_drvdata(spi); 381 381 - struct ad8366_state *st = iio_priv(indio_dev); 382 382 - struct regulator *reg = st->reg; 383 383 - 384 384 - iio_device_unregister(indio_dev); 385 385 - 386 386 - if (!IS_ERR(reg)) 387 387 - regulator_disable(reg); 288 288 + return devm_iio_device_register(dev, indio_dev); 388 289 } 389 290 390 291 static const struct spi_device_id ad8366_id[] = { 391 391 - {"ad8366", ID_AD8366}, 392 392 - {"ada4961", ID_ADA4961}, 393 393 - {"adl5240", ID_ADL5240}, 394 394 - {"hmc792a", ID_HMC792}, 395 395 - {"hmc1119", ID_HMC1119}, 292 292 + { "ad8366", (kernel_ulong_t)&ad8366_chip_info }, 293 293 + { "ada4961", (kernel_ulong_t)&ada4961_chip_info }, 294 294 + { "adl5240", (kernel_ulong_t)&adl5240_chip_info }, 295 295 + { "adrf5702", (kernel_ulong_t)&adrf5702_chip_info }, 296 296 + { "adrf5703", (kernel_ulong_t)&adrf5703_chip_info }, 297 297 + { "adrf5720", (kernel_ulong_t)&adrf5720_chip_info }, 298 298 + { "adrf5730", (kernel_ulong_t)&adrf5730_chip_info }, 299 299 + { "adrf5731", (kernel_ulong_t)&adrf5731_chip_info }, 300 300 + { "hmc271a", (kernel_ulong_t)&hmc271_chip_info }, 301 301 + { "hmc792a", (kernel_ulong_t)&hmc792_chip_info }, 302 302 + { "hmc1018a", (kernel_ulong_t)&hmc1018_chip_info }, 303 303 + { "hmc1019a", (kernel_ulong_t)&hmc1019_chip_info }, 304 304 + { "hmc1119", (kernel_ulong_t)&hmc1119_chip_info }, 396 305 { } 397 306 }; 398 307 MODULE_DEVICE_TABLE(spi, ad8366_id); 399 308 309 309 + static const struct of_device_id ad8366_of_match[] = { 310 310 + { .compatible = "adi,ad8366", .data = &ad8366_chip_info }, 311 311 + { .compatible = "adi,ada4961", .data = &ada4961_chip_info }, 312 312 + { .compatible = "adi,adl5240", .data = &adl5240_chip_info }, 313 313 + { .compatible = "adi,adrf5702", .data = &adrf5702_chip_info }, 314 314 + { .compatible = "adi,adrf5703", .data = &adrf5703_chip_info }, 315 315 + { .compatible = "adi,adrf5720", .data = &adrf5720_chip_info }, 316 316 + { .compatible = "adi,adrf5730", .data = &adrf5730_chip_info }, 317 317 + { .compatible = "adi,adrf5731", .data = &adrf5731_chip_info }, 318 318 + { .compatible = "adi,hmc271a", .data = &hmc271_chip_info }, 319 319 + { .compatible = "adi,hmc792a", .data = &hmc792_chip_info }, 320 320 + { .compatible = "adi,hmc1018a", .data = &hmc1018_chip_info }, 321 321 + { .compatible = "adi,hmc1019a", .data = &hmc1019_chip_info }, 322 322 + { .compatible = "adi,hmc1119", .data = &hmc1119_chip_info }, 323 323 + { } 324 324 + }; 325 325 + MODULE_DEVICE_TABLE(of, ad8366_of_match); 326 326 + 400 327 static struct spi_driver ad8366_driver = { 401 328 .driver = { 402 402 - .name = KBUILD_MODNAME, 329 329 + .name = KBUILD_MODNAME, 330 330 + .of_match_table = ad8366_of_match, 403 331 }, 404 332 .probe = ad8366_probe, 405 405 - .remove = ad8366_remove, 406 333 .id_table = ad8366_id, 407 334 }; 408 335

+1 -1

drivers/iio/amplifiers/ada4250.c

reviewed

··· 109 109 110 110 /* 111 111 * Compute Range and Voltage per LSB for the Sensor Offset Calibration 112 112 - * Example of computation for Range 1 and Range 2 (Curren Bias Set = AVDD): 112 112 + * Example of computation for Range 1 and Range 2 (Current Bias Set = AVDD): 113 113 * Range 1 Range 2 114 114 * Gain | Max Vos(mV) | LSB(mV) | Max Vos(mV) | LSB(mV) | 115 115 * 2 | X1*127 | X1=0.126(AVDD-1) | X1*3*127 | X1*3 |

+7 -4

drivers/iio/buffer/industrialio-hw-consumer.c

reviewed

··· 28 28 struct list_head head; 29 29 struct iio_dev *indio_dev; 30 30 struct iio_buffer buffer; 31 31 - long scan_mask[]; 32 31 }; 33 32 34 33 static struct hw_consumer_buffer *iio_buffer_to_hw_consumer_buffer( ··· 51 52 static struct hw_consumer_buffer *iio_hw_consumer_get_buffer( 52 53 struct iio_hw_consumer *hwc, struct iio_dev *indio_dev) 53 54 { 54 54 - unsigned int mask_longs = BITS_TO_LONGS(iio_get_masklength(indio_dev)); 55 55 struct hw_consumer_buffer *buf; 56 56 57 57 list_for_each_entry(buf, &hwc->buffers, head) { ··· 58 60 return buf; 59 61 } 60 62 61 61 - buf = kzalloc_flex(*buf, scan_mask, mask_longs); 63 63 + buf = kzalloc_obj(*buf); 62 64 if (!buf) 63 65 return NULL; 64 66 65 67 buf->buffer.access = &iio_hw_buf_access; 66 68 buf->indio_dev = indio_dev; 67 67 - buf->buffer.scan_mask = buf->scan_mask; 69 69 + buf->buffer.scan_mask = bitmap_zalloc(iio_get_masklength(indio_dev), 70 70 + GFP_KERNEL); 71 71 + if (!buf->buffer.scan_mask) { 72 72 + kfree(buf); 73 73 + return NULL; 74 74 + } 68 75 69 76 iio_buffer_init(&buf->buffer); 70 77 list_add_tail(&buf->head, &hwc->buffers);

+11 -30

drivers/iio/buffer/kfifo_buf.c

reviewed

··· 224 224 } 225 225 EXPORT_SYMBOL(iio_kfifo_free); 226 226 227 227 - static void devm_iio_kfifo_release(struct device *dev, void *res) 227 227 + static void devm_iio_kfifo_release(void *buffer) 228 228 { 229 229 - iio_kfifo_free(*(struct iio_buffer **)res); 230 230 - } 231 231 - 232 232 - /** 233 233 - * devm_iio_kfifo_allocate - Resource-managed iio_kfifo_allocate() 234 234 - * @dev: Device to allocate kfifo buffer for 235 235 - * 236 236 - * RETURNS: 237 237 - * Pointer to allocated iio_buffer on success, NULL on failure. 238 238 - */ 239 239 - static struct iio_buffer *devm_iio_kfifo_allocate(struct device *dev) 240 240 - { 241 241 - struct iio_buffer **ptr, *r; 242 242 - 243 243 - ptr = devres_alloc(devm_iio_kfifo_release, sizeof(*ptr), GFP_KERNEL); 244 244 - if (!ptr) 245 245 - return NULL; 246 246 - 247 247 - r = iio_kfifo_allocate(); 248 248 - if (r) { 249 249 - *ptr = r; 250 250 - devres_add(dev, ptr); 251 251 - } else { 252 252 - devres_free(ptr); 253 253 - } 254 254 - 255 255 - return r; 229 229 + iio_kfifo_free(buffer); 256 230 } 257 231 258 232 /** ··· 236 262 * @setup_ops: The setup_ops required to configure the HW part of the buffer (optional) 237 263 * @buffer_attrs: Extra sysfs buffer attributes for this IIO buffer 238 264 * 239 239 - * This function allocates a kfifo buffer via devm_iio_kfifo_allocate() and 265 265 + * This function allocates a kfifo buffer via iio_kfifo_allocate() and 240 266 * attaches it to the IIO device via iio_device_attach_buffer(). 241 267 * This is meant to be a bit of a short-hand/helper function as there are a few 242 268 * drivers that seem to do this. 269 269 + * 270 270 + * Return: 0 on success, negative error code on failure. 243 271 */ 244 272 int devm_iio_kfifo_buffer_setup_ext(struct device *dev, 245 273 struct iio_dev *indio_dev, ··· 249 273 const struct iio_dev_attr **buffer_attrs) 250 274 { 251 275 struct iio_buffer *buffer; 276 276 + int ret; 252 277 253 253 - buffer = devm_iio_kfifo_allocate(dev); 278 278 + buffer = iio_kfifo_allocate(); 254 279 if (!buffer) 255 280 return -ENOMEM; 281 281 + 282 282 + ret = devm_add_action_or_reset(dev, devm_iio_kfifo_release, buffer); 283 283 + if (ret) 284 284 + return ret; 256 285 257 286 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 258 287 indio_dev->setup_ops = setup_ops;

+1 -1

drivers/iio/cdc/ad7150.c

reviewed

··· 306 306 dir); 307 307 if (ret) 308 308 goto error_ret; 309 309 - /* reenable any irq's we disabled whilst changing mode */ 309 309 + /* re-enable any IRQs we disabled whilst changing mode */ 310 310 enable_irq(chip->interrupts[0]); 311 311 enable_irq(chip->interrupts[1]); 312 312 }

+1 -1

drivers/iio/cdc/ad7746.c

reviewed

··· 606 606 return ret; 607 607 608 608 /* 609 609 - * Offset applied internally becaue the _offset userspace interface is 609 609 + * Offset applied internally because the _offset userspace interface is 610 610 * needed for the CAP DACs which apply a controllable offset. 611 611 */ 612 612 *val = get_unaligned_be24(data) - 0x800000;

+1 -1

drivers/iio/chemical/bme680_core.c

reviewed

··· 807 807 adc_gas_res = FIELD_GET(BME680_ADC_GAS_RES, gas_regs_val); 808 808 809 809 /* 810 810 - * occurs if either the gas heating duration was insuffient 810 810 + * This may occur if either the gas heating duration was insufficient 811 811 * to reach the target heater temperature or the target 812 812 * heater temperature was too high for the heater sink to 813 813 * reach.

+1 -1

drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c

reviewed

··· 106 106 switch (st->core.type) { 107 107 case MOTIONSENSE_TYPE_ACCEL: 108 108 /* 109 109 - * EC returns data in g, iio exepects m/s^2. 109 109 + * EC returns data in g, IIO expects m/s^2. 110 110 * Do not use IIO_G_TO_M_S_2 to avoid precision loss. 111 111 */ 112 112 *val = div_s64(val64 * 980665, 10);

+1 -1

drivers/iio/common/hid-sensors/hid-sensor-attributes.c

reviewed

··· 346 346 EXPORT_SYMBOL_NS(hid_sensor_write_raw_hyst_rel_value, "IIO_HID"); 347 347 348 348 /* 349 349 - * This fuction applies the unit exponent to the scale. 349 349 + * This function applies the unit exponent to the scale. 350 350 * For example: 351 351 * 9.806650000 ->exp:2-> val0[980]val1[665000000] 352 352 * 9.000806000 ->exp:2-> val0[900]val1[80600000]

+2 -2

drivers/iio/common/inv_sensors/inv_sensors_timestamp.c

reviewed

··· 154 154 valid = inv_update_chip_period(ts, period); 155 155 } 156 156 157 157 - /* no previous data, compute theoritical value from interrupt */ 157 157 + /* no previous data, compute theoretical value from interrupt */ 158 158 if (ts->timestamp == 0) { 159 159 /* elapsed time: sensor period * sensor samples number */ 160 160 interval = (int64_t)ts->period * (int64_t)sample_nb; ··· 185 185 186 186 /* 187 187 * After ODR change the time interval with the previous sample is 188 188 - * undertermined (depends when the change occures). So we compute the 188 188 + * undertermined (depends when the change occurs). So we compute the 189 189 * timestamp from the current interrupt using the new FIFO period, the 190 190 * total number of samples and the current sample numero. 191 191 */

+1 -1

drivers/iio/common/ms_sensors/ms_sensors_i2c.c

reviewed

··· 96 96 * 97 97 * Generic ADC conversion & read function for Measurement Specialties 98 98 * devices. 99 99 - * The function will issue conversion command, sleep appopriate delay, and 99 99 + * The function will issue conversion command, sleep appropriate delay, and 100 100 * issue command to read ADC. 101 101 * 102 102 * Return: 0 on success, negative errno otherwise.

+3 -8

drivers/iio/common/st_sensors/st_sensors_core.c

reviewed

··· 501 501 502 502 byte_for_channel = DIV_ROUND_UP(ch->scan_type.realbits + 503 503 ch->scan_type.shift, 8); 504 504 - outdata = kmalloc(byte_for_channel, GFP_DMA | GFP_KERNEL); 505 505 - if (!outdata) 506 506 - return -ENOMEM; 504 504 + outdata = sdata->buffer_data; 507 505 508 506 err = regmap_bulk_read(sdata->regmap, ch->address, 509 507 outdata, byte_for_channel); 510 508 if (err < 0) 511 511 - goto st_sensors_free_memory; 509 509 + return err; 512 510 513 511 if (byte_for_channel == 1) 514 512 *data = (s8)*outdata; ··· 515 517 else if (byte_for_channel == 3) 516 518 *data = (s32)sign_extend32(get_unaligned_le24(outdata), 23); 517 519 518 518 - st_sensors_free_memory: 519 519 - kfree(outdata); 520 520 - 521 521 - return err; 520 520 + return 0; 522 521 } 523 522 524 523 int st_sensors_read_info_raw(struct iio_dev *indio_dev,

+1

drivers/iio/dac/Kconfig

reviewed

··· 408 408 config DS4424 409 409 tristate "Maxim Integrated DS4422/DS4424 DAC driver" 410 410 depends on I2C 411 411 + select REGMAP_I2C 411 412 help 412 413 If you say yes here you get support for Maxim chips DS4422, DS4424. 413 414

+9 -20

drivers/iio/dac/ad5360.c

reviewed

··· 206 206 static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd, 207 207 unsigned int addr, unsigned int val, unsigned int shift) 208 208 { 209 209 - int ret; 210 209 struct ad5360_state *st = iio_priv(indio_dev); 211 210 212 212 - mutex_lock(&st->lock); 213 213 - ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift); 214 214 - mutex_unlock(&st->lock); 215 215 - 216 216 - return ret; 211 211 + guard(mutex)(&st->lock); 212 212 + return ad5360_write_unlocked(indio_dev, cmd, addr, val, shift); 217 213 } 218 214 219 215 static int ad5360_read(struct iio_dev *indio_dev, unsigned int type, ··· 228 232 }, 229 233 }; 230 234 231 231 - mutex_lock(&st->lock); 235 235 + guard(mutex)(&st->lock); 232 236 233 237 st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) | 234 238 AD5360_ADDR(AD5360_REG_SF_READBACK) | ··· 236 240 AD5360_READBACK_ADDR(addr)); 237 241 238 242 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 239 239 - if (ret >= 0) 240 240 - ret = be32_to_cpu(st->data[1].d32) & 0xffff; 243 243 + if (ret < 0) 244 244 + return ret; 241 245 242 242 - mutex_unlock(&st->lock); 243 243 - 244 244 - return ret; 246 246 + return be32_to_cpu(st->data[1].d32) & 0xffff; 245 247 } 246 248 247 249 static ssize_t ad5360_read_dac_powerdown(struct device *dev, ··· 256 262 unsigned int clr) 257 263 { 258 264 struct ad5360_state *st = iio_priv(indio_dev); 259 259 - int ret; 260 265 261 261 - mutex_lock(&st->lock); 266 266 + guard(mutex)(&st->lock); 262 267 263 268 st->ctrl |= set; 264 269 st->ctrl &= ~clr; 265 270 266 266 - ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION, 267 267 - AD5360_REG_SF_CTRL, st->ctrl, 0); 268 268 - 269 269 - mutex_unlock(&st->lock); 270 270 - 271 271 - return ret; 271 271 + return ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION, 272 272 + AD5360_REG_SF_CTRL, st->ctrl, 0); 272 273 } 273 274 274 275 static ssize_t ad5360_write_dac_powerdown(struct device *dev,

+15 -16

drivers/iio/dac/ad7293.c

reviewed

··· 776 776 777 777 static int ad7293_properties_parse(struct ad7293_state *st) 778 778 { 779 779 - struct spi_device *spi = st->spi; 779 779 + struct device *dev = &st->spi->dev; 780 780 int ret; 781 781 782 782 - ret = devm_regulator_get_enable(&spi->dev, "avdd"); 782 782 + ret = devm_regulator_get_enable(dev, "avdd"); 783 783 if (ret) 784 784 - return dev_err_probe(&spi->dev, ret, "failed to enable AVDD\n"); 784 784 + return dev_err_probe(dev, ret, "failed to enable AVDD\n"); 785 785 786 786 - ret = devm_regulator_get_enable(&spi->dev, "vdrive"); 786 786 + ret = devm_regulator_get_enable(dev, "vdrive"); 787 787 if (ret) 788 788 - return dev_err_probe(&spi->dev, ret, "failed to enable VDRIVE\n"); 788 788 + return dev_err_probe(dev, ret, "failed to enable VDRIVE\n"); 789 789 790 790 - ret = devm_regulator_get_enable_optional(&spi->dev, "vrefin"); 790 790 + ret = devm_regulator_get_enable_optional(dev, "vrefin"); 791 791 if (ret < 0 && ret != -ENODEV) 792 792 - return dev_err_probe(&spi->dev, ret, "failed to enable VREFIN\n"); 792 792 + return dev_err_probe(dev, ret, "failed to enable VREFIN\n"); 793 793 794 794 st->vrefin_en = ret != -ENODEV; 795 795 796 796 - st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", 796 796 + st->gpio_reset = devm_gpiod_get_optional(dev, "reset", 797 797 GPIOD_OUT_HIGH); 798 798 if (IS_ERR(st->gpio_reset)) 799 799 - return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_reset), 799 799 + return dev_err_probe(dev, PTR_ERR(st->gpio_reset), 800 800 "failed to get the reset GPIO\n"); 801 801 802 802 return 0; ··· 806 806 { 807 807 int ret; 808 808 u16 chip_id; 809 809 - struct spi_device *spi = st->spi; 809 809 + struct device *dev = &st->spi->dev; 810 810 811 811 ret = ad7293_properties_parse(st); 812 812 if (ret) ··· 821 821 if (ret) 822 822 return ret; 823 823 824 824 - if (chip_id != AD7293_CHIP_ID) { 825 825 - dev_err(&spi->dev, "Invalid Chip ID.\n"); 826 826 - return -EINVAL; 827 827 - } 824 824 + if (chip_id != AD7293_CHIP_ID) 825 825 + return dev_err_probe(dev, -EINVAL, "Invalid Chip ID.\n"); 828 826 829 827 if (!st->vrefin_en) 830 828 return __ad7293_spi_update_bits(st, AD7293_REG_GENERAL, ··· 843 845 { 844 846 struct iio_dev *indio_dev; 845 847 struct ad7293_state *st; 848 848 + struct device *dev = &spi->dev; 846 849 int ret; 847 850 848 848 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 851 851 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 849 852 if (!indio_dev) 850 853 return -ENOMEM; 851 854 ··· 866 867 if (ret) 867 868 return ret; 868 869 869 869 - return devm_iio_device_register(&spi->dev, indio_dev); 870 870 + return devm_iio_device_register(dev, indio_dev); 870 871 } 871 872 872 873 static const struct spi_device_id ad7293_id[] = {

+2 -1

drivers/iio/dac/adi-axi-dac.c

reviewed

··· 114 114 const struct axi_dac_info *info; 115 115 u64 dac_clk; 116 116 u32 reg_config; 117 117 - bool int_tone; 118 117 int dac_clk_rate; 119 118 }; 120 119 ··· 868 869 static const struct iio_backend_info axi_dac_generic = { 869 870 .name = "axi-dac", 870 871 .ops = &axi_dac_generic_ops, 872 872 + .caps = IIO_BACKEND_CAP_BUFFER | IIO_BACKEND_CAP_ENABLE, 871 873 }; 872 874 873 875 static const struct iio_backend_info axi_ad3552r = { 874 876 .name = "axi-ad3552r", 875 877 .ops = &axi_ad3552r_ops, 878 878 + .caps = IIO_BACKEND_CAP_BUFFER | IIO_BACKEND_CAP_ENABLE, 876 879 }; 877 880 878 881 static const struct regmap_config axi_dac_regmap_config = {

+247 -130

drivers/iio/dac/ds4424.c

reviewed

··· 5 5 * Copyright (C) 2017 Maxim Integrated 6 6 */ 7 7 8 8 + #include <linux/array_size.h> 9 9 + #include <linux/bits.h> 10 10 + #include <linux/delay.h> 11 11 + #include <linux/err.h> 12 12 + #include <linux/i2c.h> 8 13 #include <linux/kernel.h> 9 14 #include <linux/module.h> 10 10 - #include <linux/i2c.h> 15 15 + #include <linux/property.h> 16 16 + #include <linux/regmap.h> 11 17 #include <linux/regulator/consumer.h> 12 12 - #include <linux/err.h> 13 13 - #include <linux/delay.h> 14 14 - #include <linux/iio/iio.h> 18 18 + #include <linux/time64.h> 19 19 + #include <linux/types.h> 20 20 + 15 21 #include <linux/iio/driver.h> 22 22 + #include <linux/iio/iio.h> 16 23 #include <linux/iio/machine.h> 17 24 18 25 #define DS4422_MAX_DAC_CHANNELS 2 19 26 #define DS4424_MAX_DAC_CHANNELS 4 20 27 28 28 + #define DS4424_DAC_MASK GENMASK(6, 0) 29 29 + #define DS4404_DAC_MASK GENMASK(4, 0) 30 30 + #define DS4424_DAC_SOURCE BIT(7) 31 31 + 21 32 #define DS4424_DAC_ADDR(chan) ((chan) + 0xf8) 22 22 - #define DS4424_SOURCE_I 1 23 23 - #define DS4424_SINK_I 0 24 33 25 34 #define DS4424_CHANNEL(chan) { \ 26 35 .type = IIO_CURRENT, \ ··· 39 30 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 40 31 } 41 32 42 42 - /* 43 43 - * DS4424 DAC control register 8 bits 44 44 - * [7] 0: to sink; 1: to source 45 45 - * [6:0] steps to sink/source 46 46 - * bit[7] looks like a sign bit, but the value of the register is 47 47 - * not a two's complement code considering the bit[6:0] is a absolute 48 48 - * distance from the zero point. 49 49 - */ 50 50 - union ds4424_raw_data { 51 51 - struct { 52 52 - u8 dx:7; 53 53 - u8 source_bit:1; 54 54 - }; 55 55 - u8 bits; 33 33 + #define DS4424_CHANNEL_WITH_SCALE(chan) { \ 34 34 + .type = IIO_CURRENT, \ 35 35 + .indexed = 1, \ 36 36 + .output = 1, \ 37 37 + .channel = chan, \ 38 38 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 39 39 + BIT(IIO_CHAN_INFO_SCALE), \ 40 40 + } 41 41 + 42 42 + struct ds4424_chip_info { 43 43 + const char *name; 44 44 + int vref_mV; 45 45 + int scale_denom; 46 46 + u8 result_mask; 47 47 + u8 num_channels; 56 48 }; 57 49 58 58 - enum ds4424_device_ids { 59 59 - ID_DS4422, 60 60 - ID_DS4424, 50 50 + static const struct ds4424_chip_info ds4402_info = { 51 51 + .name = "ds4402", 52 52 + .vref_mV = 1230, 53 53 + .scale_denom = 4, 54 54 + .result_mask = DS4404_DAC_MASK, 55 55 + .num_channels = DS4422_MAX_DAC_CHANNELS, 56 56 + }; 57 57 + 58 58 + static const struct ds4424_chip_info ds4404_info = { 59 59 + .name = "ds4404", 60 60 + .vref_mV = 1230, 61 61 + .scale_denom = 4, 62 62 + .result_mask = DS4404_DAC_MASK, 63 63 + .num_channels = DS4424_MAX_DAC_CHANNELS, 64 64 + }; 65 65 + 66 66 + static const struct ds4424_chip_info ds4422_info = { 67 67 + .name = "ds4422", 68 68 + .vref_mV = 976, 69 69 + .scale_denom = 16, 70 70 + .result_mask = DS4424_DAC_MASK, 71 71 + .num_channels = DS4422_MAX_DAC_CHANNELS, 72 72 + }; 73 73 + 74 74 + static const struct ds4424_chip_info ds4424_info = { 75 75 + .name = "ds4424", 76 76 + .vref_mV = 976, 77 77 + .scale_denom = 16, 78 78 + .result_mask = DS4424_DAC_MASK, 79 79 + .num_channels = DS4424_MAX_DAC_CHANNELS, 61 80 }; 62 81 63 82 struct ds4424_data { 64 64 - struct i2c_client *client; 65 65 - struct mutex lock; 66 66 - uint8_t save[DS4424_MAX_DAC_CHANNELS]; 83 83 + struct regmap *regmap; 67 84 struct regulator *vcc_reg; 68 68 - uint8_t raw[DS4424_MAX_DAC_CHANNELS]; 85 85 + const struct ds4424_chip_info *chip_info; 86 86 + u32 rfs_ohms[DS4424_MAX_DAC_CHANNELS]; 87 87 + bool has_rfs; 69 88 }; 70 89 71 90 static const struct iio_chan_spec ds4424_channels[] = { ··· 103 66 DS4424_CHANNEL(3), 104 67 }; 105 68 106 106 - static int ds4424_get_value(struct iio_dev *indio_dev, 107 107 - int *val, int channel) 69 69 + static const struct iio_chan_spec ds4424_channels_with_scale[] = { 70 70 + DS4424_CHANNEL_WITH_SCALE(0), 71 71 + DS4424_CHANNEL_WITH_SCALE(1), 72 72 + DS4424_CHANNEL_WITH_SCALE(2), 73 73 + DS4424_CHANNEL_WITH_SCALE(3), 74 74 + }; 75 75 + 76 76 + static const struct regmap_range ds44x2_ranges[] = { 77 77 + regmap_reg_range(DS4424_DAC_ADDR(0), DS4424_DAC_ADDR(1)), 78 78 + }; 79 79 + 80 80 + static const struct regmap_range ds44x4_ranges[] = { 81 81 + regmap_reg_range(DS4424_DAC_ADDR(0), DS4424_DAC_ADDR(3)), 82 82 + }; 83 83 + 84 84 + static const struct regmap_access_table ds44x2_table = { 85 85 + .yes_ranges = ds44x2_ranges, 86 86 + .n_yes_ranges = ARRAY_SIZE(ds44x2_ranges), 87 87 + }; 88 88 + 89 89 + static const struct regmap_access_table ds44x4_table = { 90 90 + .yes_ranges = ds44x4_ranges, 91 91 + .n_yes_ranges = ARRAY_SIZE(ds44x4_ranges), 92 92 + }; 93 93 + 94 94 + static const struct regmap_config ds44x2_regmap_config = { 95 95 + .reg_bits = 8, 96 96 + .val_bits = 8, 97 97 + .cache_type = REGCACHE_MAPLE, 98 98 + .max_register = DS4424_DAC_ADDR(1), 99 99 + .rd_table = &ds44x2_table, 100 100 + .wr_table = &ds44x2_table, 101 101 + }; 102 102 + 103 103 + static const struct regmap_config ds44x4_regmap_config = { 104 104 + .reg_bits = 8, 105 105 + .val_bits = 8, 106 106 + .cache_type = REGCACHE_MAPLE, 107 107 + .max_register = DS4424_DAC_ADDR(3), 108 108 + .rd_table = &ds44x4_table, 109 109 + .wr_table = &ds44x4_table, 110 110 + }; 111 111 + 112 112 + static int ds4424_init_regmap(struct i2c_client *client, 113 113 + struct iio_dev *indio_dev) 108 114 { 109 115 struct ds4424_data *data = iio_priv(indio_dev); 116 116 + const struct regmap_config *regmap_config; 117 117 + u8 vals[DS4424_MAX_DAC_CHANNELS]; 110 118 int ret; 111 119 112 112 - mutex_lock(&data->lock); 113 113 - ret = i2c_smbus_read_byte_data(data->client, DS4424_DAC_ADDR(channel)); 114 114 - if (ret < 0) 115 115 - goto fail; 120 120 + if (indio_dev->num_channels == DS4424_MAX_DAC_CHANNELS) 121 121 + regmap_config = &ds44x4_regmap_config; 122 122 + else 123 123 + regmap_config = &ds44x2_regmap_config; 116 124 117 117 - *val = ret; 125 125 + data->regmap = devm_regmap_init_i2c(client, regmap_config); 126 126 + if (IS_ERR(data->regmap)) 127 127 + return dev_err_probe(&client->dev, PTR_ERR(data->regmap), 128 128 + "Failed to init regmap.\n"); 118 129 119 119 - fail: 120 120 - mutex_unlock(&data->lock); 121 121 - return ret; 122 122 - } 130 130 + /* 131 131 + * Prime the cache with the bootloader's configuration. 132 132 + * regmap_bulk_read() will automatically populate the cache with 133 133 + * the values read from the hardware. 134 134 + */ 135 135 + ret = regmap_bulk_read(data->regmap, DS4424_DAC_ADDR(0), vals, 136 136 + indio_dev->num_channels); 137 137 + if (ret) 138 138 + return dev_err_probe(&client->dev, ret, 139 139 + "Failed to read hardware values\n"); 123 140 124 124 - static int ds4424_set_value(struct iio_dev *indio_dev, 125 125 - int val, struct iio_chan_spec const *chan) 126 126 - { 127 127 - struct ds4424_data *data = iio_priv(indio_dev); 128 128 - int ret; 129 129 - 130 130 - mutex_lock(&data->lock); 131 131 - ret = i2c_smbus_write_byte_data(data->client, 132 132 - DS4424_DAC_ADDR(chan->channel), val); 133 133 - if (ret < 0) 134 134 - goto fail; 135 135 - 136 136 - data->raw[chan->channel] = val; 137 137 - 138 138 - fail: 139 139 - mutex_unlock(&data->lock); 140 140 - return ret; 141 141 + return 0; 141 142 } 142 143 143 144 static int ds4424_read_raw(struct iio_dev *indio_dev, 144 145 struct iio_chan_spec const *chan, 145 146 int *val, int *val2, long mask) 146 147 { 147 147 - union ds4424_raw_data raw; 148 148 + struct ds4424_data *data = iio_priv(indio_dev); 149 149 + unsigned int regval; 148 150 int ret; 149 151 150 152 switch (mask) { 151 153 case IIO_CHAN_INFO_RAW: 152 152 - ret = ds4424_get_value(indio_dev, val, chan->channel); 154 154 + ret = regmap_read(data->regmap, DS4424_DAC_ADDR(chan->channel), 155 155 + &regval); 153 156 if (ret < 0) { 154 154 - pr_err("%s : ds4424_get_value returned %d\n", 155 155 - __func__, ret); 157 157 + dev_err_ratelimited(indio_dev->dev.parent, 158 158 + "Failed to read channel %d: %pe\n", 159 159 + chan->channel, ERR_PTR(ret)); 156 160 return ret; 157 161 } 158 158 - raw.bits = *val; 159 159 - *val = raw.dx; 160 160 - if (raw.source_bit == DS4424_SINK_I) 162 162 + 163 163 + *val = regval & data->chip_info->result_mask; 164 164 + if (!(regval & DS4424_DAC_SOURCE)) 161 165 *val = -*val; 166 166 + 162 167 return IIO_VAL_INT; 168 168 + case IIO_CHAN_INFO_SCALE: 169 169 + if (!data->has_rfs) 170 170 + return -EINVAL; 171 171 + 172 172 + /* SCALE is mA/step: mV / Ohm = mA. */ 173 173 + *val = data->chip_info->vref_mV; 174 174 + *val2 = data->rfs_ohms[chan->channel] * 175 175 + data->chip_info->scale_denom; 176 176 + return IIO_VAL_FRACTIONAL; 163 177 164 178 default: 165 179 return -EINVAL; ··· 221 133 struct iio_chan_spec const *chan, 222 134 int val, int val2, long mask) 223 135 { 224 224 - union ds4424_raw_data raw; 136 136 + struct ds4424_data *data = iio_priv(indio_dev); 137 137 + unsigned int abs_val; 225 138 226 139 if (val2 != 0) 227 140 return -EINVAL; 228 141 229 142 switch (mask) { 230 143 case IIO_CHAN_INFO_RAW: 231 231 - if (val <= S8_MIN || val > S8_MAX) 144 144 + abs_val = abs(val); 145 145 + if (abs_val > data->chip_info->result_mask) 232 146 return -EINVAL; 233 147 234 234 - if (val > 0) { 235 235 - raw.source_bit = DS4424_SOURCE_I; 236 236 - raw.dx = val; 237 237 - } else { 238 238 - raw.source_bit = DS4424_SINK_I; 239 239 - raw.dx = -val; 240 240 - } 148 148 + /* 149 149 + * Currents exiting the IC (Source) are positive. 0 is a valid 150 150 + * value for no current flow; the direction bit (Source vs Sink) 151 151 + * is treated as don't-care by the hardware at 0. 152 152 + */ 153 153 + if (val > 0) 154 154 + abs_val |= DS4424_DAC_SOURCE; 241 155 242 242 - return ds4424_set_value(indio_dev, raw.bits, chan); 156 156 + return regmap_write(data->regmap, DS4424_DAC_ADDR(chan->channel), 157 157 + abs_val); 243 158 244 159 default: 245 160 return -EINVAL; 246 161 } 247 162 } 248 163 249 249 - static int ds4424_verify_chip(struct iio_dev *indio_dev) 164 164 + static int ds4424_parse_rfs(struct i2c_client *client, 165 165 + struct ds4424_data *data, 166 166 + struct iio_dev *indio_dev) 250 167 { 251 251 - int ret, val; 168 168 + struct device *dev = &client->dev; 169 169 + int count, ret; 252 170 253 253 - ret = ds4424_get_value(indio_dev, &val, 0); 254 254 - if (ret < 0) 255 255 - dev_err(&indio_dev->dev, 256 256 - "%s failed. ret: %d\n", __func__, ret); 171 171 + if (!device_property_present(dev, "maxim,rfs-ohms")) 172 172 + return 0; 257 173 258 258 - return ret; 174 174 + count = device_property_count_u32(dev, "maxim,rfs-ohms"); 175 175 + if (count < 0) 176 176 + return dev_err_probe(dev, count, "Failed to count maxim,rfs-ohms entries\n"); 177 177 + if (count != indio_dev->num_channels) 178 178 + return dev_err_probe(dev, -EINVAL, "maxim,rfs-ohms must have %u entries\n", 179 179 + indio_dev->num_channels); 180 180 + 181 181 + ret = device_property_read_u32_array(dev, "maxim,rfs-ohms", 182 182 + data->rfs_ohms, 183 183 + indio_dev->num_channels); 184 184 + if (ret) 185 185 + return dev_err_probe(dev, ret, "Failed to read maxim,rfs-ohms property\n"); 186 186 + 187 187 + for (unsigned int i = 0; i < indio_dev->num_channels; i++) { 188 188 + if (!data->rfs_ohms[i]) 189 189 + return dev_err_probe(dev, -EINVAL, "maxim,rfs-ohms entry %u is zero\n", i); 190 190 + } 191 191 + 192 192 + data->has_rfs = true; 193 193 + 194 194 + return 0; 259 195 } 260 196 261 197 static int ds4424_suspend(struct device *dev) 262 198 { 263 263 - struct i2c_client *client = to_i2c_client(dev); 264 264 - struct iio_dev *indio_dev = i2c_get_clientdata(client); 199 199 + struct iio_dev *indio_dev = dev_get_drvdata(dev); 265 200 struct ds4424_data *data = iio_priv(indio_dev); 266 266 - int ret = 0; 267 267 - int i; 201 201 + u8 zero_buf[DS4424_MAX_DAC_CHANNELS] = { }; 202 202 + int ret; 268 203 269 269 - for (i = 0; i < indio_dev->num_channels; i++) { 270 270 - data->save[i] = data->raw[i]; 271 271 - ret = ds4424_set_value(indio_dev, 0, 272 272 - &indio_dev->channels[i]); 273 273 - if (ret < 0) 274 274 - return ret; 204 204 + /* Disable all outputs, bypass cache so the '0' isn't saved */ 205 205 + regcache_cache_bypass(data->regmap, true); 206 206 + ret = regmap_bulk_write(data->regmap, DS4424_DAC_ADDR(0), 207 207 + zero_buf, indio_dev->num_channels); 208 208 + regcache_cache_bypass(data->regmap, false); 209 209 + if (ret) { 210 210 + dev_err(dev, "Failed to zero outputs: %pe\n", ERR_PTR(ret)); 211 211 + return ret; 275 212 } 276 276 - return ret; 213 213 + 214 214 + regcache_cache_only(data->regmap, true); 215 215 + regcache_mark_dirty(data->regmap); 216 216 + 217 217 + return 0; 277 218 } 278 219 279 220 static int ds4424_resume(struct device *dev) 280 221 { 281 281 - struct i2c_client *client = to_i2c_client(dev); 282 282 - struct iio_dev *indio_dev = i2c_get_clientdata(client); 222 222 + struct iio_dev *indio_dev = dev_get_drvdata(dev); 283 223 struct ds4424_data *data = iio_priv(indio_dev); 284 284 - int ret = 0; 285 285 - int i; 286 224 287 287 - for (i = 0; i < indio_dev->num_channels; i++) { 288 288 - ret = ds4424_set_value(indio_dev, data->save[i], 289 289 - &indio_dev->channels[i]); 290 290 - if (ret < 0) 291 291 - return ret; 292 292 - } 293 293 - return ret; 225 225 + regcache_cache_only(data->regmap, false); 226 226 + return regcache_sync(data->regmap); 294 227 } 295 228 296 229 static DEFINE_SIMPLE_DEV_PM_OPS(ds4424_pm_ops, ds4424_suspend, ds4424_resume); 297 230 298 298 - static const struct iio_info ds4424_info = { 231 231 + static const struct iio_info ds4424_iio_info = { 299 232 .read_raw = ds4424_read_raw, 300 233 .write_raw = ds4424_write_raw, 301 234 }; 302 235 303 236 static int ds4424_probe(struct i2c_client *client) 304 237 { 305 305 - const struct i2c_device_id *id = i2c_client_get_device_id(client); 238 238 + const struct ds4424_chip_info *chip_info; 306 239 struct ds4424_data *data; 307 240 struct iio_dev *indio_dev; 308 241 int ret; 242 242 + 243 243 + chip_info = i2c_get_match_data(client); 244 244 + if (!chip_info) 245 245 + return -ENODEV; 309 246 310 247 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 311 248 if (!indio_dev) ··· 338 225 339 226 data = iio_priv(indio_dev); 340 227 i2c_set_clientdata(client, indio_dev); 341 341 - data->client = client; 342 342 - indio_dev->name = id->name; 228 228 + indio_dev->name = chip_info->name; 229 229 + data->chip_info = chip_info; 343 230 344 231 data->vcc_reg = devm_regulator_get(&client->dev, "vcc"); 345 232 if (IS_ERR(data->vcc_reg)) 346 233 return dev_err_probe(&client->dev, PTR_ERR(data->vcc_reg), 347 234 "Failed to get vcc-supply regulator.\n"); 348 235 349 349 - mutex_init(&data->lock); 350 236 ret = regulator_enable(data->vcc_reg); 351 237 if (ret < 0) { 352 238 dev_err(&client->dev, ··· 353 241 return ret; 354 242 } 355 243 356 356 - usleep_range(1000, 1200); 357 357 - ret = ds4424_verify_chip(indio_dev); 358 358 - if (ret < 0) 359 359 - goto fail; 244 244 + /* 245 245 + * The datasheet does not specify a power-up to I2C ready time. 246 246 + * Maintain the existing conservative 1ms delay to ensure the 247 247 + * device is ready for communication. 248 248 + */ 249 249 + fsleep(1 * USEC_PER_MSEC); 360 250 361 361 - switch (id->driver_data) { 362 362 - case ID_DS4422: 363 363 - indio_dev->num_channels = DS4422_MAX_DAC_CHANNELS; 364 364 - break; 365 365 - case ID_DS4424: 366 366 - indio_dev->num_channels = DS4424_MAX_DAC_CHANNELS; 367 367 - break; 368 368 - default: 369 369 - dev_err(&client->dev, 370 370 - "ds4424: Invalid chip id.\n"); 371 371 - ret = -ENXIO; 372 372 - goto fail; 373 373 - } 374 374 - 375 375 - indio_dev->channels = ds4424_channels; 251 251 + indio_dev->num_channels = chip_info->num_channels; 376 252 indio_dev->modes = INDIO_DIRECT_MODE; 377 377 - indio_dev->info = &ds4424_info; 253 253 + indio_dev->info = &ds4424_iio_info; 254 254 + 255 255 + ret = ds4424_init_regmap(client, indio_dev); 256 256 + if (ret) 257 257 + goto fail; 258 258 + 259 259 + ret = ds4424_parse_rfs(client, data, indio_dev); 260 260 + if (ret) 261 261 + goto fail; 262 262 + 263 263 + if (data->has_rfs) 264 264 + indio_dev->channels = ds4424_channels_with_scale; 265 265 + else 266 266 + indio_dev->channels = ds4424_channels; 378 267 379 268 ret = iio_device_register(indio_dev); 380 269 if (ret < 0) { ··· 401 288 } 402 289 403 290 static const struct i2c_device_id ds4424_id[] = { 404 404 - { "ds4422", ID_DS4422 }, 405 405 - { "ds4424", ID_DS4424 }, 291 291 + { "ds4402", (kernel_ulong_t)&ds4402_info }, 292 292 + { "ds4404", (kernel_ulong_t)&ds4404_info }, 293 293 + { "ds4422", (kernel_ulong_t)&ds4422_info }, 294 294 + { "ds4424", (kernel_ulong_t)&ds4424_info }, 406 295 { } 407 296 }; 408 297 409 298 MODULE_DEVICE_TABLE(i2c, ds4424_id); 410 299 411 300 static const struct of_device_id ds4424_of_match[] = { 412 412 - { .compatible = "maxim,ds4422" }, 413 413 - { .compatible = "maxim,ds4424" }, 301 301 + { .compatible = "maxim,ds4402", .data = &ds4402_info }, 302 302 + { .compatible = "maxim,ds4404", .data = &ds4404_info }, 303 303 + { .compatible = "maxim,ds4422", .data = &ds4422_info }, 304 304 + { .compatible = "maxim,ds4424", .data = &ds4424_info }, 414 305 { } 415 306 }; 416 307

+165 -188

drivers/iio/dac/ltc2632.c

reviewed

··· 48 48 int vref_mv; 49 49 }; 50 50 51 51 - enum ltc2632_supported_device_ids { 52 52 - ID_LTC2632L12, 53 53 - ID_LTC2632L10, 54 54 - ID_LTC2632L8, 55 55 - ID_LTC2632H12, 56 56 - ID_LTC2632H10, 57 57 - ID_LTC2632H8, 58 58 - ID_LTC2634L12, 59 59 - ID_LTC2634L10, 60 60 - ID_LTC2634L8, 61 61 - ID_LTC2634H12, 62 62 - ID_LTC2634H10, 63 63 - ID_LTC2634H8, 64 64 - ID_LTC2636L12, 65 65 - ID_LTC2636L10, 66 66 - ID_LTC2636L8, 67 67 - ID_LTC2636H12, 68 68 - ID_LTC2636H10, 69 69 - ID_LTC2636H8, 70 70 - }; 71 71 - 72 51 static int ltc2632_spi_write(struct spi_device *spi, 73 52 u8 cmd, u8 addr, u16 val, u8 shift) 74 53 { ··· 58 79 * The input shift register is 24 bits wide. 59 80 * The next four are the command bits, C3 to C0, 60 81 * followed by the 4-bit DAC address, A3 to A0, and then the 61 61 - * 12-, 10-, 8-bit data-word. The data-word comprises the 12-, 62 62 - * 10-, 8-bit input code followed by 4, 6, or 8 don't care bits. 82 82 + * 16-, 12-, 10-, 8-bit data-word. The data-word comprises the 83 83 + * 16-, 12-, 10-, 8-bit input code followed by 0, 4, 6, or 8 84 84 + * don't care bits. 63 85 */ 64 86 data = (cmd << 20) | (addr << 16) | (val << shift); 65 87 put_unaligned_be24(data, &msg[0]); ··· 186 206 LTC2632_CHANNEL(7, _bits), \ 187 207 } 188 208 209 209 + static DECLARE_LTC2632_CHANNELS(ltc2632x16, 16); 189 210 static DECLARE_LTC2632_CHANNELS(ltc2632x12, 12); 190 211 static DECLARE_LTC2632_CHANNELS(ltc2632x10, 10); 191 212 static DECLARE_LTC2632_CHANNELS(ltc2632x8, 8); 192 213 193 193 - static const struct ltc2632_chip_info ltc2632_chip_info_tbl[] = { 194 194 - [ID_LTC2632L12] = { 195 195 - .channels = ltc2632x12_channels, 196 196 - .num_channels = 2, 197 197 - .vref_mv = 2500, 198 198 - }, 199 199 - [ID_LTC2632L10] = { 200 200 - .channels = ltc2632x10_channels, 201 201 - .num_channels = 2, 202 202 - .vref_mv = 2500, 203 203 - }, 204 204 - [ID_LTC2632L8] = { 205 205 - .channels = ltc2632x8_channels, 206 206 - .num_channels = 2, 207 207 - .vref_mv = 2500, 208 208 - }, 209 209 - [ID_LTC2632H12] = { 210 210 - .channels = ltc2632x12_channels, 211 211 - .num_channels = 2, 212 212 - .vref_mv = 4096, 213 213 - }, 214 214 - [ID_LTC2632H10] = { 215 215 - .channels = ltc2632x10_channels, 216 216 - .num_channels = 2, 217 217 - .vref_mv = 4096, 218 218 - }, 219 219 - [ID_LTC2632H8] = { 220 220 - .channels = ltc2632x8_channels, 221 221 - .num_channels = 2, 222 222 - .vref_mv = 4096, 223 223 - }, 224 224 - [ID_LTC2634L12] = { 225 225 - .channels = ltc2632x12_channels, 226 226 - .num_channels = 4, 227 227 - .vref_mv = 2500, 228 228 - }, 229 229 - [ID_LTC2634L10] = { 230 230 - .channels = ltc2632x10_channels, 231 231 - .num_channels = 4, 232 232 - .vref_mv = 2500, 233 233 - }, 234 234 - [ID_LTC2634L8] = { 235 235 - .channels = ltc2632x8_channels, 236 236 - .num_channels = 4, 237 237 - .vref_mv = 2500, 238 238 - }, 239 239 - [ID_LTC2634H12] = { 240 240 - .channels = ltc2632x12_channels, 241 241 - .num_channels = 4, 242 242 - .vref_mv = 4096, 243 243 - }, 244 244 - [ID_LTC2634H10] = { 245 245 - .channels = ltc2632x10_channels, 246 246 - .num_channels = 4, 247 247 - .vref_mv = 4096, 248 248 - }, 249 249 - [ID_LTC2634H8] = { 250 250 - .channels = ltc2632x8_channels, 251 251 - .num_channels = 4, 252 252 - .vref_mv = 4096, 253 253 - }, 254 254 - [ID_LTC2636L12] = { 255 255 - .channels = ltc2632x12_channels, 256 256 - .num_channels = 8, 257 257 - .vref_mv = 2500, 258 258 - }, 259 259 - [ID_LTC2636L10] = { 260 260 - .channels = ltc2632x10_channels, 261 261 - .num_channels = 8, 262 262 - .vref_mv = 2500, 263 263 - }, 264 264 - [ID_LTC2636L8] = { 265 265 - .channels = ltc2632x8_channels, 266 266 - .num_channels = 8, 267 267 - .vref_mv = 2500, 268 268 - }, 269 269 - [ID_LTC2636H12] = { 270 270 - .channels = ltc2632x12_channels, 271 271 - .num_channels = 8, 272 272 - .vref_mv = 4096, 273 273 - }, 274 274 - [ID_LTC2636H10] = { 275 275 - .channels = ltc2632x10_channels, 276 276 - .num_channels = 8, 277 277 - .vref_mv = 4096, 278 278 - }, 279 279 - [ID_LTC2636H8] = { 280 280 - .channels = ltc2632x8_channels, 281 281 - .num_channels = 8, 282 282 - .vref_mv = 4096, 283 283 - }, 214 214 + static const struct ltc2632_chip_info ltc2632l12_chip_info = { 215 215 + .channels = ltc2632x12_channels, 216 216 + .num_channels = 2, 217 217 + .vref_mv = 2500, 218 218 + }; 219 219 + 220 220 + static const struct ltc2632_chip_info ltc2632l10_chip_info = { 221 221 + .channels = ltc2632x10_channels, 222 222 + .num_channels = 2, 223 223 + .vref_mv = 2500, 224 224 + }; 225 225 + 226 226 + static const struct ltc2632_chip_info ltc2632l8_chip_info = { 227 227 + .channels = ltc2632x8_channels, 228 228 + .num_channels = 2, 229 229 + .vref_mv = 2500, 230 230 + }; 231 231 + 232 232 + static const struct ltc2632_chip_info ltc2632h12_chip_info = { 233 233 + .channels = ltc2632x12_channels, 234 234 + .num_channels = 2, 235 235 + .vref_mv = 4096, 236 236 + }; 237 237 + 238 238 + static const struct ltc2632_chip_info ltc2632h10_chip_info = { 239 239 + .channels = ltc2632x10_channels, 240 240 + .num_channels = 2, 241 241 + .vref_mv = 4096, 242 242 + }; 243 243 + 244 244 + static const struct ltc2632_chip_info ltc2632h8_chip_info = { 245 245 + .channels = ltc2632x8_channels, 246 246 + .num_channels = 2, 247 247 + .vref_mv = 4096, 248 248 + }; 249 249 + 250 250 + static const struct ltc2632_chip_info ltc2634l12_chip_info = { 251 251 + .channels = ltc2632x12_channels, 252 252 + .num_channels = 4, 253 253 + .vref_mv = 2500, 254 254 + }; 255 255 + 256 256 + static const struct ltc2632_chip_info ltc2634l10_chip_info = { 257 257 + .channels = ltc2632x10_channels, 258 258 + .num_channels = 4, 259 259 + .vref_mv = 2500, 260 260 + }; 261 261 + 262 262 + static const struct ltc2632_chip_info ltc2634l8_chip_info = { 263 263 + .channels = ltc2632x8_channels, 264 264 + .num_channels = 4, 265 265 + .vref_mv = 2500, 266 266 + }; 267 267 + 268 268 + static const struct ltc2632_chip_info ltc2634h12_chip_info = { 269 269 + .channels = ltc2632x12_channels, 270 270 + .num_channels = 4, 271 271 + .vref_mv = 4096, 272 272 + }; 273 273 + 274 274 + static const struct ltc2632_chip_info ltc2634h10_chip_info = { 275 275 + .channels = ltc2632x10_channels, 276 276 + .num_channels = 4, 277 277 + .vref_mv = 4096, 278 278 + }; 279 279 + 280 280 + static const struct ltc2632_chip_info ltc2634h8_chip_info = { 281 281 + .channels = ltc2632x8_channels, 282 282 + .num_channels = 4, 283 283 + .vref_mv = 4096, 284 284 + }; 285 285 + 286 286 + static const struct ltc2632_chip_info ltc2636l12_chip_info = { 287 287 + .channels = ltc2632x12_channels, 288 288 + .num_channels = 8, 289 289 + .vref_mv = 2500, 290 290 + }; 291 291 + 292 292 + static const struct ltc2632_chip_info ltc2636l10_chip_info = { 293 293 + .channels = ltc2632x10_channels, 294 294 + .num_channels = 8, 295 295 + .vref_mv = 2500, 296 296 + }; 297 297 + 298 298 + static const struct ltc2632_chip_info ltc2636l8_chip_info = { 299 299 + .channels = ltc2632x8_channels, 300 300 + .num_channels = 8, 301 301 + .vref_mv = 2500, 302 302 + }; 303 303 + 304 304 + static const struct ltc2632_chip_info ltc2636h12_chip_info = { 305 305 + .channels = ltc2632x12_channels, 306 306 + .num_channels = 8, 307 307 + .vref_mv = 4096, 308 308 + }; 309 309 + 310 310 + static const struct ltc2632_chip_info ltc2636h10_chip_info = { 311 311 + .channels = ltc2632x10_channels, 312 312 + .num_channels = 8, 313 313 + .vref_mv = 4096, 314 314 + }; 315 315 + 316 316 + static const struct ltc2632_chip_info ltc2636h8_chip_info = { 317 317 + .channels = ltc2632x8_channels, 318 318 + .num_channels = 8, 319 319 + .vref_mv = 4096, 320 320 + }; 321 321 + 322 322 + static const struct ltc2632_chip_info ltc2654l16_chip_info = { 323 323 + .channels = ltc2632x16_channels, 324 324 + .num_channels = 4, 325 325 + .vref_mv = 2500, 326 326 + }; 327 327 + 328 328 + static const struct ltc2632_chip_info ltc2654h16_chip_info = { 329 329 + .channels = ltc2632x16_channels, 330 330 + .num_channels = 4, 331 331 + .vref_mv = 4096, 284 332 }; 285 333 286 334 static int ltc2632_probe(struct spi_device *spi) ··· 362 354 } 363 355 364 356 static const struct spi_device_id ltc2632_id[] = { 365 365 - { "ltc2632-l12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632L12] }, 366 366 - { "ltc2632-l10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632L10] }, 367 367 - { "ltc2632-l8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632L8] }, 368 368 - { "ltc2632-h12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632H12] }, 369 369 - { "ltc2632-h10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632H10] }, 370 370 - { "ltc2632-h8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632H8] }, 371 371 - { "ltc2634-l12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634L12] }, 372 372 - { "ltc2634-l10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634L10] }, 373 373 - { "ltc2634-l8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634L8] }, 374 374 - { "ltc2634-h12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634H12] }, 375 375 - { "ltc2634-h10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634H10] }, 376 376 - { "ltc2634-h8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634H8] }, 377 377 - { "ltc2636-l12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636L12] }, 378 378 - { "ltc2636-l10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636L10] }, 379 379 - { "ltc2636-l8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636L8] }, 380 380 - { "ltc2636-h12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636H12] }, 381 381 - { "ltc2636-h10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636H10] }, 382 382 - { "ltc2636-h8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636H8] }, 357 357 + { "ltc2632-l12", (kernel_ulong_t)&ltc2632l12_chip_info }, 358 358 + { "ltc2632-l10", (kernel_ulong_t)&ltc2632l10_chip_info }, 359 359 + { "ltc2632-l8", (kernel_ulong_t)&ltc2632l8_chip_info }, 360 360 + { "ltc2632-h12", (kernel_ulong_t)&ltc2632h12_chip_info }, 361 361 + { "ltc2632-h10", (kernel_ulong_t)&ltc2632h10_chip_info }, 362 362 + { "ltc2632-h8", (kernel_ulong_t)&ltc2632h8_chip_info }, 363 363 + { "ltc2634-l12", (kernel_ulong_t)&ltc2634l12_chip_info }, 364 364 + { "ltc2634-l10", (kernel_ulong_t)&ltc2634l10_chip_info }, 365 365 + { "ltc2634-l8", (kernel_ulong_t)&ltc2634l8_chip_info }, 366 366 + { "ltc2634-h12", (kernel_ulong_t)&ltc2634h12_chip_info }, 367 367 + { "ltc2634-h10", (kernel_ulong_t)&ltc2634h10_chip_info }, 368 368 + { "ltc2634-h8", (kernel_ulong_t)&ltc2634h8_chip_info }, 369 369 + { "ltc2636-l12", (kernel_ulong_t)&ltc2636l12_chip_info }, 370 370 + { "ltc2636-l10", (kernel_ulong_t)&ltc2636l10_chip_info }, 371 371 + { "ltc2636-l8", (kernel_ulong_t)&ltc2636l8_chip_info }, 372 372 + { "ltc2636-h12", (kernel_ulong_t)&ltc2636h12_chip_info }, 373 373 + { "ltc2636-h10", (kernel_ulong_t)&ltc2636h10_chip_info }, 374 374 + { "ltc2636-h8", (kernel_ulong_t)&ltc2636h8_chip_info }, 375 375 + { "ltc2654-l16", (kernel_ulong_t)&ltc2654l16_chip_info }, 376 376 + { "ltc2654-l12", (kernel_ulong_t)&ltc2634l12_chip_info }, 377 377 + { "ltc2654-h16", (kernel_ulong_t)&ltc2654h16_chip_info }, 378 378 + { "ltc2654-h12", (kernel_ulong_t)&ltc2634h12_chip_info }, 383 379 { } 384 380 }; 385 381 MODULE_DEVICE_TABLE(spi, ltc2632_id); 386 382 387 383 static const struct of_device_id ltc2632_of_match[] = { 388 388 - { 389 389 - .compatible = "lltc,ltc2632-l12", 390 390 - .data = &ltc2632_chip_info_tbl[ID_LTC2632L12] 391 391 - }, { 392 392 - .compatible = "lltc,ltc2632-l10", 393 393 - .data = &ltc2632_chip_info_tbl[ID_LTC2632L10] 394 394 - }, { 395 395 - .compatible = "lltc,ltc2632-l8", 396 396 - .data = &ltc2632_chip_info_tbl[ID_LTC2632L8] 397 397 - }, { 398 398 - .compatible = "lltc,ltc2632-h12", 399 399 - .data = &ltc2632_chip_info_tbl[ID_LTC2632H12] 400 400 - }, { 401 401 - .compatible = "lltc,ltc2632-h10", 402 402 - .data = &ltc2632_chip_info_tbl[ID_LTC2632H10] 403 403 - }, { 404 404 - .compatible = "lltc,ltc2632-h8", 405 405 - .data = &ltc2632_chip_info_tbl[ID_LTC2632H8] 406 406 - }, { 407 407 - .compatible = "lltc,ltc2634-l12", 408 408 - .data = &ltc2632_chip_info_tbl[ID_LTC2634L12] 409 409 - }, { 410 410 - .compatible = "lltc,ltc2634-l10", 411 411 - .data = &ltc2632_chip_info_tbl[ID_LTC2634L10] 412 412 - }, { 413 413 - .compatible = "lltc,ltc2634-l8", 414 414 - .data = &ltc2632_chip_info_tbl[ID_LTC2634L8] 415 415 - }, { 416 416 - .compatible = "lltc,ltc2634-h12", 417 417 - .data = &ltc2632_chip_info_tbl[ID_LTC2634H12] 418 418 - }, { 419 419 - .compatible = "lltc,ltc2634-h10", 420 420 - .data = &ltc2632_chip_info_tbl[ID_LTC2634H10] 421 421 - }, { 422 422 - .compatible = "lltc,ltc2634-h8", 423 423 - .data = &ltc2632_chip_info_tbl[ID_LTC2634H8] 424 424 - }, { 425 425 - .compatible = "lltc,ltc2636-l12", 426 426 - .data = &ltc2632_chip_info_tbl[ID_LTC2636L12] 427 427 - }, { 428 428 - .compatible = "lltc,ltc2636-l10", 429 429 - .data = &ltc2632_chip_info_tbl[ID_LTC2636L10] 430 430 - }, { 431 431 - .compatible = "lltc,ltc2636-l8", 432 432 - .data = &ltc2632_chip_info_tbl[ID_LTC2636L8] 433 433 - }, { 434 434 - .compatible = "lltc,ltc2636-h12", 435 435 - .data = &ltc2632_chip_info_tbl[ID_LTC2636H12] 436 436 - }, { 437 437 - .compatible = "lltc,ltc2636-h10", 438 438 - .data = &ltc2632_chip_info_tbl[ID_LTC2636H10] 439 439 - }, { 440 440 - .compatible = "lltc,ltc2636-h8", 441 441 - .data = &ltc2632_chip_info_tbl[ID_LTC2636H8] 442 442 - }, 384 384 + { .compatible = "lltc,ltc2632-l12", .data = &ltc2632l12_chip_info }, 385 385 + { .compatible = "lltc,ltc2632-l10", .data = &ltc2632l10_chip_info }, 386 386 + { .compatible = "lltc,ltc2632-l8", .data = &ltc2632l8_chip_info }, 387 387 + { .compatible = "lltc,ltc2632-h12", .data = &ltc2632h12_chip_info }, 388 388 + { .compatible = "lltc,ltc2632-h10", .data = &ltc2632h10_chip_info }, 389 389 + { .compatible = "lltc,ltc2632-h8", .data = &ltc2632h8_chip_info }, 390 390 + { .compatible = "lltc,ltc2634-l12", .data = &ltc2634l12_chip_info }, 391 391 + { .compatible = "lltc,ltc2634-l10", .data = &ltc2634l10_chip_info }, 392 392 + { .compatible = "lltc,ltc2634-l8", .data = &ltc2634l8_chip_info }, 393 393 + { .compatible = "lltc,ltc2634-h12", .data = &ltc2634h12_chip_info }, 394 394 + { .compatible = "lltc,ltc2634-h10", .data = &ltc2634h10_chip_info }, 395 395 + { .compatible = "lltc,ltc2634-h8", .data = &ltc2634h8_chip_info }, 396 396 + { .compatible = "lltc,ltc2636-l12", .data = &ltc2636l12_chip_info }, 397 397 + { .compatible = "lltc,ltc2636-l10", .data = &ltc2636l10_chip_info }, 398 398 + { .compatible = "lltc,ltc2636-l8", .data = &ltc2636l8_chip_info }, 399 399 + { .compatible = "lltc,ltc2636-h12", .data = &ltc2636h12_chip_info }, 400 400 + { .compatible = "lltc,ltc2636-h10", .data = &ltc2636h10_chip_info }, 401 401 + { .compatible = "lltc,ltc2636-h8", .data = &ltc2636h8_chip_info }, 402 402 + { .compatible = "lltc,ltc2654-l16", .data = &ltc2654l16_chip_info }, 403 403 + { .compatible = "lltc,ltc2654-h16", .data = &ltc2654h16_chip_info }, 443 404 { } 444 405 }; 445 406 MODULE_DEVICE_TABLE(of, ltc2632_of_match); ··· 424 447 module_spi_driver(ltc2632_driver); 425 448 426 449 MODULE_AUTHOR("Maxime Roussin-Belanger <maxime.roussinbelanger@gmail.com>"); 427 427 - MODULE_DESCRIPTION("LTC2632 DAC SPI driver"); 450 450 + MODULE_DESCRIPTION("LTC2632 and similar DAC SPI driver"); 428 451 MODULE_LICENSE("GPL v2");

+7 -15

drivers/iio/dac/max5522.c

reviewed

··· 14 14 #include <linux/regulator/consumer.h> 15 15 #include <linux/slab.h> 16 16 #include <linux/spi/spi.h> 17 17 + #include <linux/units.h> 17 18 18 19 #include <linux/iio/iio.h> 19 20 ··· 35 34 struct regmap *regmap; 36 35 const struct max5522_chip_info *chip_info; 37 36 unsigned short dac_cache[2]; 38 38 - struct regulator *vrefin_reg; 37 37 + int vref_mV; 39 38 }; 40 39 41 40 #define MAX5522_CHANNEL(chan) { \ ··· 80 79 int *val, int *val2, long info) 81 80 { 82 81 struct max5522_state *state = iio_priv(indio_dev); 83 83 - int ret; 84 82 85 83 switch (info) { 86 84 case IIO_CHAN_INFO_RAW: 87 85 *val = state->dac_cache[chan->channel]; 88 86 return IIO_VAL_INT; 89 87 case IIO_CHAN_INFO_SCALE: 90 90 - ret = regulator_get_voltage(state->vrefin_reg); 91 91 - if (ret < 0) 92 92 - return -EINVAL; 93 93 - *val = ret / 1000; 88 88 + *val = state->vref_mV; 94 89 *val2 = 10; 95 90 return IIO_VAL_FRACTIONAL_LOG2; 96 91 default: ··· 144 147 if (!state->chip_info) 145 148 return -EINVAL; 146 149 147 147 - state->vrefin_reg = devm_regulator_get(&spi->dev, "vrefin"); 148 148 - if (IS_ERR(state->vrefin_reg)) 149 149 - return dev_err_probe(&spi->dev, PTR_ERR(state->vrefin_reg), 150 150 - "Vrefin regulator not specified\n"); 151 151 - 152 152 - ret = regulator_enable(state->vrefin_reg); 153 153 - if (ret) { 150 150 + ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vrefin"); 151 151 + if (ret < 0) 154 152 return dev_err_probe(&spi->dev, ret, 155 155 - "Failed to enable vref regulators\n"); 156 156 - } 153 153 + "Failed to get vrefin regulator\n"); 154 154 + state->vref_mV = ret / (MICRO / MILLI); 157 155 158 156 state->regmap = devm_regmap_init_spi(spi, &max5522_regmap_config); 159 157

-1

drivers/iio/dac/ti-dac5571.c

reviewed

··· 45 45 46 46 struct dac5571_data { 47 47 struct i2c_client *client; 48 48 - int id; 49 48 struct mutex lock; 50 49 struct regulator *vref; 51 50 u16 val[4];

+27 -33

drivers/iio/filter/admv8818.c

reviewed

··· 657 657 static int admv8818_init(struct admv8818_state *st) 658 658 { 659 659 int ret; 660 660 - struct spi_device *spi = st->spi; 660 660 + struct device *dev = &st->spi->dev; 661 661 unsigned int chip_id; 662 662 663 663 ret = regmap_write(st->regmap, ADMV8818_REG_SPI_CONFIG_A, 664 664 ADMV8818_SOFTRESET_N_MSK | ADMV8818_SOFTRESET_MSK); 665 665 - if (ret) { 666 666 - dev_err(&spi->dev, "ADMV8818 Soft Reset failed.\n"); 667 667 - return ret; 668 668 - } 665 665 + if (ret) 666 666 + return dev_err_probe(dev, ret, "ADMV8818 Soft Reset failed.\n"); 669 667 670 668 ret = regmap_write(st->regmap, ADMV8818_REG_SPI_CONFIG_A, 671 669 ADMV8818_SDOACTIVE_N_MSK | ADMV8818_SDOACTIVE_MSK); 672 672 - if (ret) { 673 673 - dev_err(&spi->dev, "ADMV8818 SDO Enable failed.\n"); 674 674 - return ret; 675 675 - } 670 670 + if (ret) 671 671 + return dev_err_probe(dev, ret, "ADMV8818 SDO Enable failed.\n"); 676 672 677 673 ret = regmap_read(st->regmap, ADMV8818_REG_CHIPTYPE, &chip_id); 678 678 - if (ret) { 679 679 - dev_err(&spi->dev, "ADMV8818 Chip ID read failed.\n"); 680 680 - return ret; 681 681 - } 674 674 + if (ret) 675 675 + return dev_err_probe(dev, ret, 676 676 + "ADMV8818 Chip ID read failed.\n"); 682 677 683 683 - if (chip_id != 0x1) { 684 684 - dev_err(&spi->dev, "ADMV8818 Invalid Chip ID.\n"); 685 685 - return -EINVAL; 686 686 - } 678 678 + if (chip_id != 0x1) 679 679 + return dev_err_probe(dev, -EINVAL, 680 680 + "ADMV8818 Invalid Chip ID.\n"); 687 681 688 682 ret = regmap_update_bits(st->regmap, ADMV8818_REG_SPI_CONFIG_B, 689 683 ADMV8818_SINGLE_INSTRUCTION_MSK, 690 684 FIELD_PREP(ADMV8818_SINGLE_INSTRUCTION_MSK, 1)); 691 691 - if (ret) { 692 692 - dev_err(&spi->dev, "ADMV8818 Single Instruction failed.\n"); 693 693 - return ret; 694 694 - } 685 685 + if (ret) 686 686 + return dev_err_probe(dev, ret, 687 687 + "ADMV8818 Single Instruction failed.\n"); 695 688 696 689 if (st->clkin) 697 690 return admv8818_rfin_band_select(st); 698 698 - else 699 699 - return 0; 691 691 + 692 692 + return 0; 700 693 } 701 694 702 695 static int admv8818_clk_setup(struct admv8818_state *st) 703 696 { 704 704 - struct spi_device *spi = st->spi; 697 697 + struct device *dev = &st->spi->dev; 705 698 int ret; 706 699 707 707 - st->clkin = devm_clk_get_optional(&spi->dev, "rf_in"); 700 700 + st->clkin = devm_clk_get_optional(dev, "rf_in"); 708 701 if (IS_ERR(st->clkin)) 709 709 - return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), 702 702 + return dev_err_probe(dev, PTR_ERR(st->clkin), 710 703 "failed to get the input clock\n"); 711 704 else if (!st->clkin) 712 705 return 0; ··· 708 715 if (ret) 709 716 return ret; 710 717 711 711 - ret = devm_add_action_or_reset(&spi->dev, admv8818_clk_disable, st); 718 718 + ret = devm_add_action_or_reset(dev, admv8818_clk_disable, st); 712 719 if (ret) 713 720 return ret; 714 721 ··· 717 724 if (ret < 0) 718 725 return ret; 719 726 720 720 - return devm_add_action_or_reset(&spi->dev, admv8818_clk_notifier_unreg, st); 727 727 + return devm_add_action_or_reset(dev, admv8818_clk_notifier_unreg, st); 721 728 } 722 729 723 730 static int admv8818_read_properties(struct admv8818_state *st) 724 731 { 725 725 - struct spi_device *spi = st->spi; 732 732 + struct device *dev = &st->spi->dev; 726 733 u32 mhz; 727 734 int ret; 728 735 729 729 - ret = device_property_read_u32(&spi->dev, "adi,lpf-margin-mhz", &mhz); 736 736 + ret = device_property_read_u32(dev, "adi,lpf-margin-mhz", &mhz); 730 737 if (ret == 0) 731 738 st->lpf_margin_hz = (u64)mhz * HZ_PER_MHZ; 732 739 else if (ret == -EINVAL) ··· 735 742 return ret; 736 743 737 744 738 738 - ret = device_property_read_u32(&spi->dev, "adi,hpf-margin-mhz", &mhz); 745 745 + ret = device_property_read_u32(dev, "adi,hpf-margin-mhz", &mhz); 739 746 if (ret == 0) 740 747 st->hpf_margin_hz = (u64)mhz * HZ_PER_MHZ; 741 748 else if (ret == -EINVAL) ··· 751 758 struct iio_dev *indio_dev; 752 759 struct regmap *regmap; 753 760 struct admv8818_state *st; 761 761 + struct device *dev = &spi->dev; 754 762 int ret; 755 763 756 756 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 764 764 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 757 765 if (!indio_dev) 758 766 return -ENOMEM; 759 767 ··· 786 792 if (ret) 787 793 return ret; 788 794 789 789 - return devm_iio_device_register(&spi->dev, indio_dev); 795 795 + return devm_iio_device_register(dev, indio_dev); 790 796 } 791 797 792 798 static const struct spi_device_id admv8818_id[] = {

+35 -57

drivers/iio/frequency/ad9523.c

reviewed

··· 167 167 168 168 /* AD9523_CHANNEL_CLOCK_DIST */ 169 169 #define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18) 170 170 - #define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F) 170 170 + #define AD9523_CLK_DIST_DIV_PHASE_REV(x) (((x) >> 18) & 0x3F) 171 171 #define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8) 172 172 - #define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1) 172 172 + #define AD9523_CLK_DIST_DIV_REV(x) ((((x) >> 8) & 0x3FF) + 1) 173 173 #define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7) 174 174 #define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6) 175 175 #define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5) ··· 558 558 return ret; 559 559 } 560 560 561 561 - static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO, 562 562 - ad9523_show, 563 563 - NULL, 564 564 - AD9523_STAT_PLL1_LD); 561 561 + static IIO_DEVICE_ATTR(pll1_locked, 0444, ad9523_show, NULL, 562 562 + AD9523_STAT_PLL1_LD); 565 563 566 566 - static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO, 567 567 - ad9523_show, 568 568 - NULL, 569 569 - AD9523_STAT_PLL2_LD); 564 564 + static IIO_DEVICE_ATTR(pll2_locked, 0444, ad9523_show, NULL, 565 565 + AD9523_STAT_PLL2_LD); 570 566 571 571 - static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO, 572 572 - ad9523_show, 573 573 - NULL, 574 574 - AD9523_STAT_REFA); 567 567 + static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, 0444, ad9523_show, NULL, 568 568 + AD9523_STAT_REFA); 575 569 576 576 - static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO, 577 577 - ad9523_show, 578 578 - NULL, 579 579 - AD9523_STAT_REFB); 570 570 + static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, 0444, ad9523_show, NULL, 571 571 + AD9523_STAT_REFB); 580 572 581 581 - static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO, 582 582 - ad9523_show, 583 583 - NULL, 584 584 - AD9523_STAT_REF_TEST); 573 573 + static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, 0444, ad9523_show, NULL, 574 574 + AD9523_STAT_REF_TEST); 585 575 586 586 - static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO, 587 587 - ad9523_show, 588 588 - NULL, 589 589 - AD9523_STAT_VCXO); 576 576 + static IIO_DEVICE_ATTR(vcxo_clk_present, 0444, ad9523_show, NULL, 577 577 + AD9523_STAT_VCXO); 590 578 591 591 - static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO, 592 592 - ad9523_show, 593 593 - NULL, 594 594 - AD9523_STAT_PLL2_FB_CLK); 579 579 + static IIO_DEVICE_ATTR(pll2_feedback_clk_present, 0444, ad9523_show, NULL, 580 580 + AD9523_STAT_PLL2_FB_CLK); 595 581 596 596 - static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO, 597 597 - ad9523_show, 598 598 - NULL, 599 599 - AD9523_STAT_PLL2_REF_CLK); 582 582 + static IIO_DEVICE_ATTR(pll2_reference_clk_present, 0444, ad9523_show, NULL, 583 583 + AD9523_STAT_PLL2_REF_CLK); 600 584 601 601 - static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR, 602 602 - NULL, 603 603 - ad9523_store, 604 604 - AD9523_SYNC); 585 585 + static IIO_DEVICE_ATTR(sync_dividers, 0200, NULL, ad9523_store, 586 586 + AD9523_SYNC); 605 587 606 606 - static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR, 607 607 - NULL, 608 608 - ad9523_store, 609 609 - AD9523_EEPROM); 588 588 + static IIO_DEVICE_ATTR(store_eeprom, 0200, NULL, ad9523_store, 589 589 + AD9523_EEPROM); 610 590 611 591 static struct attribute *ad9523_attributes[] = { 612 592 &iio_dev_attr_sync_dividers.dev_attr.attr, ··· 777 797 return ret; 778 798 779 799 ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL, 780 780 - AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata-> 781 781 - pll1_charge_pump_current_nA) | 800 800 + AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata->pll1_charge_pump_current_nA) | 782 801 AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL | 783 802 AD9523_PLL1_BACKLASH_PW_MIN); 784 803 if (ret < 0) ··· 821 842 */ 822 843 823 844 ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP, 824 824 - AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata-> 825 825 - pll2_charge_pump_current_nA)); 845 845 + AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata->pll2_charge_pump_current_nA)); 826 846 if (ret < 0) 827 847 return ret; 828 848 ··· 948 970 949 971 static int ad9523_probe(struct spi_device *spi) 950 972 { 951 951 - struct ad9523_platform_data *pdata = dev_get_platdata(&spi->dev); 973 973 + struct device *dev = &spi->dev; 974 974 + struct ad9523_platform_data *pdata; 952 975 struct iio_dev *indio_dev; 953 976 struct ad9523_state *st; 954 977 int ret; 955 978 956 956 - if (!pdata) { 957 957 - dev_err(&spi->dev, "no platform data?\n"); 958 958 - return -EINVAL; 959 959 - } 979 979 + pdata = dev_get_platdata(dev); 980 980 + if (!pdata) 981 981 + return dev_err_probe(dev, -EINVAL, "no platform data?\n"); 960 982 961 961 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 983 983 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 962 984 if (indio_dev == NULL) 963 985 return -ENOMEM; 964 986 ··· 966 988 967 989 mutex_init(&st->lock); 968 990 969 969 - ret = devm_regulator_get_enable(&spi->dev, "vcc"); 991 991 + ret = devm_regulator_get_enable(dev, "vcc"); 970 992 if (ret) 971 993 return ret; 972 994 973 973 - st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 995 995 + st->pwrdown_gpio = devm_gpiod_get_optional(dev, "powerdown", 974 996 GPIOD_OUT_HIGH); 975 997 if (IS_ERR(st->pwrdown_gpio)) 976 998 return PTR_ERR(st->pwrdown_gpio); 977 999 978 978 - st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", 1000 1000 + st->reset_gpio = devm_gpiod_get_optional(dev, "reset", 979 1001 GPIOD_OUT_LOW); 980 1002 if (IS_ERR(st->reset_gpio)) 981 1003 return PTR_ERR(st->reset_gpio); ··· 985 1007 gpiod_direction_output(st->reset_gpio, 1); 986 1008 } 987 1009 988 988 - st->sync_gpio = devm_gpiod_get_optional(&spi->dev, "sync", 1010 1010 + st->sync_gpio = devm_gpiod_get_optional(dev, "sync", 989 1011 GPIOD_OUT_HIGH); 990 1012 if (IS_ERR(st->sync_gpio)) 991 1013 return PTR_ERR(st->sync_gpio); ··· 1005 1027 if (ret < 0) 1006 1028 return ret; 1007 1029 1008 1008 - return devm_iio_device_register(&spi->dev, indio_dev); 1030 1030 + return devm_iio_device_register(dev, indio_dev); 1009 1031 } 1010 1032 1011 1033 static const struct spi_device_id ad9523_id[] = {

+5 -5

drivers/iio/frequency/adf4350.c

reviewed

··· 152 152 st->r4_rf_div_sel = 0; 153 153 154 154 /* 155 155 - * !\TODO: The below computation is making sure we get a power of 2 156 156 - * shift (st->r4_rf_div_sel) so that freq becomes higher or equal to 157 157 - * ADF4350_MIN_VCO_FREQ. This might be simplified with fls()/fls_long() 158 158 - * and friends. 155 155 + * NOTE: This iteratively shifts freq by a power of 2 156 156 + * (st->r4_rf_div_sel) to meet or exceed ADF4350_MIN_VCO_FREQ. 157 157 + * A constant-time approach using fls_long() was attempted but 158 158 + * deemed more complex without meaningful benefit for init code. 159 159 */ 160 160 while (freq < ADF4350_MIN_VCO_FREQ) { 161 161 freq <<= 1; ··· 607 607 if (dev_fwnode(&spi->dev)) { 608 608 pdata = adf4350_parse_dt(&spi->dev); 609 609 if (pdata == NULL) 610 610 - return -EINVAL; 610 610 + return -ENOMEM; 611 611 } else { 612 612 pdata = dev_get_platdata(&spi->dev); 613 613 }

+26 -30

drivers/iio/frequency/adf4377.c

reviewed

··· 706 706 707 707 static int adf4377_init(struct adf4377_state *st) 708 708 { 709 709 - struct spi_device *spi = st->spi; 709 709 + struct device *dev = &st->spi->dev; 710 710 int ret; 711 711 712 712 adf4377_gpio_init(st); 713 713 714 714 ret = adf4377_soft_reset(st); 715 715 - if (ret) { 716 716 - dev_err(&spi->dev, "Failed to soft reset.\n"); 717 717 - return ret; 718 718 - } 715 715 + if (ret) 716 716 + return dev_err_probe(dev, ret, "Failed to soft reset.\n"); 719 717 720 718 ret = regmap_multi_reg_write(st->regmap, adf4377_reg_defaults, 721 719 ARRAY_SIZE(adf4377_reg_defaults)); 722 722 - if (ret) { 723 723 - dev_err(&spi->dev, "Failed to set default registers.\n"); 724 724 - return ret; 725 725 - } 720 720 + if (ret) 721 721 + return dev_err_probe(dev, ret, 722 722 + "Failed to set default registers.\n"); 726 723 727 724 ret = regmap_update_bits(st->regmap, 0x00, 728 725 ADF4377_0000_SDO_ACTIVE_MSK | ADF4377_0000_SDO_ACTIVE_R_MSK, ··· 727 730 ADF4377_0000_SDO_ACTIVE_SPI_4W) | 728 731 FIELD_PREP(ADF4377_0000_SDO_ACTIVE_R_MSK, 729 732 ADF4377_0000_SDO_ACTIVE_SPI_4W)); 730 730 - if (ret) { 731 731 - dev_err(&spi->dev, "Failed to set 4-Wire Operation.\n"); 732 732 - return ret; 733 733 - } 733 733 + if (ret) 734 734 + return dev_err_probe(dev, ret, 735 735 + "Failed to set 4-Wire Operation.\n"); 734 736 735 737 st->clkin_freq = clk_get_rate(st->clkin); 736 738 ··· 743 747 FIELD_PREP(ADF4377_001A_PD_PFDCP_MSK, 0) | 744 748 FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) | 745 749 FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0)); 746 746 - if (ret) { 747 747 - dev_err(&spi->dev, "Failed to set power down registers.\n"); 748 748 - return ret; 749 749 - } 750 750 + if (ret) 751 751 + return dev_err_probe(dev, ret, 752 752 + "Failed to set power down registers.\n"); 750 753 751 754 /* Set Mux Output */ 752 755 ret = regmap_update_bits(st->regmap, 0x1D, ··· 877 882 878 883 static int adf4377_properties_parse(struct adf4377_state *st) 879 884 { 880 880 - struct spi_device *spi = st->spi; 885 885 + struct device *dev = &st->spi->dev; 881 886 int ret; 882 887 883 883 - st->clkin = devm_clk_get_enabled(&spi->dev, "ref_in"); 888 888 + st->clkin = devm_clk_get_enabled(dev, "ref_in"); 884 889 if (IS_ERR(st->clkin)) 885 885 - return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), 890 890 + return dev_err_probe(dev, PTR_ERR(st->clkin), 886 891 "failed to get the reference input clock\n"); 887 892 888 888 - st->gpio_ce = devm_gpiod_get_optional(&st->spi->dev, "chip-enable", 893 893 + st->gpio_ce = devm_gpiod_get_optional(dev, "chip-enable", 889 894 GPIOD_OUT_LOW); 890 895 if (IS_ERR(st->gpio_ce)) 891 891 - return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_ce), 896 896 + return dev_err_probe(dev, PTR_ERR(st->gpio_ce), 892 897 "failed to get the CE GPIO\n"); 893 898 894 894 - st->gpio_enclk1 = devm_gpiod_get_optional(&st->spi->dev, "clk1-enable", 899 899 + st->gpio_enclk1 = devm_gpiod_get_optional(dev, "clk1-enable", 895 900 GPIOD_OUT_LOW); 896 901 if (IS_ERR(st->gpio_enclk1)) 897 897 - return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_enclk1), 902 902 + return dev_err_probe(dev, PTR_ERR(st->gpio_enclk1), 898 903 "failed to get the CE GPIO\n"); 899 904 900 905 if (st->chip_info->has_gpio_enclk2) { 901 901 - st->gpio_enclk2 = devm_gpiod_get_optional(&st->spi->dev, "clk2-enable", 906 906 + st->gpio_enclk2 = devm_gpiod_get_optional(dev, "clk2-enable", 902 907 GPIOD_OUT_LOW); 903 908 if (IS_ERR(st->gpio_enclk2)) 904 904 - return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_enclk2), 909 909 + return dev_err_probe(dev, PTR_ERR(st->gpio_enclk2), 905 910 "failed to get the CE GPIO\n"); 906 911 } 907 912 908 908 - ret = device_property_match_property_string(&spi->dev, "adi,muxout-select", 913 913 + ret = device_property_match_property_string(dev, "adi,muxout-select", 909 914 adf4377_muxout_modes, 910 915 ARRAY_SIZE(adf4377_muxout_modes)); 911 916 if (ret >= 0) ··· 1050 1055 struct iio_dev *indio_dev; 1051 1056 struct regmap *regmap; 1052 1057 struct adf4377_state *st; 1058 1058 + struct device *dev = &spi->dev; 1053 1059 int ret; 1054 1060 1055 1055 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1061 1061 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1056 1062 if (!indio_dev) 1057 1063 return -ENOMEM; 1058 1064 ··· 1076 1080 return ret; 1077 1081 1078 1082 st->nb.notifier_call = adf4377_freq_change; 1079 1079 - ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb); 1083 1083 + ret = devm_clk_notifier_register(dev, st->clkin, &st->nb); 1080 1084 if (ret) 1081 1085 return ret; 1082 1086 ··· 1093 1097 indio_dev->num_channels = ARRAY_SIZE(adf4377_channels); 1094 1098 } 1095 1099 1096 1096 - return devm_iio_device_register(&spi->dev, indio_dev); 1100 1100 + return devm_iio_device_register(dev, indio_dev); 1097 1101 } 1098 1102 1099 1103 static const struct spi_device_id adf4377_id[] = {

+55 -49

drivers/iio/frequency/admv1013.c

reviewed

··· 85 85 }; 86 86 87 87 enum { 88 88 - ADMV1013_SE_MODE_POS = 6, 89 89 - ADMV1013_SE_MODE_NEG = 9, 90 90 - ADMV1013_SE_MODE_DIFF = 12 88 88 + ADMV1013_SE_MODE_POS, 89 89 + ADMV1013_SE_MODE_NEG, 90 90 + ADMV1013_SE_MODE_DIFF, 91 91 }; 92 92 93 93 struct admv1013_state { ··· 441 441 { 442 442 int ret; 443 443 unsigned int data; 444 444 - struct spi_device *spi = st->spi; 444 444 + struct device *dev = &st->spi->dev; 445 445 446 446 /* Perform a software reset */ 447 447 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL, ··· 461 461 return ret; 462 462 463 463 data = FIELD_GET(ADMV1013_CHIP_ID_MSK, data); 464 464 - if (data != ADMV1013_CHIP_ID) { 465 465 - dev_err(&spi->dev, "Invalid Chip ID.\n"); 466 466 - return -EINVAL; 467 467 - } 464 464 + if (data != ADMV1013_CHIP_ID) 465 465 + return dev_err_probe(dev, -EINVAL, "Invalid Chip ID.\n"); 468 466 469 467 ret = __admv1013_spi_write(st, ADMV1013_REG_VVA_TEMP_COMP, 0xE700); 470 468 if (ret) 471 469 return ret; 472 470 473 473 - data = FIELD_PREP(ADMV1013_QUAD_SE_MODE_MSK, st->quad_se_mode); 471 471 + switch (st->quad_se_mode) { 472 472 + case ADMV1013_SE_MODE_POS: 473 473 + data = 6; 474 474 + break; 475 475 + case ADMV1013_SE_MODE_NEG: 476 476 + data = 9; 477 477 + break; 478 478 + case ADMV1013_SE_MODE_DIFF: 479 479 + data = 12; 480 480 + break; 481 481 + default: 482 482 + return -EINVAL; 483 483 + } 474 484 475 485 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD, 476 476 - ADMV1013_QUAD_SE_MODE_MSK, data); 486 486 + ADMV1013_QUAD_SE_MODE_MSK, 487 487 + FIELD_PREP(ADMV1013_QUAD_SE_MODE_MSK, data)); 477 488 if (ret) 478 489 return ret; 479 490 ··· 525 514 admv1013_spi_update_bits(data, ADMV1013_REG_ENABLE, enable_reg_msk, enable_reg); 526 515 } 527 516 517 517 + static const char * const admv1013_input_modes[] = { 518 518 + [ADMV1013_IQ_MODE] = "iq", 519 519 + [ADMV1013_IF_MODE] = "if", 520 520 + }; 521 521 + 522 522 + static const char * const admv1013_quad_se_modes[] = { 523 523 + [ADMV1013_SE_MODE_POS] = "se-pos", 524 524 + [ADMV1013_SE_MODE_NEG] = "se-neg", 525 525 + [ADMV1013_SE_MODE_DIFF] = "diff", 526 526 + }; 527 527 + 528 528 static int admv1013_properties_parse(struct admv1013_state *st) 529 529 { 530 530 int ret; 531 531 - const char *str; 532 532 - struct spi_device *spi = st->spi; 531 531 + struct device *dev = &st->spi->dev; 533 532 534 534 - st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable"); 533 533 + st->det_en = device_property_read_bool(dev, "adi,detector-enable"); 535 534 536 536 - ret = device_property_read_string(&spi->dev, "adi,input-mode", &str); 537 537 - if (ret) 538 538 - st->input_mode = ADMV1013_IQ_MODE; 535 535 + ret = device_property_match_property_string(dev, "adi,input-mode", 536 536 + admv1013_input_modes, 537 537 + ARRAY_SIZE(admv1013_input_modes)); 538 538 + st->input_mode = ret >= 0 ? ret : ADMV1013_IQ_MODE; 539 539 540 540 - if (!strcmp(str, "iq")) 541 541 - st->input_mode = ADMV1013_IQ_MODE; 542 542 - else if (!strcmp(str, "if")) 543 543 - st->input_mode = ADMV1013_IF_MODE; 544 544 - else 545 545 - return -EINVAL; 540 540 + ret = device_property_match_property_string(dev, "adi,quad-se-mode", 541 541 + admv1013_quad_se_modes, 542 542 + ARRAY_SIZE(admv1013_quad_se_modes)); 543 543 + st->quad_se_mode = ret >= 0 ? ret : ADMV1013_SE_MODE_DIFF; 546 544 547 547 - ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str); 548 548 - if (ret) 549 549 - st->quad_se_mode = ADMV1013_SE_MODE_DIFF; 550 550 - 551 551 - if (!strcmp(str, "diff")) 552 552 - st->quad_se_mode = ADMV1013_SE_MODE_DIFF; 553 553 - else if (!strcmp(str, "se-pos")) 554 554 - st->quad_se_mode = ADMV1013_SE_MODE_POS; 555 555 - else if (!strcmp(str, "se-neg")) 556 556 - st->quad_se_mode = ADMV1013_SE_MODE_NEG; 557 557 - else 558 558 - return -EINVAL; 559 559 - 560 560 - ret = devm_regulator_bulk_get_enable(&st->spi->dev, 545 545 + ret = devm_regulator_bulk_get_enable(dev, 561 546 ARRAY_SIZE(admv1013_vcc_regs), 562 547 admv1013_vcc_regs); 563 548 if (ret) { 564 564 - dev_err_probe(&spi->dev, ret, 549 549 + dev_err_probe(dev, ret, 565 550 "Failed to request VCC regulators\n"); 566 551 return ret; 567 552 } ··· 569 562 { 570 563 struct iio_dev *indio_dev; 571 564 struct admv1013_state *st; 565 565 + struct device *dev = &spi->dev; 572 566 int ret, vcm_uv; 573 567 574 574 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 568 568 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 575 569 if (!indio_dev) 576 570 return -ENOMEM; 577 571 ··· 589 581 if (ret) 590 582 return ret; 591 583 592 592 - ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vcm"); 584 584 + ret = devm_regulator_get_enable_read_voltage(dev, "vcm"); 593 585 if (ret < 0) 594 594 - return dev_err_probe(&spi->dev, ret, 586 586 + return dev_err_probe(dev, ret, 595 587 "failed to get the common-mode voltage\n"); 596 588 597 589 vcm_uv = ret; 598 590 599 599 - st->clkin = devm_clk_get_enabled(&spi->dev, "lo_in"); 591 591 + st->clkin = devm_clk_get_enabled(dev, "lo_in"); 600 592 if (IS_ERR(st->clkin)) 601 601 - return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), 593 593 + return dev_err_probe(dev, PTR_ERR(st->clkin), 602 594 "failed to get the LO input clock\n"); 603 595 604 596 st->nb.notifier_call = admv1013_freq_change; 605 605 - ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb); 597 597 + ret = devm_clk_notifier_register(dev, st->clkin, &st->nb); 606 598 if (ret) 607 599 return ret; 608 600 609 601 mutex_init(&st->lock); 610 602 611 603 ret = admv1013_init(st, vcm_uv); 612 612 - if (ret) { 613 613 - dev_err(&spi->dev, "admv1013 init failed\n"); 614 614 - return ret; 615 615 - } 604 604 + if (ret) 605 605 + return dev_err_probe(dev, ret, "admv1013 init failed\n"); 616 606 617 617 - ret = devm_add_action_or_reset(&spi->dev, admv1013_powerdown, st); 607 607 + ret = devm_add_action_or_reset(dev, admv1013_powerdown, st); 618 608 if (ret) 619 609 return ret; 620 610 621 621 - return devm_iio_device_register(&spi->dev, indio_dev); 611 611 + return devm_iio_device_register(dev, indio_dev); 622 612 } 623 613 624 614 static const struct spi_device_id admv1013_id[] = {

+40 -49

drivers/iio/frequency/admv1014.c

reviewed

··· 610 610 { 611 611 unsigned int chip_id, enable_reg, enable_reg_msk; 612 612 struct spi_device *spi = st->spi; 613 613 + struct device *dev = &spi->dev; 613 614 int ret; 614 615 615 616 ret = regulator_bulk_enable(ADMV1014_NUM_REGULATORS, st->regulators); 616 616 - if (ret) { 617 617 - dev_err(&spi->dev, "Failed to enable regulators"); 618 618 - return ret; 619 619 - } 617 617 + if (ret) 618 618 + return dev_err_probe(dev, ret, "Failed to enable regulators"); 620 619 621 621 - ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->regulators); 620 620 + ret = devm_add_action_or_reset(dev, admv1014_reg_disable, st->regulators); 622 621 if (ret) 623 622 return ret; 624 623 ··· 625 626 if (ret) 626 627 return ret; 627 628 628 628 - ret = devm_add_action_or_reset(&spi->dev, admv1014_clk_disable, st->clkin); 629 629 + ret = devm_add_action_or_reset(dev, admv1014_clk_disable, st->clkin); 629 630 if (ret) 630 631 return ret; 631 632 632 633 st->nb.notifier_call = admv1014_freq_change; 633 633 - ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb); 634 634 + ret = devm_clk_notifier_register(dev, st->clkin, &st->nb); 634 635 if (ret) 635 636 return ret; 636 637 637 637 - ret = devm_add_action_or_reset(&spi->dev, admv1014_powerdown, st); 638 638 + ret = devm_add_action_or_reset(dev, admv1014_powerdown, st); 638 639 if (ret) 639 640 return ret; 640 641 ··· 642 643 ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, 643 644 ADMV1014_SPI_SOFT_RESET_MSK, 644 645 FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 1)); 645 645 - if (ret) { 646 646 - dev_err(&spi->dev, "ADMV1014 SPI software reset failed.\n"); 647 647 - return ret; 648 648 - } 646 646 + if (ret) 647 647 + return dev_err_probe(dev, ret, 648 648 + "ADMV1014 SPI software reset failed.\n"); 649 649 650 650 ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, 651 651 ADMV1014_SPI_SOFT_RESET_MSK, 652 652 FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 0)); 653 653 - if (ret) { 654 654 - dev_err(&spi->dev, "ADMV1014 SPI software reset disable failed.\n"); 655 655 - return ret; 656 656 - } 653 653 + if (ret) 654 654 + return dev_err_probe(dev, ret, 655 655 + "ADMV1014 SPI software reset disable failed.\n"); 657 656 658 657 ret = __admv1014_spi_write(st, ADMV1014_REG_VVA_TEMP_COMP, 0x727C); 659 659 - if (ret) { 660 660 - dev_err(&spi->dev, "Writing default Temperature Compensation value failed.\n"); 661 661 - return ret; 662 662 - } 658 658 + if (ret) 659 659 + return dev_err_probe(dev, ret, 660 660 + "Writing default Temperature Compensation value failed.\n"); 663 661 664 662 ret = __admv1014_spi_read(st, ADMV1014_REG_SPI_CONTROL, &chip_id); 665 663 if (ret) 666 664 return ret; 667 665 668 666 chip_id = FIELD_GET(ADMV1014_CHIP_ID_MSK, chip_id); 669 669 - if (chip_id != ADMV1014_CHIP_ID) { 670 670 - dev_err(&spi->dev, "Invalid Chip ID.\n"); 671 671 - return -EINVAL; 672 672 - } 667 667 + if (chip_id != ADMV1014_CHIP_ID) 668 668 + return dev_err_probe(dev, -EINVAL, "Invalid Chip ID.\n"); 673 669 674 670 ret = __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD, 675 671 ADMV1014_QUAD_SE_MODE_MSK, 676 672 FIELD_PREP(ADMV1014_QUAD_SE_MODE_MSK, 677 673 st->quad_se_mode)); 678 678 - if (ret) { 679 679 - dev_err(&spi->dev, "Writing Quad SE Mode failed.\n"); 680 680 - return ret; 681 681 - } 674 674 + if (ret) 675 675 + return dev_err_probe(dev, ret, 676 676 + "Writing Quad SE Mode failed.\n"); 682 677 683 678 ret = admv1014_update_quad_filters(st); 684 684 - if (ret) { 685 685 - dev_err(&spi->dev, "Update Quad Filters failed.\n"); 686 686 - return ret; 687 687 - } 679 679 + if (ret) 680 680 + return dev_err_probe(dev, ret, 681 681 + "Update Quad Filters failed.\n"); 688 682 689 683 ret = admv1014_update_vcm_settings(st); 690 690 - if (ret) { 691 691 - dev_err(&spi->dev, "Update VCM Settings failed.\n"); 692 692 - return ret; 693 693 - } 684 684 + if (ret) 685 685 + return dev_err_probe(dev, ret, 686 686 + "Update VCM Settings failed.\n"); 694 687 695 688 enable_reg_msk = ADMV1014_P1DB_COMPENSATION_MSK | 696 689 ADMV1014_IF_AMP_PD_MSK | ··· 703 712 { 704 713 unsigned int i; 705 714 struct spi_device *spi = st->spi; 715 715 + struct device *dev = &spi->dev; 706 716 int ret; 707 717 708 708 - st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable"); 718 718 + st->det_en = device_property_read_bool(dev, "adi,detector-enable"); 709 719 710 710 - st->p1db_comp = device_property_read_bool(&spi->dev, "adi,p1db-compensation-enable"); 720 720 + st->p1db_comp = device_property_read_bool(dev, "adi,p1db-compensation-enable"); 711 721 712 712 - ret = device_property_match_property_string(&spi->dev, "adi,input-mode", 722 722 + ret = device_property_match_property_string(dev, "adi,input-mode", 713 723 input_mode_names, 714 724 ARRAY_SIZE(input_mode_names)); 715 725 if (ret >= 0) ··· 718 726 else 719 727 st->input_mode = ADMV1014_IQ_MODE; 720 728 721 721 - ret = device_property_match_property_string(&spi->dev, "adi,quad-se-mode", 729 729 + ret = device_property_match_property_string(dev, "adi,quad-se-mode", 722 730 quad_se_mode_names, 723 731 ARRAY_SIZE(quad_se_mode_names)); 724 732 if (ret >= 0) ··· 729 737 for (i = 0; i < ADMV1014_NUM_REGULATORS; ++i) 730 738 st->regulators[i].supply = admv1014_reg_name[i]; 731 739 732 732 - ret = devm_regulator_bulk_get(&st->spi->dev, ADMV1014_NUM_REGULATORS, 740 740 + ret = devm_regulator_bulk_get(dev, ADMV1014_NUM_REGULATORS, 733 741 st->regulators); 734 734 - if (ret) { 735 735 - dev_err(&spi->dev, "Failed to request regulators"); 736 736 - return ret; 737 737 - } 742 742 + if (ret) 743 743 + return dev_err_probe(dev, ret, "Failed to request regulators"); 738 744 739 739 - st->clkin = devm_clk_get(&spi->dev, "lo_in"); 745 745 + st->clkin = devm_clk_get(dev, "lo_in"); 740 746 if (IS_ERR(st->clkin)) 741 741 - return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), 747 747 + return dev_err_probe(dev, PTR_ERR(st->clkin), 742 748 "failed to get the LO input clock\n"); 743 749 744 750 return 0; ··· 746 756 { 747 757 struct iio_dev *indio_dev; 748 758 struct admv1014_state *st; 759 759 + struct device *dev = &spi->dev; 749 760 int ret; 750 761 751 751 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 762 762 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 752 763 if (!indio_dev) 753 764 return -ENOMEM; 754 765 ··· 778 787 if (ret) 779 788 return ret; 780 789 781 781 - return devm_iio_device_register(&spi->dev, indio_dev); 790 790 + return devm_iio_device_register(dev, indio_dev); 782 791 } 783 792 784 793 static const struct spi_device_id admv1014_id[] = {

+17 -20

drivers/iio/frequency/admv4420.c

reviewed

··· 243 243 st->n_counter.n_counter = 1; 244 244 } 245 245 if (!sol_found) 246 246 - return -1; 246 246 + return -EINVAL; 247 247 248 248 st->n_counter.int_val = div_u64_rem(st->n_counter.n_counter, 10, &st->n_counter.frac_val); 249 249 st->n_counter.mod_val = 10; ··· 279 279 if (ret) 280 280 return ret; 281 281 282 282 - if (val != ADMV4420_SCRATCH_PAD_VAL_1) { 283 283 - dev_err(dev, "Failed ADMV4420 to read/write scratchpad %x ", val); 284 284 - return -EIO; 285 285 - } 282 282 + if (val != ADMV4420_SCRATCH_PAD_VAL_1) 283 283 + return dev_err_probe(dev, -EIO, 284 284 + "Failed ADMV4420 to read/write scratchpad %x\n", val); 286 285 287 286 ret = regmap_write(st->regmap, 288 287 ADMV4420_SCRATCHPAD, ··· 293 294 if (ret) 294 295 return ret; 295 296 296 296 - if (val != ADMV4420_SCRATCH_PAD_VAL_2) { 297 297 - dev_err(dev, "Failed to read/write scratchpad %x ", val); 298 298 - return -EIO; 299 299 - } 297 297 + if (val != ADMV4420_SCRATCH_PAD_VAL_2) 298 298 + return dev_err_probe(dev, -EIO, 299 299 + "Failed to read/write scratchpad %x\n", val); 300 300 301 301 st->mux_sel = ADMV4420_LOCK_DTCT; 302 302 st->lo_freq_hz = ADMV4420_DEFAULT_LO_FREQ_HZ; ··· 303 305 admv4420_fw_parse(st); 304 306 305 307 ret = admv4420_calc_parameters(st); 306 306 - if (ret) { 307 307 - dev_err(dev, "Failed calc parameters for %lld ", st->vco_freq_hz); 308 308 - return ret; 309 309 - } 308 308 + if (ret) 309 309 + return dev_err_probe(dev, ret, 310 310 + "Failed calc parameters for %llu\n", 311 311 + st->vco_freq_hz); 310 312 311 313 ret = regmap_write(st->regmap, ADMV4420_R_DIV_L, 312 314 FIELD_GET(0xFF, st->ref_block.divider)); ··· 342 344 343 345 static int admv4420_probe(struct spi_device *spi) 344 346 { 347 347 + struct device *dev = &spi->dev; 345 348 struct iio_dev *indio_dev; 346 349 struct admv4420_state *st; 347 350 struct regmap *regmap; 348 351 int ret; 349 352 350 350 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 353 353 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 351 354 if (!indio_dev) 352 355 return -ENOMEM; 353 356 354 357 regmap = devm_regmap_init_spi(spi, &admv4420_regmap_config); 355 358 if (IS_ERR(regmap)) 356 356 - return dev_err_probe(&spi->dev, PTR_ERR(regmap), 359 359 + return dev_err_probe(dev, PTR_ERR(regmap), 357 360 "Failed to initializing spi regmap\n"); 358 361 359 362 st = iio_priv(indio_dev); ··· 367 368 indio_dev->num_channels = ARRAY_SIZE(admv4420_channels); 368 369 369 370 ret = admv4420_setup(indio_dev); 370 370 - if (ret) { 371 371 - dev_err(&spi->dev, "Setup ADMV4420 failed (%d)\n", ret); 372 372 - return ret; 373 373 - } 371 371 + if (ret) 372 372 + return dev_err_probe(dev, ret, "Setup ADMV4420 failed\n"); 374 373 375 375 - return devm_iio_device_register(&spi->dev, indio_dev); 374 374 + return devm_iio_device_register(dev, indio_dev); 376 375 } 377 376 378 377 static const struct of_device_id admv4420_of_match[] = {

+28 -30

drivers/iio/frequency/adrf6780.c

reviewed

··· 346 346 static int adrf6780_reset(struct adrf6780_state *st) 347 347 { 348 348 int ret; 349 349 - struct spi_device *spi = st->spi; 349 349 + struct device *dev = &st->spi->dev; 350 350 351 351 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL, 352 352 ADRF6780_SOFT_RESET_MSK, 353 353 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 1)); 354 354 - if (ret) { 355 355 - dev_err(&spi->dev, "ADRF6780 SPI software reset failed.\n"); 356 356 - return ret; 357 357 - } 354 354 + if (ret) 355 355 + return dev_err_probe(dev, ret, 356 356 + "ADRF6780 SPI software reset failed.\n"); 358 357 359 358 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL, 360 359 ADRF6780_SOFT_RESET_MSK, 361 360 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 0)); 362 362 - if (ret) { 363 363 - dev_err(&spi->dev, "ADRF6780 SPI software reset disable failed.\n"); 364 364 - return ret; 365 365 - } 361 361 + if (ret) 362 362 + return dev_err_probe(dev, ret, 363 363 + "ADRF6780 SPI software reset disable failed.\n"); 366 364 367 365 return 0; 368 366 } ··· 369 371 { 370 372 int ret; 371 373 unsigned int chip_id, enable_reg, enable_reg_msk; 372 372 - struct spi_device *spi = st->spi; 374 374 + struct device *dev = &st->spi->dev; 373 375 374 376 /* Perform a software reset */ 375 377 ret = adrf6780_reset(st); ··· 381 383 return ret; 382 384 383 385 chip_id = FIELD_GET(ADRF6780_CHIP_ID_MSK, chip_id); 384 384 - if (chip_id != ADRF6780_CHIP_ID) { 385 385 - dev_err(&spi->dev, "ADRF6780 Invalid Chip ID.\n"); 386 386 - return -EINVAL; 387 387 - } 386 386 + if (chip_id != ADRF6780_CHIP_ID) 387 387 + return dev_err_probe(dev, -EINVAL, 388 388 + "ADRF6780 Invalid Chip ID.\n"); 388 389 389 390 enable_reg_msk = ADRF6780_VGA_BUFFER_EN_MSK | 390 391 ADRF6780_DETECTOR_EN_MSK | ··· 423 426 424 427 static void adrf6780_properties_parse(struct adrf6780_state *st) 425 428 { 426 426 - struct spi_device *spi = st->spi; 429 429 + struct device *dev = &st->spi->dev; 427 430 428 428 - st->vga_buff_en = device_property_read_bool(&spi->dev, "adi,vga-buff-en"); 429 429 - st->lo_buff_en = device_property_read_bool(&spi->dev, "adi,lo-buff-en"); 430 430 - st->if_mode_en = device_property_read_bool(&spi->dev, "adi,if-mode-en"); 431 431 - st->iq_mode_en = device_property_read_bool(&spi->dev, "adi,iq-mode-en"); 432 432 - st->lo_x2_en = device_property_read_bool(&spi->dev, "adi,lo-x2-en"); 433 433 - st->lo_ppf_en = device_property_read_bool(&spi->dev, "adi,lo-ppf-en"); 434 434 - st->lo_en = device_property_read_bool(&spi->dev, "adi,lo-en"); 435 435 - st->uc_bias_en = device_property_read_bool(&spi->dev, "adi,uc-bias-en"); 436 436 - st->lo_sideband = device_property_read_bool(&spi->dev, "adi,lo-sideband"); 437 437 - st->vdet_out_en = device_property_read_bool(&spi->dev, "adi,vdet-out-en"); 431 431 + st->vga_buff_en = device_property_read_bool(dev, "adi,vga-buff-en"); 432 432 + st->lo_buff_en = device_property_read_bool(dev, "adi,lo-buff-en"); 433 433 + st->if_mode_en = device_property_read_bool(dev, "adi,if-mode-en"); 434 434 + st->iq_mode_en = device_property_read_bool(dev, "adi,iq-mode-en"); 435 435 + st->lo_x2_en = device_property_read_bool(dev, "adi,lo-x2-en"); 436 436 + st->lo_ppf_en = device_property_read_bool(dev, "adi,lo-ppf-en"); 437 437 + st->lo_en = device_property_read_bool(dev, "adi,lo-en"); 438 438 + st->uc_bias_en = device_property_read_bool(dev, "adi,uc-bias-en"); 439 439 + st->lo_sideband = device_property_read_bool(dev, "adi,lo-sideband"); 440 440 + st->vdet_out_en = device_property_read_bool(dev, "adi,vdet-out-en"); 438 441 } 439 442 440 443 static void adrf6780_powerdown(void *data) ··· 447 450 { 448 451 struct iio_dev *indio_dev; 449 452 struct adrf6780_state *st; 453 453 + struct device *dev = &spi->dev; 450 454 int ret; 451 455 452 452 - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 456 456 + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 453 457 if (!indio_dev) 454 458 return -ENOMEM; 455 459 ··· 465 467 466 468 adrf6780_properties_parse(st); 467 469 468 468 - st->clkin = devm_clk_get_enabled(&spi->dev, "lo_in"); 470 470 + st->clkin = devm_clk_get_enabled(dev, "lo_in"); 469 471 if (IS_ERR(st->clkin)) 470 470 - return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), 472 472 + return dev_err_probe(dev, PTR_ERR(st->clkin), 471 473 "failed to get the LO input clock\n"); 472 474 473 475 mutex_init(&st->lock); ··· 476 478 if (ret) 477 479 return ret; 478 480 479 479 - ret = devm_add_action_or_reset(&spi->dev, adrf6780_powerdown, st); 481 481 + ret = devm_add_action_or_reset(dev, adrf6780_powerdown, st); 480 482 if (ret) 481 483 return ret; 482 484 483 483 - return devm_iio_device_register(&spi->dev, indio_dev); 485 485 + return devm_iio_device_register(dev, indio_dev); 484 486 } 485 487 486 488 static const struct spi_device_id adrf6780_id[] = {

+3 -3

drivers/iio/gyro/hid-sensor-gyro-3d.c

reviewed

··· 42 42 HID_USAGE_SENSOR_ANGL_VELOCITY_Z_AXIS 43 43 }; 44 44 45 45 - static const u32 gryo_3d_sensitivity_addresses[] = { 45 45 + static const u32 gyro_3d_sensitivity_addresses[] = { 46 46 HID_USAGE_SENSOR_DATA_ANGL_VELOCITY, 47 47 }; 48 48 ··· 297 297 ret = hid_sensor_parse_common_attributes(hsdev, 298 298 HID_USAGE_SENSOR_GYRO_3D, 299 299 &gyro_state->common_attributes, 300 300 - gryo_3d_sensitivity_addresses, 301 301 - ARRAY_SIZE(gryo_3d_sensitivity_addresses)); 300 300 + gyro_3d_sensitivity_addresses, 301 301 + ARRAY_SIZE(gyro_3d_sensitivity_addresses)); 302 302 if (ret) { 303 303 dev_err(&pdev->dev, "failed to setup common attributes\n"); 304 304 return ret;

-1

drivers/iio/humidity/hdc2010.c

reviewed

··· 44 44 struct i2c_client *client; 45 45 struct mutex lock; 46 46 u8 measurement_config; 47 47 - u8 interrupt_config; 48 47 u8 drdy_config; 49 48 }; 50 49

-1

drivers/iio/imu/bmi323/bmi323_core.c

reviewed

··· 156 156 struct iio_mount_matrix orientation; 157 157 enum bmi323_irq_pin irq_pin; 158 158 struct iio_trigger *trig; 159 159 - bool drdy_trigger_enabled; 160 159 enum bmi323_state state; 161 160 s64 fifo_tstamp, old_fifo_tstamp; 162 161 u32 odrns[BMI323_SENSORS_CNT];

+1 -1

drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c

reviewed

··· 1211 1211 ssize_t i, size; 1212 1212 unsigned int no; 1213 1213 const void *accel, *gyro, *timestamp; 1214 1214 - const int8_t *temp; 1214 1214 + const s8 *temp; 1215 1215 unsigned int odr; 1216 1216 int64_t ts_val; 1217 1217 /* buffer is copied to userspace, zeroing it to avoid any data leak */

+1 -1

drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c

reviewed

··· 125 125 } 126 126 127 127 /* 128 128 - * Sensitivity adjustement and scale to Gauss 128 128 + * Sensitivity adjustment and scale to Gauss 129 129 * 130 130 * Hadj = H * (((ASA - 128) * 0.5 / 128) + 1) 131 131 * Factor simplification:

+1

drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c

reviewed

··· 144 144 145 145 static const struct acpi_device_id st_lsm6dsx_i2c_acpi_match[] = { 146 146 { "SMO8B30", ST_LSM6DS3TRC_ID, }, 147 147 + { "SMOCF00", ST_LSM6DSO_ID, }, 147 148 { } 148 149 }; 149 150 MODULE_DEVICE_TABLE(acpi, st_lsm6dsx_i2c_acpi_match);

+18 -4

drivers/iio/industrialio-backend.c

reviewed

··· 56 56 void *priv; 57 57 const char *name; 58 58 unsigned int cached_reg_addr; 59 59 + u32 caps; 59 60 /* 60 61 * This index is relative to the frontend. Meaning that for 61 62 * frontends with multiple backends, this will be the index of this ··· 775 774 } 776 775 EXPORT_SYMBOL_NS_GPL(iio_backend_extend_chan_spec, "IIO_BACKEND"); 777 776 777 777 + /** 778 778 + * iio_backend_has_caps - Check if backend has specific capabilities 779 779 + * @back: Backend device 780 780 + * @caps: Capabilities to check 781 781 + * 782 782 + * RETURNS: 783 783 + * True if backend has all the requested capabilities, false otherwise. 784 784 + */ 785 785 + bool iio_backend_has_caps(struct iio_backend *back, u32 caps) 786 786 + { 787 787 + return (back->caps & caps) == caps; 788 788 + } 789 789 + EXPORT_SYMBOL_NS_GPL(iio_backend_has_caps, "IIO_BACKEND"); 790 790 + 778 791 static void iio_backend_release(void *arg) 779 792 { 780 793 struct iio_backend *back = arg; ··· 967 952 static struct iio_backend *__devm_iio_backend_fwnode_get(struct device *dev, const char *name, 968 953 struct fwnode_handle *fwnode) 969 954 { 970 970 - struct fwnode_handle *fwnode_back; 971 955 struct iio_backend *back; 972 956 unsigned int index; 973 957 int ret; ··· 981 967 index = 0; 982 968 } 983 969 984 984 - fwnode_back = fwnode_find_reference(fwnode, "io-backends", index); 970 970 + struct fwnode_handle *fwnode_back __free(fwnode_handle) = 971 971 + fwnode_find_reference(fwnode, "io-backends", index); 985 972 if (IS_ERR(fwnode_back)) 986 973 return dev_err_cast_probe(dev, fwnode_back, 987 974 "Cannot get Firmware reference\n"); ··· 992 977 if (!device_match_fwnode(back->dev, fwnode_back)) 993 978 continue; 994 979 995 995 - fwnode_handle_put(fwnode_back); 996 980 ret = __devm_iio_backend_get(dev, back); 997 981 if (ret) 998 982 return ERR_PTR(ret); ··· 1002 988 return back; 1003 989 } 1004 990 1005 1005 - fwnode_handle_put(fwnode_back); 1006 991 return ERR_PTR(-EPROBE_DEFER); 1007 992 } 1008 993 ··· 1127 1114 1128 1115 back->ops = info->ops; 1129 1116 back->name = info->name; 1117 1117 + back->caps = info->caps; 1130 1118 back->owner = dev->driver->owner; 1131 1119 back->dev = dev; 1132 1120 back->priv = priv;

+1

drivers/iio/industrialio-event.c

reviewed

··· 256 256 [IIO_EV_INFO_TAP2_MIN_DELAY] = "tap2_min_delay", 257 257 [IIO_EV_INFO_RUNNING_PERIOD] = "runningperiod", 258 258 [IIO_EV_INFO_RUNNING_COUNT] = "runningcount", 259 259 + [IIO_EV_INFO_SCALE] = "scale", 259 260 }; 260 261 261 262 static enum iio_event_direction iio_ev_attr_dir(struct iio_dev_attr *attr)

+15 -18

drivers/iio/industrialio-trigger.c

reviewed

··· 561 561 if (!trig) 562 562 return NULL; 563 563 564 564 - trig->dev.parent = parent; 565 565 - trig->dev.type = &iio_trig_type; 566 566 - trig->dev.bus = &iio_bus_type; 567 567 - device_initialize(&trig->dev); 568 564 INIT_WORK(&trig->reenable_work, iio_reenable_work_fn); 569 565 570 566 mutex_init(&trig->pool_lock); ··· 587 591 irq_modify_status(trig->subirq_base + i, 588 592 IRQ_NOREQUEST | IRQ_NOAUTOEN, IRQ_NOPROBE); 589 593 } 594 594 + 595 595 + trig->dev.parent = parent; 596 596 + trig->dev.type = &iio_trig_type; 597 597 + trig->dev.bus = &iio_bus_type; 598 598 + device_initialize(&trig->dev); 590 599 591 600 return trig; 592 601 ··· 635 634 } 636 635 EXPORT_SYMBOL(iio_trigger_free); 637 636 638 638 - static void devm_iio_trigger_release(struct device *dev, void *res) 637 637 + static void devm_iio_trigger_release(void *trig) 639 638 { 640 640 - iio_trigger_free(*(struct iio_trigger **)res); 639 639 + iio_trigger_free(trig); 641 640 } 642 641 643 642 /** ··· 659 658 struct module *this_mod, 660 659 const char *fmt, ...) 661 660 { 662 662 - struct iio_trigger **ptr, *trig; 661 661 + struct iio_trigger *trig; 663 662 va_list vargs; 664 664 - 665 665 - ptr = devres_alloc(devm_iio_trigger_release, sizeof(*ptr), 666 666 - GFP_KERNEL); 667 667 - if (!ptr) 668 668 - return NULL; 663 663 + int ret; 669 664 670 665 /* use raw alloc_dr for kmalloc caller tracing */ 671 666 va_start(vargs, fmt); 672 667 trig = viio_trigger_alloc(parent, this_mod, fmt, vargs); 673 668 va_end(vargs); 674 674 - if (trig) { 675 675 - *ptr = trig; 676 676 - devres_add(parent, ptr); 677 677 - } else { 678 678 - devres_free(ptr); 679 679 - } 669 669 + if (!trig) 670 670 + return NULL; 671 671 + 672 672 + ret = devm_add_action_or_reset(parent, devm_iio_trigger_release, trig); 673 673 + if (ret) 674 674 + return NULL; 680 675 681 676 return trig; 682 677 }

+1 -1

drivers/iio/light/Kconfig

reviewed

··· 359 359 select IIO_KFIFO_BUF 360 360 help 361 361 Enable support for the ROHM BU27034 ambient light sensor. ROHM BU27034 362 362 - is an ambient light sesnor with 3 channels and 3 photo diodes capable 362 362 + is an ambient light sensor with 3 channels and 3 photo diodes capable 363 363 of detecting a very wide range of illuminance. 364 364 Typical application is adjusting LCD and backlight power of TVs and 365 365 mobile phones.

+26 -16

drivers/iio/light/acpi-als.c

reviewed

··· 18 18 #include <linux/err.h> 19 19 #include <linux/irq.h> 20 20 #include <linux/mutex.h> 21 21 + #include <linux/platform_device.h> 21 22 22 23 #include <linux/iio/iio.h> 23 24 #include <linux/iio/buffer.h> ··· 91 90 return 0; 92 91 } 93 92 94 94 - static void acpi_als_notify(struct acpi_device *device, u32 event) 93 93 + static void acpi_als_notify(acpi_handle handle, u32 event, void *data) 95 94 { 96 96 - struct iio_dev *indio_dev = acpi_driver_data(device); 95 95 + struct iio_dev *indio_dev = data; 97 96 struct acpi_als *als = iio_priv(indio_dev); 98 97 99 98 if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev)) { ··· 103 102 break; 104 103 default: 105 104 /* Unhandled event */ 106 106 - dev_dbg(&device->dev, 105 105 + dev_dbg(&als->device->dev, 107 106 "Unhandled ACPI ALS event (%08x)!\n", 108 107 event); 109 108 } ··· 176 175 return IRQ_HANDLED; 177 176 } 178 177 179 179 - static int acpi_als_add(struct acpi_device *device) 178 178 + static int acpi_als_probe(struct platform_device *pdev) 180 179 { 181 181 - struct device *dev = &device->dev; 180 180 + struct device *dev = &pdev->dev; 181 181 + struct acpi_device *device = ACPI_COMPANION(dev); 182 182 struct iio_dev *indio_dev; 183 183 struct acpi_als *als; 184 184 int ret; ··· 190 188 191 189 als = iio_priv(indio_dev); 192 190 193 193 - device->driver_data = indio_dev; 194 191 als->device = device; 195 192 mutex_init(&als->lock); 196 193 ··· 219 218 if (ret) 220 219 return ret; 221 220 222 222 - return devm_iio_device_register(dev, indio_dev); 221 221 + ret = devm_iio_device_register(dev, indio_dev); 222 222 + if (ret) 223 223 + return ret; 224 224 + 225 225 + return acpi_dev_install_notify_handler(device, ACPI_DEVICE_NOTIFY, 226 226 + acpi_als_notify, indio_dev); 227 227 + } 228 228 + 229 229 + static void acpi_als_remove(struct platform_device *pdev) 230 230 + { 231 231 + acpi_dev_remove_notify_handler(ACPI_COMPANION(&pdev->dev), 232 232 + ACPI_DEVICE_NOTIFY, acpi_als_notify); 223 233 } 224 234 225 235 static const struct acpi_device_id acpi_als_device_ids[] = { ··· 240 228 241 229 MODULE_DEVICE_TABLE(acpi, acpi_als_device_ids); 242 230 243 243 - static struct acpi_driver acpi_als_driver = { 244 244 - .name = "acpi_als", 245 245 - .class = ACPI_ALS_CLASS, 246 246 - .ids = acpi_als_device_ids, 247 247 - .ops = { 248 248 - .add = acpi_als_add, 249 249 - .notify = acpi_als_notify, 231 231 + static struct platform_driver acpi_als_driver = { 232 232 + .probe = acpi_als_probe, 233 233 + .remove = acpi_als_remove, 234 234 + .driver = { 235 235 + .name = "acpi_als", 236 236 + .acpi_match_table = acpi_als_device_ids, 250 237 }, 251 238 }; 252 252 - 253 253 - module_acpi_driver(acpi_als_driver); 239 239 + module_platform_driver(acpi_als_driver); 254 240 255 241 MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>"); 256 242 MODULE_AUTHOR("Martin Liska <marxin.liska@gmail.com>");

+1 -1

drivers/iio/light/apds9160.c

reviewed

··· 620 620 621 621 /* 622 622 * The PS intelligent cancellation level register allows 623 623 - * for an on-chip substraction of the ADC count caused by 623 623 + * for an on-chip subtraction of the ADC count caused by 624 624 * unwanted reflected light from PS ADC output. 625 625 */ 626 626 static int apds9160_set_ps_cancellation_level(struct apds9160_chip *data,

+1 -3

drivers/iio/light/apds9306.c

reviewed

··· 168 168 * respectively. 169 169 * @regmap: Regmap structure pointer 170 170 * @rf: Regmap register fields structure 171 171 - * @nlux_per_count: Nano lux per ADC count for a particular model 172 171 * @read_data_available: Flag set by IRQ handler for ADC data available 173 172 */ 174 173 struct apds9306_data { ··· 179 180 struct regmap *regmap; 180 181 struct apds9306_regfields rf; 181 182 182 182 - int nlux_per_count; 183 183 int read_data_available; 184 184 }; 185 185 ··· 1174 1176 1175 1177 static void apds9306_powerdown(void *ptr) 1176 1178 { 1177 1177 - struct apds9306_data *data = (struct apds9306_data *)ptr; 1179 1179 + struct apds9306_data *data = ptr; 1178 1180 struct apds9306_regfields *rf = &data->rf; 1179 1181 int ret; 1180 1182

-3

drivers/iio/light/as73211.c

reviewed

··· 677 677 (char *)&scan.chan[0], 3 * sizeof(scan.chan[0])); 678 678 if (ret < 0) 679 679 goto done; 680 680 - 681 681 - /* Avoid pushing uninitialized data */ 682 682 - scan.chan[3] = 0; 683 680 } 684 681 685 682 if (data_result) {

+123 -187

drivers/iio/light/gp2ap020a00f.c

reviewed

··· 31 31 * the other one. 32 32 */ 33 33 34 34 + #include <linux/cleanup.h> 34 35 #include <linux/debugfs.h> 35 36 #include <linux/delay.h> 36 37 #include <linux/i2c.h> 37 38 #include <linux/interrupt.h> 38 39 #include <linux/irq.h> 39 40 #include <linux/irq_work.h> 41 41 + #include <linux/minmax.h> 40 42 #include <linux/module.h> 41 43 #include <linux/mod_devicetable.h> 42 44 #include <linux/mutex.h> ··· 46 44 #include <linux/regulator/consumer.h> 47 45 #include <linux/slab.h> 48 46 #include <linux/unaligned.h> 47 47 + 49 48 #include <linux/iio/buffer.h> 50 49 #include <linux/iio/events.h> 51 50 #include <linux/iio/iio.h> ··· 54 51 #include <linux/iio/trigger.h> 55 52 #include <linux/iio/trigger_consumer.h> 56 53 #include <linux/iio/triggered_buffer.h> 57 57 - 58 58 - #define GP2A_I2C_NAME "gp2ap020a00f" 59 54 60 55 /* Registers */ 61 56 #define GP2AP020A00F_OP_REG 0x00 /* Basic operations */ ··· 175 174 #define GP2AP020A00F_CHAN_TIMESTAMP 3 176 175 177 176 #define GP2AP020A00F_DATA_READY_TIMEOUT msecs_to_jiffies(1000) 178 178 - #define GP2AP020A00F_DATA_REG(chan) (GP2AP020A00F_D0_L_REG + \ 179 179 - (chan) * 2) 180 180 - #define GP2AP020A00F_THRESH_REG(th_val_id) (GP2AP020A00F_TL_L_REG + \ 181 181 - (th_val_id) * 2) 177 177 + #define GP2AP020A00F_DATA_REG(chan) (GP2AP020A00F_D0_L_REG + (chan) * 2) 178 178 + #define GP2AP020A00F_THRESH_REG(th_val_id) (GP2AP020A00F_TL_L_REG + (th_val_id) * 2) 182 179 #define GP2AP020A00F_THRESH_VAL_ID(reg_addr) ((reg_addr - 4) / 2) 183 180 184 181 #define GP2AP020A00F_SUBTRACT_MODE 0 ··· 193 194 GP2AP020A00F_OPMODE_ALS_AND_PS, 194 195 GP2AP020A00F_OPMODE_PROX_DETECT, 195 196 GP2AP020A00F_OPMODE_SHUTDOWN, 196 196 - GP2AP020A00F_NUM_OPMODES, 197 197 + GP2AP020A00F_NUM_OPMODES 197 198 }; 198 199 199 200 enum gp2ap020a00f_cmd { ··· 245 246 struct iio_trigger *trig; 246 247 struct regmap *regmap; 247 248 unsigned int thresh_val[4]; 248 248 - u8 debug_reg_addr; 249 249 struct irq_work work; 250 250 wait_queue_head_t data_ready_queue; 251 251 }; ··· 387 389 } 388 390 389 391 err = regmap_update_bits(data->regmap, GP2AP020A00F_ALS_REG, 390 390 - GP2AP020A00F_PRST_MASK, opmode_regs_settings[op] 391 391 - .als_reg); 392 392 + GP2AP020A00F_PRST_MASK, opmode_regs_settings[op].als_reg); 392 393 if (err < 0) 393 394 return err; 394 395 395 396 err = regmap_update_bits(data->regmap, GP2AP020A00F_PS_REG, 396 396 - GP2AP020A00F_INTTYPE_MASK, opmode_regs_settings[op] 397 397 - .ps_reg); 397 397 + GP2AP020A00F_INTTYPE_MASK, opmode_regs_settings[op].ps_reg); 398 398 if (err < 0) 399 399 return err; 400 400 401 401 err = regmap_update_bits(data->regmap, GP2AP020A00F_LED_REG, 402 402 - GP2AP020A00F_PIN_MASK, opmode_regs_settings[op] 403 403 - .led_reg); 402 402 + GP2AP020A00F_PIN_MASK, opmode_regs_settings[op].led_reg); 404 403 if (err < 0) 405 404 return err; 406 405 } ··· 448 453 */ 449 454 thresh_reg_val = data->thresh_val[th_val_id] / 16; 450 455 else 451 451 - thresh_reg_val = data->thresh_val[th_val_id] > 16000 ? 452 452 - 16000 : 453 453 - data->thresh_val[th_val_id]; 456 456 + thresh_reg_val = min(data->thresh_val[th_val_id], 16000U); 454 457 455 458 thresh_buf = cpu_to_le16(thresh_reg_val); 456 459 457 460 return regmap_bulk_write(data->regmap, 458 461 GP2AP020A00F_THRESH_REG(th_val_id), 459 459 - (u8 *)&thresh_buf, 2); 462 462 + &thresh_buf, sizeof(thresh_buf)); 460 463 } 461 464 462 465 static int gp2ap020a00f_alter_opmode(struct gp2ap020a00f_data *data, ··· 486 493 static int gp2ap020a00f_exec_cmd(struct gp2ap020a00f_data *data, 487 494 enum gp2ap020a00f_cmd cmd) 488 495 { 489 489 - int err = 0; 496 496 + int err; 490 497 491 498 switch (cmd) { 492 499 case GP2AP020A00F_CMD_READ_RAW_CLEAR: 493 500 if (data->cur_opmode != GP2AP020A00F_OPMODE_SHUTDOWN) 494 501 return -EBUSY; 495 495 - err = gp2ap020a00f_set_operation_mode(data, 502 502 + return gp2ap020a00f_set_operation_mode(data, 496 503 GP2AP020A00F_OPMODE_READ_RAW_CLEAR); 497 497 - break; 498 504 case GP2AP020A00F_CMD_READ_RAW_IR: 499 505 if (data->cur_opmode != GP2AP020A00F_OPMODE_SHUTDOWN) 500 506 return -EBUSY; 501 501 - err = gp2ap020a00f_set_operation_mode(data, 507 507 + return gp2ap020a00f_set_operation_mode(data, 502 508 GP2AP020A00F_OPMODE_READ_RAW_IR); 503 503 - break; 504 509 case GP2AP020A00F_CMD_READ_RAW_PROXIMITY: 505 510 if (data->cur_opmode != GP2AP020A00F_OPMODE_SHUTDOWN) 506 511 return -EBUSY; 507 507 - err = gp2ap020a00f_set_operation_mode(data, 512 512 + return gp2ap020a00f_set_operation_mode(data, 508 513 GP2AP020A00F_OPMODE_READ_RAW_PROXIMITY); 509 509 - break; 510 514 case GP2AP020A00F_CMD_TRIGGER_CLEAR_EN: 511 515 if (data->cur_opmode == GP2AP020A00F_OPMODE_PROX_DETECT) 512 516 return -EBUSY; ··· 511 521 err = gp2ap020a00f_alter_opmode(data, 512 522 GP2AP020A00F_OPMODE_ALS, 513 523 GP2AP020A00F_ADD_MODE); 524 524 + else 525 525 + err = 0; 514 526 set_bit(GP2AP020A00F_FLAG_ALS_CLEAR_TRIGGER, &data->flags); 515 515 - break; 527 527 + return err; 516 528 case GP2AP020A00F_CMD_TRIGGER_CLEAR_DIS: 517 529 clear_bit(GP2AP020A00F_FLAG_ALS_CLEAR_TRIGGER, &data->flags); 518 530 if (gp2ap020a00f_als_enabled(data)) 519 531 break; 520 520 - err = gp2ap020a00f_alter_opmode(data, 532 532 + return gp2ap020a00f_alter_opmode(data, 521 533 GP2AP020A00F_OPMODE_ALS, 522 534 GP2AP020A00F_SUBTRACT_MODE); 523 523 - break; 524 535 case GP2AP020A00F_CMD_TRIGGER_IR_EN: 525 536 if (data->cur_opmode == GP2AP020A00F_OPMODE_PROX_DETECT) 526 537 return -EBUSY; ··· 529 538 err = gp2ap020a00f_alter_opmode(data, 530 539 GP2AP020A00F_OPMODE_ALS, 531 540 GP2AP020A00F_ADD_MODE); 541 541 + else 542 542 + err = 0; 532 543 set_bit(GP2AP020A00F_FLAG_ALS_IR_TRIGGER, &data->flags); 533 533 - break; 544 544 + return err; 534 545 case GP2AP020A00F_CMD_TRIGGER_IR_DIS: 535 546 clear_bit(GP2AP020A00F_FLAG_ALS_IR_TRIGGER, &data->flags); 536 547 if (gp2ap020a00f_als_enabled(data)) 537 548 break; 538 538 - err = gp2ap020a00f_alter_opmode(data, 549 549 + return gp2ap020a00f_alter_opmode(data, 539 550 GP2AP020A00F_OPMODE_ALS, 540 551 GP2AP020A00F_SUBTRACT_MODE); 541 541 - break; 542 552 case GP2AP020A00F_CMD_TRIGGER_PROX_EN: 543 553 if (data->cur_opmode == GP2AP020A00F_OPMODE_PROX_DETECT) 544 554 return -EBUSY; ··· 547 555 GP2AP020A00F_OPMODE_PS, 548 556 GP2AP020A00F_ADD_MODE); 549 557 set_bit(GP2AP020A00F_FLAG_PROX_TRIGGER, &data->flags); 550 550 - break; 558 558 + return err; 551 559 case GP2AP020A00F_CMD_TRIGGER_PROX_DIS: 552 560 clear_bit(GP2AP020A00F_FLAG_PROX_TRIGGER, &data->flags); 553 553 - err = gp2ap020a00f_alter_opmode(data, 561 561 + return gp2ap020a00f_alter_opmode(data, 554 562 GP2AP020A00F_OPMODE_PS, 555 563 GP2AP020A00F_SUBTRACT_MODE); 556 556 - break; 557 564 case GP2AP020A00F_CMD_ALS_HIGH_EV_EN: 558 565 if (test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags)) 559 566 return 0; ··· 566 575 return err; 567 576 } 568 577 set_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags); 569 569 - err = gp2ap020a00f_write_event_threshold(data, 578 578 + return gp2ap020a00f_write_event_threshold(data, 570 579 GP2AP020A00F_THRESH_TH, true); 571 571 - break; 572 580 case GP2AP020A00F_CMD_ALS_HIGH_EV_DIS: 573 581 if (!test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags)) 574 582 return 0; ··· 579 589 if (err < 0) 580 590 return err; 581 591 } 582 582 - err = gp2ap020a00f_write_event_threshold(data, 592 592 + return gp2ap020a00f_write_event_threshold(data, 583 593 GP2AP020A00F_THRESH_TH, false); 584 584 - break; 585 594 case GP2AP020A00F_CMD_ALS_LOW_EV_EN: 586 595 if (test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags)) 587 596 return 0; ··· 594 605 return err; 595 606 } 596 607 set_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags); 597 597 - err = gp2ap020a00f_write_event_threshold(data, 608 608 + return gp2ap020a00f_write_event_threshold(data, 598 609 GP2AP020A00F_THRESH_TL, true); 599 599 - break; 600 610 case GP2AP020A00F_CMD_ALS_LOW_EV_DIS: 601 611 if (!test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags)) 602 612 return 0; ··· 607 619 if (err < 0) 608 620 return err; 609 621 } 610 610 - err = gp2ap020a00f_write_event_threshold(data, 622 622 + return gp2ap020a00f_write_event_threshold(data, 611 623 GP2AP020A00F_THRESH_TL, false); 612 612 - break; 613 624 case GP2AP020A00F_CMD_PROX_HIGH_EV_EN: 614 625 if (test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags)) 615 626 return 0; ··· 622 635 return err; 623 636 } 624 637 set_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags); 625 625 - err = gp2ap020a00f_write_event_threshold(data, 638 638 + return gp2ap020a00f_write_event_threshold(data, 626 639 GP2AP020A00F_THRESH_PH, true); 627 627 - break; 628 640 case GP2AP020A00F_CMD_PROX_HIGH_EV_DIS: 629 641 if (!test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags)) 630 642 return 0; ··· 632 646 GP2AP020A00F_OPMODE_SHUTDOWN); 633 647 if (err < 0) 634 648 return err; 635 635 - err = gp2ap020a00f_write_event_threshold(data, 649 649 + return gp2ap020a00f_write_event_threshold(data, 636 650 GP2AP020A00F_THRESH_PH, false); 637 637 - break; 638 651 case GP2AP020A00F_CMD_PROX_LOW_EV_EN: 639 652 if (test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags)) 640 653 return 0; ··· 647 662 return err; 648 663 } 649 664 set_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags); 650 650 - err = gp2ap020a00f_write_event_threshold(data, 665 665 + return gp2ap020a00f_write_event_threshold(data, 651 666 GP2AP020A00F_THRESH_PL, true); 652 652 - break; 653 667 case GP2AP020A00F_CMD_PROX_LOW_EV_DIS: 654 668 if (!test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags)) 655 669 return 0; ··· 657 673 GP2AP020A00F_OPMODE_SHUTDOWN); 658 674 if (err < 0) 659 675 return err; 660 660 - err = gp2ap020a00f_write_event_threshold(data, 676 676 + return gp2ap020a00f_write_event_threshold(data, 661 677 GP2AP020A00F_THRESH_PL, false); 662 662 - break; 663 678 } 664 679 665 665 - return err; 680 680 + return 0; 666 681 } 667 682 668 683 static int wait_conversion_complete_irq(struct gp2ap020a00f_data *data) ··· 680 697 static int gp2ap020a00f_read_output(struct gp2ap020a00f_data *data, 681 698 unsigned int output_reg, int *val) 682 699 { 683 683 - u8 reg_buf[2]; 700 700 + __le16 reg_buf; 684 701 int err; 685 702 686 703 err = wait_conversion_complete_irq(data); 687 704 if (err < 0) 688 705 dev_dbg(&data->client->dev, "data ready timeout\n"); 689 706 690 690 - err = regmap_bulk_read(data->regmap, output_reg, reg_buf, 2); 707 707 + err = regmap_bulk_read(data->regmap, output_reg, &reg_buf, sizeof(reg_buf)); 691 708 if (err < 0) 692 709 return err; 693 710 694 694 - *val = le16_to_cpup((__le16 *)reg_buf); 711 711 + *val = le16_to_cpu(reg_buf); 695 712 696 713 return err; 697 714 } ··· 849 866 { 850 867 struct iio_dev *indio_dev = data; 851 868 struct gp2ap020a00f_data *priv = iio_priv(indio_dev); 852 852 - u8 op_reg_flags, d0_reg_buf[2]; 853 869 unsigned int output_val, op_reg_val; 870 870 + __le16 d0_reg_buf; 871 871 + u8 op_reg_flags; 854 872 int thresh_val_id, ret; 855 873 856 874 /* Read interrupt flags */ 857 857 - ret = regmap_read(priv->regmap, GP2AP020A00F_OP_REG, 858 858 - &op_reg_val); 875 875 + ret = regmap_read(priv->regmap, GP2AP020A00F_OP_REG, &op_reg_val); 859 876 if (ret < 0) 860 877 goto done; 861 878 ··· 867 884 868 885 /* Clear interrupt flags (if not in INTTYPE_PULSE mode) */ 869 886 if (priv->cur_opmode != GP2AP020A00F_OPMODE_PROX_DETECT) { 870 870 - ret = regmap_write(priv->regmap, GP2AP020A00F_OP_REG, 871 871 - op_reg_val); 887 887 + ret = regmap_write(priv->regmap, GP2AP020A00F_OP_REG, op_reg_val); 872 888 if (ret < 0) 873 889 goto done; 874 890 } ··· 877 895 * transition is required. 878 896 */ 879 897 ret = regmap_bulk_read(priv->regmap, GP2AP020A00F_D0_L_REG, 880 880 - d0_reg_buf, 2); 898 898 + &d0_reg_buf, sizeof(d0_reg_buf)); 881 899 if (ret < 0) 882 900 goto done; 883 901 884 884 - output_val = le16_to_cpup((__le16 *)d0_reg_buf); 902 902 + output_val = le16_to_cpu(d0_reg_buf); 885 903 886 904 if (gp2ap020a00f_adjust_lux_mode(priv, output_val)) 887 905 goto done; ··· 948 966 int i, out_val, ret; 949 967 950 968 iio_for_each_active_channel(indio_dev, i) { 951 951 - ret = regmap_bulk_read(priv->regmap, 952 952 - GP2AP020A00F_DATA_REG(i), 953 953 - &priv->buffer[d_size], 2); 969 969 + ret = regmap_bulk_read(priv->regmap, GP2AP020A00F_DATA_REG(i), 970 970 + &priv->buffer[d_size], 2); 954 971 if (ret < 0) 955 972 goto done; 956 973 957 974 if (i == GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR || 958 975 i == GP2AP020A00F_SCAN_MODE_LIGHT_IR) { 959 959 - out_val = le16_to_cpup((__le16 *)&priv->buffer[d_size]); 976 976 + out_val = get_unaligned_le16(&priv->buffer[d_size]); 960 977 gp2ap020a00f_output_to_lux(priv, &out_val); 961 961 - 962 978 put_unaligned_le32(out_val, &priv->buffer[d_size]); 963 979 d_size += 4; 964 980 } else { ··· 964 984 } 965 985 } 966 986 967 967 - iio_push_to_buffers_with_timestamp(indio_dev, priv->buffer, 968 968 - pf->timestamp); 987 987 + iio_push_to_buffers_with_timestamp(indio_dev, priv->buffer, pf->timestamp); 969 988 done: 970 989 iio_trigger_notify_done(indio_dev->trig); 971 990 972 991 return IRQ_HANDLED; 973 992 } 974 993 975 975 - static u8 gp2ap020a00f_get_thresh_reg(const struct iio_chan_spec *chan, 976 976 - enum iio_event_direction event_dir) 994 994 + static int gp2ap020a00f_get_thresh_reg(const struct iio_chan_spec *chan, 995 995 + enum iio_event_direction event_dir) 977 996 { 978 997 switch (chan->type) { 979 998 case IIO_PROXIMITY: ··· 986 1007 else 987 1008 return GP2AP020A00F_TL_L_REG; 988 1009 default: 989 989 - break; 1010 1010 + return -EINVAL; 990 1011 } 991 991 - 992 992 - return -EINVAL; 993 1012 } 994 1013 995 1014 static int gp2ap020a00f_write_event_val(struct iio_dev *indio_dev, ··· 1000 1023 struct gp2ap020a00f_data *data = iio_priv(indio_dev); 1001 1024 bool event_en = false; 1002 1025 u8 thresh_val_id; 1003 1003 - u8 thresh_reg_l; 1004 1004 - int err = 0; 1026 1026 + int thresh_reg_l; 1005 1027 1006 1006 - mutex_lock(&data->lock); 1028 1028 + guard(mutex)(&data->lock); 1007 1029 1008 1030 thresh_reg_l = gp2ap020a00f_get_thresh_reg(chan, dir); 1009 1009 - thresh_val_id = GP2AP020A00F_THRESH_VAL_ID(thresh_reg_l); 1031 1031 + if (thresh_reg_l < 0) 1032 1032 + return thresh_reg_l; 1010 1033 1011 1011 - if (thresh_val_id > GP2AP020A00F_THRESH_PH) { 1012 1012 - err = -EINVAL; 1013 1013 - goto error_unlock; 1014 1014 - } 1034 1034 + thresh_val_id = GP2AP020A00F_THRESH_VAL_ID(thresh_reg_l); 1035 1035 + if (thresh_val_id > GP2AP020A00F_THRESH_PH) 1036 1036 + return -EINVAL; 1015 1037 1016 1038 switch (thresh_reg_l) { 1017 1039 case GP2AP020A00F_TH_L_REG: 1018 1018 - event_en = test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, 1019 1019 - &data->flags); 1040 1040 + event_en = test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags); 1020 1041 break; 1021 1042 case GP2AP020A00F_TL_L_REG: 1022 1022 - event_en = test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, 1023 1023 - &data->flags); 1043 1043 + event_en = test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags); 1024 1044 break; 1025 1045 case GP2AP020A00F_PH_L_REG: 1026 1026 - if (val == 0) { 1027 1027 - err = -EINVAL; 1028 1028 - goto error_unlock; 1029 1029 - } 1030 1030 - event_en = test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, 1031 1031 - &data->flags); 1046 1046 + if (val == 0) 1047 1047 + return -EINVAL; 1048 1048 + 1049 1049 + event_en = test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags); 1032 1050 break; 1033 1051 case GP2AP020A00F_PL_L_REG: 1034 1034 - if (val == 0) { 1035 1035 - err = -EINVAL; 1036 1036 - goto error_unlock; 1037 1037 - } 1038 1038 - event_en = test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, 1039 1039 - &data->flags); 1052 1052 + if (val == 0) 1053 1053 + return -EINVAL; 1054 1054 + 1055 1055 + event_en = test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags); 1040 1056 break; 1041 1057 } 1042 1058 1043 1059 data->thresh_val[thresh_val_id] = val; 1044 1044 - err = gp2ap020a00f_write_event_threshold(data, thresh_val_id, 1045 1045 - event_en); 1046 1046 - error_unlock: 1047 1047 - mutex_unlock(&data->lock); 1048 1048 - 1049 1049 - return err; 1060 1060 + return gp2ap020a00f_write_event_threshold(data, thresh_val_id, event_en); 1050 1061 } 1051 1062 1052 1063 static int gp2ap020a00f_read_event_val(struct iio_dev *indio_dev, ··· 1045 1080 int *val, int *val2) 1046 1081 { 1047 1082 struct gp2ap020a00f_data *data = iio_priv(indio_dev); 1048 1048 - u8 thresh_reg_l; 1049 1049 - int err = IIO_VAL_INT; 1083 1083 + int thresh_reg_l; 1050 1084 1051 1051 - mutex_lock(&data->lock); 1085 1085 + guard(mutex)(&data->lock); 1052 1086 1053 1087 thresh_reg_l = gp2ap020a00f_get_thresh_reg(chan, dir); 1054 1054 - 1055 1055 - if (thresh_reg_l > GP2AP020A00F_PH_L_REG) { 1056 1056 - err = -EINVAL; 1057 1057 - goto error_unlock; 1058 1058 - } 1088 1088 + if (thresh_reg_l < 0) 1089 1089 + return thresh_reg_l; 1090 1090 + if (thresh_reg_l > GP2AP020A00F_PH_L_REG) 1091 1091 + return -EINVAL; 1059 1092 1060 1093 *val = data->thresh_val[GP2AP020A00F_THRESH_VAL_ID(thresh_reg_l)]; 1061 1094 1062 1062 - error_unlock: 1063 1063 - mutex_unlock(&data->lock); 1064 1064 - 1065 1065 - return err; 1095 1095 + return IIO_VAL_INT; 1066 1096 } 1067 1097 1068 1098 static int gp2ap020a00f_write_prox_event_config(struct iio_dev *indio_dev, ··· 1123 1163 { 1124 1164 struct gp2ap020a00f_data *data = iio_priv(indio_dev); 1125 1165 enum gp2ap020a00f_cmd cmd; 1126 1126 - int err; 1127 1166 1128 1128 - mutex_lock(&data->lock); 1167 1167 + guard(mutex)(&data->lock); 1129 1168 1130 1169 switch (chan->type) { 1131 1170 case IIO_PROXIMITY: 1132 1132 - err = gp2ap020a00f_write_prox_event_config(indio_dev, state); 1133 1133 - break; 1171 1171 + return gp2ap020a00f_write_prox_event_config(indio_dev, state); 1134 1172 case IIO_LIGHT: 1135 1173 if (dir == IIO_EV_DIR_RISING) { 1136 1174 cmd = state ? GP2AP020A00F_CMD_ALS_HIGH_EV_EN : 1137 1175 GP2AP020A00F_CMD_ALS_HIGH_EV_DIS; 1138 1138 - err = gp2ap020a00f_exec_cmd(data, cmd); 1176 1176 + return gp2ap020a00f_exec_cmd(data, cmd); 1139 1177 } else { 1140 1178 cmd = state ? GP2AP020A00F_CMD_ALS_LOW_EV_EN : 1141 1179 GP2AP020A00F_CMD_ALS_LOW_EV_DIS; 1142 1142 - err = gp2ap020a00f_exec_cmd(data, cmd); 1180 1180 + return gp2ap020a00f_exec_cmd(data, cmd); 1143 1181 } 1144 1144 - break; 1145 1182 default: 1146 1146 - err = -EINVAL; 1183 1183 + return -EINVAL; 1147 1184 } 1148 1148 - 1149 1149 - mutex_unlock(&data->lock); 1150 1150 - 1151 1151 - return err; 1152 1185 } 1153 1186 1154 1187 static int gp2ap020a00f_read_event_config(struct iio_dev *indio_dev, ··· 1150 1197 enum iio_event_direction dir) 1151 1198 { 1152 1199 struct gp2ap020a00f_data *data = iio_priv(indio_dev); 1153 1153 - int event_en = 0; 1154 1200 1155 1155 - mutex_lock(&data->lock); 1201 1201 + guard(mutex)(&data->lock); 1156 1202 1157 1203 switch (chan->type) { 1158 1204 case IIO_PROXIMITY: 1159 1205 if (dir == IIO_EV_DIR_RISING) 1160 1160 - event_en = test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, 1161 1161 - &data->flags); 1206 1206 + return test_bit(GP2AP020A00F_FLAG_PROX_RISING_EV, &data->flags); 1162 1207 else 1163 1163 - event_en = test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, 1164 1164 - &data->flags); 1165 1165 - break; 1208 1208 + return test_bit(GP2AP020A00F_FLAG_PROX_FALLING_EV, &data->flags); 1166 1209 case IIO_LIGHT: 1167 1210 if (dir == IIO_EV_DIR_RISING) 1168 1168 - event_en = test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, 1169 1169 - &data->flags); 1211 1211 + return test_bit(GP2AP020A00F_FLAG_ALS_RISING_EV, &data->flags); 1170 1212 else 1171 1171 - event_en = test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, 1172 1172 - &data->flags); 1173 1173 - break; 1213 1213 + return test_bit(GP2AP020A00F_FLAG_ALS_FALLING_EV, &data->flags); 1174 1214 default: 1175 1175 - event_en = -EINVAL; 1176 1176 - break; 1215 1215 + return -EINVAL; 1177 1216 } 1178 1178 - 1179 1179 - mutex_unlock(&data->lock); 1180 1180 - 1181 1181 - return event_en; 1182 1217 } 1183 1218 1184 1219 static int gp2ap020a00f_read_channel(struct gp2ap020a00f_data *data, 1185 1220 struct iio_chan_spec const *chan, int *val) 1186 1221 { 1222 1222 + struct device *dev = &data->client->dev; 1187 1223 enum gp2ap020a00f_cmd cmd; 1188 1224 int err; 1189 1225 ··· 1192 1250 1193 1251 err = gp2ap020a00f_exec_cmd(data, cmd); 1194 1252 if (err < 0) { 1195 1195 - dev_err(&data->client->dev, 1196 1196 - "gp2ap020a00f_exec_cmd failed\n"); 1197 1197 - goto error_ret; 1253 1253 + dev_err(dev, "gp2ap020a00f_exec_cmd failed\n"); 1254 1254 + return err; 1198 1255 } 1199 1256 1200 1257 err = gp2ap020a00f_read_output(data, chan->address, val); 1201 1258 if (err < 0) 1202 1202 - dev_err(&data->client->dev, 1203 1203 - "gp2ap020a00f_read_output failed\n"); 1259 1259 + dev_err(dev, "gp2ap020a00f_read_output failed\n"); 1204 1260 1205 1261 err = gp2ap020a00f_set_operation_mode(data, 1206 1262 GP2AP020A00F_OPMODE_SHUTDOWN); 1207 1263 if (err < 0) 1208 1208 - dev_err(&data->client->dev, 1209 1209 - "Failed to shut down the device.\n"); 1264 1264 + dev_err(dev, "Failed to shut down the device.\n"); 1210 1265 1211 1266 if (cmd == GP2AP020A00F_CMD_READ_RAW_CLEAR || 1212 1267 cmd == GP2AP020A00F_CMD_READ_RAW_IR) 1213 1268 gp2ap020a00f_output_to_lux(data, val); 1214 1269 1215 1215 - error_ret: 1216 1270 return err; 1217 1271 } 1218 1272 ··· 1321 1383 static int gp2ap020a00f_buffer_postenable(struct iio_dev *indio_dev) 1322 1384 { 1323 1385 struct gp2ap020a00f_data *data = iio_priv(indio_dev); 1324 1324 - int i, err = 0; 1386 1386 + int i, err; 1325 1387 1326 1326 - mutex_lock(&data->lock); 1388 1388 + guard(mutex)(&data->lock); 1327 1389 1328 1390 /* 1329 1391 * Enable triggers according to the scan_mask. Enabling either ··· 1347 1409 err = gp2ap020a00f_exec_cmd(data, 1348 1410 GP2AP020A00F_CMD_TRIGGER_PROX_EN); 1349 1411 break; 1412 1412 + default: 1413 1413 + err = -EINVAL; 1414 1414 + break; 1350 1415 } 1416 1416 + if (err) 1417 1417 + return err; 1351 1418 } 1352 1352 - 1353 1353 - if (err < 0) 1354 1354 - goto error_unlock; 1355 1419 1356 1420 data->buffer = kmalloc(indio_dev->scan_bytes, GFP_KERNEL); 1357 1421 if (!data->buffer) 1358 1358 - err = -ENOMEM; 1422 1422 + return -ENOMEM; 1359 1423 1360 1360 - error_unlock: 1361 1361 - mutex_unlock(&data->lock); 1362 1362 - 1363 1363 - return err; 1424 1424 + return 0; 1364 1425 } 1365 1426 1366 1427 static int gp2ap020a00f_buffer_predisable(struct iio_dev *indio_dev) 1367 1428 { 1368 1429 struct gp2ap020a00f_data *data = iio_priv(indio_dev); 1369 1369 - int i, err = 0; 1430 1430 + int i, err; 1370 1431 1371 1371 - mutex_lock(&data->lock); 1432 1432 + guard(mutex)(&data->lock); 1372 1433 1373 1434 iio_for_each_active_channel(indio_dev, i) { 1374 1435 switch (i) { ··· 1383 1446 err = gp2ap020a00f_exec_cmd(data, 1384 1447 GP2AP020A00F_CMD_TRIGGER_PROX_DIS); 1385 1448 break; 1449 1449 + default: 1450 1450 + err = -EINVAL; 1451 1451 + break; 1386 1452 } 1453 1453 + if (err) 1454 1454 + return err; 1387 1455 } 1388 1456 1389 1389 - if (err == 0) 1390 1390 - kfree(data->buffer); 1391 1391 - 1392 1392 - mutex_unlock(&data->lock); 1393 1393 - 1394 1394 - return err; 1457 1457 + kfree(data->buffer); 1458 1458 + return 0; 1395 1459 } 1396 1460 1397 1461 static const struct iio_buffer_setup_ops gp2ap020a00f_buffer_setup_ops = { ··· 1403 1465 static int gp2ap020a00f_probe(struct i2c_client *client) 1404 1466 { 1405 1467 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1468 1468 + struct device *dev = &client->dev; 1406 1469 struct gp2ap020a00f_data *data; 1407 1470 struct iio_dev *indio_dev; 1408 1471 struct regmap *regmap; 1409 1472 int err; 1410 1473 1411 1411 - indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1474 1474 + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1412 1475 if (!indio_dev) 1413 1476 return -ENOMEM; 1414 1477 1415 1478 data = iio_priv(indio_dev); 1416 1479 1417 1417 - data->vled_reg = devm_regulator_get(&client->dev, "vled"); 1480 1480 + data->vled_reg = devm_regulator_get(dev, "vled"); 1418 1481 if (IS_ERR(data->vled_reg)) 1419 1482 return PTR_ERR(data->vled_reg); 1420 1483 ··· 1425 1486 1426 1487 regmap = devm_regmap_init_i2c(client, &gp2ap020a00f_regmap_config); 1427 1488 if (IS_ERR(regmap)) { 1428 1428 - dev_err(&client->dev, "Regmap initialization failed.\n"); 1489 1489 + dev_err(dev, "Regmap initialization failed.\n"); 1429 1490 err = PTR_ERR(regmap); 1430 1491 goto error_regulator_disable; 1431 1492 } ··· 1436 1497 ARRAY_SIZE(gp2ap020a00f_reg_init_tab)); 1437 1498 1438 1499 if (err < 0) { 1439 1439 - dev_err(&client->dev, "Device initialization failed.\n"); 1500 1500 + dev_err(dev, "Device initialization failed.\n"); 1440 1501 goto error_regulator_disable; 1441 1502 } 1442 1503 ··· 1461 1522 goto error_regulator_disable; 1462 1523 1463 1524 /* Allocate trigger */ 1464 1464 - data->trig = devm_iio_trigger_alloc(&client->dev, "%s-trigger", 1465 1465 - indio_dev->name); 1525 1525 + data->trig = devm_iio_trigger_alloc(dev, "%s-trigger", indio_dev->name); 1466 1526 if (data->trig == NULL) { 1467 1527 err = -ENOMEM; 1468 1468 - dev_err(&indio_dev->dev, "Failed to allocate iio trigger.\n"); 1528 1528 + dev_err(dev, "Failed to allocate iio trigger.\n"); 1469 1529 goto error_uninit_buffer; 1470 1530 } 1471 1531 ··· 1476 1538 "gp2ap020a00f_als_event", 1477 1539 indio_dev); 1478 1540 if (err < 0) { 1479 1479 - dev_err(&client->dev, "Irq request failed.\n"); 1541 1541 + dev_err(dev, "Irq request failed.\n"); 1480 1542 goto error_uninit_buffer; 1481 1543 } 1482 1544 ··· 1484 1546 1485 1547 err = iio_trigger_register(data->trig); 1486 1548 if (err < 0) { 1487 1487 - dev_err(&client->dev, "Failed to register iio trigger.\n"); 1549 1549 + dev_err(dev, "Failed to register iio trigger.\n"); 1488 1550 goto error_free_irq; 1489 1551 } 1490 1552 ··· 1510 1572 { 1511 1573 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1512 1574 struct gp2ap020a00f_data *data = iio_priv(indio_dev); 1575 1575 + struct device *dev = &client->dev; 1513 1576 int err; 1514 1577 1515 1515 - err = gp2ap020a00f_set_operation_mode(data, 1516 1516 - GP2AP020A00F_OPMODE_SHUTDOWN); 1578 1578 + err = gp2ap020a00f_set_operation_mode(data, GP2AP020A00F_OPMODE_SHUTDOWN); 1517 1579 if (err < 0) 1518 1518 - dev_err(&indio_dev->dev, "Failed to power off the device.\n"); 1580 1580 + dev_err(dev, "Failed to power off the device.\n"); 1519 1581 1520 1582 iio_device_unregister(indio_dev); 1521 1583 iio_trigger_unregister(data->trig); ··· 1525 1587 } 1526 1588 1527 1589 static const struct i2c_device_id gp2ap020a00f_id[] = { 1528 1528 - { GP2A_I2C_NAME }, 1590 1590 + { "gp2ap020a00f" }, 1529 1591 { } 1530 1592 }; 1531 1531 - 1532 1593 MODULE_DEVICE_TABLE(i2c, gp2ap020a00f_id); 1533 1594 1534 1595 static const struct of_device_id gp2ap020a00f_of_match[] = { ··· 1538 1601 1539 1602 static struct i2c_driver gp2ap020a00f_driver = { 1540 1603 .driver = { 1541 1541 - .name = GP2A_I2C_NAME, 1604 1604 + .name = "gp2ap020a00f", 1542 1605 .of_match_table = gp2ap020a00f_of_match, 1543 1606 }, 1544 1607 .probe = gp2ap020a00f_probe, 1545 1608 .remove = gp2ap020a00f_remove, 1546 1609 .id_table = gp2ap020a00f_id, 1547 1610 }; 1548 1548 - 1549 1611 module_i2c_driver(gp2ap020a00f_driver); 1550 1612 1551 1613 MODULE_AUTHOR("Jacek Anaszewski <j.anaszewski@samsung.com>");

+1 -1

drivers/iio/light/ltr390.c

reviewed

··· 101 101 struct ltr390_data { 102 102 struct regmap *regmap; 103 103 struct i2c_client *client; 104 104 - /* Protects device from simulataneous reads */ 104 104 + /* Protects device from simultaneous reads */ 105 105 struct mutex lock; 106 106 enum ltr390_mode mode; 107 107 int gain;

+3 -3

drivers/iio/light/ltr501.c

reviewed

··· 754 754 if (val == gain[i].scale && val2 == gain[i].uscale) 755 755 return i; 756 756 757 757 - return -1; 757 757 + return -EINVAL; 758 758 } 759 759 760 760 static int __ltr501_write_raw(struct iio_dev *indio_dev, ··· 773 773 info->als_gain_tbl_size, 774 774 val, val2); 775 775 if (i < 0) 776 776 - return -EINVAL; 776 776 + return i; 777 777 778 778 data->als_contr &= ~info->als_gain_mask; 779 779 data->als_contr |= i << info->als_gain_shift; ··· 785 785 info->ps_gain_tbl_size, 786 786 val, val2); 787 787 if (i < 0) 788 788 - return -EINVAL; 788 788 + return i; 789 789 790 790 data->ps_contr &= ~LTR501_CONTR_PS_GAIN_MASK; 791 791 data->ps_contr |= i << LTR501_CONTR_PS_GAIN_SHIFT;

+1 -1

drivers/iio/light/opt3001.c

reviewed

··· 91 91 */ 92 92 int factor_integer; 93 93 /* 94 94 - * Factor used to align decimal part of proccessed value to six decimal 94 94 + * Factor used to align decimal part of processed value to six decimal 95 95 * places. 96 96 */ 97 97 int factor_decimal;

+1 -1

drivers/iio/light/tsl2772.c

reviewed

··· 190 190 }; 191 191 192 192 /* 193 193 - * Different devices require different coefficents, and these numbers were 193 193 + * Different devices require different coefficients, and these numbers were 194 194 * derived from the 'Lux Equation' section of the various device datasheets. 195 195 * All of these coefficients assume a Glass Attenuation (GA) factor of 1. 196 196 * The coefficients are multiplied by 1000 to avoid floating point operations.

+90 -41

drivers/iio/light/vcnl4000.c

reviewed

··· 18 18 */ 19 19 20 20 #include <linux/bitfield.h> 21 21 - #include <linux/module.h> 22 22 - #include <linux/i2c.h> 23 23 - #include <linux/err.h> 24 21 #include <linux/delay.h> 25 25 - #include <linux/pm_runtime.h> 22 22 + #include <linux/err.h> 23 23 + #include <linux/i2c.h> 26 24 #include <linux/interrupt.h> 25 25 + #include <linux/module.h> 26 26 + #include <linux/pm_runtime.h> 27 27 + #include <linux/regulator/consumer.h> 27 28 #include <linux/units.h> 28 29 29 30 #include <linux/iio/buffer.h> ··· 186 185 #define VCNL4000_SLEEP_DELAY_MS 2000 /* before we enter pm_runtime_suspend */ 187 186 188 187 enum vcnl4000_device_ids { 188 188 + CM36672P, 189 189 VCNL4000, 190 190 VCNL4010, 191 191 VCNL4040, ··· 237 235 }; 238 236 239 237 static const struct i2c_device_id vcnl4000_id[] = { 238 238 + { "cm36672p", CM36672P }, 239 239 + { "cm36686", VCNL4040 }, 240 240 { "vcnl4000", VCNL4000 }, 241 241 { "vcnl4010", VCNL4010 }, 242 242 { "vcnl4020", VCNL4010 }, ··· 281 277 data->rev = ret & 0xf; 282 278 data->al_scale = 250000; 283 279 284 284 - return data->chip_spec->set_power_state(data, true); 280 280 + return 0; 285 281 }; 286 282 287 283 static ssize_t vcnl4000_write_als_enable(struct vcnl4000_data *data, bool en) ··· 357 353 358 354 static int vcnl4200_init(struct vcnl4000_data *data) 359 355 { 356 356 + struct i2c_client *client = data->client; 357 357 + struct device *dev = &client->dev; 360 358 int ret, id; 361 359 u16 regval; 362 360 363 363 - ret = i2c_smbus_read_word_data(data->client, VCNL4200_DEV_ID); 361 361 + ret = i2c_smbus_read_word_data(client, VCNL4200_DEV_ID); 364 362 if (ret < 0) 365 363 return ret; 366 364 367 365 id = ret & 0xff; 368 366 369 367 if (id != VCNL4200_PROD_ID) { 370 370 - ret = i2c_smbus_read_word_data(data->client, VCNL4040_DEV_ID); 368 368 + ret = i2c_smbus_read_word_data(client, VCNL4040_DEV_ID); 371 369 if (ret < 0) 372 370 return ret; 373 371 ··· 379 373 return -ENODEV; 380 374 } 381 375 382 382 - dev_dbg(&data->client->dev, "device id 0x%x", id); 376 376 + dev_dbg(dev, "device id 0x%x", id); 383 377 384 378 data->rev = (ret >> 8) & 0xf; 385 379 data->ps_int = 0; ··· 403 397 } 404 398 data->al_scale = data->chip_spec->ulux_step; 405 399 data->ps_scale = 16; 406 406 - mutex_init(&data->vcnl4200_al.lock); 407 407 - mutex_init(&data->vcnl4200_ps.lock); 400 400 + 401 401 + ret = devm_mutex_init(dev, &data->vcnl4200_al.lock); 402 402 + if (ret) 403 403 + return ret; 404 404 + 405 405 + ret = devm_mutex_init(dev, &data->vcnl4200_ps.lock); 406 406 + if (ret) 407 407 + return ret; 408 408 409 409 /* Use 16 bits proximity sensor readings */ 410 410 - ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); 410 410 + ret = i2c_smbus_read_word_data(client, VCNL4200_PS_CONF1); 411 411 if (ret < 0) 412 412 return ret; 413 413 414 414 regval = ret | VCNL4040_PS_CONF2_PS_HD; 415 415 - ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1, 416 416 - regval); 415 415 + ret = i2c_smbus_write_word_data(client, VCNL4200_PS_CONF1, regval); 417 416 if (ret < 0) 418 417 return ret; 419 418 420 419 /* Align proximity sensor sample rate to 16 bits data width */ 421 421 - ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF3); 420 420 + ret = i2c_smbus_read_word_data(client, VCNL4200_PS_CONF3); 422 421 if (ret < 0) 423 422 return ret; 424 423 425 424 regval = ret | VCNL4040_CONF3_PS_SAMPLE_16BITS; 426 426 - ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF3, 427 427 - regval); 428 428 - if (ret < 0) 429 429 - return ret; 430 430 - 431 431 - ret = data->chip_spec->set_power_state(data, true); 425 425 + ret = i2c_smbus_write_word_data(client, VCNL4200_PS_CONF3, regval); 432 426 if (ret < 0) 433 427 return ret; 434 428 ··· 1848 1842 } 1849 1843 }; 1850 1844 1845 1845 + static const struct iio_chan_spec cm36672p_channels[] = { 1846 1846 + { 1847 1847 + .type = IIO_PROXIMITY, 1848 1848 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1849 1849 + BIT(IIO_CHAN_INFO_INT_TIME) | 1850 1850 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | 1851 1851 + BIT(IIO_CHAN_INFO_CALIBBIAS), 1852 1852 + .info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME) | 1853 1853 + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | 1854 1854 + BIT(IIO_CHAN_INFO_CALIBBIAS), 1855 1855 + .ext_info = vcnl4000_ext_info, 1856 1856 + .event_spec = vcnl4040_event_spec, 1857 1857 + .num_event_specs = ARRAY_SIZE(vcnl4040_event_spec), 1858 1858 + }, 1859 1859 + }; 1860 1860 + 1851 1861 static const struct iio_info vcnl4000_info = { 1852 1862 .read_raw = vcnl4000_read_raw, 1853 1863 }; ··· 1889 1867 }; 1890 1868 1891 1869 static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = { 1870 1870 + [CM36672P] = { 1871 1871 + .prod = "CM36672P", 1872 1872 + .init = vcnl4200_init, 1873 1873 + .measure_proximity = vcnl4200_measure_proximity, 1874 1874 + .set_power_state = vcnl4200_set_power_state, 1875 1875 + .channels = cm36672p_channels, 1876 1876 + .num_channels = ARRAY_SIZE(cm36672p_channels), 1877 1877 + .info = &vcnl4040_info, 1878 1878 + .irq_thread = vcnl4040_irq_thread, 1879 1879 + .int_reg = VCNL4040_INT_FLAGS, 1880 1880 + .ps_it_times = &vcnl4040_ps_it_times, 1881 1881 + .num_ps_it_times = ARRAY_SIZE(vcnl4040_ps_it_times), 1882 1882 + }, 1892 1883 [VCNL4000] = { 1893 1884 .prod = "VCNL4000", 1894 1885 .init = vcnl4000_init, ··· 1986 1951 static int vcnl4000_probe(struct i2c_client *client) 1987 1952 { 1988 1953 const struct i2c_device_id *id = i2c_client_get_device_id(client); 1954 1954 + const char * const regulator_names[] = { "vdd", "vio", "vled" }; 1955 1955 + struct device *dev = &client->dev; 1989 1956 struct vcnl4000_data *data; 1990 1957 struct iio_dev *indio_dev; 1991 1958 int ret; 1992 1959 1993 1993 - indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1960 1960 + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1994 1961 if (!indio_dev) 1995 1962 return -ENOMEM; 1996 1963 ··· 2002 1965 data->id = id->driver_data; 2003 1966 data->chip_spec = &vcnl4000_chip_spec_cfg[data->id]; 2004 1967 2005 2005 - mutex_init(&data->vcnl4000_lock); 1968 1968 + ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names), 1969 1969 + regulator_names); 1970 1970 + if (ret) 1971 1971 + return ret; 1972 1972 + 1973 1973 + ret = devm_mutex_init(dev, &data->vcnl4000_lock); 1974 1974 + if (ret) 1975 1975 + return ret; 2006 1976 2007 1977 ret = data->chip_spec->init(data); 2008 1978 if (ret < 0) 2009 1979 return ret; 2010 1980 2011 2011 - dev_dbg(&client->dev, "%s Ambient light/proximity sensor, Rev: %02x\n", 1981 1981 + ret = data->chip_spec->set_power_state(data, true); 1982 1982 + if (ret) 1983 1983 + return ret; 1984 1984 + 1985 1985 + dev_dbg(dev, "%s Ambient light/proximity sensor, Rev: %02x\n", 2012 1986 data->chip_spec->prod, data->rev); 2013 1987 2014 2014 - if (device_property_read_u32(&client->dev, "proximity-near-level", 2015 2015 - &data->near_level)) 2016 2016 - data->near_level = 0; 1988 1988 + device_property_read_u32(dev, "proximity-near-level", &data->near_level); 2017 1989 2018 1990 indio_dev->info = data->chip_spec->info; 2019 1991 indio_dev->channels = data->chip_spec->channels; ··· 2032 1986 2033 1987 if (data->chip_spec->trig_buffer_func && 2034 1988 data->chip_spec->buffer_setup_ops) { 2035 2035 - ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, 2036 2036 - NULL, 1989 1989 + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 2037 1990 data->chip_spec->trig_buffer_func, 2038 1991 data->chip_spec->buffer_setup_ops); 2039 2039 - if (ret < 0) { 2040 2040 - dev_err(&client->dev, 2041 2041 - "unable to setup iio triggered buffer\n"); 1992 1992 + if (ret < 0) 2042 1993 return ret; 2043 2043 - } 2044 1994 } 2045 1995 2046 1996 if (client->irq && data->chip_spec->irq_thread) { 2047 2047 - ret = devm_request_threaded_irq(&client->dev, client->irq, 2048 2048 - NULL, data->chip_spec->irq_thread, 1997 1997 + ret = devm_request_threaded_irq(dev, client->irq, NULL, 1998 1998 + data->chip_spec->irq_thread, 2049 1999 IRQF_TRIGGER_FALLING | 2050 2000 IRQF_ONESHOT, 2051 2001 "vcnl4000_irq", 2052 2002 indio_dev); 2053 2053 - if (ret < 0) { 2054 2054 - dev_err(&client->dev, "irq request failed\n"); 2003 2003 + if (ret < 0) 2055 2004 return ret; 2056 2056 - } 2057 2005 2058 2006 ret = vcnl4010_probe_trigger(indio_dev); 2059 2007 if (ret < 0) 2060 2008 return ret; 2061 2009 } 2062 2010 2063 2063 - ret = pm_runtime_set_active(&client->dev); 2011 2011 + ret = pm_runtime_set_active(dev); 2064 2012 if (ret < 0) 2065 2013 goto fail_poweroff; 2066 2014 ··· 2062 2022 if (ret < 0) 2063 2023 goto fail_poweroff; 2064 2024 2065 2065 - pm_runtime_enable(&client->dev); 2066 2066 - pm_runtime_set_autosuspend_delay(&client->dev, VCNL4000_SLEEP_DELAY_MS); 2067 2067 - pm_runtime_use_autosuspend(&client->dev); 2025 2025 + pm_runtime_enable(dev); 2026 2026 + pm_runtime_set_autosuspend_delay(dev, VCNL4000_SLEEP_DELAY_MS); 2027 2027 + pm_runtime_use_autosuspend(dev); 2068 2028 2069 2029 return 0; 2070 2030 fail_poweroff: ··· 2073 2033 } 2074 2034 2075 2035 static const struct of_device_id vcnl_4000_of_match[] = { 2036 2036 + { 2037 2037 + .compatible = "capella,cm36672p", 2038 2038 + .data = (void *)CM36672P, 2039 2039 + }, 2040 2040 + /* Capella CM36686 is fully compatible with Vishay VCNL4040 */ 2041 2041 + { 2042 2042 + .compatible = "capella,cm36686", 2043 2043 + .data = (void *)VCNL4040, 2044 2044 + }, 2076 2045 { 2077 2046 .compatible = "vishay,vcnl4000", 2078 2047 .data = (void *)VCNL4000,

+18 -29

drivers/iio/light/zopt2201.c

reviewed

··· 10 10 * TODO: interrupt support, ALS/UVB raw mode 11 11 */ 12 12 13 13 - #include <linux/module.h> 14 14 - #include <linux/i2c.h> 15 15 - #include <linux/mutex.h> 16 16 - #include <linux/err.h> 13 13 + #include <linux/cleanup.h> 17 14 #include <linux/delay.h> 15 15 + #include <linux/err.h> 16 16 + #include <linux/i2c.h> 17 17 + #include <linux/module.h> 18 18 + #include <linux/mutex.h> 19 19 + #include <linux/unaligned.h> 18 20 19 21 #include <linux/iio/iio.h> 20 22 #include <linux/iio/sysfs.h> 21 21 - 22 22 - #include <linux/unaligned.h> 23 23 24 24 #define ZOPT2201_DRV_NAME "zopt2201" 25 25 ··· 186 186 u8 buf[3]; 187 187 int ret; 188 188 189 189 - mutex_lock(&data->lock); 189 189 + guard(mutex)(&data->lock); 190 190 ret = zopt2201_enable_mode(data, reg == ZOPT2201_UVB_DATA); 191 191 if (ret < 0) 192 192 - goto fail; 192 192 + return ret; 193 193 194 194 while (tries--) { 195 195 unsigned long t = zopt2201_resolution[data->res].us; ··· 200 200 msleep(t / 1000); 201 201 ret = i2c_smbus_read_byte_data(client, ZOPT2201_MAIN_STATUS); 202 202 if (ret < 0) 203 203 - goto fail; 203 203 + return ret; 204 204 if (ret & ZOPT2201_MAIN_STATUS_DRDY) 205 205 break; 206 206 } 207 207 208 208 if (tries < 0) { 209 209 ret = -ETIMEDOUT; 210 210 - goto fail; 210 210 + return ret; 211 211 } 212 212 213 213 ret = i2c_smbus_read_i2c_block_data(client, reg, sizeof(buf), buf); 214 214 if (ret < 0) 215 215 - goto fail; 215 215 + return ret; 216 216 217 217 ret = i2c_smbus_write_byte_data(client, ZOPT2201_MAIN_CTRL, 0x00); 218 218 if (ret < 0) 219 219 - goto fail; 220 220 - mutex_unlock(&data->lock); 219 219 + return ret; 221 220 222 221 return get_unaligned_le24(&buf[0]); 223 223 - 224 224 - fail: 225 225 - mutex_unlock(&data->lock); 226 226 - return ret; 227 222 } 228 223 229 224 static const struct iio_chan_spec zopt2201_channels[] = { ··· 312 317 static int zopt2201_write_resolution(struct zopt2201_data *data, 313 318 int val, int val2) 314 319 { 315 315 - int i, ret; 320 320 + int i; 316 321 317 322 if (val != 0) 318 323 return -EINVAL; 319 324 320 325 for (i = 0; i < ARRAY_SIZE(zopt2201_resolution); i++) 321 326 if (val2 == zopt2201_resolution[i].us) { 322 322 - mutex_lock(&data->lock); 323 323 - ret = zopt2201_set_resolution(data, i); 324 324 - mutex_unlock(&data->lock); 325 325 - return ret; 327 327 + guard(mutex)(&data->lock); 328 328 + return zopt2201_set_resolution(data, i); 326 329 } 327 330 328 331 return -EINVAL; ··· 344 351 { 345 352 int ret; 346 353 347 347 - mutex_lock(&data->lock); 354 354 + guard(mutex)(&data->lock); 348 355 ret = zopt2201_set_resolution(data, zopt2201_scale_array[idx].res); 349 356 if (ret < 0) 350 350 - goto unlock; 357 357 + return ret; 351 358 352 352 - ret = zopt2201_set_gain(data, zopt2201_scale_array[idx].gain); 353 353 - 354 354 - unlock: 355 355 - mutex_unlock(&data->lock); 356 356 - return ret; 359 359 + return zopt2201_set_gain(data, zopt2201_scale_array[idx].gain); 357 360 } 358 361 359 362 static int zopt2201_write_scale_als(struct zopt2201_data *data,

+1 -1

drivers/iio/magnetometer/ak8974.c

reviewed

··· 577 577 /* 578 578 * This explicit cast to (s16) is necessary as the measurement 579 579 * is done in 2's complement with positive and negative values. 580 580 - * The follwing assignment to *val will then convert the signed 580 580 + * The following assignment to *val will then convert the signed 581 581 * s16 value to a signed int value. 582 582 */ 583 583 *val = (s16)le16_to_cpu(hw_values[address]);

+3 -3

drivers/iio/magnetometer/ak8975.c

reviewed

··· 545 545 return ret; 546 546 } 547 547 data->cntl_cache = regval; 548 548 - /* After mode change wait atleast 100us */ 548 548 + /* After mode change wait at least 100us */ 549 549 usleep_range(100, 500); 550 550 551 551 return 0; ··· 697 697 return read_status; 698 698 } 699 699 700 700 - /* Returns 0 if the end of conversion interrupt occured or -ETIME otherwise */ 700 700 + /* Returns 0 if the end of conversion interrupt occurred or -ETIME otherwise */ 701 701 static int wait_conversion_complete_interrupt(struct ak8975_data *data) 702 702 { 703 703 int ret; ··· 759 759 if (ret < 0) 760 760 goto exit; 761 761 762 762 - /* Read out ST2 for release lock on measurment data. */ 762 762 + /* Read out ST2 for release lock on measurement data. */ 763 763 ret = i2c_smbus_read_byte_data(client, data->def->ctrl_regs[ST2]); 764 764 if (ret < 0) { 765 765 dev_err(&client->dev, "Error in reading ST2\n");

+62 -83

drivers/iio/magnetometer/bmc150_magn.c

reviewed

··· 12 12 #include <linux/module.h> 13 13 #include <linux/i2c.h> 14 14 #include <linux/interrupt.h> 15 15 + #include <linux/cleanup.h> 15 16 #include <linux/delay.h> 16 17 #include <linux/slab.h> 17 18 #include <linux/pm.h> ··· 149 148 static const struct { 150 149 int freq; 151 150 u8 reg_val; 152 152 - } bmc150_magn_samp_freq_table[] = { {2, 0x01}, 153 153 - {6, 0x02}, 154 154 - {8, 0x03}, 155 155 - {10, 0x00}, 156 156 - {15, 0x04}, 157 157 - {20, 0x05}, 158 158 - {25, 0x06}, 159 159 - {30, 0x07} }; 151 151 + } bmc150_magn_samp_freq_table[] = { 152 152 + { 2, 0x01 }, 153 153 + { 6, 0x02 }, 154 154 + { 8, 0x03 }, 155 155 + { 10, 0x00 }, 156 156 + { 15, 0x04 }, 157 157 + { 20, 0x05 }, 158 158 + { 25, 0x06 }, 159 159 + { 30, 0x07 }, 160 160 + }; 160 161 161 162 enum bmc150_magn_presets { 162 163 LOW_POWER_PRESET, ··· 172 169 u8 rep_z; 173 170 u8 odr; 174 171 } bmc150_magn_presets_table[] = { 175 175 - [LOW_POWER_PRESET] = {3, 3, 10}, 176 176 - [REGULAR_PRESET] = {9, 15, 10}, 177 177 - [ENHANCED_REGULAR_PRESET] = {15, 27, 10}, 178 178 - [HIGH_ACCURACY_PRESET] = {47, 83, 20}, 172 172 + [LOW_POWER_PRESET] = { 3, 3, 10 }, 173 173 + [REGULAR_PRESET] = { 9, 15, 10 }, 174 174 + [ENHANCED_REGULAR_PRESET] = { 15, 27, 10 }, 175 175 + [HIGH_ACCURACY_PRESET] = { 47, 83, 20 }, 179 176 }; 180 177 181 178 #define BMC150_MAGN_DEFAULT_PRESET REGULAR_PRESET ··· 256 253 } 257 254 258 255 return -EINVAL; 256 256 + } 257 257 + 258 258 + static int bmc150_magn_set_power_mode_locked(struct bmc150_magn_data *data, 259 259 + enum bmc150_magn_power_modes mode) 260 260 + { 261 261 + guard(mutex)(&data->mutex); 262 262 + return bmc150_magn_set_power_mode(data, mode, true); 259 263 } 260 264 261 265 static int bmc150_magn_set_power_state(struct bmc150_magn_data *data, bool on) ··· 463 453 s32 values[AXIS_XYZ_MAX]; 464 454 465 455 switch (mask) { 466 466 - case IIO_CHAN_INFO_RAW: 456 456 + case IIO_CHAN_INFO_RAW: { 467 457 if (iio_buffer_enabled(indio_dev)) 468 458 return -EBUSY; 469 469 - mutex_lock(&data->mutex); 459 459 + 460 460 + guard(mutex)(&data->mutex); 470 461 471 462 ret = bmc150_magn_set_power_state(data, true); 472 472 - if (ret < 0) { 473 473 - mutex_unlock(&data->mutex); 463 463 + if (ret < 0) 474 464 return ret; 475 475 - } 476 465 477 466 ret = bmc150_magn_read_xyz(data, values); 478 467 if (ret < 0) { 479 468 bmc150_magn_set_power_state(data, false); 480 480 - mutex_unlock(&data->mutex); 481 469 return ret; 482 470 } 483 471 *val = values[chan->scan_index]; 484 472 485 473 ret = bmc150_magn_set_power_state(data, false); 486 486 - if (ret < 0) { 487 487 - mutex_unlock(&data->mutex); 474 474 + if (ret < 0) 488 475 return ret; 489 489 - } 490 476 491 491 - mutex_unlock(&data->mutex); 492 477 return IIO_VAL_INT; 478 478 + } 493 479 case IIO_CHAN_INFO_SCALE: 494 480 /* 495 481 * The API/driver performs an off-chip temperature ··· 533 527 int ret; 534 528 535 529 switch (mask) { 536 536 - case IIO_CHAN_INFO_SAMP_FREQ: 530 530 + case IIO_CHAN_INFO_SAMP_FREQ: { 537 531 if (val > data->max_odr) 538 532 return -EINVAL; 539 539 - mutex_lock(&data->mutex); 540 540 - ret = bmc150_magn_set_odr(data, val); 541 541 - mutex_unlock(&data->mutex); 542 542 - return ret; 533 533 + guard(mutex)(&data->mutex); 534 534 + return bmc150_magn_set_odr(data, val); 535 535 + } 543 536 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 544 537 switch (chan->channel2) { 545 538 case IIO_MOD_X: 546 546 - case IIO_MOD_Y: 539 539 + case IIO_MOD_Y: { 547 540 if (val < 1 || val > 511) 548 541 return -EINVAL; 549 549 - mutex_lock(&data->mutex); 542 542 + guard(mutex)(&data->mutex); 550 543 ret = bmc150_magn_set_max_odr(data, val, 0, 0); 551 551 - if (ret < 0) { 552 552 - mutex_unlock(&data->mutex); 544 544 + if (ret < 0) 553 545 return ret; 554 554 - } 555 555 - ret = regmap_update_bits(data->regmap, 546 546 + return regmap_update_bits(data->regmap, 556 547 BMC150_MAGN_REG_REP_XY, 557 548 BMC150_MAGN_REG_REP_DATAMASK, 558 558 - BMC150_MAGN_REPXY_TO_REGVAL 559 559 - (val)); 560 560 - mutex_unlock(&data->mutex); 561 561 - return ret; 562 562 - case IIO_MOD_Z: 549 549 + BMC150_MAGN_REPXY_TO_REGVAL(val)); 550 550 + } 551 551 + case IIO_MOD_Z: { 563 552 if (val < 1 || val > 256) 564 553 return -EINVAL; 565 565 - mutex_lock(&data->mutex); 554 554 + guard(mutex)(&data->mutex); 566 555 ret = bmc150_magn_set_max_odr(data, 0, val, 0); 567 567 - if (ret < 0) { 568 568 - mutex_unlock(&data->mutex); 556 556 + if (ret < 0) 569 557 return ret; 570 570 - } 571 571 - ret = regmap_update_bits(data->regmap, 558 558 + return regmap_update_bits(data->regmap, 572 559 BMC150_MAGN_REG_REP_Z, 573 560 BMC150_MAGN_REG_REP_DATAMASK, 574 574 - BMC150_MAGN_REPZ_TO_REGVAL 575 575 - (val)); 576 576 - mutex_unlock(&data->mutex); 577 577 - return ret; 561 561 + BMC150_MAGN_REPZ_TO_REGVAL(val)); 562 562 + } 578 563 default: 579 564 return -EINVAL; 580 565 } ··· 652 655 }; 653 656 654 657 static const unsigned long bmc150_magn_scan_masks[] = { 655 655 - BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 656 656 - 0}; 658 658 + BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 659 659 + 0 660 660 + }; 657 661 658 662 static irqreturn_t bmc150_magn_trigger_handler(int irq, void *p) 659 663 { ··· 693 695 * 3ms power-on time according to datasheet, let's better 694 696 * be safe than sorry and set this delay to 5ms. 695 697 */ 696 696 - msleep(5); 698 698 + fsleep(5 * USEC_PER_MSEC); 697 699 698 700 ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, 699 701 false); ··· 780 782 if (!data->dready_trigger_on) 781 783 return; 782 784 783 783 - mutex_lock(&data->mutex); 785 785 + guard(mutex)(&data->mutex); 784 786 ret = bmc150_magn_reset_intr(data); 785 785 - mutex_unlock(&data->mutex); 786 787 if (ret) 787 788 dev_err(data->dev, "Failed to reset interrupt\n"); 788 789 } ··· 791 794 { 792 795 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 793 796 struct bmc150_magn_data *data = iio_priv(indio_dev); 794 794 - int ret = 0; 797 797 + int ret; 795 798 796 796 - mutex_lock(&data->mutex); 799 799 + guard(mutex)(&data->mutex); 800 800 + 797 801 if (state == data->dready_trigger_on) 798 798 - goto err_unlock; 802 802 + return 0; 799 803 800 804 ret = regmap_update_bits(data->regmap, BMC150_MAGN_REG_INT_DRDY, 801 805 BMC150_MAGN_MASK_DRDY_EN, 802 806 state << BMC150_MAGN_SHIFT_DRDY_EN); 803 807 if (ret < 0) 804 804 - goto err_unlock; 808 808 + return ret; 805 809 806 810 data->dready_trigger_on = state; 807 811 808 812 if (state) { 809 813 ret = bmc150_magn_reset_intr(data); 810 814 if (ret < 0) 811 811 - goto err_unlock; 815 815 + return ret; 812 816 } 813 813 - mutex_unlock(&data->mutex); 814 817 815 818 return 0; 816 816 - 817 817 - err_unlock: 818 818 - mutex_unlock(&data->mutex); 819 819 - return ret; 820 819 } 821 820 822 821 static const struct iio_trigger_ops bmc150_magn_trigger_ops = { ··· 970 977 if (data->dready_trig) 971 978 iio_trigger_unregister(data->dready_trig); 972 979 973 973 - mutex_lock(&data->mutex); 974 974 - bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true); 975 975 - mutex_unlock(&data->mutex); 980 980 + bmc150_magn_set_power_mode_locked(data, BMC150_MAGN_POWER_MODE_SUSPEND); 976 981 977 982 regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators); 978 983 } ··· 983 992 struct bmc150_magn_data *data = iio_priv(indio_dev); 984 993 int ret; 985 994 986 986 - mutex_lock(&data->mutex); 987 987 - ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SLEEP, 988 988 - true); 989 989 - mutex_unlock(&data->mutex); 995 995 + ret = bmc150_magn_set_power_mode_locked(data, 996 996 + BMC150_MAGN_POWER_MODE_SLEEP); 990 997 if (ret < 0) { 991 998 dev_err(dev, "powering off device failed\n"); 992 999 return ret; ··· 1010 1021 { 1011 1022 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1012 1023 struct bmc150_magn_data *data = iio_priv(indio_dev); 1013 1013 - int ret; 1014 1024 1015 1015 - mutex_lock(&data->mutex); 1016 1016 - ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SLEEP, 1017 1017 - true); 1018 1018 - mutex_unlock(&data->mutex); 1019 1019 - 1020 1020 - return ret; 1025 1025 + return bmc150_magn_set_power_mode_locked(data, 1026 1026 + BMC150_MAGN_POWER_MODE_SLEEP); 1021 1027 } 1022 1028 1023 1029 static int bmc150_magn_resume(struct device *dev) 1024 1030 { 1025 1031 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1026 1032 struct bmc150_magn_data *data = iio_priv(indio_dev); 1027 1027 - int ret; 1028 1033 1029 1029 - mutex_lock(&data->mutex); 1030 1030 - ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL, 1031 1031 - true); 1032 1032 - mutex_unlock(&data->mutex); 1033 1033 - 1034 1034 - return ret; 1034 1034 + return bmc150_magn_set_power_mode_locked(data, 1035 1035 + BMC150_MAGN_POWER_MODE_NORMAL); 1035 1036 } 1036 1037 #endif 1037 1038

+7 -14

drivers/iio/magnetometer/si7210.c

reviewed

··· 128 128 struct si7210_data { 129 129 struct regmap *regmap; 130 130 struct i2c_client *client; 131 131 - struct regulator *vdd; 132 131 struct mutex fetch_lock; /* lock for a single measurement fetch */ 132 132 + unsigned int vdd_uV; 133 133 s8 temp_offset; 134 134 s8 temp_gain; 135 135 s8 scale_20_a[A_REGS_COUNT]; ··· 221 221 temp *= (1 + (data->temp_gain / 2048)); 222 222 temp += (int)(MICRO / 16) * data->temp_offset; 223 223 224 224 - ret = regulator_get_voltage(data->vdd); 225 225 - if (ret < 0) 226 226 - return ret; 227 227 - 228 224 /* temp -= 0.222 * VDD */ 229 229 - temp -= 222 * div_s64(ret, MILLI); 225 225 + temp -= 222 * (data->vdd_uV / MILLI); 230 226 231 227 *val = div_s64(temp, MILLI); 232 228 ··· 392 396 return dev_err_probe(&client->dev, PTR_ERR(data->regmap), 393 397 "failed to register regmap\n"); 394 398 395 395 - data->vdd = devm_regulator_get(&client->dev, "vdd"); 396 396 - if (IS_ERR(data->vdd)) 397 397 - return dev_err_probe(&client->dev, PTR_ERR(data->vdd), 398 398 - "failed to get VDD regulator\n"); 399 399 - 400 400 - ret = regulator_enable(data->vdd); 401 401 - if (ret) 402 402 - return ret; 399 399 + ret = devm_regulator_get_enable_read_voltage(&client->dev, "vdd"); 400 400 + if (ret < 0) 401 401 + return dev_err_probe(&client->dev, ret, 402 402 + "Failed to get vdd regulator\n"); 403 403 + data->vdd_uV = ret; 403 404 404 405 indio_dev->name = dev_name(&client->dev); 405 406 indio_dev->modes = INDIO_DIRECT_MODE;

+1 -1

drivers/iio/magnetometer/yamaha-yas530.c

reviewed

··· 1223 1223 * as the values for [x, y1, y2]. The value is +/-31 1224 1224 * but the effect on the raw values is much larger. 1225 1225 * The effect of the offset is to bring the measure 1226 1226 - * rougly to the center. 1226 1226 + * roughly to the center. 1227 1227 */ 1228 1228 ox = 0; 1229 1229 oy1 = 0;

+1 -1

drivers/iio/pressure/bmp280-spi.c

reviewed

··· 47 47 return -EINVAL; 48 48 49 49 /* 50 50 - * According to the BMP3xx datasheets, for a basic SPI read opertion, 50 50 + * According to the BMP3xx datasheets, for a basic SPI read operation, 51 51 * the first byte needs to be dropped and the rest are the requested 52 52 * data. 53 53 */

+1 -1

drivers/iio/pressure/hsc030pa.c

reviewed

··· 273 273 * @data: structure containing instantiated sensor data 274 274 * Return: true only if both status bits are zero 275 275 * 276 276 - * the two MSB from the first transfered byte contain a status code 276 276 + * The two MSB from the first transferred byte contain a status code 277 277 * 00 - normal operation, valid data 278 278 * 01 - device in factory programming mode 279 279 * 10 - stale data

+6 -1

drivers/iio/pressure/hsc030pa_i2c.c

reviewed

··· 34 34 msg.buf = data->buffer; 35 35 36 36 ret = i2c_transfer(client->adapter, &msg, 1); 37 37 + if (ret < 0) 38 38 + return ret; 37 39 38 38 - return (ret == 2) ? 0 : ret; 40 40 + if (ret != 1) 41 41 + return -EIO; 42 42 + 43 43 + return 0; 39 44 } 40 45 41 46 static int hsc_i2c_probe(struct i2c_client *client)

+1 -1

drivers/iio/pressure/rohm-bm1390.c

reviewed

··· 440 440 * the timestamps. If we are ran from IRQ, then the 441 441 * IRQF_ONESHOT has us covered - but if we are ran by the 442 442 * user-space read we need to disable the IRQ to be on a safe 443 443 - * side. We do this usng synchronous disable so that if the 443 443 + * side. We do this using synchronous disable so that if the 444 444 * IRQ thread is being ran on other CPU we wait for it to be 445 445 * finished. 446 446 */

+1 -1

drivers/iio/pressure/zpa2326.c

reviewed

··· 840 840 841 841 complete: 842 842 /* 843 843 - * Wake up direct or externaly triggered buffer mode waiters: see 843 843 + * Wake up direct or externally triggered buffer mode waiters: see 844 844 * zpa2326_sample_oneshot() and zpa2326_trigger_handler(). 845 845 */ 846 846 complete(&priv->data_ready);

+15

drivers/iio/proximity/Kconfig

reviewed

··· 244 244 To compile this driver as a module, choose M here: the 245 245 module will be called vl53l0x-i2c. 246 246 247 247 + config VL53L1X_I2C 248 248 + tristate "STMicroelectronics VL53L1X ToF ranger sensor (I2C)" 249 249 + depends on I2C 250 250 + select IIO_BUFFER 251 251 + select IIO_TRIGGERED_BUFFER 252 252 + select REGMAP_I2C 253 253 + select RESET_CONTROLLER 254 254 + help 255 255 + Say Y here to build a driver for STMicroelectronics VL53L1X 256 256 + ToF ranger sensors with i2c interface. 257 257 + This driver can be used to measure the distance of objects. 258 258 + 259 259 + To compile this driver as a module, choose M here: the 260 260 + module will be called vl53l1x-i2c. 261 261 + 247 262 config AW96103 248 263 tristate "AW96103/AW96105 Awinic proximity sensor" 249 264 select REGMAP_I2C

+1

drivers/iio/proximity/Makefile

reviewed

··· 23 23 obj-$(CONFIG_SX9500) += sx9500.o 24 24 obj-$(CONFIG_VCNL3020) += vcnl3020.o 25 25 obj-$(CONFIG_VL53L0X_I2C) += vl53l0x-i2c.o 26 26 + obj-$(CONFIG_VL53L1X_I2C) += vl53l1x-i2c.o 26 27 obj-$(CONFIG_AW96103) += aw96103.o 27 28

+4 -1

drivers/iio/proximity/hx9023s.c

reviewed

··· 1088 1088 struct device *dev = &client->dev; 1089 1089 struct iio_dev *indio_dev; 1090 1090 struct hx9023s_data *data; 1091 1091 + const char *fw_name; 1091 1092 int ret; 1092 1093 1093 1094 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); ··· 1126 1125 if (ret) 1127 1126 return dev_err_probe(dev, ret, "channel config failed\n"); 1128 1127 1129 1129 - ret = request_firmware_nowait(THIS_MODULE, true, "hx9023s.bin", dev, 1128 1128 + fw_name = "hx9023s.bin"; 1129 1129 + device_property_read_string(dev, "firmware-name", &fw_name); 1130 1130 + ret = request_firmware_nowait(THIS_MODULE, true, fw_name, dev, 1130 1131 GFP_KERNEL, data, hx9023s_cfg_update); 1131 1132 if (ret) 1132 1133 return dev_err_probe(dev, ret, "reg config failed\n");

+1 -1

drivers/iio/proximity/sx9324.c

reviewed

··· 821 821 { SX9324_REG_ADV_CTRL10, 0x00, "adv_ctrl10" }, 822 822 { SX9324_REG_ADV_CTRL11, 0x00, "adv_ctrl11" }, 823 823 { SX9324_REG_ADV_CTRL12, 0x00, "adv_ctrl12" }, 824 824 - /* TODO(gwendal): SAR currenly disabled */ 824 824 + /* TODO(gwendal): SAR currently disabled */ 825 825 { SX9324_REG_ADV_CTRL13, 0x00, "adv_ctrl13" }, 826 826 { SX9324_REG_ADV_CTRL14, 0x00, "adv_ctrl14" }, 827 827 { SX9324_REG_ADV_CTRL15, 0x00, "adv_ctrl15" },

+756

drivers/iio/proximity/vl53l1x-i2c.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 2 + /* 3 3 + * Support for ST VL53L1X FlightSense ToF Ranging Sensor on a i2c bus. 4 4 + * 5 5 + * Copyright (C) 2026 Siratul Islam <email@sirat.me> 6 6 + * 7 7 + * Datasheet available at 8 8 + * <https://www.st.com/resource/en/datasheet/vl53l1x.pdf> 9 9 + * 10 10 + * Default 7-bit i2c slave address 0x29. 11 11 + * 12 12 + * The VL53L1X requires a firmware configuration blob to be loaded at boot. 13 13 + * Register values for the default configuration are taken from 14 14 + * ST's VL53L1X Ultra Lite Driver (STSW-IMG009). 15 15 + */ 16 16 + 17 17 + #include <linux/array_size.h> 18 18 + #include <linux/bits.h> 19 19 + #include <linux/bitfield.h> 20 20 + #include <linux/completion.h> 21 21 + #include <linux/delay.h> 22 22 + #include <linux/dev_printk.h> 23 23 + #include <linux/err.h> 24 24 + #include <linux/i2c.h> 25 25 + #include <linux/interrupt.h> 26 26 + #include <linux/math.h> 27 27 + #include <linux/mod_devicetable.h> 28 28 + #include <linux/module.h> 29 29 + #include <linux/regmap.h> 30 30 + #include <linux/regulator/consumer.h> 31 31 + #include <linux/reset.h> 32 32 + #include <linux/time.h> 33 33 + #include <linux/types.h> 34 34 + 35 35 + #include <asm/byteorder.h> 36 36 + 37 37 + #include <linux/iio/buffer.h> 38 38 + #include <linux/iio/iio.h> 39 39 + #include <linux/iio/trigger.h> 40 40 + #include <linux/iio/trigger_consumer.h> 41 41 + #include <linux/iio/triggered_buffer.h> 42 42 + 43 43 + #define VL53L1X_REG_SOFT_RESET 0x0000 44 44 + #define VL53L1X_REG_VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x0008 45 45 + #define VL53L1X_REG_VHV_CONFIG__INIT 0x000B 46 46 + #define VL53L1X_REG_GPIO_HV_MUX__CTRL 0x0030 47 47 + #define VL53L1X_REG_GPIO__TIO_HV_STATUS 0x0031 48 48 + #define VL53L1X_REG_SYSTEM__INTERRUPT_CONFIG_GPIO 0x0046 49 49 + #define VL53L1X_REG_PHASECAL_CONFIG__TIMEOUT_MACROP 0x004B 50 50 + #define VL53L1X_REG_RANGE_CONFIG__TIMEOUT_MACROP_A 0x005E 51 51 + #define VL53L1X_REG_RANGE_CONFIG__VCSEL_PERIOD_A 0x0060 52 52 + #define VL53L1X_REG_RANGE_CONFIG__TIMEOUT_MACROP_B 0x0061 53 53 + #define VL53L1X_REG_RANGE_CONFIG__VCSEL_PERIOD_B 0x0063 54 54 + #define VL53L1X_REG_RANGE_CONFIG__VALID_PHASE_HIGH 0x0069 55 55 + #define VL53L1X_REG_SYSTEM__INTERMEASUREMENT_PERIOD 0x006C 56 56 + #define VL53L1X_REG_SD_CONFIG__WOI_SD0 0x0078 57 57 + #define VL53L1X_REG_SD_CONFIG__WOI_SD1 0x0079 58 58 + #define VL53L1X_REG_SD_CONFIG__INITIAL_PHASE_SD0 0x007A 59 59 + #define VL53L1X_REG_SD_CONFIG__INITIAL_PHASE_SD1 0x007B 60 60 + #define VL53L1X_REG_SYSTEM__INTERRUPT_CLEAR 0x0086 61 61 + #define VL53L1X_REG_SYSTEM__MODE_START 0x0087 62 62 + #define VL53L1X_REG_RESULT__RANGE_STATUS 0x0089 63 63 + #define VL53L1X_REG_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0096 64 64 + #define VL53L1X_REG_RESULT__OSC_CALIBRATE_VAL 0x00DE 65 65 + #define VL53L1X_REG_FIRMWARE__SYSTEM_STATUS 0x00E5 66 66 + #define VL53L1X_REG_IDENTIFICATION__MODEL_ID 0x010F 67 67 + #define VL53L1X_REG_DEFAULT_CONFIG 0x002D 68 68 + 69 69 + #define VL53L1X_MODEL_ID_VAL 0xEACC 70 70 + 71 71 + #define VL53L1X_MODE_START_TIMED 0x40 72 72 + #define VL53L1X_MODE_START_STOP 0x00 73 73 + 74 74 + #define VL53L1X_INT_NEW_SAMPLE_READY 0x02 75 75 + 76 76 + #define VL53L1X_GPIO_HV_MUX_POLARITY BIT(4) 77 77 + 78 78 + #define VL53L1X_VHV_LOOP_BOUND_TWO 0x09 79 79 + 80 80 + #define VL53L1X_RANGE_STATUS_MASK GENMASK(4, 0) 81 81 + #define VL53L1X_RANGE_STATUS_VALID 9 82 82 + 83 83 + #define VL53L1X_OSC_CALIBRATE_MASK GENMASK(9, 0) 84 84 + 85 85 + /* Inter-measurement period uses PLL divider with 1.075 oscillator correction */ 86 86 + static const struct u32_fract vl53l1x_osc_correction = { 87 87 + .numerator = 1075, 88 88 + .denominator = 1000, 89 89 + }; 90 90 + 91 91 + enum vl53l1x_distance_mode { 92 92 + VL53L1X_SHORT, 93 93 + VL53L1X_LONG, 94 94 + }; 95 95 + 96 96 + struct vl53l1x_data { 97 97 + struct regmap *regmap; 98 98 + struct completion completion; 99 99 + struct reset_control *xshut_reset; 100 100 + enum vl53l1x_distance_mode distance_mode; 101 101 + u8 gpio_polarity; 102 102 + int irq; 103 103 + }; 104 104 + 105 105 + static const struct regmap_range vl53l1x_volatile_ranges[] = { 106 106 + regmap_reg_range(VL53L1X_REG_GPIO__TIO_HV_STATUS, 107 107 + VL53L1X_REG_GPIO__TIO_HV_STATUS), 108 108 + regmap_reg_range(VL53L1X_REG_RESULT__RANGE_STATUS, 109 109 + VL53L1X_REG_RESULT__RANGE_STATUS), 110 110 + regmap_reg_range(VL53L1X_REG_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0, 111 111 + VL53L1X_REG_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 + 1), 112 112 + regmap_reg_range(VL53L1X_REG_RESULT__OSC_CALIBRATE_VAL, 113 113 + VL53L1X_REG_RESULT__OSC_CALIBRATE_VAL + 1), 114 114 + regmap_reg_range(VL53L1X_REG_FIRMWARE__SYSTEM_STATUS, 115 115 + VL53L1X_REG_FIRMWARE__SYSTEM_STATUS), 116 116 + }; 117 117 + 118 118 + static const struct regmap_access_table vl53l1x_volatile_table = { 119 119 + .yes_ranges = vl53l1x_volatile_ranges, 120 120 + .n_yes_ranges = ARRAY_SIZE(vl53l1x_volatile_ranges), 121 121 + }; 122 122 + 123 123 + static const struct regmap_range vl53l1x_write_only_ranges[] = { 124 124 + regmap_reg_range(VL53L1X_REG_SOFT_RESET, VL53L1X_REG_SOFT_RESET), 125 125 + regmap_reg_range(VL53L1X_REG_SYSTEM__INTERRUPT_CLEAR, 126 126 + VL53L1X_REG_SYSTEM__MODE_START), 127 127 + }; 128 128 + 129 129 + static const struct regmap_access_table vl53l1x_readable_table = { 130 130 + .no_ranges = vl53l1x_write_only_ranges, 131 131 + .n_no_ranges = ARRAY_SIZE(vl53l1x_write_only_ranges), 132 132 + }; 133 133 + 134 134 + static const struct regmap_config vl53l1x_regmap_config = { 135 135 + .reg_bits = 16, 136 136 + .val_bits = 8, 137 137 + /* MODEL_ID is 16-bit. +1 covers the second byte at 0x0110 */ 138 138 + .max_register = VL53L1X_REG_IDENTIFICATION__MODEL_ID + 1, 139 139 + .cache_type = REGCACHE_MAPLE, 140 140 + .volatile_table = &vl53l1x_volatile_table, 141 141 + .rd_table = &vl53l1x_readable_table, 142 142 + }; 143 143 + 144 144 + static int vl53l1x_read_u16(struct vl53l1x_data *data, u16 reg, u16 *val) 145 145 + { 146 146 + __be16 buf; 147 147 + int ret; 148 148 + 149 149 + ret = regmap_bulk_read(data->regmap, reg, &buf, sizeof(buf)); 150 150 + if (ret) 151 151 + return ret; 152 152 + 153 153 + *val = be16_to_cpu(buf); 154 154 + return 0; 155 155 + } 156 156 + 157 157 + static int vl53l1x_write_u16(struct vl53l1x_data *data, u16 reg, u16 val) 158 158 + { 159 159 + __be16 buf = cpu_to_be16(val); 160 160 + 161 161 + return regmap_bulk_write(data->regmap, reg, &buf, sizeof(buf)); 162 162 + } 163 163 + 164 164 + static int vl53l1x_write_u32(struct vl53l1x_data *data, u16 reg, u32 val) 165 165 + { 166 166 + __be32 buf = cpu_to_be32(val); 167 167 + 168 168 + return regmap_bulk_write(data->regmap, reg, &buf, sizeof(buf)); 169 169 + } 170 170 + 171 171 + static int vl53l1x_clear_irq(struct vl53l1x_data *data) 172 172 + { 173 173 + return regmap_write(data->regmap, VL53L1X_REG_SYSTEM__INTERRUPT_CLEAR, 0x01); 174 174 + } 175 175 + 176 176 + static int vl53l1x_start_ranging(struct vl53l1x_data *data) 177 177 + { 178 178 + int ret; 179 179 + 180 180 + ret = vl53l1x_clear_irq(data); 181 181 + if (ret) 182 182 + return ret; 183 183 + 184 184 + return regmap_write(data->regmap, VL53L1X_REG_SYSTEM__MODE_START, 185 185 + VL53L1X_MODE_START_TIMED); 186 186 + } 187 187 + 188 188 + static int vl53l1x_stop_ranging(struct vl53l1x_data *data) 189 189 + { 190 190 + return regmap_write(data->regmap, VL53L1X_REG_SYSTEM__MODE_START, 191 191 + VL53L1X_MODE_START_STOP); 192 192 + } 193 193 + 194 194 + /* 195 195 + * Default configuration blob from ST's VL53L1X Ultra Lite Driver 196 196 + * (STSW-IMG009). 197 197 + */ 198 198 + static const u8 vl53l1x_default_config[] = { 199 199 + 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x02, 0x08, /* reg 0x2d..0x34 */ 200 200 + 0x00, 0x08, 0x10, 0x01, 0x01, 0x00, 0x00, 0x00, /* reg 0x35..0x3c */ 201 201 + 0x00, 0xFF, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, /* reg 0x3d..0x44 */ 202 202 + 0x00, 0x20, 0x0B, 0x00, 0x00, 0x02, 0x0A, 0x21, /* reg 0x45..0x4c */ 203 203 + 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0xC8, /* reg 0x4d..0x54 */ 204 204 + 0x00, 0x00, 0x38, 0xFF, 0x01, 0x00, 0x08, 0x00, /* reg 0x55..0x5c */ 205 205 + 0x00, 0x01, 0xCC, 0x0F, 0x01, 0xF1, 0x0D, 0x01, /* reg 0x5d..0x64 */ 206 206 + 0x68, 0x00, 0x80, 0x08, 0xB8, 0x00, 0x00, 0x00, /* reg 0x65..0x6c */ 207 207 + 0x00, 0x0F, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, /* reg 0x6d..0x74 */ 208 208 + 0x00, 0x00, 0x01, 0x0F, 0x0D, 0x0E, 0x0E, 0x00, /* reg 0x75..0x7c */ 209 209 + 0x00, 0x02, 0xC7, 0xFF, 0x9B, 0x00, 0x00, 0x00, /* reg 0x7d..0x84 */ 210 210 + 0x01, 0x00, 0x00, /* reg 0x85..0x87 */ 211 211 + }; 212 212 + 213 213 + static int vl53l1x_chip_init(struct vl53l1x_data *data) 214 214 + { 215 215 + struct device *dev = regmap_get_device(data->regmap); 216 216 + unsigned int val; 217 217 + u16 model_id; 218 218 + int ret; 219 219 + 220 220 + if (!data->xshut_reset) { 221 221 + ret = regmap_write(data->regmap, VL53L1X_REG_SOFT_RESET, 0x00); 222 222 + if (ret) 223 223 + return ret; 224 224 + fsleep(100); /* conservative reset pulse, no spec */ 225 225 + 226 226 + ret = regmap_write(data->regmap, VL53L1X_REG_SOFT_RESET, 0x01); 227 227 + if (ret) 228 228 + return ret; 229 229 + fsleep(1000); /* conservative boot wait, no spec */ 230 230 + } 231 231 + 232 232 + ret = regmap_read_poll_timeout(data->regmap, 233 233 + VL53L1X_REG_FIRMWARE__SYSTEM_STATUS, val, 234 234 + val & BIT(0), 235 235 + 1 * USEC_PER_MSEC, 236 236 + 100 * USEC_PER_MSEC); 237 237 + if (ret) 238 238 + return dev_err_probe(dev, ret, "firmware boot timeout\n"); 239 239 + 240 240 + ret = vl53l1x_read_u16(data, VL53L1X_REG_IDENTIFICATION__MODEL_ID, 241 241 + &model_id); 242 242 + if (ret) 243 243 + return ret; 244 244 + 245 245 + if (model_id != VL53L1X_MODEL_ID_VAL) 246 246 + dev_info(dev, "unknown model id: 0x%04x, continuing\n", model_id); 247 247 + 248 248 + ret = regmap_bulk_write(data->regmap, VL53L1X_REG_DEFAULT_CONFIG, 249 249 + vl53l1x_default_config, 250 250 + sizeof(vl53l1x_default_config)); 251 251 + if (ret) 252 252 + return ret; 253 253 + 254 254 + ret = regmap_read(data->regmap, VL53L1X_REG_GPIO_HV_MUX__CTRL, &val); 255 255 + if (ret) 256 256 + return ret; 257 257 + data->gpio_polarity = !!(val & VL53L1X_GPIO_HV_MUX_POLARITY); 258 258 + 259 259 + /* Initial ranging cycle for VHV calibration */ 260 260 + ret = vl53l1x_start_ranging(data); 261 261 + if (ret) 262 262 + return ret; 263 263 + 264 264 + /* 1ms poll, 1s timeout covers max timing budgets (per ST Ultra Lite Driver) */ 265 265 + ret = regmap_read_poll_timeout(data->regmap, 266 266 + VL53L1X_REG_GPIO__TIO_HV_STATUS, val, 267 267 + (val & 1) != data->gpio_polarity, 268 268 + 1 * USEC_PER_MSEC, 269 269 + 1000 * USEC_PER_MSEC); 270 270 + if (ret) 271 271 + return ret; 272 272 + 273 273 + ret = vl53l1x_clear_irq(data); 274 274 + if (ret) 275 275 + return ret; 276 276 + 277 277 + ret = vl53l1x_stop_ranging(data); 278 278 + if (ret) 279 279 + return ret; 280 280 + 281 281 + ret = regmap_write(data->regmap, 282 282 + VL53L1X_REG_VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND, 283 283 + VL53L1X_VHV_LOOP_BOUND_TWO); 284 284 + if (ret) 285 285 + return ret; 286 286 + 287 287 + return regmap_write(data->regmap, VL53L1X_REG_VHV_CONFIG__INIT, 0x00); 288 288 + } 289 289 + 290 290 + static const struct reg_sequence vl53l1x_mode_short[] = { 291 291 + { VL53L1X_REG_PHASECAL_CONFIG__TIMEOUT_MACROP, 0x14 }, 292 292 + { VL53L1X_REG_RANGE_CONFIG__VCSEL_PERIOD_A, 0x07 }, 293 293 + { VL53L1X_REG_RANGE_CONFIG__VCSEL_PERIOD_B, 0x05 }, 294 294 + { VL53L1X_REG_RANGE_CONFIG__VALID_PHASE_HIGH, 0x38 }, 295 295 + { VL53L1X_REG_SD_CONFIG__WOI_SD0, 0x07 }, 296 296 + { VL53L1X_REG_SD_CONFIG__WOI_SD1, 0x05 }, 297 297 + { VL53L1X_REG_SD_CONFIG__INITIAL_PHASE_SD0, 0x06 }, 298 298 + { VL53L1X_REG_SD_CONFIG__INITIAL_PHASE_SD1, 0x06 }, 299 299 + }; 300 300 + 301 301 + static const struct reg_sequence vl53l1x_mode_long[] = { 302 302 + { VL53L1X_REG_PHASECAL_CONFIG__TIMEOUT_MACROP, 0x0A }, 303 303 + { VL53L1X_REG_RANGE_CONFIG__VCSEL_PERIOD_A, 0x0F }, 304 304 + { VL53L1X_REG_RANGE_CONFIG__VCSEL_PERIOD_B, 0x0D }, 305 305 + { VL53L1X_REG_RANGE_CONFIG__VALID_PHASE_HIGH, 0xB8 }, 306 306 + { VL53L1X_REG_SD_CONFIG__WOI_SD0, 0x0F }, 307 307 + { VL53L1X_REG_SD_CONFIG__WOI_SD1, 0x0D }, 308 308 + { VL53L1X_REG_SD_CONFIG__INITIAL_PHASE_SD0, 0x0E }, 309 309 + { VL53L1X_REG_SD_CONFIG__INITIAL_PHASE_SD1, 0x0E }, 310 310 + }; 311 311 + 312 312 + static const struct { 313 313 + const struct reg_sequence *regs; 314 314 + size_t num_regs; 315 315 + } vl53l1x_mode_configs[] = { 316 316 + [VL53L1X_SHORT] = { vl53l1x_mode_short, ARRAY_SIZE(vl53l1x_mode_short) }, 317 317 + [VL53L1X_LONG] = { vl53l1x_mode_long, ARRAY_SIZE(vl53l1x_mode_long) }, 318 318 + }; 319 319 + 320 320 + static int vl53l1x_set_distance_mode(struct vl53l1x_data *data, 321 321 + enum vl53l1x_distance_mode mode) 322 322 + { 323 323 + int ret; 324 324 + 325 325 + if (mode >= ARRAY_SIZE(vl53l1x_mode_configs)) 326 326 + return -EINVAL; 327 327 + 328 328 + ret = regmap_multi_reg_write(data->regmap, 329 329 + vl53l1x_mode_configs[mode].regs, 330 330 + vl53l1x_mode_configs[mode].num_regs); 331 331 + if (ret) 332 332 + return ret; 333 333 + 334 334 + data->distance_mode = mode; 335 335 + return 0; 336 336 + } 337 337 + 338 338 + /* 339 339 + * The timing budget controls how long the sensor spends collecting 340 340 + * a single range measurement. Pre-computed TIMEOUT_MACROP register 341 341 + * values from ST's VL53L1X Ultra Lite Driver. 342 342 + */ 343 343 + static int vl53l1x_set_timing_budget(struct vl53l1x_data *data, u16 budget_ms) 344 344 + { 345 345 + u16 timeout_a, timeout_b; 346 346 + int ret; 347 347 + 348 348 + switch (data->distance_mode) { 349 349 + case VL53L1X_SHORT: 350 350 + switch (budget_ms) { 351 351 + case 15: 352 352 + timeout_a = 0x001D; 353 353 + timeout_b = 0x0027; 354 354 + break; 355 355 + case 20: 356 356 + timeout_a = 0x0051; 357 357 + timeout_b = 0x006E; 358 358 + break; 359 359 + case 33: 360 360 + timeout_a = 0x00D6; 361 361 + timeout_b = 0x006E; 362 362 + break; 363 363 + case 50: 364 364 + timeout_a = 0x01AE; 365 365 + timeout_b = 0x01E8; 366 366 + break; 367 367 + case 100: 368 368 + timeout_a = 0x02E1; 369 369 + timeout_b = 0x0388; 370 370 + break; 371 371 + case 200: 372 372 + timeout_a = 0x03E1; 373 373 + timeout_b = 0x0496; 374 374 + break; 375 375 + case 500: 376 376 + timeout_a = 0x0591; 377 377 + timeout_b = 0x05C1; 378 378 + break; 379 379 + default: 380 380 + return -EINVAL; 381 381 + } 382 382 + break; 383 383 + case VL53L1X_LONG: 384 384 + switch (budget_ms) { 385 385 + case 20: 386 386 + timeout_a = 0x001E; 387 387 + timeout_b = 0x0022; 388 388 + break; 389 389 + case 33: 390 390 + timeout_a = 0x0060; 391 391 + timeout_b = 0x006E; 392 392 + break; 393 393 + case 50: 394 394 + timeout_a = 0x00AD; 395 395 + timeout_b = 0x00C6; 396 396 + break; 397 397 + case 100: 398 398 + timeout_a = 0x01CC; 399 399 + timeout_b = 0x01EA; 400 400 + break; 401 401 + case 200: 402 402 + timeout_a = 0x02D9; 403 403 + timeout_b = 0x02F8; 404 404 + break; 405 405 + case 500: 406 406 + timeout_a = 0x048F; 407 407 + timeout_b = 0x04A4; 408 408 + break; 409 409 + default: 410 410 + return -EINVAL; 411 411 + } 412 412 + break; 413 413 + default: 414 414 + return -EINVAL; 415 415 + } 416 416 + 417 417 + ret = vl53l1x_write_u16(data, VL53L1X_REG_RANGE_CONFIG__TIMEOUT_MACROP_A, 418 418 + timeout_a); 419 419 + if (ret) 420 420 + return ret; 421 421 + 422 422 + return vl53l1x_write_u16(data, VL53L1X_REG_RANGE_CONFIG__TIMEOUT_MACROP_B, 423 423 + timeout_b); 424 424 + } 425 425 + 426 426 + static int vl53l1x_set_inter_measurement_ms(struct vl53l1x_data *data, 427 427 + u16 period_ms) 428 428 + { 429 429 + u16 osc_calibrate_val; 430 430 + u16 clock_pll; 431 431 + u32 inter_meas; 432 432 + int ret; 433 433 + 434 434 + ret = vl53l1x_read_u16(data, VL53L1X_REG_RESULT__OSC_CALIBRATE_VAL, 435 435 + &osc_calibrate_val); 436 436 + if (ret) 437 437 + return ret; 438 438 + 439 439 + clock_pll = osc_calibrate_val & VL53L1X_OSC_CALIBRATE_MASK; 440 440 + inter_meas = (clock_pll * period_ms * vl53l1x_osc_correction.numerator) / 441 441 + vl53l1x_osc_correction.denominator; 442 442 + 443 443 + return vl53l1x_write_u32(data, 444 444 + VL53L1X_REG_SYSTEM__INTERMEASUREMENT_PERIOD, 445 445 + inter_meas); 446 446 + } 447 447 + 448 448 + static int vl53l1x_read_proximity(struct vl53l1x_data *data, int *val) 449 449 + { 450 450 + unsigned int range_status; 451 451 + u16 distance; 452 452 + int ret; 453 453 + 454 454 + if (data->irq) { 455 455 + reinit_completion(&data->completion); 456 456 + 457 457 + ret = vl53l1x_clear_irq(data); 458 458 + if (ret) 459 459 + return ret; 460 460 + 461 461 + if (!wait_for_completion_timeout(&data->completion, HZ)) 462 462 + return -ETIMEDOUT; 463 463 + } else { 464 464 + unsigned int rdy; 465 465 + 466 466 + /* 1ms poll, 1s timeout covers max timing budgets (per ST Ultra Lite Driver) */ 467 467 + ret = regmap_read_poll_timeout(data->regmap, 468 468 + VL53L1X_REG_GPIO__TIO_HV_STATUS, rdy, 469 469 + (rdy & 1) != data->gpio_polarity, 470 470 + 1 * USEC_PER_MSEC, 471 471 + 1000 * USEC_PER_MSEC); 472 472 + if (ret) 473 473 + return ret; 474 474 + } 475 475 + 476 476 + ret = regmap_read(data->regmap, VL53L1X_REG_RESULT__RANGE_STATUS, 477 477 + &range_status); 478 478 + if (ret) 479 479 + goto clear_irq; 480 480 + 481 481 + if (FIELD_GET(VL53L1X_RANGE_STATUS_MASK, range_status) != 482 482 + VL53L1X_RANGE_STATUS_VALID) { 483 483 + ret = -EIO; 484 484 + goto clear_irq; 485 485 + } 486 486 + 487 487 + ret = vl53l1x_read_u16(data, 488 488 + VL53L1X_REG_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0, 489 489 + &distance); 490 490 + if (ret) 491 491 + goto clear_irq; 492 492 + 493 493 + *val = distance; 494 494 + 495 495 + clear_irq: 496 496 + vl53l1x_clear_irq(data); 497 497 + return ret; 498 498 + } 499 499 + 500 500 + static const struct iio_chan_spec vl53l1x_channels[] = { 501 501 + { 502 502 + .type = IIO_DISTANCE, 503 503 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 504 504 + BIT(IIO_CHAN_INFO_SCALE), 505 505 + .scan_index = 0, 506 506 + .scan_type = { 507 507 + .sign = 'u', 508 508 + .realbits = 16, 509 509 + .storagebits = 16, 510 510 + }, 511 511 + }, 512 512 + IIO_CHAN_SOFT_TIMESTAMP(1), 513 513 + }; 514 514 + 515 515 + static int vl53l1x_read_raw(struct iio_dev *indio_dev, 516 516 + const struct iio_chan_spec *chan, 517 517 + int *val, int *val2, long mask) 518 518 + { 519 519 + struct vl53l1x_data *data = iio_priv(indio_dev); 520 520 + int ret; 521 521 + 522 522 + if (chan->type != IIO_DISTANCE) 523 523 + return -EINVAL; 524 524 + 525 525 + switch (mask) { 526 526 + case IIO_CHAN_INFO_RAW: 527 527 + if (!iio_device_claim_direct(indio_dev)) 528 528 + return -EBUSY; 529 529 + ret = vl53l1x_read_proximity(data, val); 530 530 + iio_device_release_direct(indio_dev); 531 531 + if (ret) 532 532 + return ret; 533 533 + return IIO_VAL_INT; 534 534 + case IIO_CHAN_INFO_SCALE: 535 535 + *val = 0; 536 536 + *val2 = 1000; 537 537 + return IIO_VAL_INT_PLUS_MICRO; 538 538 + default: 539 539 + return -EINVAL; 540 540 + } 541 541 + } 542 542 + 543 543 + static const struct iio_info vl53l1x_info = { 544 544 + .read_raw = vl53l1x_read_raw, 545 545 + .validate_trigger = iio_validate_own_trigger, 546 546 + }; 547 547 + 548 548 + static irqreturn_t vl53l1x_trigger_handler(int irq, void *priv) 549 549 + { 550 550 + struct iio_poll_func *pf = priv; 551 551 + struct iio_dev *indio_dev = pf->indio_dev; 552 552 + struct vl53l1x_data *data = iio_priv(indio_dev); 553 553 + struct { 554 554 + u16 distance; 555 555 + aligned_s64 timestamp; 556 556 + } scan = { }; 557 557 + unsigned int range_status; 558 558 + int ret; 559 559 + 560 560 + ret = regmap_read(data->regmap, VL53L1X_REG_RESULT__RANGE_STATUS, 561 561 + &range_status); 562 562 + if (ret) 563 563 + goto notify_and_clear_irq; 564 564 + if (FIELD_GET(VL53L1X_RANGE_STATUS_MASK, range_status) != 565 565 + VL53L1X_RANGE_STATUS_VALID) 566 566 + goto notify_and_clear_irq; 567 567 + 568 568 + ret = vl53l1x_read_u16(data, 569 569 + VL53L1X_REG_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0, 570 570 + &scan.distance); 571 571 + if (ret) 572 572 + goto notify_and_clear_irq; 573 573 + 574 574 + iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan), 575 575 + iio_get_time_ns(indio_dev)); 576 576 + 577 577 + notify_and_clear_irq: 578 578 + iio_trigger_notify_done(indio_dev->trig); 579 579 + vl53l1x_clear_irq(data); 580 580 + 581 581 + return IRQ_HANDLED; 582 582 + } 583 583 + 584 584 + static irqreturn_t vl53l1x_irq_handler(int irq, void *priv) 585 585 + { 586 586 + struct iio_dev *indio_dev = priv; 587 587 + struct vl53l1x_data *data = iio_priv(indio_dev); 588 588 + 589 589 + if (iio_buffer_enabled(indio_dev)) 590 590 + iio_trigger_poll(indio_dev->trig); 591 591 + else 592 592 + complete(&data->completion); 593 593 + 594 594 + return IRQ_HANDLED; 595 595 + } 596 596 + 597 597 + static const struct iio_trigger_ops vl53l1x_trigger_ops = { 598 598 + .validate_device = iio_trigger_validate_own_device, 599 599 + }; 600 600 + 601 601 + static void vl53l1x_stop_ranging_action(void *priv) 602 602 + { 603 603 + vl53l1x_stop_ranging(priv); 604 604 + } 605 605 + 606 606 + static int vl53l1x_configure_irq(struct device *dev, int irq, 607 607 + struct iio_dev *indio_dev) 608 608 + { 609 609 + struct vl53l1x_data *data = iio_priv(indio_dev); 610 610 + int ret; 611 611 + 612 612 + ret = devm_request_irq(dev, irq, vl53l1x_irq_handler, IRQF_NO_THREAD, 613 613 + indio_dev->name, indio_dev); 614 614 + if (ret) 615 615 + return ret; 616 616 + 617 617 + ret = regmap_write(data->regmap, VL53L1X_REG_SYSTEM__INTERRUPT_CONFIG_GPIO, 618 618 + VL53L1X_INT_NEW_SAMPLE_READY); 619 619 + if (ret) 620 620 + return dev_err_probe(dev, ret, "failed to configure IRQ\n"); 621 621 + 622 622 + return 0; 623 623 + } 624 624 + 625 625 + static int vl53l1x_probe(struct i2c_client *client) 626 626 + { 627 627 + struct device *dev = &client->dev; 628 628 + struct vl53l1x_data *data; 629 629 + struct iio_dev *indio_dev; 630 630 + int ret; 631 631 + 632 632 + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 633 633 + if (!indio_dev) 634 634 + return -ENOMEM; 635 635 + 636 636 + data = iio_priv(indio_dev); 637 637 + data->irq = client->irq; 638 638 + 639 639 + data->regmap = devm_regmap_init_i2c(client, &vl53l1x_regmap_config); 640 640 + if (IS_ERR(data->regmap)) 641 641 + return dev_err_probe(dev, PTR_ERR(data->regmap), 642 642 + "regmap initialization failed\n"); 643 643 + 644 644 + ret = devm_regulator_get_enable(dev, "vdd"); 645 645 + if (ret) 646 646 + return dev_err_probe(dev, ret, "Failed to enable VDD regulator\n"); 647 647 + 648 648 + /* 649 649 + * XSHUT held low puts the chip in hardware standby. All register 650 650 + * state is lost on de-assert so this is functionally a reset. 651 651 + */ 652 652 + data->xshut_reset = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); 653 653 + if (IS_ERR(data->xshut_reset)) 654 654 + return dev_err_probe(dev, PTR_ERR(data->xshut_reset), 655 655 + "Cannot get reset control\n"); 656 656 + 657 657 + /* 658 658 + * 1.2 ms max boot duration. 659 659 + * Datasheet Section 3.6 "Power up and boot sequence". 660 660 + */ 661 661 + fsleep(1200); 662 662 + 663 663 + ret = vl53l1x_chip_init(data); 664 664 + if (ret) 665 665 + return ret; 666 666 + 667 667 + ret = vl53l1x_set_distance_mode(data, VL53L1X_LONG); 668 668 + if (ret) 669 669 + return ret; 670 670 + 671 671 + /* 50 ms timing budget (per ST Ultra Lite Driver) */ 672 672 + ret = vl53l1x_set_timing_budget(data, 50); 673 673 + if (ret) 674 674 + return ret; 675 675 + 676 676 + /* 50 ms inter-measurement period (per ST Ultra Lite Driver) */ 677 677 + ret = vl53l1x_set_inter_measurement_ms(data, 50); 678 678 + if (ret) 679 679 + return ret; 680 680 + 681 681 + /* 682 682 + * The hardware only supports "autonomous" continuous ranging mode. 683 683 + * Start ranging here and leave it running for the lifetime of 684 684 + * the device. Both direct reads and the buffer path rely on this. 685 685 + */ 686 686 + ret = vl53l1x_start_ranging(data); 687 687 + if (ret) 688 688 + return ret; 689 689 + 690 690 + ret = devm_add_action_or_reset(dev, vl53l1x_stop_ranging_action, data); 691 691 + if (ret) 692 692 + return ret; 693 693 + 694 694 + indio_dev->name = "vl53l1x"; 695 695 + indio_dev->info = &vl53l1x_info; 696 696 + indio_dev->channels = vl53l1x_channels; 697 697 + indio_dev->num_channels = ARRAY_SIZE(vl53l1x_channels); 698 698 + indio_dev->modes = INDIO_DIRECT_MODE; 699 699 + 700 700 + if (client->irq) { 701 701 + struct iio_trigger *trig; 702 702 + 703 703 + init_completion(&data->completion); 704 704 + 705 705 + trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, 706 706 + iio_device_id(indio_dev)); 707 707 + if (!trig) 708 708 + return -ENOMEM; 709 709 + 710 710 + trig->ops = &vl53l1x_trigger_ops; 711 711 + iio_trigger_set_drvdata(trig, indio_dev); 712 712 + ret = devm_iio_trigger_register(dev, trig); 713 713 + if (ret) 714 714 + return ret; 715 715 + 716 716 + indio_dev->trig = iio_trigger_get(trig); 717 717 + 718 718 + ret = vl53l1x_configure_irq(dev, client->irq, indio_dev); 719 719 + if (ret) 720 720 + return ret; 721 721 + 722 722 + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 723 723 + &vl53l1x_trigger_handler, 724 724 + NULL); 725 725 + if (ret) 726 726 + return ret; 727 727 + } 728 728 + 729 729 + return devm_iio_device_register(dev, indio_dev); 730 730 + } 731 731 + 732 732 + static const struct i2c_device_id vl53l1x_id[] = { 733 733 + { "vl53l1x" }, 734 734 + { } 735 735 + }; 736 736 + MODULE_DEVICE_TABLE(i2c, vl53l1x_id); 737 737 + 738 738 + static const struct of_device_id st_vl53l1x_dt_match[] = { 739 739 + { .compatible = "st,vl53l1x" }, 740 740 + { } 741 741 + }; 742 742 + MODULE_DEVICE_TABLE(of, st_vl53l1x_dt_match); 743 743 + 744 744 + static struct i2c_driver vl53l1x_driver = { 745 745 + .driver = { 746 746 + .name = "vl53l1x-i2c", 747 747 + .of_match_table = st_vl53l1x_dt_match, 748 748 + }, 749 749 + .probe = vl53l1x_probe, 750 750 + .id_table = vl53l1x_id, 751 751 + }; 752 752 + module_i2c_driver(vl53l1x_driver); 753 753 + 754 754 + MODULE_AUTHOR("Siratul Islam <email@sirat.me>"); 755 755 + MODULE_DESCRIPTION("ST VL53L1X ToF ranging sensor driver"); 756 756 + MODULE_LICENSE("Dual BSD/GPL");

+3 -3

drivers/iio/resolver/ad2s1210.c

reviewed

··· 896 896 .mask_separate = BIT(IIO_EV_INFO_VALUE), 897 897 }, 898 898 { 899 899 - /* Sine/cosine DOS overrange fault.*/ 899 899 + /* Sine/cosine DOS overrange fault. */ 900 900 .type = IIO_EV_TYPE_THRESH, 901 901 .dir = IIO_EV_DIR_RISING, 902 902 - /* Degredation of signal overrange threshold. */ 902 902 + /* Degradation of signal overrange threshold. */ 903 903 .mask_separate = BIT(IIO_EV_INFO_VALUE), 904 904 }, 905 905 { 906 906 - /* Sine/cosine DOS mismatch fault.*/ 906 906 + /* Sine/cosine DOS mismatch fault. */ 907 907 .type = IIO_EV_TYPE_MAG, 908 908 .dir = IIO_EV_DIR_RISING, 909 909 .mask_separate = BIT(IIO_EV_INFO_VALUE),

+2 -2

drivers/iio/temperature/ltc2983.c

reviewed

··· 709 709 ret = fwnode_property_read_u32(ref, "reg", &thermo->cold_junction_chan); 710 710 if (ret) 711 711 /* 712 712 - * This would be catched later but we can just return 712 712 + * This would be caught later but we can just return 713 713 * the error right away. 714 714 */ 715 715 return dev_err_ptr_probe(&st->spi->dev, ret, ··· 798 798 * For 4wire RTD with rotation, the channel selection cannot be 799 799 * >=19 since the chann + 1 is used in this configuration. 800 800 * For 4wire RTDs with kelvin rsense, the rsense channel cannot be 801 801 - * <=1 since chanel - 1 and channel - 2 are used. 801 801 + * <=1 since channel - 1 and channel - 2 are used. 802 802 */ 803 803 if (rtd->sensor_config & LTC2983_RTD_4_WIRE_MASK) { 804 804 /* 4-wire */

+1 -1

drivers/iio/test/iio-test-gts.c

reviewed

··· 20 20 * 21 21 * If yes, then adding a test is probably a good idea but please stop for a 22 22 * moment and consider the effort of changing all the tests when code gets 23 23 - * refactored. Eventually it neeeds to be. 23 23 + * refactored. Eventually it needs to be. 24 24 */ 25 25 26 26 #define TEST_TSEL_50 1

+8 -8

drivers/staging/iio/adc/ad7816.c

reviewed

··· 124 124 struct ad7816_chip_info *chip = iio_priv(indio_dev); 125 125 126 126 if (chip->mode) 127 127 - return sprintf(buf, "power-save\n"); 128 128 - return sprintf(buf, "full\n"); 127 127 + return sysfs_emit(buf, "power-save\n"); 128 128 + return sysfs_emit(buf, "full\n"); 129 129 } 130 130 131 131 static ssize_t ad7816_store_mode(struct device *dev, ··· 156 156 struct device_attribute *attr, 157 157 char *buf) 158 158 { 159 159 - return sprintf(buf, "full\npower-save\n"); 159 159 + return sysfs_emit(buf, "full\npower-save\n"); 160 160 } 161 161 162 162 static IIO_DEVICE_ATTR(available_modes, 0444, ad7816_show_available_modes, ··· 169 169 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 170 170 struct ad7816_chip_info *chip = iio_priv(indio_dev); 171 171 172 172 - return sprintf(buf, "%d\n", chip->channel_id); 172 172 + return sysfs_emit(buf, "%d\n", chip->channel_id); 173 173 } 174 174 175 175 static ssize_t ad7816_store_channel(struct device *dev, ··· 231 231 data &= AD7816_TEMP_FLOAT_MASK; 232 232 if (value < 0) 233 233 data = BIT(AD7816_TEMP_FLOAT_OFFSET) - data; 234 234 - return sprintf(buf, "%d.%.2d\n", value, data * 25); 234 234 + return sysfs_emit(buf, "%d.%.2d\n", value, data * 25); 235 235 } 236 236 - return sprintf(buf, "%u\n", data); 236 236 + return sysfs_emit(buf, "%u\n", data); 237 237 } 238 238 239 239 static IIO_DEVICE_ATTR(value, 0444, ad7816_show_value, NULL, 0); ··· 281 281 value = AD7816_BOUND_VALUE_MIN + 282 282 (chip->oti_data[chip->channel_id] - 283 283 AD7816_BOUND_VALUE_BASE); 284 284 - return sprintf(buf, "%d\n", value); 284 284 + return sysfs_emit(buf, "%d\n", value); 285 285 } 286 286 - return sprintf(buf, "%u\n", chip->oti_data[chip->channel_id]); 286 286 + return sysfs_emit(buf, "%u\n", chip->oti_data[chip->channel_id]); 287 287 } 288 288 289 289 static inline ssize_t ad7816_set_oti(struct device *dev,

+6 -14

drivers/staging/iio/frequency/ad9834.c

reviewed

··· 281 281 { 282 282 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 283 283 struct ad9834_state *st = iio_priv(indio_dev); 284 284 - char *str; 285 284 286 285 if (st->devid == ID_AD9833 || st->devid == ID_AD9837) 287 287 - str = "sine triangle square"; 288 288 - else if (st->control & AD9834_OPBITEN) 289 289 - str = "sine"; 290 290 - else 291 291 - str = "sine triangle"; 292 292 - 293 293 - return sprintf(buf, "%s\n", str); 286 286 + return sysfs_emit(buf, "sine triangle square\n"); 287 287 + if (st->control & AD9834_OPBITEN) 288 288 + return sysfs_emit(buf, "sine\n"); 289 289 + return sysfs_emit(buf, "sine triangle\n"); 294 290 } 295 291 296 292 static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444, ··· 299 303 { 300 304 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 301 305 struct ad9834_state *st = iio_priv(indio_dev); 302 302 - char *str; 303 306 304 307 if (st->control & AD9834_MODE) 305 305 - str = ""; 306 306 - else 307 307 - str = "square"; 308 308 - 309 309 - return sprintf(buf, "%s\n", str); 308 308 + return sysfs_emit(buf, "\n"); 309 309 + return sysfs_emit(buf, "square\n"); 310 310 } 311 311 312 312 static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444,

+14 -14

drivers/staging/iio/impedance-analyzer/ad5933.c

reviewed

··· 5 5 * Copyright 2011 Analog Devices Inc. 6 6 */ 7 7 8 8 + #include <linux/bits.h> 8 9 #include <linux/clk.h> 9 10 #include <linux/delay.h> 10 11 #include <linux/device.h> ··· 195 194 u8 d8[4]; 196 195 } dat; 197 196 198 198 - freqreg = (u64)freq * (u64)(1 << 27); 199 199 - do_div(freqreg, st->mclk_hz / 4); 197 197 + freqreg = div64_ul(BIT_ULL(27) * freq, st->mclk_hz / 4); 200 198 201 199 switch (reg) { 202 200 case AD5933_REG_FREQ_START: ··· 285 285 freqreg = (u64)freqreg * (u64)(st->mclk_hz / 4); 286 286 do_div(freqreg, BIT(27)); 287 287 288 288 - return sprintf(buf, "%d\n", (int)freqreg); 288 288 + return sysfs_emit(buf, "%llu\n", freqreg); 289 289 } 290 290 291 291 static ssize_t ad5933_store_frequency(struct device *dev, ··· 338 338 mutex_lock(&st->lock); 339 339 switch ((u32)this_attr->address) { 340 340 case AD5933_OUT_RANGE: 341 341 - len = sprintf(buf, "%u\n", 342 342 - st->range_avail[(st->ctrl_hb >> 1) & 0x3]); 341 341 + len = sysfs_emit(buf, "%u\n", 342 342 + st->range_avail[(st->ctrl_hb >> 1) & 0x3]); 343 343 break; 344 344 case AD5933_OUT_RANGE_AVAIL: 345 345 - len = sprintf(buf, "%u %u %u %u\n", st->range_avail[0], 346 346 - st->range_avail[3], st->range_avail[2], 347 347 - st->range_avail[1]); 345 345 + len = sysfs_emit(buf, "%u %u %u %u\n", st->range_avail[0], 346 346 + st->range_avail[3], st->range_avail[2], 347 347 + st->range_avail[1]); 348 348 break; 349 349 case AD5933_OUT_SETTLING_CYCLES: 350 350 - len = sprintf(buf, "%d\n", st->settling_cycles); 350 350 + len = sysfs_emit(buf, "%d\n", st->settling_cycles); 351 351 break; 352 352 case AD5933_IN_PGA_GAIN: 353 353 - len = sprintf(buf, "%s\n", 354 354 - (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ? 355 355 - "1" : "0.2"); 353 353 + len = sysfs_emit(buf, "%s\n", 354 354 + (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ? 355 355 + "1" : "0.2"); 356 356 break; 357 357 case AD5933_IN_PGA_GAIN_AVAIL: 358 358 - len = sprintf(buf, "1 0.2\n"); 358 358 + len = sysfs_emit(buf, "1 0.2\n"); 359 359 break; 360 360 case AD5933_FREQ_POINTS: 361 361 - len = sprintf(buf, "%d\n", st->freq_points); 361 361 + len = sysfs_emit(buf, "%d\n", st->freq_points); 362 362 break; 363 363 default: 364 364 ret = -EINVAL;

+211

include/linux/iio/adc/qcom-adc5-gen3-common.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 4 + * 5 5 + * Code used in the main and auxiliary Qualcomm PMIC voltage ADCs 6 6 + * of type ADC5 Gen3. 7 7 + */ 8 8 + 9 9 + #ifndef QCOM_ADC5_GEN3_COMMON_H 10 10 + #define QCOM_ADC5_GEN3_COMMON_H 11 11 + 12 12 + #include <linux/auxiliary_bus.h> 13 13 + #include <linux/bitfield.h> 14 14 + #include <linux/bits.h> 15 15 + #include <linux/device.h> 16 16 + #include <linux/iio/adc/qcom-vadc-common.h> 17 17 + #include <linux/regmap.h> 18 18 + #include <linux/types.h> 19 19 + 20 20 + #define ADC5_GEN3_HS 0x45 21 21 + #define ADC5_GEN3_HS_BUSY BIT(7) 22 22 + #define ADC5_GEN3_HS_READY BIT(0) 23 23 + 24 24 + #define ADC5_GEN3_STATUS1 0x46 25 25 + #define ADC5_GEN3_STATUS1_CONV_FAULT BIT(7) 26 26 + #define ADC5_GEN3_STATUS1_THR_CROSS BIT(6) 27 27 + #define ADC5_GEN3_STATUS1_EOC BIT(0) 28 28 + 29 29 + #define ADC5_GEN3_TM_EN_STS 0x47 30 30 + #define ADC5_GEN3_TM_HIGH_STS 0x48 31 31 + #define ADC5_GEN3_TM_LOW_STS 0x49 32 32 + 33 33 + #define ADC5_GEN3_EOC_STS 0x4a 34 34 + #define ADC5_GEN3_EOC_CHAN_0 BIT(0) 35 35 + 36 36 + #define ADC5_GEN3_EOC_CLR 0x4b 37 37 + #define ADC5_GEN3_TM_HIGH_STS_CLR 0x4c 38 38 + #define ADC5_GEN3_TM_LOW_STS_CLR 0x4d 39 39 + #define ADC5_GEN3_CONV_ERR_CLR 0x4e 40 40 + #define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0) 41 41 + 42 42 + #define ADC5_GEN3_SID 0x4f 43 43 + #define ADC5_GEN3_SID_MASK GENMASK(3, 0) 44 44 + 45 45 + #define ADC5_GEN3_PERPH_CH 0x50 46 46 + #define ADC5_GEN3_CHAN_CONV_REQ BIT(7) 47 47 + 48 48 + #define ADC5_GEN3_TIMER_SEL 0x51 49 49 + #define ADC5_GEN3_TIME_IMMEDIATE 0x1 50 50 + 51 51 + #define ADC5_GEN3_DIG_PARAM 0x52 52 52 + #define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4) 53 53 + #define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2) 54 54 + 55 55 + #define ADC5_GEN3_FAST_AVG 0x53 56 56 + #define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7) 57 57 + #define ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK GENMASK(2, 0) 58 58 + 59 59 + #define ADC5_GEN3_ADC_CH_SEL_CTL 0x54 60 60 + #define ADC5_GEN3_DELAY_CTL 0x55 61 61 + #define ADC5_GEN3_HW_SETTLE_DELAY_MASK GENMASK(3, 0) 62 62 + 63 63 + #define ADC5_GEN3_CH_EN 0x56 64 64 + #define ADC5_GEN3_HIGH_THR_INT_EN BIT(1) 65 65 + #define ADC5_GEN3_LOW_THR_INT_EN BIT(0) 66 66 + 67 67 + #define ADC5_GEN3_LOW_THR0 0x57 68 68 + #define ADC5_GEN3_LOW_THR1 0x58 69 69 + #define ADC5_GEN3_HIGH_THR0 0x59 70 70 + #define ADC5_GEN3_HIGH_THR1 0x5a 71 71 + 72 72 + #define ADC5_GEN3_CH_DATA0(channel) (0x5c + (channel) * 2) 73 73 + #define ADC5_GEN3_CH_DATA1(channel) (0x5d + (channel) * 2) 74 74 + 75 75 + #define ADC5_GEN3_CONV_REQ 0xe5 76 76 + #define ADC5_GEN3_CONV_REQ_REQ BIT(0) 77 77 + 78 78 + #define ADC5_GEN3_VIRTUAL_SID_MASK GENMASK(15, 8) 79 79 + #define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0) 80 80 + #define ADC5_GEN3_V_CHAN(x) \ 81 81 + (FIELD_PREP(ADC5_GEN3_VIRTUAL_SID_MASK, (x).sid) | (x).channel) 82 82 + 83 83 + /* ADC channels for PMIC5 Gen3 */ 84 84 + #define ADC5_GEN3_REF_GND 0x00 85 85 + #define ADC5_GEN3_1P25VREF 0x01 86 86 + #define ADC5_GEN3_DIE_TEMP 0x03 87 87 + #define ADC5_GEN3_USB_SNS_V_16 0x11 88 88 + #define ADC5_GEN3_VIN_DIV16_MUX 0x12 89 89 + #define ADC5_GEN3_VPH_PWR 0x8e 90 90 + #define ADC5_GEN3_VBAT_SNS_QBG 0x8f 91 91 + /* 100k pull-up channels */ 92 92 + #define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 93 93 + #define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 94 94 + #define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 95 95 + #define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 96 96 + #define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 97 97 + #define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 98 98 + #define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a 99 99 + #define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b 100 100 + #define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c 101 101 + #define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d 102 102 + 103 103 + #define ADC5_MAX_CHANNEL 0xc0 104 104 + 105 105 + enum adc5_cal_method { 106 106 + ADC5_NO_CAL = 0, 107 107 + ADC5_RATIOMETRIC_CAL, 108 108 + ADC5_ABSOLUTE_CAL, 109 109 + }; 110 110 + 111 111 + enum adc5_time_select { 112 112 + MEAS_INT_DISABLE = 0, 113 113 + MEAS_INT_IMMEDIATE, 114 114 + MEAS_INT_50MS, 115 115 + MEAS_INT_100MS, 116 116 + MEAS_INT_1S, 117 117 + MEAS_INT_NONE, 118 118 + }; 119 119 + 120 120 + /** 121 121 + * struct adc5_sdam_data - data per SDAM allocated for adc usage 122 122 + * @base_addr: base address for the ADC SDAM peripheral. 123 123 + * @irq_name: ADC IRQ name. 124 124 + * @irq: ADC IRQ number. 125 125 + */ 126 126 + struct adc5_sdam_data { 127 127 + u16 base_addr; 128 128 + const char *irq_name; 129 129 + int irq; 130 130 + }; 131 131 + 132 132 + /** 133 133 + * struct adc5_device_data - Top-level ADC device data 134 134 + * @regmap: ADC peripheral register map field. 135 135 + * @base: array of SDAM data. 136 136 + * @num_sdams: number of ADC SDAM peripherals. 137 137 + */ 138 138 + struct adc5_device_data { 139 139 + struct regmap *regmap; 140 140 + struct adc5_sdam_data *base; 141 141 + int num_sdams; 142 142 + }; 143 143 + 144 144 + /** 145 145 + * struct adc5_channel_common_prop - ADC channel properties (common to ADC and TM). 146 146 + * @channel: channel number, refer to the channel list. 147 147 + * @cal_method: calibration method. 148 148 + * @decimation: sampling rate supported for the channel. 149 149 + * @sid: ID of PMIC owning the channel. 150 150 + * @label: Channel name used in device tree. 151 151 + * @prescale: channel scaling performed on the input signal. 152 152 + * @hw_settle_time_us: the time between AMUX being configured and the 153 153 + * start of conversion in uS. 154 154 + * @avg_samples: ability to provide single result from the ADC 155 155 + * that is an average of multiple measurements. 156 156 + * @scale_fn_type: Represents the scaling function to convert voltage 157 157 + * physical units desired by the client for the channel. 158 158 + */ 159 159 + struct adc5_channel_common_prop { 160 160 + unsigned int channel; 161 161 + enum adc5_cal_method cal_method; 162 162 + unsigned int decimation; 163 163 + unsigned int sid; 164 164 + const char *label; 165 165 + unsigned int prescale; 166 166 + unsigned int hw_settle_time_us; 167 167 + unsigned int avg_samples; 168 168 + enum vadc_scale_fn_type scale_fn_type; 169 169 + }; 170 170 + 171 171 + /** 172 172 + * struct tm5_aux_dev_wrapper - wrapper structure around TM auxiliary device 173 173 + * @aux_dev: TM auxiliary device structure. 174 174 + * @dev_data: Top-level ADC device data. 175 175 + * @tm_props: Array of common ADC channel properties for TM channels. 176 176 + * @n_tm_channels: number of TM channels. 177 177 + */ 178 178 + struct tm5_aux_dev_wrapper { 179 179 + struct auxiliary_device aux_dev; 180 180 + struct adc5_device_data *dev_data; 181 181 + struct adc5_channel_common_prop *tm_props; 182 182 + unsigned int n_tm_channels; 183 183 + }; 184 184 + 185 185 + int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index, 186 186 + u16 offset, u8 *data, int len); 187 187 + 188 188 + int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index, 189 189 + u16 offset, u8 *data, int len); 190 190 + 191 191 + int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc, 192 192 + unsigned int sdam_index); 193 193 + 194 194 + void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, 195 195 + u8 *data); 196 196 + 197 197 + int adc5_gen3_status_clear(struct adc5_device_data *adc, 198 198 + int sdam_index, u16 offset, u8 *val, int len); 199 199 + 200 200 + void adc5_gen3_mutex_lock(struct device *dev); 201 201 + void adc5_gen3_mutex_unlock(struct device *dev); 202 202 + int adc5_gen3_get_scaled_reading(struct device *dev, 203 203 + struct adc5_channel_common_prop *common_props, 204 204 + int *val); 205 205 + int adc5_gen3_therm_code_to_temp(struct device *dev, 206 206 + struct adc5_channel_common_prop *common_props, 207 207 + u16 code, int *val); 208 208 + void adc5_gen3_register_tm_event_notifier(struct device *dev, 209 209 + void (*handler)(struct auxiliary_device *)); 210 210 + 211 211 + #endif /* QCOM_ADC5_GEN3_COMMON_H */

+24

include/linux/iio/backend.h

reviewed

··· 85 85 }; 86 86 87 87 /** 88 88 + * enum iio_backend_capabilities - Backend capabilities 89 89 + * Backend capabilities can be used by frontends to check if a given 90 90 + * functionality is supported by the backend. This is useful for frontend 91 91 + * devices which are expected to work with alternative backend 92 92 + * implementations. Capabilities are loosely coupled with operations, 93 93 + * meaning that a capability requires certain operations to be implemented 94 94 + * by the backend. A capability might be mapped to a single operation or 95 95 + * multiple operations. 96 96 + * 97 97 + * @IIO_BACKEND_CAP_CALIBRATION: Backend supports digital interface 98 98 + * calibration. Calibration procedure is device specific. 99 99 + * @IIO_BACKEND_CAP_BUFFER: Support for IIO buffer interface. 100 100 + * @IIO_BACKEND_CAP_ENABLE: Backend can be explicitly enabled/disabled. 101 101 + */ 102 102 + enum iio_backend_capabilities { 103 103 + IIO_BACKEND_CAP_CALIBRATION = BIT(0), 104 104 + IIO_BACKEND_CAP_BUFFER = BIT(1), 105 105 + IIO_BACKEND_CAP_ENABLE = BIT(2), 106 106 + }; 107 107 + 108 108 + /** 88 109 * struct iio_backend_ops - operations structure for an iio_backend 89 110 * @enable: Enable backend. 90 111 * @disable: Disable backend. ··· 200 179 * struct iio_backend_info - info structure for an iio_backend 201 180 * @name: Backend name. 202 181 * @ops: Backend operations. 182 182 + * @caps: Backend capabilities. (bitmask of enum iio_backend_capabilities). 203 183 */ 204 184 struct iio_backend_info { 205 185 const char *name; 206 186 const struct iio_backend_ops *ops; 187 187 + u32 caps; 207 188 }; 208 189 209 190 int iio_backend_chan_enable(struct iio_backend *back, unsigned int chan); ··· 258 235 long mask); 259 236 int iio_backend_extend_chan_spec(struct iio_backend *back, 260 237 struct iio_chan_spec *chan); 238 238 + bool iio_backend_has_caps(struct iio_backend *back, u32 caps); 261 239 void *iio_backend_get_priv(const struct iio_backend *conv); 262 240 struct iio_backend *devm_iio_backend_get(struct device *dev, const char *name); 263 241 struct iio_backend *devm_iio_backend_fwnode_get(struct device *dev,

+6 -5

include/linux/iio/common/st_sensors.h

reviewed

··· 160 160 161 161 /** 162 162 * struct st_sensor_data_ready_irq - ST sensor device data-ready interrupt 163 163 - * struct int1 - data-ready configuration register for INT1 pin. 164 164 - * struct int2 - data-ready configuration register for INT2 pin. 163 163 + * @int1: data-ready configuration register for INT1 pin. 164 164 + * @int2: data-ready configuration register for INT2 pin. 165 165 * @addr_ihl: address to enable/disable active low on the INT lines. 166 166 * @mask_ihl: mask to enable/disable active low on the INT lines. 167 167 - * struct stat_drdy - status register of DRDY (data ready) interrupt. 168 168 - * struct ig1 - represents the Interrupt Generator 1 of sensors. 167 167 + * @stat_drdy: status register of DRDY (data ready) interrupt. 168 168 + * @ig1: represents the Interrupt Generator 1 of sensors. 169 169 * @en_addr: address of the enable ig1 register. 170 170 * @en_mask: mask to write the on/off value for enable. 171 171 */ ··· 190 190 * @wai_addr: The address of WhoAmI register. 191 191 * @sensors_supported: List of supported sensors by struct itself. 192 192 * @ch: IIO channels for the sensor. 193 193 + * @num_ch: Number of IIO channels in @ch 193 194 * @odr: Output data rate register and ODR list available. 194 195 * @pw: Power register of the sensor. 195 196 * @enable_axis: Enable one or more axis of the sensor. ··· 229 228 * @regmap: Pointer to specific sensor regmap configuration. 230 229 * @enabled: Status of the sensor (false->off, true->on). 231 230 * @odr: Output data rate of the sensor [Hz]. 232 232 - * num_data_channels: Number of data channels used in buffer. 231 231 + * @num_data_channels: Number of data channels used in buffer. 233 232 * @drdy_int_pin: Redirect DRDY on pin 1 (1) or pin 2 (2). 234 233 * @int_pin_open_drain: Set the interrupt/DRDY to open drain. 235 234 * @irq: the IRQ number.

+1

include/linux/iio/types.h

reviewed

··· 21 21 IIO_EV_INFO_TAP2_MIN_DELAY, 22 22 IIO_EV_INFO_RUNNING_PERIOD, 23 23 IIO_EV_INFO_RUNNING_COUNT, 24 24 + IIO_EV_INFO_SCALE, 24 25 }; 25 26 26 27 #define IIO_VAL_INT 1

+2 -2

include/linux/platform_data/tsl2772.h

reviewed

··· 61 61 * @prox_pulse_count: Number if proximity emitter pulses. 62 62 * @prox_max_samples_cal: The number of samples that are taken when performing 63 63 * a proximity calibration. 64 64 - * @prox_diode Which diode(s) to use for driving the external 64 64 + * @prox_diode: Which diode(s) to use for driving the external 65 65 * LED(s) for proximity sensing. 66 66 - * @prox_power The amount of power to use for the external LED(s). 66 66 + * @prox_power: The amount of power to use for the external LED(s). 67 67 */ 68 68 struct tsl2772_settings { 69 69 int als_time;