Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
locking: Copy out qspinlock.c to kernel/bpf/rqspinlock.c
In preparation for introducing a new lock implementation, Resilient
Queued Spin Lock, or rqspinlock, we first begin our modifications by
using the existing qspinlock.c code as the base. Simply copy the code to
a new file and rename functions and variables from 'queued' to
'resilient_queued'.
Since we place the file in kernel/bpf, include needs to be relative.
This helps each subsequent commit in clearly showing how and where the
code is being changed. The only change after a literal copy in this
commit is renaming the functions where necessary, and rename qnodes to
rqnodes. Let's also use EXPORT_SYMBOL_GPL for rqspinlock slowpath.
Reviewed-by: Barret Rhoden <brho@google.com>
Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
Link: https://lore.kernel.org/r/20250316040541.108729-5-memxor@gmail.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
authored by
Kumar Kartikeya Dwivedi
and committed by
Alexei Starovoitov
a8fcf2a3
c0149a03
+410
+410
kernel/bpf/rqspinlock.c
+410
kernel/bpf/rqspinlock.c
···
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Resilient Queued Spin Lock
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*
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* (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
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* (C) Copyright 2013-2014,2018 Red Hat, Inc.
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* (C) Copyright 2015 Intel Corp.
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* (C) Copyright 2015 Hewlett-Packard Enterprise Development LP
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*
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* Authors: Waiman Long <longman@redhat.com>
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* Peter Zijlstra <peterz@infradead.org>
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*/
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#ifndef _GEN_PV_LOCK_SLOWPATH
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#include <linux/smp.h>
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#include <linux/bug.h>
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#include <linux/cpumask.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <linux/mutex.h>
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#include <linux/prefetch.h>
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#include <asm/byteorder.h>
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#include <asm/qspinlock.h>
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#include <trace/events/lock.h>
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/*
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* Include queued spinlock definitions and statistics code
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*/
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#include "../locking/qspinlock.h"
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#include "../locking/qspinlock_stat.h"
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/*
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* The basic principle of a queue-based spinlock can best be understood
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* by studying a classic queue-based spinlock implementation called the
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* MCS lock. A copy of the original MCS lock paper ("Algorithms for Scalable
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* Synchronization on Shared-Memory Multiprocessors by Mellor-Crummey and
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* Scott") is available at
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*
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* https://bugzilla.kernel.org/show_bug.cgi?id=206115
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*
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* This queued spinlock implementation is based on the MCS lock, however to
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* make it fit the 4 bytes we assume spinlock_t to be, and preserve its
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* existing API, we must modify it somehow.
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*
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* In particular; where the traditional MCS lock consists of a tail pointer
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* (8 bytes) and needs the next pointer (another 8 bytes) of its own node to
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* unlock the next pending (next->locked), we compress both these: {tail,
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* next->locked} into a single u32 value.
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*
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* Since a spinlock disables recursion of its own context and there is a limit
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* to the contexts that can nest; namely: task, softirq, hardirq, nmi. As there
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* are at most 4 nesting levels, it can be encoded by a 2-bit number. Now
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* we can encode the tail by combining the 2-bit nesting level with the cpu
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* number. With one byte for the lock value and 3 bytes for the tail, only a
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* 32-bit word is now needed. Even though we only need 1 bit for the lock,
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* we extend it to a full byte to achieve better performance for architectures
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* that support atomic byte write.
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*
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* We also change the first spinner to spin on the lock bit instead of its
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* node; whereby avoiding the need to carry a node from lock to unlock, and
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* preserving existing lock API. This also makes the unlock code simpler and
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* faster.
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*
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* N.B. The current implementation only supports architectures that allow
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* atomic operations on smaller 8-bit and 16-bit data types.
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*
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*/
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#include "../locking/mcs_spinlock.h"
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/*
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* Per-CPU queue node structures; we can never have more than 4 nested
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* contexts: task, softirq, hardirq, nmi.
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*
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* Exactly fits one 64-byte cacheline on a 64-bit architecture.
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*
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* PV doubles the storage and uses the second cacheline for PV state.
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*/
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static DEFINE_PER_CPU_ALIGNED(struct qnode, rqnodes[_Q_MAX_NODES]);
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/*
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* Generate the native code for resilient_queued_spin_unlock_slowpath(); provide NOPs
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* for all the PV callbacks.
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*/
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static __always_inline void __pv_init_node(struct mcs_spinlock *node) { }
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static __always_inline void __pv_wait_node(struct mcs_spinlock *node,
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struct mcs_spinlock *prev) { }
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static __always_inline void __pv_kick_node(struct qspinlock *lock,
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struct mcs_spinlock *node) { }
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static __always_inline u32 __pv_wait_head_or_lock(struct qspinlock *lock,
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struct mcs_spinlock *node)
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{ return 0; }
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#define pv_enabled() false
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#define pv_init_node __pv_init_node
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#define pv_wait_node __pv_wait_node
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#define pv_kick_node __pv_kick_node
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#define pv_wait_head_or_lock __pv_wait_head_or_lock
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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#define resilient_queued_spin_lock_slowpath native_resilient_queued_spin_lock_slowpath
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#endif
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#endif /* _GEN_PV_LOCK_SLOWPATH */
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/**
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* resilient_queued_spin_lock_slowpath - acquire the queued spinlock
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* @lock: Pointer to queued spinlock structure
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* @val: Current value of the queued spinlock 32-bit word
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*
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* (queue tail, pending bit, lock value)
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*
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* fast : slow : unlock
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* : :
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* uncontended (0,0,0) -:--> (0,0,1) ------------------------------:--> (*,*,0)
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* : | ^--------.------. / :
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* : v \ \ | :
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* pending : (0,1,1) +--> (0,1,0) \ | :
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* : | ^--' | | :
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* : v | | :
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* uncontended : (n,x,y) +--> (n,0,0) --' | :
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* queue : | ^--' | :
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* : v | :
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* contended : (*,x,y) +--> (*,0,0) ---> (*,0,1) -' :
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* queue : ^--' :
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*/
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void __lockfunc resilient_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
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{
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struct mcs_spinlock *prev, *next, *node;
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u32 old, tail;
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int idx;
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BUILD_BUG_ON(CONFIG_NR_CPUS >= (1U << _Q_TAIL_CPU_BITS));
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if (pv_enabled())
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goto pv_queue;
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+
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if (virt_spin_lock(lock))
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return;
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/*
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* Wait for in-progress pending->locked hand-overs with a bounded
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* number of spins so that we guarantee forward progress.
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*
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* 0,1,0 -> 0,0,1
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*/
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if (val == _Q_PENDING_VAL) {
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int cnt = _Q_PENDING_LOOPS;
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val = atomic_cond_read_relaxed(&lock->val,
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(VAL != _Q_PENDING_VAL) || !cnt--);
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}
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/*
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* If we observe any contention; queue.
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*/
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if (val & ~_Q_LOCKED_MASK)
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goto queue;
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/*
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* trylock || pending
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*
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* 0,0,* -> 0,1,* -> 0,0,1 pending, trylock
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*/
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val = queued_fetch_set_pending_acquire(lock);
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/*
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* If we observe contention, there is a concurrent locker.
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*
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* Undo and queue; our setting of PENDING might have made the
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* n,0,0 -> 0,0,0 transition fail and it will now be waiting
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* on @next to become !NULL.
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*/
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if (unlikely(val & ~_Q_LOCKED_MASK)) {
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/* Undo PENDING if we set it. */
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if (!(val & _Q_PENDING_MASK))
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clear_pending(lock);
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goto queue;
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}
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/*
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* We're pending, wait for the owner to go away.
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*
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* 0,1,1 -> *,1,0
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*
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* this wait loop must be a load-acquire such that we match the
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* store-release that clears the locked bit and create lock
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* sequentiality; this is because not all
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* clear_pending_set_locked() implementations imply full
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* barriers.
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*/
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if (val & _Q_LOCKED_MASK)
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smp_cond_load_acquire(&lock->locked, !VAL);
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/*
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* take ownership and clear the pending bit.
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*
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* 0,1,0 -> 0,0,1
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*/
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clear_pending_set_locked(lock);
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lockevent_inc(lock_pending);
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return;
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/*
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* End of pending bit optimistic spinning and beginning of MCS
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* queuing.
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*/
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queue:
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lockevent_inc(lock_slowpath);
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pv_queue:
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node = this_cpu_ptr(&rqnodes[0].mcs);
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idx = node->count++;
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tail = encode_tail(smp_processor_id(), idx);
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trace_contention_begin(lock, LCB_F_SPIN);
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/*
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* 4 nodes are allocated based on the assumption that there will
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* not be nested NMIs taking spinlocks. That may not be true in
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* some architectures even though the chance of needing more than
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* 4 nodes will still be extremely unlikely. When that happens,
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* we fall back to spinning on the lock directly without using
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* any MCS node. This is not the most elegant solution, but is
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* simple enough.
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*/
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if (unlikely(idx >= _Q_MAX_NODES)) {
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lockevent_inc(lock_no_node);
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while (!queued_spin_trylock(lock))
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cpu_relax();
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goto release;
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}
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+
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node = grab_mcs_node(node, idx);
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+
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/*
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* Keep counts of non-zero index values:
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*/
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lockevent_cond_inc(lock_use_node2 + idx - 1, idx);
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+
244
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/*
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* Ensure that we increment the head node->count before initialising
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* the actual node. If the compiler is kind enough to reorder these
247
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* stores, then an IRQ could overwrite our assignments.
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*/
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barrier();
250
+
251
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node->locked = 0;
252
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node->next = NULL;
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pv_init_node(node);
254
+
255
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/*
256
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* We touched a (possibly) cold cacheline in the per-cpu queue node;
257
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* attempt the trylock once more in the hope someone let go while we
258
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* weren't watching.
259
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*/
260
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if (queued_spin_trylock(lock))
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goto release;
262
+
263
+
/*
264
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* Ensure that the initialisation of @node is complete before we
265
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* publish the updated tail via xchg_tail() and potentially link
266
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* @node into the waitqueue via WRITE_ONCE(prev->next, node) below.
267
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*/
268
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smp_wmb();
269
+
270
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/*
271
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* Publish the updated tail.
272
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* We have already touched the queueing cacheline; don't bother with
273
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* pending stuff.
274
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*
275
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* p,*,* -> n,*,*
276
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*/
277
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old = xchg_tail(lock, tail);
278
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next = NULL;
279
+
280
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/*
281
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* if there was a previous node; link it and wait until reaching the
282
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* head of the waitqueue.
283
+
*/
284
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if (old & _Q_TAIL_MASK) {
285
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prev = decode_tail(old, rqnodes);
286
+
287
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/* Link @node into the waitqueue. */
288
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WRITE_ONCE(prev->next, node);
289
+
290
+
pv_wait_node(node, prev);
291
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arch_mcs_spin_lock_contended(&node->locked);
292
+
293
+
/*
294
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* While waiting for the MCS lock, the next pointer may have
295
+
* been set by another lock waiter. We optimistically load
296
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* the next pointer & prefetch the cacheline for writing
297
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* to reduce latency in the upcoming MCS unlock operation.
298
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*/
299
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next = READ_ONCE(node->next);
300
+
if (next)
301
+
prefetchw(next);
302
+
}
303
+
304
+
/*
305
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* we're at the head of the waitqueue, wait for the owner & pending to
306
+
* go away.
307
+
*
308
+
* *,x,y -> *,0,0
309
+
*
310
+
* this wait loop must use a load-acquire such that we match the
311
+
* store-release that clears the locked bit and create lock
312
+
* sequentiality; this is because the set_locked() function below
313
+
* does not imply a full barrier.
314
+
*
315
+
* The PV pv_wait_head_or_lock function, if active, will acquire
316
+
* the lock and return a non-zero value. So we have to skip the
317
+
* atomic_cond_read_acquire() call. As the next PV queue head hasn't
318
+
* been designated yet, there is no way for the locked value to become
319
+
* _Q_SLOW_VAL. So both the set_locked() and the
320
+
* atomic_cmpxchg_relaxed() calls will be safe.
321
+
*
322
+
* If PV isn't active, 0 will be returned instead.
323
+
*
324
+
*/
325
+
if ((val = pv_wait_head_or_lock(lock, node)))
326
+
goto locked;
327
+
328
+
val = atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK));
329
+
330
+
locked:
331
+
/*
332
+
* claim the lock:
333
+
*
334
+
* n,0,0 -> 0,0,1 : lock, uncontended
335
+
* *,*,0 -> *,*,1 : lock, contended
336
+
*
337
+
* If the queue head is the only one in the queue (lock value == tail)
338
+
* and nobody is pending, clear the tail code and grab the lock.
339
+
* Otherwise, we only need to grab the lock.
340
+
*/
341
+
342
+
/*
343
+
* In the PV case we might already have _Q_LOCKED_VAL set, because
344
+
* of lock stealing; therefore we must also allow:
345
+
*
346
+
* n,0,1 -> 0,0,1
347
+
*
348
+
* Note: at this point: (val & _Q_PENDING_MASK) == 0, because of the
349
+
* above wait condition, therefore any concurrent setting of
350
+
* PENDING will make the uncontended transition fail.
351
+
*/
352
+
if ((val & _Q_TAIL_MASK) == tail) {
353
+
if (atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL))
354
+
goto release; /* No contention */
355
+
}
356
+
357
+
/*
358
+
* Either somebody is queued behind us or _Q_PENDING_VAL got set
359
+
* which will then detect the remaining tail and queue behind us
360
+
* ensuring we'll see a @next.
361
+
*/
362
+
set_locked(lock);
363
+
364
+
/*
365
+
* contended path; wait for next if not observed yet, release.
366
+
*/
367
+
if (!next)
368
+
next = smp_cond_load_relaxed(&node->next, (VAL));
369
+
370
+
arch_mcs_spin_unlock_contended(&next->locked);
371
+
pv_kick_node(lock, next);
372
+
373
+
release:
374
+
trace_contention_end(lock, 0);
375
+
376
+
/*
377
+
* release the node
378
+
*/
379
+
__this_cpu_dec(rqnodes[0].mcs.count);
380
+
}
381
+
EXPORT_SYMBOL_GPL(resilient_queued_spin_lock_slowpath);
382
+
383
+
/*
384
+
* Generate the paravirt code for resilient_queued_spin_unlock_slowpath().
385
+
*/
386
+
#if !defined(_GEN_PV_LOCK_SLOWPATH) && defined(CONFIG_PARAVIRT_SPINLOCKS)
387
+
#define _GEN_PV_LOCK_SLOWPATH
388
+
389
+
#undef pv_enabled
390
+
#define pv_enabled() true
391
+
392
+
#undef pv_init_node
393
+
#undef pv_wait_node
394
+
#undef pv_kick_node
395
+
#undef pv_wait_head_or_lock
396
+
397
+
#undef resilient_queued_spin_lock_slowpath
398
+
#define resilient_queued_spin_lock_slowpath __pv_resilient_queued_spin_lock_slowpath
399
+
400
+
#include "../locking/qspinlock_paravirt.h"
401
+
#include "rqspinlock.c"
402
+
403
+
bool nopvspin;
404
+
static __init int parse_nopvspin(char *arg)
405
+
{
406
+
nopvspin = true;
407
+
return 0;
408
+
}
409
+
early_param("nopvspin", parse_nopvspin);
410
+
#endif