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ARM: dts: oxnas: remove obsolete device tree files

Due to lack of maintainance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support
for OX810 and OX820 devices.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

authored by

Neil Armstrong and committed by
Arnd Bergmann a9414bef 63d2b927

-867
-3
arch/arm/boot/dts/Makefile
··· 1041 1041 pxa300-raumfeld-speaker-m.dtb \ 1042 1042 pxa300-raumfeld-speaker-one.dtb \ 1043 1043 pxa300-raumfeld-speaker-s.dtb 1044 - dtb-$(CONFIG_ARCH_OXNAS) += \ 1045 - ox810se-wd-mbwe.dtb \ 1046 - ox820-cloudengines-pogoplug-series-3.dtb 1047 1044 dtb-$(CONFIG_ARCH_QCOM) += \ 1048 1045 qcom-apq8016-sbc.dtb \ 1049 1046 qcom-apq8026-asus-sparrow.dtb \
-115
arch/arm/boot/dts/ox810se-wd-mbwe.dts
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition 4 - * 5 - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> 6 - */ 7 - 8 - /dts-v1/; 9 - #include "ox810se.dtsi" 10 - 11 - / { 12 - model = "Western Digital My Book World Edition"; 13 - 14 - compatible = "wd,mbwe", "oxsemi,ox810se"; 15 - 16 - chosen { 17 - bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; 18 - }; 19 - 20 - memory { 21 - /* 128Mbytes DDR */ 22 - reg = <0x48000000 0x8000000>; 23 - }; 24 - 25 - aliases { 26 - serial1 = &uart1; 27 - gpio0 = &gpio0; 28 - gpio1 = &gpio1; 29 - }; 30 - 31 - gpio-keys-polled { 32 - compatible = "gpio-keys-polled"; 33 - #address-cells = <1>; 34 - #size-cells = <0>; 35 - poll-interval = <100>; 36 - 37 - power { 38 - label = "power"; 39 - gpios = <&gpio0 0 1>; 40 - linux,code = <0x198>; 41 - }; 42 - 43 - recovery { 44 - label = "recovery"; 45 - gpios = <&gpio0 4 1>; 46 - linux,code = <0xab>; 47 - }; 48 - }; 49 - 50 - leds { 51 - compatible = "gpio-leds"; 52 - 53 - a0 { 54 - label = "activity0"; 55 - gpios = <&gpio0 25 0>; 56 - default-state = "keep"; 57 - }; 58 - 59 - a1 { 60 - label = "activity1"; 61 - gpios = <&gpio0 26 0>; 62 - default-state = "keep"; 63 - }; 64 - 65 - a2 { 66 - label = "activity2"; 67 - gpios = <&gpio0 5 0>; 68 - default-state = "keep"; 69 - }; 70 - 71 - a3 { 72 - label = "activity3"; 73 - gpios = <&gpio0 6 0>; 74 - default-state = "keep"; 75 - }; 76 - 77 - a4 { 78 - label = "activity4"; 79 - gpios = <&gpio0 7 0>; 80 - default-state = "keep"; 81 - }; 82 - 83 - a5 { 84 - label = "activity5"; 85 - gpios = <&gpio1 2 0>; 86 - default-state = "keep"; 87 - }; 88 - }; 89 - 90 - i2c-gpio { 91 - compatible = "i2c-gpio"; 92 - gpios = <&gpio0 3 0 /* sda */ 93 - &gpio0 2 0 /* scl */ 94 - >; 95 - i2c-gpio,delay-us = <2>; /* ~100 kHz */ 96 - #address-cells = <1>; 97 - #size-cells = <0>; 98 - 99 - rtc0: rtc@48 { 100 - compatible = "st,m41t00"; 101 - reg = <0x68>; 102 - }; 103 - }; 104 - }; 105 - 106 - &etha { 107 - status = "okay"; 108 - }; 109 - 110 - &uart1 { 111 - status = "okay"; 112 - 113 - pinctrl-names = "default"; 114 - pinctrl-0 = <&pinctrl_uart1>; 115 - };
-357
arch/arm/boot/dts/ox810se.dtsi
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC 4 - * 5 - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> 6 - */ 7 - 8 - #include <dt-bindings/clock/oxsemi,ox810se.h> 9 - #include <dt-bindings/reset/oxsemi,ox810se.h> 10 - 11 - / { 12 - #address-cells = <1>; 13 - #size-cells = <1>; 14 - compatible = "oxsemi,ox810se"; 15 - 16 - cpus { 17 - #address-cells = <0>; 18 - #size-cells = <0>; 19 - 20 - cpu { 21 - device_type = "cpu"; 22 - compatible = "arm,arm926ej-s"; 23 - clocks = <&armclk>; 24 - }; 25 - }; 26 - 27 - memory { 28 - device_type = "memory"; 29 - /* Max 256MB @ 0x48000000 */ 30 - reg = <0x48000000 0x10000000>; 31 - }; 32 - 33 - clocks { 34 - osc: oscillator { 35 - compatible = "fixed-clock"; 36 - #clock-cells = <0>; 37 - clock-frequency = <25000000>; 38 - }; 39 - 40 - gmacclk: gmacclk { 41 - compatible = "fixed-clock"; 42 - #clock-cells = <0>; 43 - clock-frequency = <125000000>; 44 - }; 45 - 46 - rpsclk: rpsclk { 47 - compatible = "fixed-factor-clock"; 48 - #clock-cells = <0>; 49 - clock-div = <1>; 50 - clock-mult = <1>; 51 - clocks = <&osc>; 52 - }; 53 - 54 - pll400: pll400 { 55 - compatible = "fixed-clock"; 56 - #clock-cells = <0>; 57 - clock-frequency = <733333333>; 58 - }; 59 - 60 - sysclk: sysclk { 61 - compatible = "fixed-factor-clock"; 62 - #clock-cells = <0>; 63 - clock-div = <4>; 64 - clock-mult = <1>; 65 - clocks = <&pll400>; 66 - }; 67 - 68 - armclk: armclk { 69 - compatible = "fixed-factor-clock"; 70 - #clock-cells = <0>; 71 - clock-div = <2>; 72 - clock-mult = <1>; 73 - clocks = <&pll400>; 74 - }; 75 - }; 76 - 77 - soc { 78 - #address-cells = <1>; 79 - #size-cells = <1>; 80 - compatible = "simple-bus"; 81 - ranges; 82 - interrupt-parent = <&intc>; 83 - 84 - etha: ethernet@40400000 { 85 - compatible = "oxsemi,ox810se-dwmac", "snps,dwmac"; 86 - reg = <0x40400000 0x2000>; 87 - interrupts = <8>; 88 - interrupt-names = "macirq"; 89 - mac-address = [000000000000]; /* Filled in by U-Boot */ 90 - phy-mode = "rgmii"; 91 - 92 - clocks = <&stdclk 6>, <&gmacclk>; 93 - clock-names = "gmac", "stmmaceth"; 94 - resets = <&reset 6>; 95 - 96 - /* Regmap for sys registers */ 97 - oxsemi,sys-ctrl = <&sys>; 98 - 99 - status = "disabled"; 100 - }; 101 - 102 - apb-bridge@44000000 { 103 - #address-cells = <1>; 104 - #size-cells = <1>; 105 - compatible = "simple-bus"; 106 - ranges = <0 0x44000000 0x1000000>; 107 - 108 - pinctrl: pinctrl { 109 - compatible = "oxsemi,ox810se-pinctrl"; 110 - 111 - /* Regmap for sys registers */ 112 - oxsemi,sys-ctrl = <&sys>; 113 - 114 - pinctrl_uart0: uart0 { 115 - uart0a { 116 - pins = "gpio31"; 117 - function = "fct3"; 118 - }; 119 - uart0b { 120 - pins = "gpio32"; 121 - function = "fct3"; 122 - }; 123 - }; 124 - 125 - pinctrl_uart0_modem: uart0_modem { 126 - uart0c { 127 - pins = "gpio27"; 128 - function = "fct3"; 129 - }; 130 - uart0d { 131 - pins = "gpio28"; 132 - function = "fct3"; 133 - }; 134 - uart0e { 135 - pins = "gpio29"; 136 - function = "fct3"; 137 - }; 138 - uart0f { 139 - pins = "gpio30"; 140 - function = "fct3"; 141 - }; 142 - uart0g { 143 - pins = "gpio33"; 144 - function = "fct3"; 145 - }; 146 - uart0h { 147 - pins = "gpio34"; 148 - function = "fct3"; 149 - }; 150 - }; 151 - 152 - pinctrl_uart1: uart1 { 153 - uart1a { 154 - pins = "gpio20"; 155 - function = "fct3"; 156 - }; 157 - uart1b { 158 - pins = "gpio22"; 159 - function = "fct3"; 160 - }; 161 - }; 162 - 163 - pinctrl_uart1_modem: uart1_modem { 164 - uart1c { 165 - pins = "gpio8"; 166 - function = "fct3"; 167 - }; 168 - uart1d { 169 - pins = "gpio9"; 170 - function = "fct3"; 171 - }; 172 - uart1e { 173 - pins = "gpio23"; 174 - function = "fct3"; 175 - }; 176 - uart1f { 177 - pins = "gpio24"; 178 - function = "fct3"; 179 - }; 180 - uart1g { 181 - pins = "gpio25"; 182 - function = "fct3"; 183 - }; 184 - uart1h { 185 - pins = "gpio26"; 186 - function = "fct3"; 187 - }; 188 - }; 189 - 190 - pinctrl_uart2: uart2 { 191 - uart2a { 192 - pins = "gpio6"; 193 - function = "fct3"; 194 - }; 195 - uart2b { 196 - pins = "gpio7"; 197 - function = "fct3"; 198 - }; 199 - }; 200 - 201 - pinctrl_uart2_modem: uart2_modem { 202 - uart2c { 203 - pins = "gpio0"; 204 - function = "fct3"; 205 - }; 206 - uart2d { 207 - pins = "gpio1"; 208 - function = "fct3"; 209 - }; 210 - uart2e { 211 - pins = "gpio2"; 212 - function = "fct3"; 213 - }; 214 - uart2f { 215 - pins = "gpio3"; 216 - function = "fct3"; 217 - }; 218 - uart2g { 219 - pins = "gpio4"; 220 - function = "fct3"; 221 - }; 222 - uart2h { 223 - pins = "gpio5"; 224 - function = "fct3"; 225 - }; 226 - }; 227 - }; 228 - 229 - gpio0: gpio@0 { 230 - compatible = "oxsemi,ox810se-gpio"; 231 - reg = <0x000000 0x100000>; 232 - interrupts = <21>; 233 - #gpio-cells = <2>; 234 - gpio-controller; 235 - interrupt-controller; 236 - #interrupt-cells = <2>; 237 - ngpios = <32>; 238 - oxsemi,gpio-bank = <0>; 239 - gpio-ranges = <&pinctrl 0 0 32>; 240 - }; 241 - 242 - gpio1: gpio@100000 { 243 - compatible = "oxsemi,ox810se-gpio"; 244 - reg = <0x100000 0x100000>; 245 - interrupts = <22>; 246 - #gpio-cells = <2>; 247 - gpio-controller; 248 - interrupt-controller; 249 - #interrupt-cells = <2>; 250 - ngpios = <3>; 251 - oxsemi,gpio-bank = <1>; 252 - gpio-ranges = <&pinctrl 0 32 3>; 253 - }; 254 - 255 - uart0: serial@200000 { 256 - compatible = "ns16550a"; 257 - reg = <0x200000 0x100000>; 258 - clocks = <&sysclk>; 259 - interrupts = <23>; 260 - reg-shift = <0>; 261 - fifo-size = <16>; 262 - reg-io-width = <1>; 263 - current-speed = <115200>; 264 - no-loopback-test; 265 - status = "disabled"; 266 - resets = <&reset RESET_UART1>; 267 - }; 268 - 269 - uart1: serial@300000 { 270 - compatible = "ns16550a"; 271 - reg = <0x300000 0x100000>; 272 - clocks = <&sysclk>; 273 - interrupts = <24>; 274 - reg-shift = <0>; 275 - fifo-size = <16>; 276 - reg-io-width = <1>; 277 - current-speed = <115200>; 278 - no-loopback-test; 279 - status = "disabled"; 280 - resets = <&reset RESET_UART2>; 281 - }; 282 - 283 - uart2: serial@900000 { 284 - compatible = "ns16550a"; 285 - reg = <0x900000 0x100000>; 286 - clocks = <&sysclk>; 287 - interrupts = <29>; 288 - reg-shift = <0>; 289 - fifo-size = <16>; 290 - reg-io-width = <1>; 291 - current-speed = <115200>; 292 - no-loopback-test; 293 - status = "disabled"; 294 - resets = <&reset RESET_UART3>; 295 - }; 296 - 297 - uart3: serial@a00000 { 298 - compatible = "ns16550a"; 299 - reg = <0xa00000 0x100000>; 300 - clocks = <&sysclk>; 301 - interrupts = <30>; 302 - reg-shift = <0>; 303 - fifo-size = <16>; 304 - reg-io-width = <1>; 305 - current-speed = <115200>; 306 - no-loopback-test; 307 - status = "disabled"; 308 - resets = <&reset RESET_UART4>; 309 - }; 310 - }; 311 - 312 - apb-bridge@45000000 { 313 - #address-cells = <1>; 314 - #size-cells = <1>; 315 - compatible = "simple-bus"; 316 - ranges = <0 0x45000000 0x1000000>; 317 - 318 - sys: sys-ctrl@0 { 319 - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; 320 - reg = <0x000000 0x100000>; 321 - 322 - reset: reset-controller { 323 - compatible = "oxsemi,ox810se-reset"; 324 - #reset-cells = <1>; 325 - }; 326 - 327 - stdclk: stdclk { 328 - compatible = "oxsemi,ox810se-stdclk"; 329 - #clock-cells = <1>; 330 - }; 331 - }; 332 - 333 - rps@300000 { 334 - #address-cells = <1>; 335 - #size-cells = <1>; 336 - compatible = "simple-bus"; 337 - ranges = <0 0x300000 0x100000>; 338 - 339 - intc: interrupt-controller@0 { 340 - compatible = "oxsemi,ox810se-rps-irq"; 341 - interrupt-controller; 342 - reg = <0 0x200>; 343 - #interrupt-cells = <1>; 344 - valid-mask = <0xffffffff>; 345 - clear-mask = <0xffffffff>; 346 - }; 347 - 348 - timer0: timer@200 { 349 - compatible = "oxsemi,ox810se-rps-timer"; 350 - reg = <0x200 0x40>; 351 - clocks = <&rpsclk>; 352 - interrupts = <4 5>; 353 - }; 354 - }; 355 - }; 356 - }; 357 - };
-93
arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 4 - * 5 - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> 6 - */ 7 - 8 - /dts-v1/; 9 - #include "ox820.dtsi" 10 - 11 - / { 12 - model = "Cloud Engines PogoPlug Series 3"; 13 - 14 - compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; 15 - 16 - chosen { 17 - bootargs = "earlyprintk"; 18 - stdout-path = "serial0:115200n8"; 19 - }; 20 - 21 - memory { 22 - /* 128Mbytes DDR */ 23 - reg = <0x60000000 0x8000000>; 24 - }; 25 - 26 - aliases { 27 - serial0 = &uart0; 28 - gpio0 = &gpio0; 29 - gpio1 = &gpio1; 30 - }; 31 - 32 - leds { 33 - compatible = "gpio-leds"; 34 - 35 - blue { 36 - label = "pogoplug:blue"; 37 - gpios = <&gpio0 2 0>; 38 - default-state = "keep"; 39 - }; 40 - 41 - orange { 42 - label = "pogoplug:orange"; 43 - gpios = <&gpio1 16 1>; 44 - default-state = "keep"; 45 - }; 46 - 47 - green { 48 - label = "pogoplug:green"; 49 - gpios = <&gpio1 17 1>; 50 - default-state = "keep"; 51 - }; 52 - }; 53 - }; 54 - 55 - &uart0 { 56 - status = "okay"; 57 - 58 - pinctrl-names = "default"; 59 - pinctrl-0 = <&pinctrl_uart0>; 60 - }; 61 - 62 - &nandc { 63 - status = "okay"; 64 - 65 - pinctrl-names = "default"; 66 - pinctrl-0 = <&pinctrl_nand>; 67 - 68 - nand@0 { 69 - reg = <0>; 70 - #address-cells = <1>; 71 - #size-cells = <1>; 72 - nand-ecc-mode = "soft"; 73 - nand-ecc-algo = "hamming"; 74 - 75 - partition@0 { 76 - label = "boot"; 77 - reg = <0x00000000 0x00e00000>; 78 - read-only; 79 - }; 80 - 81 - partition@e00000 { 82 - label = "ubi"; 83 - reg = <0x00e00000 0x07200000>; 84 - }; 85 - }; 86 - }; 87 - 88 - &etha { 89 - status = "okay"; 90 - 91 - pinctrl-names = "default"; 92 - pinctrl-0 = <&pinctrl_etha_mdio>; 93 - };
-299
arch/arm/boot/dts/ox820.dtsi
··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC 4 - * 5 - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> 6 - */ 7 - 8 - #include <dt-bindings/interrupt-controller/arm-gic.h> 9 - #include <dt-bindings/clock/oxsemi,ox820.h> 10 - #include <dt-bindings/reset/oxsemi,ox820.h> 11 - 12 - / { 13 - #address-cells = <1>; 14 - #size-cells = <1>; 15 - compatible = "oxsemi,ox820"; 16 - 17 - cpus { 18 - #address-cells = <1>; 19 - #size-cells = <0>; 20 - enable-method = "oxsemi,ox820-smp"; 21 - 22 - cpu@0 { 23 - device_type = "cpu"; 24 - compatible = "arm,arm11mpcore"; 25 - clocks = <&armclk>; 26 - reg = <0>; 27 - }; 28 - 29 - cpu@1 { 30 - device_type = "cpu"; 31 - compatible = "arm,arm11mpcore"; 32 - clocks = <&armclk>; 33 - reg = <1>; 34 - }; 35 - }; 36 - 37 - memory { 38 - device_type = "memory"; 39 - /* Max 512MB @ 0x60000000 */ 40 - reg = <0x60000000 0x20000000>; 41 - }; 42 - 43 - clocks { 44 - osc: oscillator { 45 - compatible = "fixed-clock"; 46 - #clock-cells = <0>; 47 - clock-frequency = <25000000>; 48 - }; 49 - 50 - gmacclk: gmacclk { 51 - compatible = "fixed-clock"; 52 - #clock-cells = <0>; 53 - clock-frequency = <125000000>; 54 - }; 55 - 56 - sysclk: sysclk { 57 - compatible = "fixed-factor-clock"; 58 - #clock-cells = <0>; 59 - clock-div = <4>; 60 - clock-mult = <1>; 61 - clocks = <&osc>; 62 - }; 63 - 64 - plla: plla { 65 - compatible = "fixed-clock"; 66 - #clock-cells = <0>; 67 - clock-frequency = <850000000>; 68 - }; 69 - 70 - armclk: armclk { 71 - compatible = "fixed-factor-clock"; 72 - #clock-cells = <0>; 73 - clock-div = <2>; 74 - clock-mult = <1>; 75 - clocks = <&plla>; 76 - }; 77 - }; 78 - 79 - soc { 80 - #address-cells = <1>; 81 - #size-cells = <1>; 82 - compatible = "simple-bus"; 83 - ranges; 84 - interrupt-parent = <&gic>; 85 - 86 - nandc: nand-controller@41000000 { 87 - compatible = "oxsemi,ox820-nand"; 88 - reg = <0x41000000 0x100000>; 89 - clocks = <&stdclk CLK_820_NAND>; 90 - resets = <&reset RESET_NAND>; 91 - #address-cells = <1>; 92 - #size-cells = <0>; 93 - status = "disabled"; 94 - }; 95 - 96 - etha: ethernet@40400000 { 97 - compatible = "oxsemi,ox820-dwmac", "snps,dwmac"; 98 - reg = <0x40400000 0x2000>; 99 - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 100 - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 101 - interrupt-names = "macirq", "eth_wake_irq"; 102 - mac-address = [000000000000]; /* Filled in by U-Boot */ 103 - phy-mode = "rgmii"; 104 - 105 - clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>; 106 - clock-names = "gmac", "stmmaceth"; 107 - resets = <&reset RESET_MAC>; 108 - 109 - /* Regmap for sys registers */ 110 - oxsemi,sys-ctrl = <&sys>; 111 - 112 - status = "disabled"; 113 - }; 114 - 115 - apb-bridge@44000000 { 116 - #address-cells = <1>; 117 - #size-cells = <1>; 118 - compatible = "simple-bus"; 119 - ranges = <0 0x44000000 0x1000000>; 120 - 121 - pinctrl: pinctrl { 122 - compatible = "oxsemi,ox820-pinctrl"; 123 - 124 - /* Regmap for sys registers */ 125 - oxsemi,sys-ctrl = <&sys>; 126 - 127 - pinctrl_uart0: uart0 { 128 - uart0 { 129 - pins = "gpio30", "gpio31"; 130 - function = "fct5"; 131 - }; 132 - }; 133 - 134 - pinctrl_uart0_modem: uart0_modem { 135 - uart0_modem_a { 136 - pins = "gpio24", "gpio24", "gpio26", "gpio27"; 137 - function = "fct4"; 138 - }; 139 - uart0_modem_b { 140 - pins = "gpio28", "gpio29"; 141 - function = "fct5"; 142 - }; 143 - }; 144 - 145 - pinctrl_uart1: uart1 { 146 - uart1 { 147 - pins = "gpio7", "gpio8"; 148 - function = "fct4"; 149 - }; 150 - }; 151 - 152 - pinctrl_uart1_modem: uart1_modem { 153 - uart1_modem { 154 - pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43"; 155 - function = "fct4"; 156 - }; 157 - }; 158 - 159 - pinctrl_etha_mdio: etha_mdio { 160 - etha_mdio { 161 - pins = "gpio3", "gpio4"; 162 - function = "fct1"; 163 - }; 164 - }; 165 - 166 - pinctrl_nand: nand { 167 - nand { 168 - pins = "gpio12", "gpio13", "gpio14", "gpio15", 169 - "gpio16", "gpio17", "gpio18", "gpio19", 170 - "gpio20", "gpio21", "gpio22", "gpio23", 171 - "gpio24"; 172 - function = "fct1"; 173 - }; 174 - }; 175 - }; 176 - 177 - gpio0: gpio@0 { 178 - compatible = "oxsemi,ox820-gpio"; 179 - reg = <0x000000 0x100000>; 180 - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 181 - #gpio-cells = <2>; 182 - gpio-controller; 183 - interrupt-controller; 184 - #interrupt-cells = <2>; 185 - ngpios = <32>; 186 - oxsemi,gpio-bank = <0>; 187 - gpio-ranges = <&pinctrl 0 0 32>; 188 - }; 189 - 190 - gpio1: gpio@100000 { 191 - compatible = "oxsemi,ox820-gpio"; 192 - reg = <0x100000 0x100000>; 193 - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 194 - #gpio-cells = <2>; 195 - gpio-controller; 196 - interrupt-controller; 197 - #interrupt-cells = <2>; 198 - ngpios = <18>; 199 - oxsemi,gpio-bank = <1>; 200 - gpio-ranges = <&pinctrl 0 32 18>; 201 - }; 202 - 203 - uart0: serial@200000 { 204 - compatible = "ns16550a"; 205 - reg = <0x200000 0x100000>; 206 - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 207 - reg-shift = <0>; 208 - fifo-size = <16>; 209 - reg-io-width = <1>; 210 - current-speed = <115200>; 211 - no-loopback-test; 212 - status = "disabled"; 213 - clocks = <&sysclk>; 214 - resets = <&reset RESET_UART1>; 215 - }; 216 - 217 - uart1: serial@300000 { 218 - compatible = "ns16550a"; 219 - reg = <0x200000 0x100000>; 220 - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 221 - reg-shift = <0>; 222 - fifo-size = <16>; 223 - reg-io-width = <1>; 224 - current-speed = <115200>; 225 - no-loopback-test; 226 - status = "disabled"; 227 - clocks = <&sysclk>; 228 - resets = <&reset RESET_UART2>; 229 - }; 230 - 231 - rps@400000 { 232 - #address-cells = <1>; 233 - #size-cells = <1>; 234 - compatible = "simple-bus"; 235 - ranges = <0 0x400000 0x100000>; 236 - 237 - intc: interrupt-controller@0 { 238 - compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq"; 239 - interrupt-controller; 240 - reg = <0 0x200>; 241 - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 242 - #interrupt-cells = <1>; 243 - valid-mask = <0xffffffff>; 244 - clear-mask = <0xffffffff>; 245 - }; 246 - 247 - timer0: timer@200 { 248 - compatible = "oxsemi,ox820-rps-timer"; 249 - reg = <0x200 0x40>; 250 - clocks = <&sysclk>; 251 - interrupt-parent = <&intc>; 252 - interrupts = <4>; 253 - }; 254 - }; 255 - 256 - sys: sys-ctrl@e00000 { 257 - compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; 258 - reg = <0xe00000 0x200000>; 259 - 260 - reset: reset-controller { 261 - compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset"; 262 - #reset-cells = <1>; 263 - }; 264 - 265 - stdclk: stdclk { 266 - compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; 267 - #clock-cells = <1>; 268 - }; 269 - }; 270 - }; 271 - 272 - apb-bridge@47000000 { 273 - #address-cells = <1>; 274 - #size-cells = <1>; 275 - compatible = "simple-bus"; 276 - ranges = <0 0x47000000 0x1000000>; 277 - 278 - scu: scu@0 { 279 - compatible = "arm,arm11mp-scu"; 280 - reg = <0x0 0x100>; 281 - }; 282 - 283 - local-timer@600 { 284 - compatible = "arm,arm11mp-twd-timer"; 285 - reg = <0x600 0x20>; 286 - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>; 287 - clocks = <&armclk>; 288 - }; 289 - 290 - gic: interrupt-controller@1000 { 291 - compatible = "arm,arm11mp-gic"; 292 - interrupt-controller; 293 - #interrupt-cells = <3>; 294 - reg = <0x1000 0x1000>, 295 - <0x100 0x500>; 296 - }; 297 - }; 298 - }; 299 - };