Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'ras-core-2020-06-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 RAS updates from Thomas Gleixner:
"RAS updates from Borislav Petkov:
- Unmap a whole guest page if an MCE is encountered in it to avoid
follow-on MCEs leading to the guest crashing, by Tony Luck.
This change collided with the entry changes and the merge
resolution would have been rather unpleasant. To avoid that the
entry branch was merged in before applying this. The resulting code
did not change over the rebase.
- AMD MCE error thresholding machinery cleanup and hotplug
sanitization, by Thomas Gleixner.
- Change the MCE notifiers to denote whether they have handled the
error and not break the chain early by returning NOTIFY_STOP, thus
giving the opportunity for the later handlers in the chain to see
it. By Tony Luck.
- Add AMD family 0x17, models 0x60-6f support, by Alexander Monakov.
- Last but not least, the usual round of fixes and improvements"
* tag 'ras-core-2020-06-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
x86/mce/dev-mcelog: Fix -Wstringop-truncation warning about strncpy()
x86/{mce,mm}: Unmap the entire page if the whole page is affected and poisoned
EDAC/amd64: Add AMD family 17h model 60h PCI IDs
hwmon: (k10temp) Add AMD family 17h model 60h PCI match
x86/amd_nb: Add AMD family 17h model 60h PCI IDs
x86/mcelog: Add compat_ioctl for 32-bit mcelog support
x86/mce: Drop bogus comment about mce.kflags
x86/mce: Fixup exception only for the correct MCEs
EDAC: Drop the EDAC report status checks
x86/mce: Add mce=print_all option
x86/mce: Change default MCE logger to check mce->kflags
x86/mce: Fix all mce notifiers to update the mce->kflags bitmask
x86/mce: Add a struct mce.kflags field
x86/mce: Convert the CEC to use the MCE notifier
x86/mce: Rename "first" function as "early"
x86/mce/amd, edac: Remove report_gart_errors
x86/mce/amd: Make threshold bank setting hotplug robust
x86/mce/amd: Cleanup threshold device remove path
x86/mce/amd: Straighten CPU hotplug path
x86/mce/amd: Sanitize thresholding device creation hotplug path
...
+307
-321
+1
arch/x86/include/asm/amd_nb.h
+1
arch/x86/include/asm/amd_nb.h
+20
-8
arch/x86/include/asm/mce.h
+20
-8
arch/x86/include/asm/mce.h
···
127
127
#define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
128
128
#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
129
129
130
+
#define XEC(x, mask) (((x) >> 16) & mask)
131
+
132
+
/* mce.kflags flag bits for logging etc. */
133
+
#define MCE_HANDLED_CEC BIT_ULL(0)
134
+
#define MCE_HANDLED_UC BIT_ULL(1)
135
+
#define MCE_HANDLED_EXTLOG BIT_ULL(2)
136
+
#define MCE_HANDLED_NFIT BIT_ULL(3)
137
+
#define MCE_HANDLED_EDAC BIT_ULL(4)
138
+
#define MCE_HANDLED_MCELOG BIT_ULL(5)
139
+
#define MCE_IN_KERNEL_RECOV BIT_ULL(6)
140
+
130
141
/*
131
142
* This structure contains all data related to the MCE log. Also
132
143
* carries a signature to make it easier to find from external
···
153
142
struct mce entry[];
154
143
};
155
144
145
+
/* Highest last */
156
146
enum mce_notifier_prios {
157
-
MCE_PRIO_FIRST = INT_MAX,
158
-
MCE_PRIO_UC = INT_MAX - 1,
159
-
MCE_PRIO_EXTLOG = INT_MAX - 2,
160
-
MCE_PRIO_NFIT = INT_MAX - 3,
161
-
MCE_PRIO_EDAC = INT_MAX - 4,
162
-
MCE_PRIO_MCELOG = 1,
163
-
MCE_PRIO_LOWEST = 0,
147
+
MCE_PRIO_LOWEST,
148
+
MCE_PRIO_MCELOG,
149
+
MCE_PRIO_EDAC,
150
+
MCE_PRIO_NFIT,
151
+
MCE_PRIO_EXTLOG,
152
+
MCE_PRIO_UC,
153
+
MCE_PRIO_EARLY,
154
+
MCE_PRIO_CEC
164
155
};
165
156
166
157
struct notifier_block;
···
360
347
#endif
361
348
362
349
static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
363
-
364
350
#endif /* _ASM_X86_MCE_H */
+13
-6
arch/x86/include/asm/set_memory.h
+13
-6
arch/x86/include/asm/set_memory.h
···
86
86
extern int kernel_set_to_readonly;
87
87
88
88
#ifdef CONFIG_X86_64
89
-
static inline int set_mce_nospec(unsigned long pfn)
89
+
/*
90
+
* Prevent speculative access to the page by either unmapping
91
+
* it (if we do not require access to any part of the page) or
92
+
* marking it uncacheable (if we want to try to retrieve data
93
+
* from non-poisoned lines in the page).
94
+
*/
95
+
static inline int set_mce_nospec(unsigned long pfn, bool unmap)
90
96
{
91
97
unsigned long decoy_addr;
92
98
int rc;
93
99
94
100
/*
95
-
* Mark the linear address as UC to make sure we don't log more
96
-
* errors because of speculative access to the page.
97
101
* We would like to just call:
98
-
* set_memory_uc((unsigned long)pfn_to_kaddr(pfn), 1);
102
+
* set_memory_XX((unsigned long)pfn_to_kaddr(pfn), 1);
99
103
* but doing that would radically increase the odds of a
100
104
* speculative access to the poison page because we'd have
101
105
* the virtual address of the kernel 1:1 mapping sitting
102
106
* around in registers.
103
107
* Instead we get tricky. We create a non-canonical address
104
108
* that looks just like the one we want, but has bit 63 flipped.
105
-
* This relies on set_memory_uc() properly sanitizing any __pa()
109
+
* This relies on set_memory_XX() properly sanitizing any __pa()
106
110
* results with __PHYSICAL_MASK or PTE_PFN_MASK.
107
111
*/
108
112
decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63));
109
113
110
-
rc = set_memory_uc(decoy_addr, 1);
114
+
if (unmap)
115
+
rc = set_memory_np(decoy_addr, 1);
116
+
else
117
+
rc = set_memory_uc(decoy_addr, 1);
111
118
if (rc)
112
119
pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn);
113
120
return rc;
+1
arch/x86/include/uapi/asm/mce.h
+1
arch/x86/include/uapi/asm/mce.h
+5
arch/x86/kernel/amd_nb.c
+5
arch/x86/kernel/amd_nb.c
···
18
18
#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
19
19
#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
20
20
#define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
21
+
#define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
21
22
#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
22
23
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
23
24
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
25
+
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
24
26
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
25
27
#define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
26
28
···
35
33
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
36
34
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
37
35
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
36
+
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
38
37
{}
39
38
};
40
39
···
53
50
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
54
51
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
55
52
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
53
+
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
56
54
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
57
55
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
58
56
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
···
69
65
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
70
66
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
71
67
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
68
+
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
72
69
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
73
70
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
74
71
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
+120
-115
arch/x86/kernel/cpu/mce/amd.c
+120
-115
arch/x86/kernel/cpu/mce/amd.c
···
192
192
static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
193
193
194
194
static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
195
-
static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */
195
+
196
+
/*
197
+
* A list of the banks enabled on each logical CPU. Controls which respective
198
+
* descriptors to initialize later in mce_threshold_create_device().
199
+
*/
200
+
static DEFINE_PER_CPU(unsigned int, bank_map);
196
201
197
202
/* Map of banks that have more than MCA_MISC0 available. */
198
203
static DEFINE_PER_CPU(u32, smca_misc_banks_map);
···
386
381
struct thresh_restart *tr = _tr;
387
382
u32 hi, lo;
388
383
384
+
/* sysfs write might race against an offline operation */
385
+
if (this_cpu_read(threshold_banks))
386
+
return;
387
+
389
388
rdmsr(tr->b->address, lo, hi);
390
389
391
390
if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
···
577
568
{
578
569
enum smca_bank_types bank_type = smca_get_bank_type(m->bank);
579
570
struct cpuinfo_x86 *c = &boot_cpu_data;
580
-
u8 xec = (m->status >> 16) & 0x3F;
581
571
582
572
/* See Family 17h Models 10h-2Fh Erratum #1114. */
583
573
if (c->x86 == 0x17 &&
584
574
c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
585
-
bank_type == SMCA_IF && xec == 10)
575
+
bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10)
586
576
return true;
577
+
578
+
/* NB GART TLB error reporting is disabled by default. */
579
+
if (c->x86 < 0x17) {
580
+
if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)
581
+
return true;
582
+
}
587
583
588
584
return false;
589
585
}
···
1029
1015
static void amd_threshold_interrupt(void)
1030
1016
{
1031
1017
struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
1018
+
struct threshold_bank **bp = this_cpu_read(threshold_banks);
1032
1019
unsigned int bank, cpu = smp_processor_id();
1020
+
1021
+
/*
1022
+
* Validate that the threshold bank has been initialized already. The
1023
+
* handler is installed at boot time, but on a hotplug event the
1024
+
* interrupt might fire before the data has been initialized.
1025
+
*/
1026
+
if (!bp)
1027
+
return;
1033
1028
1034
1029
for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
1035
1030
if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1036
1031
continue;
1037
1032
1038
-
first_block = per_cpu(threshold_banks, cpu)[bank]->blocks;
1033
+
first_block = bp[bank]->blocks;
1039
1034
if (!first_block)
1040
1035
continue;
1041
1036
···
1093
1070
memset(&tr, 0, sizeof(tr));
1094
1071
tr.b = b;
1095
1072
1096
-
smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
1073
+
if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1))
1074
+
return -ENODEV;
1097
1075
1098
1076
return size;
1099
1077
}
···
1118
1094
b->threshold_limit = new;
1119
1095
tr.b = b;
1120
1096
1121
-
smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
1097
+
if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1))
1098
+
return -ENODEV;
1122
1099
1123
1100
return size;
1124
1101
}
···
1128
1103
{
1129
1104
u32 lo, hi;
1130
1105
1131
-
rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
1106
+
/* CPU might be offline by now */
1107
+
if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi))
1108
+
return -ENODEV;
1132
1109
1133
1110
return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
1134
1111
(THRESHOLD_MAX - b->threshold_limit)));
···
1235
1208
u32 low, high;
1236
1209
int err;
1237
1210
1238
-
if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))
1211
+
if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))
1239
1212
return 0;
1240
1213
1241
-
if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1214
+
if (rdmsr_safe(address, &low, &high))
1242
1215
return 0;
1243
1216
1244
1217
if (!(high & MASK_VALID_HI)) {
···
1273
1246
1274
1247
INIT_LIST_HEAD(&b->miscj);
1275
1248
1249
+
/* This is safe as @tb is not visible yet */
1276
1250
if (tb->blocks)
1277
1251
list_add(&b->miscj, &tb->blocks->miscj);
1278
1252
else
···
1294
1266
if (b)
1295
1267
kobject_uevent(&b->kobj, KOBJ_ADD);
1296
1268
1297
-
return err;
1269
+
return 0;
1298
1270
1299
1271
out_free:
1300
1272
if (b) {
1301
-
kobject_put(&b->kobj);
1302
1273
list_del(&b->miscj);
1303
-
kfree(b);
1274
+
kobject_put(&b->kobj);
1304
1275
}
1305
1276
return err;
1306
1277
}
···
1328
1301
return err;
1329
1302
}
1330
1303
1331
-
static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1304
+
static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
1305
+
unsigned int bank)
1332
1306
{
1333
-
struct device *dev = per_cpu(mce_device, cpu);
1307
+
struct device *dev = this_cpu_read(mce_device);
1334
1308
struct amd_northbridge *nb = NULL;
1335
1309
struct threshold_bank *b = NULL;
1336
1310
const char *name = get_name(bank, NULL);
···
1351
1323
if (err)
1352
1324
goto out;
1353
1325
1354
-
per_cpu(threshold_banks, cpu)[bank] = b;
1326
+
bp[bank] = b;
1355
1327
refcount_inc(&b->cpus);
1356
1328
1357
1329
err = __threshold_add_blocks(b);
···
1366
1338
goto out;
1367
1339
}
1368
1340
1341
+
/* Associate the bank with the per-CPU MCE device */
1369
1342
b->kobj = kobject_create_and_add(name, &dev->kobj);
1370
1343
if (!b->kobj) {
1371
1344
err = -EINVAL;
···
1374
1345
}
1375
1346
1376
1347
if (is_shared_bank(bank)) {
1348
+
b->shared = 1;
1377
1349
refcount_set(&b->cpus, 1);
1378
1350
1379
1351
/* nb is already initialized, see above */
···
1386
1356
1387
1357
err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank));
1388
1358
if (err)
1389
-
goto out_free;
1359
+
goto out_kobj;
1390
1360
1391
-
per_cpu(threshold_banks, cpu)[bank] = b;
1392
-
1361
+
bp[bank] = b;
1393
1362
return 0;
1394
1363
1395
-
out_free:
1364
+
out_kobj:
1365
+
kobject_put(b->kobj);
1366
+
out_free:
1396
1367
kfree(b);
1397
-
1398
-
out:
1368
+
out:
1399
1369
return err;
1400
1370
}
1401
1371
···
1404
1374
kfree(to_block(kobj));
1405
1375
}
1406
1376
1407
-
static void deallocate_threshold_block(unsigned int cpu, unsigned int bank)
1377
+
static void deallocate_threshold_blocks(struct threshold_bank *bank)
1408
1378
{
1409
-
struct threshold_block *pos = NULL;
1410
-
struct threshold_block *tmp = NULL;
1411
-
struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
1379
+
struct threshold_block *pos, *tmp;
1412
1380
1413
-
if (!head)
1414
-
return;
1415
-
1416
-
list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1381
+
list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) {
1417
1382
list_del(&pos->miscj);
1418
1383
kobject_put(&pos->kobj);
1419
1384
}
1420
1385
1421
-
kobject_put(&head->blocks->kobj);
1386
+
kobject_put(&bank->blocks->kobj);
1422
1387
}
1423
1388
1424
1389
static void __threshold_remove_blocks(struct threshold_bank *b)
···
1427
1402
kobject_del(&pos->kobj);
1428
1403
}
1429
1404
1430
-
static void threshold_remove_bank(unsigned int cpu, int bank)
1405
+
static void threshold_remove_bank(struct threshold_bank *bank)
1431
1406
{
1432
1407
struct amd_northbridge *nb;
1433
-
struct threshold_bank *b;
1434
1408
1435
-
b = per_cpu(threshold_banks, cpu)[bank];
1436
-
if (!b)
1409
+
if (!bank->blocks)
1410
+
goto out_free;
1411
+
1412
+
if (!bank->shared)
1413
+
goto out_dealloc;
1414
+
1415
+
if (!refcount_dec_and_test(&bank->cpus)) {
1416
+
__threshold_remove_blocks(bank);
1437
1417
return;
1438
-
1439
-
if (!b->blocks)
1440
-
goto free_out;
1441
-
1442
-
if (is_shared_bank(bank)) {
1443
-
if (!refcount_dec_and_test(&b->cpus)) {
1444
-
__threshold_remove_blocks(b);
1445
-
per_cpu(threshold_banks, cpu)[bank] = NULL;
1446
-
return;
1447
-
} else {
1448
-
/*
1449
-
* the last CPU on this node using the shared bank is
1450
-
* going away, remove that bank now.
1451
-
*/
1452
-
nb = node_to_amd_nb(amd_get_nb_id(cpu));
1453
-
nb->bank4 = NULL;
1454
-
}
1418
+
} else {
1419
+
/*
1420
+
* The last CPU on this node using the shared bank is going
1421
+
* away, remove that bank now.
1422
+
*/
1423
+
nb = node_to_amd_nb(amd_get_nb_id(smp_processor_id()));
1424
+
nb->bank4 = NULL;
1455
1425
}
1456
1426
1457
-
deallocate_threshold_block(cpu, bank);
1427
+
out_dealloc:
1428
+
deallocate_threshold_blocks(bank);
1458
1429
1459
-
free_out:
1460
-
kobject_del(b->kobj);
1461
-
kobject_put(b->kobj);
1462
-
kfree(b);
1463
-
per_cpu(threshold_banks, cpu)[bank] = NULL;
1430
+
out_free:
1431
+
kobject_put(bank->kobj);
1432
+
kfree(bank);
1464
1433
}
1465
1434
1466
1435
int mce_threshold_remove_device(unsigned int cpu)
1467
1436
{
1468
-
unsigned int bank;
1437
+
struct threshold_bank **bp = this_cpu_read(threshold_banks);
1438
+
unsigned int bank, numbanks = this_cpu_read(mce_num_banks);
1469
1439
1470
-
for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) {
1471
-
if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1472
-
continue;
1473
-
threshold_remove_bank(cpu, bank);
1440
+
if (!bp)
1441
+
return 0;
1442
+
1443
+
/*
1444
+
* Clear the pointer before cleaning up, so that the interrupt won't
1445
+
* touch anything of this.
1446
+
*/
1447
+
this_cpu_write(threshold_banks, NULL);
1448
+
1449
+
for (bank = 0; bank < numbanks; bank++) {
1450
+
if (bp[bank]) {
1451
+
threshold_remove_bank(bp[bank]);
1452
+
bp[bank] = NULL;
1453
+
}
1474
1454
}
1475
-
kfree(per_cpu(threshold_banks, cpu));
1476
-
per_cpu(threshold_banks, cpu) = NULL;
1455
+
kfree(bp);
1477
1456
return 0;
1478
1457
}
1479
1458
1480
-
/* create dir/files for all valid threshold banks */
1459
+
/**
1460
+
* mce_threshold_create_device - Create the per-CPU MCE threshold device
1461
+
* @cpu: The plugged in CPU
1462
+
*
1463
+
* Create directories and files for all valid threshold banks.
1464
+
*
1465
+
* This is invoked from the CPU hotplug callback which was installed in
1466
+
* mcheck_init_device(). The invocation happens in context of the hotplug
1467
+
* thread running on @cpu. The callback is invoked on all CPUs which are
1468
+
* online when the callback is installed or during a real hotplug event.
1469
+
*/
1481
1470
int mce_threshold_create_device(unsigned int cpu)
1482
1471
{
1483
-
unsigned int bank;
1472
+
unsigned int numbanks, bank;
1484
1473
struct threshold_bank **bp;
1485
-
int err = 0;
1474
+
int err;
1486
1475
1487
-
bp = per_cpu(threshold_banks, cpu);
1476
+
if (!mce_flags.amd_threshold)
1477
+
return 0;
1478
+
1479
+
bp = this_cpu_read(threshold_banks);
1488
1480
if (bp)
1489
1481
return 0;
1490
1482
1491
-
bp = kcalloc(per_cpu(mce_num_banks, cpu), sizeof(struct threshold_bank *),
1492
-
GFP_KERNEL);
1483
+
numbanks = this_cpu_read(mce_num_banks);
1484
+
bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL);
1493
1485
if (!bp)
1494
1486
return -ENOMEM;
1495
1487
1496
-
per_cpu(threshold_banks, cpu) = bp;
1497
-
1498
-
for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) {
1499
-
if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1488
+
for (bank = 0; bank < numbanks; ++bank) {
1489
+
if (!(this_cpu_read(bank_map) & (1 << bank)))
1500
1490
continue;
1501
-
err = threshold_create_bank(cpu, bank);
1491
+
err = threshold_create_bank(bp, cpu, bank);
1502
1492
if (err)
1503
-
goto err;
1493
+
goto out_err;
1504
1494
}
1505
-
return err;
1506
-
err:
1507
-
mce_threshold_remove_device(cpu);
1508
-
return err;
1509
-
}
1510
-
1511
-
static __init int threshold_init_device(void)
1512
-
{
1513
-
unsigned lcpu = 0;
1514
-
1515
-
/* to hit CPUs online before the notifier is up */
1516
-
for_each_online_cpu(lcpu) {
1517
-
int err = mce_threshold_create_device(lcpu);
1518
-
1519
-
if (err)
1520
-
return err;
1521
-
}
1495
+
this_cpu_write(threshold_banks, bp);
1522
1496
1523
1497
if (thresholding_irq_en)
1524
1498
mce_threshold_vector = amd_threshold_interrupt;
1525
-
1526
1499
return 0;
1500
+
out_err:
1501
+
mce_threshold_remove_device(cpu);
1502
+
return err;
1527
1503
}
1528
-
/*
1529
-
* there are 3 funcs which need to be _initcalled in a logic sequence:
1530
-
* 1. xen_late_init_mcelog
1531
-
* 2. mcheck_init_device
1532
-
* 3. threshold_init_device
1533
-
*
1534
-
* xen_late_init_mcelog must register xen_mce_chrdev_device before
1535
-
* native mce_chrdev_device registration if running under xen platform;
1536
-
*
1537
-
* mcheck_init_device should be inited before threshold_init_device to
1538
-
* initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1539
-
*
1540
-
* so we use following _initcalls
1541
-
* 1. device_initcall(xen_late_init_mcelog);
1542
-
* 2. device_initcall_sync(mcheck_init_device);
1543
-
* 3. late_initcall(threshold_init_device);
1544
-
*
1545
-
* when running under xen, the initcall order is 1,2,3;
1546
-
* on baremetal, we skip 1 and we do only 2 and 3.
1547
-
*/
1548
-
late_initcall(threshold_init_device);
+55
-47
arch/x86/kernel/cpu/mce/core.c
+55
-47
arch/x86/kernel/cpu/mce/core.c
···
160
160
}
161
161
EXPORT_SYMBOL_GPL(mce_log);
162
162
163
-
/*
164
-
* We run the default notifier if we have only the UC, the first and the
165
-
* default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
166
-
* notifiers registered on the chain.
167
-
*/
168
-
#define NUM_DEFAULT_NOTIFIERS 3
169
-
static atomic_t num_notifiers;
170
-
171
163
void mce_register_decode_chain(struct notifier_block *nb)
172
164
{
173
165
if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
174
166
return;
175
-
176
-
atomic_inc(&num_notifiers);
177
167
178
168
blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
179
169
}
···
171
181
172
182
void mce_unregister_decode_chain(struct notifier_block *nb)
173
183
{
174
-
atomic_dec(&num_notifiers);
175
-
176
184
blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
177
185
}
178
186
EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
···
253
265
}
254
266
255
267
pr_cont("\n");
268
+
256
269
/*
257
270
* Note this output is parsed by external tools and old fields
258
271
* should not be changed.
···
520
531
}
521
532
EXPORT_SYMBOL_GPL(mce_is_memory_error);
522
533
534
+
static bool whole_page(struct mce *m)
535
+
{
536
+
if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
537
+
return true;
538
+
539
+
return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
540
+
}
541
+
523
542
bool mce_is_correctable(struct mce *m)
524
543
{
525
544
if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
···
543
546
}
544
547
EXPORT_SYMBOL_GPL(mce_is_correctable);
545
548
546
-
static bool cec_add_mce(struct mce *m)
547
-
{
548
-
if (!m)
549
-
return false;
550
-
551
-
/* We eat only correctable DRAM errors with usable addresses. */
552
-
if (mce_is_memory_error(m) &&
553
-
mce_is_correctable(m) &&
554
-
mce_usable_address(m))
555
-
if (!cec_add_elem(m->addr >> PAGE_SHIFT))
556
-
return true;
557
-
558
-
return false;
559
-
}
560
-
561
-
static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
549
+
static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
562
550
void *data)
563
551
{
564
552
struct mce *m = (struct mce *)data;
565
553
566
554
if (!m)
567
555
return NOTIFY_DONE;
568
-
569
-
if (cec_add_mce(m))
570
-
return NOTIFY_STOP;
571
556
572
557
/* Emit the trace record: */
573
558
trace_mce_record(m);
···
561
582
return NOTIFY_DONE;
562
583
}
563
584
564
-
static struct notifier_block first_nb = {
565
-
.notifier_call = mce_first_notifier,
566
-
.priority = MCE_PRIO_FIRST,
585
+
static struct notifier_block early_nb = {
586
+
.notifier_call = mce_early_notifier,
587
+
.priority = MCE_PRIO_EARLY,
567
588
};
568
589
569
590
static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
···
580
601
return NOTIFY_DONE;
581
602
582
603
pfn = mce->addr >> PAGE_SHIFT;
583
-
if (!memory_failure(pfn, 0))
584
-
set_mce_nospec(pfn);
604
+
if (!memory_failure(pfn, 0)) {
605
+
set_mce_nospec(pfn, whole_page(mce));
606
+
mce->kflags |= MCE_HANDLED_UC;
607
+
}
585
608
586
609
return NOTIFY_OK;
587
610
}
···
601
620
if (!m)
602
621
return NOTIFY_DONE;
603
622
604
-
if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
605
-
return NOTIFY_DONE;
606
-
607
-
__print_mce(m);
623
+
if (mca_cfg.print_all || !m->kflags)
624
+
__print_mce(m);
608
625
609
626
return NOTIFY_DONE;
610
627
}
···
1181
1202
int flags = MF_ACTION_REQUIRED;
1182
1203
1183
1204
pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1184
-
if (!(p->mce_status & MCG_STATUS_RIPV))
1205
+
1206
+
if (!p->mce_ripv)
1185
1207
flags |= MF_MUST_KILL;
1186
1208
1187
1209
if (!memory_failure(p->mce_addr >> PAGE_SHIFT, flags)) {
1188
-
set_mce_nospec(p->mce_addr >> PAGE_SHIFT);
1210
+
set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page);
1189
1211
return;
1190
1212
}
1191
1213
···
1340
1360
BUG_ON(!on_thread_stack() || !user_mode(regs));
1341
1361
1342
1362
current->mce_addr = m.addr;
1343
-
current->mce_status = m.mcgstatus;
1363
+
current->mce_ripv = !!(m.mcgstatus & MCG_STATUS_RIPV);
1364
+
current->mce_whole_page = whole_page(&m);
1344
1365
current->mce_kill_me.func = kill_me_maybe;
1345
1366
if (kill_it)
1346
1367
current->mce_kill_me.func = kill_me_now;
1347
1368
task_work_add(current, ¤t->mce_kill_me, true);
1348
1369
} else {
1349
-
if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1350
-
mce_panic("Failed kernel mode recovery", &m, msg);
1370
+
/*
1371
+
* Handle an MCE which has happened in kernel space but from
1372
+
* which the kernel can recover: ex_has_fault_handler() has
1373
+
* already verified that the rIP at which the error happened is
1374
+
* a rIP from which the kernel can recover (by jumping to
1375
+
* recovery code specified in _ASM_EXTABLE_FAULT()) and the
1376
+
* corresponding exception handler which would do that is the
1377
+
* proper one.
1378
+
*/
1379
+
if (m.kflags & MCE_IN_KERNEL_RECOV) {
1380
+
if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1381
+
mce_panic("Failed kernel mode recovery", &m, msg);
1382
+
}
1351
1383
}
1352
1384
}
1353
1385
EXPORT_SYMBOL_GPL(do_machine_check);
···
1750
1758
mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1751
1759
mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1752
1760
mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1761
+
mce_flags.amd_threshold = 1;
1753
1762
1754
1763
if (mce_flags.smca) {
1755
1764
msr_ops.ctl = smca_ctl_reg;
···
2048
2055
* mce=no_cmci Disables CMCI
2049
2056
* mce=no_lmce Disables LMCE
2050
2057
* mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2058
+
* mce=print_all Print all machine check logs to console
2051
2059
* mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2052
2060
* mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2053
2061
* monarchtimeout is how long to wait for other CPUs on machine
···
2077
2083
cfg->lmce_disabled = 1;
2078
2084
else if (!strcmp(str, "dont_log_ce"))
2079
2085
cfg->dont_log_ce = true;
2086
+
else if (!strcmp(str, "print_all"))
2087
+
cfg->print_all = true;
2080
2088
else if (!strcmp(str, "ignore_ce"))
2081
2089
cfg->ignore_ce = true;
2082
2090
else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
···
2101
2105
int __init mcheck_init(void)
2102
2106
{
2103
2107
mcheck_intel_therm_init();
2104
-
mce_register_decode_chain(&first_nb);
2108
+
mce_register_decode_chain(&early_nb);
2105
2109
mce_register_decode_chain(&mce_uc_nb);
2106
2110
mce_register_decode_chain(&mce_default_nb);
2107
2111
mcheck_vendor_init_severity();
···
2345
2349
static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2346
2350
static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2347
2351
static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2352
+
static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all);
2348
2353
2349
2354
static struct dev_ext_attribute dev_attr_check_interval = {
2350
2355
__ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
···
2370
2373
#endif
2371
2374
&dev_attr_monarch_timeout.attr,
2372
2375
&dev_attr_dont_log_ce.attr,
2376
+
&dev_attr_print_all.attr,
2373
2377
&dev_attr_ignore_ce.attr,
2374
2378
&dev_attr_cmci_disabled.attr,
2375
2379
NULL
···
2543
2545
}
2544
2546
}
2545
2547
2548
+
/*
2549
+
* When running on XEN, this initcall is ordered against the XEN mcelog
2550
+
* initcall:
2551
+
*
2552
+
* device_initcall(xen_late_init_mcelog);
2553
+
* device_initcall_sync(mcheck_init_device);
2554
+
*/
2546
2555
static __init int mcheck_init_device(void)
2547
2556
{
2548
2557
int err;
···
2581
2576
if (err)
2582
2577
goto err_out_mem;
2583
2578
2579
+
/*
2580
+
* Invokes mce_cpu_online() on all CPUs which are online when
2581
+
* the state is installed.
2582
+
*/
2584
2583
err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2585
2584
mce_cpu_online, mce_cpu_pre_down);
2586
2585
if (err < 0)
···
2674
2665
static_branch_inc(&mcsafe_key);
2675
2666
2676
2667
mcheck_debugfs_init();
2677
-
cec_init();
2678
2668
2679
2669
/*
2680
2670
* Flush out everything that has been logged during early boot, now that
+7
-1
arch/x86/kernel/cpu/mce/dev-mcelog.c
+7
-1
arch/x86/kernel/cpu/mce/dev-mcelog.c
···
39
39
struct mce *mce = (struct mce *)data;
40
40
unsigned int entry;
41
41
42
+
if (mce->kflags & MCE_HANDLED_CEC)
43
+
return NOTIFY_DONE;
44
+
42
45
mutex_lock(&mce_chrdev_read_mutex);
43
46
44
47
entry = mcelog->next;
···
59
56
60
57
memcpy(mcelog->entry + entry, mce, sizeof(struct mce));
61
58
mcelog->entry[entry].finished = 1;
59
+
mcelog->entry[entry].kflags = 0;
62
60
63
61
/* wake processes polling /dev/mcelog */
64
62
wake_up_interruptible(&mce_chrdev_wait);
···
67
63
unlock:
68
64
mutex_unlock(&mce_chrdev_read_mutex);
69
65
66
+
mce->kflags |= MCE_HANDLED_MCELOG;
70
67
return NOTIFY_OK;
71
68
}
72
69
···
329
324
.write = mce_chrdev_write,
330
325
.poll = mce_chrdev_poll,
331
326
.unlocked_ioctl = mce_chrdev_ioctl,
327
+
.compat_ioctl = compat_ptr_ioctl,
332
328
.llseek = no_llseek,
333
329
};
334
330
···
349
343
if (!mcelog)
350
344
return -ENOMEM;
351
345
352
-
strncpy(mcelog->signature, MCE_LOG_SIGNATURE, sizeof(mcelog->signature));
346
+
memcpy(mcelog->signature, MCE_LOG_SIGNATURE, sizeof(mcelog->signature));
353
347
mcelog->len = mce_log_len;
354
348
mcelog->recordlen = sizeof(struct mce);
355
349
+7
-3
arch/x86/kernel/cpu/mce/internal.h
+7
-3
arch/x86/kernel/cpu/mce/internal.h
···
119
119
bool dont_log_ce;
120
120
bool cmci_disabled;
121
121
bool ignore_ce;
122
+
bool print_all;
122
123
123
124
__u64 lmce_disabled : 1,
124
125
disabled : 1,
···
149
148
* Recovery. It indicates support for data poisoning in HW and deferred
150
149
* error interrupts.
151
150
*/
152
-
succor : 1,
151
+
succor : 1,
153
152
154
153
/*
155
154
* (AMD) SMCA: This bit indicates support for Scalable MCA which expands
···
157
156
* banks. Also, to accommodate the new banks and registers, the MCA
158
157
* register space is moved to a new MSR range.
159
158
*/
160
-
smca : 1,
159
+
smca : 1,
161
160
162
-
__reserved_0 : 61;
161
+
/* AMD-style error thresholding banks present. */
162
+
amd_threshold : 1,
163
+
164
+
__reserved_0 : 60;
163
165
};
164
166
165
167
extern struct mce_vendor_flags mce_flags;
+5
-1
arch/x86/kernel/cpu/mce/severity.c
+5
-1
arch/x86/kernel/cpu/mce/severity.c
···
213
213
{
214
214
if ((m->cs & 3) == 3)
215
215
return IN_USER;
216
-
if (mc_recoverable(m->mcgstatus) && ex_has_fault_handler(m->ip))
216
+
217
+
if (mc_recoverable(m->mcgstatus) && ex_has_fault_handler(m->ip)) {
218
+
m->kflags |= MCE_IN_KERNEL_RECOV;
217
219
return IN_KERNEL_RECOV;
220
+
}
221
+
218
222
return IN_KERNEL;
219
223
}
220
224
+3
-16
drivers/acpi/acpi_extlog.c
+3
-16
drivers/acpi/acpi_extlog.c
···
42
42
u8 rev1[12];
43
43
};
44
44
45
-
static int old_edac_report_status;
46
-
47
45
static u8 extlog_dsm_uuid[] __initdata = "663E35AF-CC10-41A4-88EA-5470AF055295";
48
46
49
47
/* L1 table related physical address */
···
144
146
static u32 err_seq;
145
147
146
148
estatus = extlog_elog_entry_check(cpu, bank);
147
-
if (estatus == NULL)
149
+
if (estatus == NULL || (mce->kflags & MCE_HANDLED_CEC))
148
150
return NOTIFY_DONE;
149
151
150
152
memcpy(elog_buf, (void *)estatus, ELOG_ENTRY_LEN);
···
174
176
}
175
177
176
178
out:
177
-
return NOTIFY_STOP;
179
+
mce->kflags |= MCE_HANDLED_EXTLOG;
180
+
return NOTIFY_OK;
178
181
}
179
182
180
183
static bool __init extlog_get_l1addr(void)
···
227
228
if (!(cap & MCG_ELOG_P) || !extlog_get_l1addr())
228
229
return -ENODEV;
229
230
230
-
if (edac_get_report_status() == EDAC_REPORTING_FORCE) {
231
-
pr_warn("Not loading eMCA, error reporting force-enabled through EDAC.\n");
232
-
return -EPERM;
233
-
}
234
-
235
231
rc = -EINVAL;
236
232
/* get L1 header to fetch necessary information */
237
233
l1_hdr_size = sizeof(struct extlog_l1_head);
···
274
280
if (elog_buf == NULL)
275
281
goto err_release_elog;
276
282
277
-
/*
278
-
* eMCA event report method has higher priority than EDAC method,
279
-
* unless EDAC event report method is mandatory.
280
-
*/
281
-
old_edac_report_status = edac_get_report_status();
282
-
edac_set_report_status(EDAC_REPORTING_DISABLED);
283
283
mce_register_decode_chain(&extlog_mce_dec);
284
284
/* enable OS to be involved to take over management from BIOS */
285
285
((struct extlog_l1_head *)extlog_l1_addr)->flags |= FLAG_OS_OPTIN;
···
295
307
296
308
static void __exit extlog_exit(void)
297
309
{
298
-
edac_set_report_status(old_edac_report_status);
299
310
mce_unregister_decode_chain(&extlog_mce_dec);
300
311
((struct extlog_l1_head *)extlog_l1_addr)->flags &= ~FLAG_OS_OPTIN;
301
312
if (extlog_l1_addr)
+1
drivers/acpi/nfit/mce.c
+1
drivers/acpi/nfit/mce.c
+14
-8
drivers/edac/amd64_edac.c
+14
-8
drivers/edac/amd64_edac.c
···
4
4
5
5
static struct edac_pci_ctl_info *pci_ctl;
6
6
7
-
static int report_gart_errors;
8
-
module_param(report_gart_errors, int, 0644);
9
-
10
7
/*
11
8
* Set by command line parameter. If BIOS has enabled the ECC, this override is
12
9
* cleared to prevent re-enabling the hardware by this driver.
···
2316
2319
.dbam_to_cs = f17_addr_mask_to_cs_size,
2317
2320
}
2318
2321
},
2322
+
[F17_M60H_CPUS] = {
2323
+
.ctl_name = "F17h_M60h",
2324
+
.f0_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F0,
2325
+
.f6_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F6,
2326
+
.max_mcs = 2,
2327
+
.ops = {
2328
+
.early_channel_count = f17_early_channel_count,
2329
+
.dbam_to_cs = f17_addr_mask_to_cs_size,
2330
+
}
2331
+
},
2319
2332
[F17_M70H_CPUS] = {
2320
2333
.ctl_name = "F17h_M70h",
2321
2334
.f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0,
···
3364
3357
fam_type = &family_types[F17_M30H_CPUS];
3365
3358
pvt->ops = &family_types[F17_M30H_CPUS].ops;
3366
3359
break;
3360
+
} else if (pvt->model >= 0x60 && pvt->model <= 0x6f) {
3361
+
fam_type = &family_types[F17_M60H_CPUS];
3362
+
pvt->ops = &family_types[F17_M60H_CPUS].ops;
3363
+
break;
3367
3364
} else if (pvt->model >= 0x70 && pvt->model <= 0x7f) {
3368
3365
fam_type = &family_types[F17_M70H_CPUS];
3369
3366
pvt->ops = &family_types[F17_M70H_CPUS].ops;
···
3692
3681
}
3693
3682
3694
3683
/* register stuff with EDAC MCE */
3695
-
if (report_gart_errors)
3696
-
amd_report_gart_errors(true);
3697
-
3698
3684
if (boot_cpu_data.x86 >= 0x17)
3699
3685
amd_register_ecc_decoder(decode_umc_error);
3700
3686
else
···
3726
3718
edac_pci_release_generic_ctl(pci_ctl);
3727
3719
3728
3720
/* unregister from EDAC MCE */
3729
-
amd_report_gart_errors(false);
3730
-
3731
3721
if (boot_cpu_data.x86 >= 0x17)
3732
3722
amd_unregister_ecc_decoder(decode_umc_error);
3733
3723
else
+3
drivers/edac/amd64_edac.h
+3
drivers/edac/amd64_edac.h
···
120
120
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
121
121
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
122
122
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
123
+
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
124
+
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e
123
125
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
124
126
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
125
127
#define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650
···
295
293
F17_CPUS,
296
294
F17_M10H_CPUS,
297
295
F17_M30H_CPUS,
296
+
F17_M60H_CPUS,
298
297
F17_M70H_CPUS,
299
298
F19_CPUS,
300
299
NUM_FAMILIES,
-61
drivers/edac/edac_mc.c
-61
drivers/edac/edac_mc.c
···
43
43
int edac_op_state = EDAC_OPSTATE_INVAL;
44
44
EXPORT_SYMBOL_GPL(edac_op_state);
45
45
46
-
static int edac_report = EDAC_REPORTING_ENABLED;
47
-
48
46
/* lock to memory controller's control array */
49
47
static DEFINE_MUTEX(mem_ctls_mutex);
50
48
static LIST_HEAD(mc_devices);
···
57
59
{
58
60
return container_of(e, struct mem_ctl_info, error_desc);
59
61
}
60
-
61
-
int edac_get_report_status(void)
62
-
{
63
-
return edac_report;
64
-
}
65
-
EXPORT_SYMBOL_GPL(edac_get_report_status);
66
-
67
-
void edac_set_report_status(int new)
68
-
{
69
-
if (new == EDAC_REPORTING_ENABLED ||
70
-
new == EDAC_REPORTING_DISABLED ||
71
-
new == EDAC_REPORTING_FORCE)
72
-
edac_report = new;
73
-
}
74
-
EXPORT_SYMBOL_GPL(edac_set_report_status);
75
-
76
-
static int edac_report_set(const char *str, const struct kernel_param *kp)
77
-
{
78
-
if (!str)
79
-
return -EINVAL;
80
-
81
-
if (!strncmp(str, "on", 2))
82
-
edac_report = EDAC_REPORTING_ENABLED;
83
-
else if (!strncmp(str, "off", 3))
84
-
edac_report = EDAC_REPORTING_DISABLED;
85
-
else if (!strncmp(str, "force", 5))
86
-
edac_report = EDAC_REPORTING_FORCE;
87
-
88
-
return 0;
89
-
}
90
-
91
-
static int edac_report_get(char *buffer, const struct kernel_param *kp)
92
-
{
93
-
int ret = 0;
94
-
95
-
switch (edac_report) {
96
-
case EDAC_REPORTING_ENABLED:
97
-
ret = sprintf(buffer, "on");
98
-
break;
99
-
case EDAC_REPORTING_DISABLED:
100
-
ret = sprintf(buffer, "off");
101
-
break;
102
-
case EDAC_REPORTING_FORCE:
103
-
ret = sprintf(buffer, "force");
104
-
break;
105
-
default:
106
-
ret = -EINVAL;
107
-
break;
108
-
}
109
-
110
-
return ret;
111
-
}
112
-
113
-
static const struct kernel_param_ops edac_report_ops = {
114
-
.set = edac_report_set,
115
-
.get = edac_report_get,
116
-
};
117
-
118
-
module_param_cb(edac_report, &edac_report_ops, &edac_report, 0644);
119
62
120
63
unsigned int edac_dimm_info_location(struct dimm_info *dimm, char *buf,
121
64
unsigned int len)
+3
-2
drivers/edac/i7core_edac.c
+3
-2
drivers/edac/i7core_edac.c
···
1815
1815
struct mem_ctl_info *mci;
1816
1816
1817
1817
i7_dev = get_i7core_dev(mce->socketid);
1818
-
if (!i7_dev)
1818
+
if (!i7_dev || (mce->kflags & MCE_HANDLED_CEC))
1819
1819
return NOTIFY_DONE;
1820
1820
1821
1821
mci = i7_dev->mci;
···
1834
1834
i7core_check_error(mci, mce);
1835
1835
1836
1836
/* Advise mcelog that the errors were handled */
1837
-
return NOTIFY_STOP;
1837
+
mce->kflags |= MCE_HANDLED_EDAC;
1838
+
return NOTIFY_OK;
1838
1839
}
1839
1840
1840
1841
static struct notifier_block i7_mce_dec = {
+4
-24
drivers/edac/mce_amd.c
+4
-24
drivers/edac/mce_amd.c
···
10
10
11
11
static u8 xec_mask = 0xf;
12
12
13
-
static bool report_gart_errors;
14
13
static void (*decode_dram_ecc)(int node_id, struct mce *m);
15
-
16
-
void amd_report_gart_errors(bool v)
17
-
{
18
-
report_gart_errors = v;
19
-
}
20
-
EXPORT_SYMBOL_GPL(amd_report_gart_errors);
21
14
22
15
void amd_register_ecc_decoder(void (*f)(int, struct mce *))
23
16
{
···
1023
1030
pr_cont("\n");
1024
1031
}
1025
1032
1026
-
/*
1027
-
* Filter out unwanted MCE signatures here.
1028
-
*/
1029
-
static bool ignore_mce(struct mce *m)
1030
-
{
1031
-
/*
1032
-
* NB GART TLB error reporting is disabled by default.
1033
-
*/
1034
-
if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5 && !report_gart_errors)
1035
-
return true;
1036
-
1037
-
return false;
1038
-
}
1039
-
1040
1033
static const char *decode_error_status(struct mce *m)
1041
1034
{
1042
1035
if (m->status & MCI_STATUS_UC) {
···
1046
1067
unsigned int fam = x86_family(m->cpuid);
1047
1068
int ecc;
1048
1069
1049
-
if (ignore_mce(m))
1050
-
return NOTIFY_STOP;
1070
+
if (m->kflags & MCE_HANDLED_CEC)
1071
+
return NOTIFY_DONE;
1051
1072
1052
1073
pr_emerg(HW_ERR "%s\n", decode_error_status(m));
1053
1074
···
1149
1170
err_code:
1150
1171
amd_decode_err_code(m->status & 0xffff);
1151
1172
1152
-
return NOTIFY_STOP;
1173
+
m->kflags |= MCE_HANDLED_EDAC;
1174
+
return NOTIFY_OK;
1153
1175
}
1154
1176
1155
1177
static struct notifier_block amd_mce_dec_nb = {
-2
drivers/edac/mce_amd.h
-2
drivers/edac/mce_amd.h
···
7
7
#include <asm/mce.h>
8
8
9
9
#define EC(x) ((x) & 0xffff)
10
-
#define XEC(x, mask) (((x) >> 16) & mask)
11
10
12
11
#define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
13
12
#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
···
76
77
bool (*mc2_mce)(u16, u8);
77
78
};
78
79
79
-
void amd_report_gart_errors(bool);
80
80
void amd_register_ecc_decoder(void (*f)(int, struct mce *));
81
81
void amd_unregister_ecc_decoder(void (*f)(int, struct mce *));
82
82
+3
-5
drivers/edac/pnd2_edac.c
+3
-5
drivers/edac/pnd2_edac.c
···
1396
1396
struct dram_addr daddr;
1397
1397
char *type;
1398
1398
1399
-
if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
1400
-
return NOTIFY_DONE;
1401
-
1402
1399
mci = pnd2_mci;
1403
-
if (!mci)
1400
+
if (!mci || (mce->kflags & MCE_HANDLED_CEC))
1404
1401
return NOTIFY_DONE;
1405
1402
1406
1403
/*
···
1426
1429
pnd2_mce_output_error(mci, mce, &daddr);
1427
1430
1428
1431
/* Advice mcelog that the error were handled */
1429
-
return NOTIFY_STOP;
1432
+
mce->kflags |= MCE_HANDLED_EDAC;
1433
+
return NOTIFY_OK;
1430
1434
}
1431
1435
1432
1436
static struct notifier_block pnd2_mce_dec = {
+3
-4
drivers/edac/sb_edac.c
+3
-4
drivers/edac/sb_edac.c
···
3134
3134
struct mem_ctl_info *mci;
3135
3135
char *type;
3136
3136
3137
-
if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
3137
+
if (mce->kflags & MCE_HANDLED_CEC)
3138
3138
return NOTIFY_DONE;
3139
3139
3140
3140
/*
···
3183
3183
sbridge_mce_output_error(mci, mce);
3184
3184
3185
3185
/* Advice mcelog that the error were handled */
3186
-
return NOTIFY_STOP;
3186
+
mce->kflags |= MCE_HANDLED_EDAC;
3187
+
return NOTIFY_OK;
3187
3188
}
3188
3189
3189
3190
static struct notifier_block sbridge_mce_dec = {
···
3524
3523
3525
3524
if (rc >= 0) {
3526
3525
mce_register_decode_chain(&sbridge_mce_dec);
3527
-
if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
3528
-
sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
3529
3526
return 0;
3530
3527
}
3531
3528
+2
-1
drivers/edac/skx_common.c
+2
-1
drivers/edac/skx_common.c
···
573
573
struct mem_ctl_info *mci;
574
574
char *type;
575
575
576
-
if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
576
+
if (mce->kflags & MCE_HANDLED_CEC)
577
577
return NOTIFY_DONE;
578
578
579
579
/* ignore unless this is memory related with an address */
···
615
615
616
616
skx_mce_output_error(mci, mce, &res);
617
617
618
+
mce->kflags |= MCE_HANDLED_EDAC;
618
619
return NOTIFY_DONE;
619
620
}
620
621
+1
drivers/hwmon/k10temp.c
+1
drivers/hwmon/k10temp.c
···
632
632
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
633
633
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
634
634
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
635
+
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
635
636
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
636
637
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
637
638
{}
+31
-2
drivers/ras/cec.c
+31
-2
drivers/ras/cec.c
···
309
309
return ret;
310
310
}
311
311
312
-
int cec_add_elem(u64 pfn)
312
+
static int cec_add_elem(u64 pfn)
313
313
{
314
314
struct ce_array *ca = &ce_arr;
315
315
unsigned int to = 0;
···
527
527
return 1;
528
528
}
529
529
530
-
void __init cec_init(void)
530
+
static int cec_notifier(struct notifier_block *nb, unsigned long val,
531
+
void *data)
532
+
{
533
+
struct mce *m = (struct mce *)data;
534
+
535
+
if (!m)
536
+
return NOTIFY_DONE;
537
+
538
+
/* We eat only correctable DRAM errors with usable addresses. */
539
+
if (mce_is_memory_error(m) &&
540
+
mce_is_correctable(m) &&
541
+
mce_usable_address(m)) {
542
+
if (!cec_add_elem(m->addr >> PAGE_SHIFT)) {
543
+
m->kflags |= MCE_HANDLED_CEC;
544
+
return NOTIFY_OK;
545
+
}
546
+
}
547
+
548
+
return NOTIFY_DONE;
549
+
}
550
+
551
+
static struct notifier_block cec_nb = {
552
+
.notifier_call = cec_notifier,
553
+
.priority = MCE_PRIO_CEC,
554
+
};
555
+
556
+
static void __init cec_init(void)
531
557
{
532
558
if (ce_arr.disabled)
533
559
return;
···
572
546
INIT_DELAYED_WORK(&cec_work, cec_work_fn);
573
547
schedule_delayed_work(&cec_work, CEC_DECAY_DEFAULT_INTERVAL);
574
548
549
+
mce_register_decode_chain(&cec_nb);
550
+
575
551
pr_info("Correctable Errors collector initialized.\n");
576
552
}
553
+
late_initcall(cec_init);
577
554
578
555
int __init parse_cec_param(char *str)
579
556
{
-8
include/linux/edac.h
-8
include/linux/edac.h
···
31
31
extern int edac_op_state;
32
32
33
33
struct bus_type *edac_get_sysfs_subsys(void);
34
-
int edac_get_report_status(void);
35
-
void edac_set_report_status(int new);
36
-
37
-
enum {
38
-
EDAC_REPORTING_ENABLED,
39
-
EDAC_REPORTING_DISABLED,
40
-
EDAC_REPORTING_FORCE
41
-
};
42
34
43
35
static inline void opstate_init(void)
44
36
{
+1
include/linux/pci_ids.h
+1
include/linux/pci_ids.h
···
550
550
#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
551
551
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
552
552
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
553
+
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 0x144b
553
554
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
554
555
#define PCI_DEVICE_ID_AMD_19H_DF_F3 0x1653
555
556
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
-5
include/linux/ras.h
-5
include/linux/ras.h
···
17
17
#endif
18
18
19
19
#ifdef CONFIG_RAS_CEC
20
-
void __init cec_init(void);
21
20
int __init parse_cec_param(char *str);
22
-
int cec_add_elem(u64 pfn);
23
-
#else
24
-
static inline void __init cec_init(void) { }
25
-
static inline int cec_add_elem(u64 pfn) { return -ENODEV; }
26
21
#endif
27
22
28
23
#ifdef CONFIG_RAS
+3
-1
include/linux/sched.h
+3
-1
include/linux/sched.h