Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

+66 -70

arch/arm/boot/compressed/head.S

··· 151 151 .L_\@: 152 152 .endm 153 153 154 + /* 155 + * The kernel build system appends the size of the 156 + * decompressed kernel at the end of the compressed data 157 + * in little-endian form. 158 + */ 159 + .macro get_inflated_image_size, res:req, tmp1:req, tmp2:req 160 + adr \res, .Linflated_image_size_offset 161 + ldr \tmp1, [\res] 162 + add \tmp1, \tmp1, \res @ address of inflated image size 163 + 164 + ldrb \res, [\tmp1] @ get_unaligned_le32 165 + ldrb \tmp2, [\tmp1, #1] 166 + orr \res, \res, \tmp2, lsl #8 167 + ldrb \tmp2, [\tmp1, #2] 168 + ldrb \tmp1, [\tmp1, #3] 169 + orr \res, \res, \tmp2, lsl #16 170 + orr \res, \res, \tmp1, lsl #24 171 + .endm 172 + 154 173 .section ".start", "ax" 155 174 /* 156 175 * sort out different calling conventions ··· 287 268 */ 288 269 mov r0, pc 289 270 cmp r0, r4 290 - ldrcc r0, LC0+32 271 + ldrcc r0, LC0+28 291 272 addcc r0, r0, pc 292 273 cmpcc r4, r0 293 274 orrcc r4, r4, #1 @ remember we skipped cache_on 294 275 blcs cache_on 295 276 296 277 restart: adr r0, LC0 297 - ldmia r0, {r1, r2, r3, r6, r10, r11, r12} 298 - ldr sp, [r0, #28] 278 + ldmia r0, {r1, r2, r3, r6, r11, r12} 279 + ldr sp, [r0, #24] 299 280 300 281 /* 301 282 * We might be running at a different address. We need ··· 303 284 */ 304 285 sub r0, r0, r1 @ calculate the delta offset 305 286 add r6, r6, r0 @ _edata 306 - add r10, r10, r0 @ inflated kernel size location 307 287 308 - /* 309 - * The kernel build system appends the size of the 310 - * decompressed kernel at the end of the compressed data 311 - * in little-endian form. 312 - */ 313 - ldrb r9, [r10, #0] 314 - ldrb lr, [r10, #1] 315 - orr r9, r9, lr, lsl #8 316 - ldrb lr, [r10, #2] 317 - ldrb r10, [r10, #3] 318 - orr r9, r9, lr, lsl #16 319 - orr r9, r9, r10, lsl #24 288 + get_inflated_image_size r9, r10, lr 320 289 321 290 #ifndef CONFIG_ZBOOT_ROM 322 291 /* malloc space is above the relocated stack (64k max) */ ··· 528 521 /* Preserve offset to relocated code. */ 529 522 sub r6, r9, r6 530 523 531 - #ifndef CONFIG_ZBOOT_ROM 532 - /* cache_clean_flush may use the stack, so relocate it */ 533 - add sp, sp, r6 534 - #endif 535 - 524 + mov r0, r9 @ start of relocated zImage 525 + add r1, sp, r6 @ end of relocated zImage 536 526 bl cache_clean_flush 537 527 538 528 badr r0, restart ··· 626 622 add r2, sp, #0x10000 @ 64k max 627 623 mov r3, r7 628 624 bl decompress_kernel 625 + 626 + get_inflated_image_size r1, r2, r3 627 + 628 + mov r0, r4 @ start of inflated image 629 + add r1, r1, r0 @ end of inflated image 629 630 bl cache_clean_flush 630 631 bl cache_off 631 632 ··· 661 652 .word __bss_start @ r2 662 653 .word _end @ r3 663 654 .word _edata @ r6 664 - .word input_data_end - 4 @ r10 (inflated size location) 665 655 .word _got_start @ r11 666 656 .word _got_end @ ip 667 657 .word .L_user_stack_end @ sp 668 658 .word _end - restart + 16384 + 1024*1024 669 659 .size LC0, . - LC0 660 + 661 + .Linflated_image_size_offset: 662 + .long (input_data_end - 4) - . 670 663 671 664 #ifdef CONFIG_ARCH_RPC 672 665 .globl params ··· 677 666 .ltorg 678 667 .align 679 668 #endif 669 + 670 + /* 671 + * dcache_line_size - get the minimum D-cache line size from the CTR register 672 + * on ARMv7. 673 + */ 674 + .macro dcache_line_size, reg, tmp 675 + #ifdef CONFIG_CPU_V7M 676 + movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR 677 + movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR 678 + ldr \tmp, [\tmp] 679 + #else 680 + mrc p15, 0, \tmp, c0, c0, 1 @ read ctr 681 + #endif 682 + lsr \tmp, \tmp, #16 683 + and \tmp, \tmp, #0xf @ cache line size encoding 684 + mov \reg, #4 @ bytes per word 685 + mov \reg, \reg, lsl \tmp @ actual cache line size 686 + .endm 680 687 681 688 /* 682 689 * Turn on the cache. We need to setup some page tables so that we ··· 1188 1159 bic r0, r0, #0x000c 1189 1160 #endif 1190 1161 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 1191 - mov r12, lr 1192 - bl __armv7_mmu_cache_flush 1193 1162 mov r0, #0 1194 1163 #ifdef CONFIG_MMU 1195 1164 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB ··· 1195 1168 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC 1196 1169 mcr p15, 0, r0, c7, c10, 4 @ DSB 1197 1170 mcr p15, 0, r0, c7, c5, 4 @ ISB 1198 - mov pc, r12 1171 + mov pc, lr 1199 1172 1200 1173 /* 1201 1174 * Clean and flush the cache to maintain consistency. 1202 1175 * 1176 + * On entry, 1177 + * r0 = start address 1178 + * r1 = end address (exclusive) 1203 1179 * On exit, 1204 1180 * r1, r2, r3, r9, r10, r11, r12 corrupted 1205 1181 * This routine must preserve: ··· 1211 1181 .align 5 1212 1182 cache_clean_flush: 1213 1183 mov r3, #16 1184 + mov r11, r1 1214 1185 b call_cache_fn 1215 1186 1216 1187 __armv4_mpu_cache_flush: ··· 1262 1231 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 1263 1232 b iflush 1264 1233 hierarchical: 1265 - mcr p15, 0, r10, c7, c10, 5 @ DMB 1266 - stmfd sp!, {r0-r7, r9-r11} 1267 - mrc p15, 1, r0, c0, c0, 1 @ read clidr 1268 - ands r3, r0, #0x7000000 @ extract loc from clidr 1269 - mov r3, r3, lsr #23 @ left align loc bit field 1270 - beq finished @ if loc is 0, then no need to clean 1271 - mov r10, #0 @ start clean at cache level 0 1272 - loop1: 1273 - add r2, r10, r10, lsr #1 @ work out 3x current cache level 1274 - mov r1, r0, lsr r2 @ extract cache type bits from clidr 1275 - and r1, r1, #7 @ mask of the bits for current cache only 1276 - cmp r1, #2 @ see what cache we have at this level 1277 - blt skip @ skip if no cache, or just i-cache 1278 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 1279 - mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr 1280 - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 1281 - and r2, r1, #7 @ extract the length of the cache lines 1282 - add r2, r2, #4 @ add 4 (line length offset) 1283 - ldr r4, =0x3ff 1284 - ands r4, r4, r1, lsr #3 @ find maximum number on the way size 1285 - clz r5, r4 @ find bit position of way size increment 1286 - ldr r7, =0x7fff 1287 - ands r7, r7, r1, lsr #13 @ extract max number of the index size 1288 - loop2: 1289 - mov r9, r4 @ create working copy of max way size 1290 - loop3: 1291 - ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 1292 - ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 1293 - THUMB( lsl r6, r9, r5 ) 1294 - THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 1295 - THUMB( lsl r6, r7, r2 ) 1296 - THUMB( orr r11, r11, r6 ) @ factor index number into r11 1297 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 1298 - subs r9, r9, #1 @ decrement the way 1299 - bge loop3 1300 - subs r7, r7, #1 @ decrement the index 1301 - bge loop2 1302 - skip: 1303 - add r10, r10, #2 @ increment cache number 1304 - cmp r3, r10 1305 - bgt loop1 1306 - finished: 1307 - ldmfd sp!, {r0-r7, r9-r11} 1308 - mov r10, #0 @ switch back to cache level 0 1309 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 1234 + dcache_line_size r1, r2 @ r1 := dcache min line size 1235 + sub r2, r1, #1 @ r2 := line size mask 1236 + bic r0, r0, r2 @ round down start to line size 1237 + sub r11, r11, #1 @ end address is exclusive 1238 + bic r11, r11, r2 @ round down end to line size 1239 + 0: cmp r0, r11 @ finished? 1240 + bgt iflush 1241 + mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA 1242 + add r0, r0, r1 1243 + b 0b 1310 1244 iflush: 1311 1245 mcr p15, 0, r10, c7, c10, 4 @ DSB 1312 1246 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB

-1

arch/arm/boot/compressed/vmlinux.lds.S

··· 36 36 *(.start) 37 37 *(.text) 38 38 *(.text.*) 39 - *(.fixup) 40 39 *(.gnu.warning) 41 40 *(.glue_7t) 42 41 *(.glue_7)

+4 -4

arch/arm/kernel/relocate_kernel.S

··· 25 25 ldr r3, [r0],#4 26 26 27 27 /* Is it a destination page. Put destination address to r4 */ 28 - tst r3,#1,0 28 + tst r3,#1 29 29 beq 1f 30 30 bic r4,r3,#1 31 31 b 0b 32 32 1: 33 33 /* Is it an indirection page */ 34 - tst r3,#2,0 34 + tst r3,#2 35 35 beq 1f 36 36 bic r0,r3,#2 37 37 b 0b 38 38 1: 39 39 40 40 /* are we done ? */ 41 - tst r3,#4,0 41 + tst r3,#4 42 42 beq 1f 43 43 b 2f 44 44 45 45 1: 46 46 /* is it source ? */ 47 - tst r3,#8,0 47 + tst r3,#8 48 48 beq 0b 49 49 bic r3,r3,#8 50 50 mov r6,#1024

+1 -1

arch/arm/kernel/unwind.c

··· 444 444 ctrl.vrs[PC] = ctrl.vrs[LR]; 445 445 446 446 /* check for infinite loop */ 447 - if (frame->pc == ctrl.vrs[PC]) 447 + if (frame->pc == ctrl.vrs[PC] && frame->sp == ctrl.vrs[SP]) 448 448 return -URC_FAILURE; 449 449 450 450 frame->fp = ctrl.vrs[FP];

+5 -7

arch/arm/mach-ebsa110/core.c

··· 201 201 return IRQ_HANDLED; 202 202 } 203 203 204 - static struct irqaction ebsa110_timer_irq = { 205 - .name = "EBSA110 Timer Tick", 206 - .flags = IRQF_TIMER | IRQF_IRQPOLL, 207 - .handler = ebsa110_timer_interrupt, 208 - }; 209 - 210 204 /* 211 205 * Set up timer interrupt. 212 206 */ 213 207 void __init ebsa110_timer_init(void) 214 208 { 209 + int irq = IRQ_EBSA110_TIMER0; 210 + 215 211 arch_gettimeoffset = ebsa110_gettimeoffset; 216 212 217 213 /* ··· 217 221 __raw_writeb(COUNT & 0xff, PIT_T1); 218 222 __raw_writeb(COUNT >> 8, PIT_T1); 219 223 220 - setup_irq(IRQ_EBSA110_TIMER0, &ebsa110_timer_irq); 224 + if (request_irq(irq, ebsa110_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, 225 + "EBSA110 Timer Tick", NULL)) 226 + pr_err("Failed to request irq %d (EBSA110 Timer Tick)\n", irq); 221 227 } 222 228 223 229 static struct plat_serial8250_port serial_platform_data[] = {

+3 -8

arch/arm/mach-footbridge/dc21285-timer.c

··· 101 101 return IRQ_HANDLED; 102 102 } 103 103 104 - static struct irqaction footbridge_timer_irq = { 105 - .name = "dc21285_timer1", 106 - .handler = timer1_interrupt, 107 - .flags = IRQF_TIMER | IRQF_IRQPOLL, 108 - .dev_id = &ckevt_dc21285, 109 - }; 110 - 111 104 /* 112 105 * Set up timer interrupt. 113 106 */ ··· 111 118 112 119 clocksource_register_hz(&cksrc_dc21285, rate); 113 120 114 - setup_irq(ce->irq, &footbridge_timer_irq); 121 + if (request_irq(ce->irq, timer1_interrupt, IRQF_TIMER | IRQF_IRQPOLL, 122 + "dc21285_timer1", &ckevt_dc21285)) 123 + pr_err("Failed to request irq %d (dc21285_timer1)", ce->irq); 115 124 116 125 ce->cpumask = cpumask_of(smp_processor_id()); 117 126 clockevents_config_and_register(ce, rate, 0x4, 0xffffff);

+4 -6

arch/arm/mach-footbridge/isa-irq.c

··· 96 96 generic_handle_irq(isa_irq); 97 97 } 98 98 99 - static struct irqaction irq_cascade = { 100 - .handler = no_action, 101 - .name = "cascade", 102 - }; 103 - 104 99 static struct resource pic1_resource = { 105 100 .name = "pic1", 106 101 .start = 0x20, ··· 155 160 156 161 request_resource(&ioport_resource, &pic1_resource); 157 162 request_resource(&ioport_resource, &pic2_resource); 158 - setup_irq(IRQ_ISA_CASCADE, &irq_cascade); 163 + 164 + irq = IRQ_ISA_CASCADE; 165 + if (request_irq(irq, no_action, 0, "cascade", NULL)) 166 + pr_err("Failed to request irq %u (cascade)\n", irq); 159 167 160 168 irq_set_chained_handler(host_irq, isa_irq_handler); 161 169

+3 -8

arch/arm/mach-footbridge/isa-timer.c

··· 25 25 return IRQ_HANDLED; 26 26 } 27 27 28 - static struct irqaction pit_timer_irq = { 29 - .name = "pit", 30 - .handler = pit_timer_interrupt, 31 - .flags = IRQF_TIMER | IRQF_IRQPOLL, 32 - .dev_id = &i8253_clockevent, 33 - }; 34 - 35 28 void __init isa_timer_init(void) 36 29 { 37 30 clocksource_i8253_init(); 38 31 39 - setup_irq(i8253_clockevent.irq, &pit_timer_irq); 32 + if (request_irq(i8253_clockevent.irq, pit_timer_interrupt, 33 + IRQF_TIMER | IRQF_IRQPOLL, "pit", &i8253_clockevent)) 34 + pr_err("Failed to request irq %d(pit)\n", i8253_clockevent.irq); 40 35 clockevent_i8253_init(false); 41 36 }

+2 -6

arch/arm/mach-rpc/time.c

··· 85 85 return IRQ_HANDLED; 86 86 } 87 87 88 - static struct irqaction ioc_timer_irq = { 89 - .name = "timer", 90 - .handler = ioc_timer_interrupt 91 - }; 92 - 93 88 /* 94 89 * Set up timer interrupt. 95 90 */ ··· 92 97 { 93 98 WARN_ON(clocksource_register_hz(&ioctime_clocksource, RPC_CLOCK_FREQ)); 94 99 ioctime_init(); 95 - setup_irq(IRQ_TIMER0, &ioc_timer_irq); 100 + if (request_irq(IRQ_TIMER0, ioc_timer_interrupt, 0, "timer", NULL)) 101 + pr_err("Failed to request irq %d (timer)\n", IRQ_TIMER0); 96 102 }

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