+1 -1

arch/x86/include/asm/cpufeature.h

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··· 125 125 #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ 126 126 #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ 127 127 #define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */ 128 128 - #define X86_FEATURE_RDRND (4*32+30) /* The RDRAND instruction */ 128 128 + #define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */ 129 129 #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ 130 130 131 131 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */

+71 -71

arch/x86/include/asm/desc.h

reviewed

··· 4 4 #include <asm/desc_defs.h> 5 5 #include <asm/ldt.h> 6 6 #include <asm/mmu.h> 7 7 + 7 8 #include <linux/smp.h> 8 9 9 9 - static inline void fill_ldt(struct desc_struct *desc, 10 10 - const struct user_desc *info) 10 10 + static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info) 11 11 { 12 12 - desc->limit0 = info->limit & 0x0ffff; 13 13 - desc->base0 = info->base_addr & 0x0000ffff; 12 12 + desc->limit0 = info->limit & 0x0ffff; 14 13 15 15 - desc->base1 = (info->base_addr & 0x00ff0000) >> 16; 16 16 - desc->type = (info->read_exec_only ^ 1) << 1; 17 17 - desc->type |= info->contents << 2; 18 18 - desc->s = 1; 19 19 - desc->dpl = 0x3; 20 20 - desc->p = info->seg_not_present ^ 1; 21 21 - desc->limit = (info->limit & 0xf0000) >> 16; 22 22 - desc->avl = info->useable; 23 23 - desc->d = info->seg_32bit; 24 24 - desc->g = info->limit_in_pages; 25 25 - desc->base2 = (info->base_addr & 0xff000000) >> 24; 14 14 + desc->base0 = (info->base_addr & 0x0000ffff); 15 15 + desc->base1 = (info->base_addr & 0x00ff0000) >> 16; 16 16 + 17 17 + desc->type = (info->read_exec_only ^ 1) << 1; 18 18 + desc->type |= info->contents << 2; 19 19 + 20 20 + desc->s = 1; 21 21 + desc->dpl = 0x3; 22 22 + desc->p = info->seg_not_present ^ 1; 23 23 + desc->limit = (info->limit & 0xf0000) >> 16; 24 24 + desc->avl = info->useable; 25 25 + desc->d = info->seg_32bit; 26 26 + desc->g = info->limit_in_pages; 27 27 + 28 28 + desc->base2 = (info->base_addr & 0xff000000) >> 24; 26 29 /* 27 30 * Don't allow setting of the lm bit. It is useless anyway 28 31 * because 64bit system calls require __USER_CS: 29 32 */ 30 30 - desc->l = 0; 33 33 + desc->l = 0; 31 34 } 32 35 33 36 extern struct desc_ptr idt_descr; ··· 39 36 struct gdt_page { 40 37 struct desc_struct gdt[GDT_ENTRIES]; 41 38 } __attribute__((aligned(PAGE_SIZE))); 39 39 + 42 40 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page); 43 41 44 42 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu) ··· 52 48 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, 53 49 unsigned dpl, unsigned ist, unsigned seg) 54 50 { 55 55 - gate->offset_low = PTR_LOW(func); 56 56 - gate->segment = __KERNEL_CS; 57 57 - gate->ist = ist; 58 58 - gate->p = 1; 59 59 - gate->dpl = dpl; 60 60 - gate->zero0 = 0; 61 61 - gate->zero1 = 0; 62 62 - gate->type = type; 63 63 - gate->offset_middle = PTR_MIDDLE(func); 64 64 - gate->offset_high = PTR_HIGH(func); 51 51 + gate->offset_low = PTR_LOW(func); 52 52 + gate->segment = __KERNEL_CS; 53 53 + gate->ist = ist; 54 54 + gate->p = 1; 55 55 + gate->dpl = dpl; 56 56 + gate->zero0 = 0; 57 57 + gate->zero1 = 0; 58 58 + gate->type = type; 59 59 + gate->offset_middle = PTR_MIDDLE(func); 60 60 + gate->offset_high = PTR_HIGH(func); 65 61 } 66 62 67 63 #else ··· 70 66 unsigned short seg) 71 67 { 72 68 gate->a = (seg << 16) | (base & 0xffff); 73 73 - gate->b = (base & 0xffff0000) | 74 74 - (((0x80 | type | (dpl << 5)) & 0xff) << 8); 69 69 + gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8); 75 70 } 76 71 77 72 #endif ··· 78 75 static inline int desc_empty(const void *ptr) 79 76 { 80 77 const u32 *desc = ptr; 78 78 + 81 79 return !(desc[0] | desc[1]); 82 80 } 83 81 84 82 #ifdef CONFIG_PARAVIRT 85 83 #include <asm/paravirt.h> 86 84 #else 87 87 - #define load_TR_desc() native_load_tr_desc() 88 88 - #define load_gdt(dtr) native_load_gdt(dtr) 89 89 - #define load_idt(dtr) native_load_idt(dtr) 90 90 - #define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) 91 91 - #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) 85 85 + #define load_TR_desc() native_load_tr_desc() 86 86 + #define load_gdt(dtr) native_load_gdt(dtr) 87 87 + #define load_idt(dtr) native_load_idt(dtr) 88 88 + #define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) 89 89 + #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) 92 90 93 93 - #define store_gdt(dtr) native_store_gdt(dtr) 94 94 - #define store_idt(dtr) native_store_idt(dtr) 95 95 - #define store_tr(tr) (tr = native_store_tr()) 91 91 + #define store_gdt(dtr) native_store_gdt(dtr) 92 92 + #define store_idt(dtr) native_store_idt(dtr) 93 93 + #define store_tr(tr) (tr = native_store_tr()) 96 94 97 97 - #define load_TLS(t, cpu) native_load_tls(t, cpu) 98 98 - #define set_ldt native_set_ldt 95 95 + #define load_TLS(t, cpu) native_load_tls(t, cpu) 96 96 + #define set_ldt native_set_ldt 99 97 100 100 - #define write_ldt_entry(dt, entry, desc) \ 101 101 - native_write_ldt_entry(dt, entry, desc) 102 102 - #define write_gdt_entry(dt, entry, desc, type) \ 103 103 - native_write_gdt_entry(dt, entry, desc, type) 104 104 - #define write_idt_entry(dt, entry, g) \ 105 105 - native_write_idt_entry(dt, entry, g) 98 98 + #define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc) 99 99 + #define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type) 100 100 + #define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g) 106 101 107 102 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) 108 103 { ··· 113 112 114 113 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) 115 114 116 116 - static inline void native_write_idt_entry(gate_desc *idt, int entry, 117 117 - const gate_desc *gate) 115 115 + static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate) 118 116 { 119 117 memcpy(&idt[entry], gate, sizeof(*gate)); 120 118 } 121 119 122 122 - static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, 123 123 - const void *desc) 120 120 + static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc) 124 121 { 125 122 memcpy(&ldt[entry], desc, 8); 126 123 } 127 124 128 128 - static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry, 129 129 - const void *desc, int type) 125 125 + static inline void 126 126 + native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type) 130 127 { 131 128 unsigned int size; 129 129 + 132 130 switch (type) { 133 133 - case DESC_TSS: 134 134 - size = sizeof(tss_desc); 135 135 - break; 136 136 - case DESC_LDT: 137 137 - size = sizeof(ldt_desc); 138 138 - break; 139 139 - default: 140 140 - size = sizeof(struct desc_struct); 141 141 - break; 131 131 + case DESC_TSS: size = sizeof(tss_desc); break; 132 132 + case DESC_LDT: size = sizeof(ldt_desc); break; 133 133 + default: size = sizeof(*gdt); break; 142 134 } 135 135 + 143 136 memcpy(&gdt[entry], desc, size); 144 137 } 145 138 ··· 149 154 } 150 155 151 156 152 152 - static inline void set_tssldt_descriptor(void *d, unsigned long addr, 153 153 - unsigned type, unsigned size) 157 157 + static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size) 154 158 { 155 159 #ifdef CONFIG_X86_64 156 160 struct ldttss_desc64 *desc = d; 161 161 + 157 162 memset(desc, 0, sizeof(*desc)); 158 158 - desc->limit0 = size & 0xFFFF; 159 159 - desc->base0 = PTR_LOW(addr); 160 160 - desc->base1 = PTR_MIDDLE(addr) & 0xFF; 161 161 - desc->type = type; 162 162 - desc->p = 1; 163 163 - desc->limit1 = (size >> 16) & 0xF; 164 164 - desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF; 165 165 - desc->base3 = PTR_HIGH(addr); 163 163 + 164 164 + desc->limit0 = size & 0xFFFF; 165 165 + desc->base0 = PTR_LOW(addr); 166 166 + desc->base1 = PTR_MIDDLE(addr) & 0xFF; 167 167 + desc->type = type; 168 168 + desc->p = 1; 169 169 + desc->limit1 = (size >> 16) & 0xF; 170 170 + desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF; 171 171 + desc->base3 = PTR_HIGH(addr); 166 172 #else 167 173 pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0); 168 174 #endif ··· 233 237 static inline unsigned long native_store_tr(void) 234 238 { 235 239 unsigned long tr; 240 240 + 236 241 asm volatile("str %0":"=r" (tr)); 242 242 + 237 243 return tr; 238 244 } 239 245 240 246 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) 241 247 { 242 242 - unsigned int i; 243 248 struct desc_struct *gdt = get_cpu_gdt_table(cpu); 249 249 + unsigned int i; 244 250 245 251 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) 246 252 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; ··· 311 313 unsigned dpl, unsigned ist, unsigned seg) 312 314 { 313 315 gate_desc s; 316 316 + 314 317 pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg); 315 318 /* 316 319 * does not need to be atomic because it is only done once at ··· 342 343 set_bit(vector, used_vectors); 343 344 if (first_system_vector > vector) 344 345 first_system_vector = vector; 345 345 - } else 346 346 + } else { 346 347 BUG(); 348 348 + } 347 349 } 348 350 349 351 static inline void alloc_intr_gate(unsigned int n, void *addr)

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arch/x86/include/asm/mmu.h

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··· 11 11 typedef struct { 12 12 void *ldt; 13 13 int size; 14 14 - struct mutex lock; 15 15 - void *vdso; 16 14 17 15 #ifdef CONFIG_X86_64 18 16 /* True if mm supports a task running in 32 bit compatibility mode. */ 19 17 unsigned short ia32_compat; 20 18 #endif 21 19 20 20 + struct mutex lock; 21 21 + void *vdso; 22 22 } mm_context_t; 23 23 24 24 #ifdef CONFIG_SMP

+385 -203

arch/x86/include/asm/uv/uv_bau.h

reviewed

··· 5 5 * 6 6 * SGI UV Broadcast Assist Unit definitions 7 7 * 8 8 - * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved. 8 8 + * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved. 9 9 */ 10 10 11 11 #ifndef _ASM_X86_UV_UV_BAU_H ··· 35 35 36 36 #define MAX_CPUS_PER_UVHUB 64 37 37 #define MAX_CPUS_PER_SOCKET 32 38 38 - #define UV_ADP_SIZE 64 /* hardware-provided max. */ 39 39 - #define UV_CPUS_PER_ACT_STATUS 32 /* hardware-provided max. */ 40 40 - #define UV_ITEMS_PER_DESCRIPTOR 8 38 38 + #define ADP_SZ 64 /* hardware-provided max. */ 39 39 + #define UV_CPUS_PER_AS 32 /* hardware-provided max. */ 40 40 + #define ITEMS_PER_DESC 8 41 41 /* the 'throttle' to prevent the hardware stay-busy bug */ 42 42 #define MAX_BAU_CONCURRENT 3 43 43 #define UV_ACT_STATUS_MASK 0x3 44 44 #define UV_ACT_STATUS_SIZE 2 45 45 #define UV_DISTRIBUTION_SIZE 256 46 46 #define UV_SW_ACK_NPENDING 8 47 47 - #define UV_NET_ENDPOINT_INTD 0x38 48 48 - #define UV_DESC_BASE_PNODE_SHIFT 49 47 47 + #define UV1_NET_ENDPOINT_INTD 0x38 48 48 + #define UV2_NET_ENDPOINT_INTD 0x28 49 49 + #define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \ 50 50 + UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD) 51 51 + #define UV_DESC_PSHIFT 49 49 52 #define UV_PAYLOADQ_PNODE_SHIFT 49 50 53 #define UV_PTC_BASENAME "sgi_uv/ptc_statistics" 51 54 #define UV_BAU_BASENAME "sgi_uv/bau_tunables" ··· 56 53 #define UV_BAU_TUNABLES_FILE "bau_tunables" 57 54 #define WHITESPACE " \t\n" 58 55 #define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask)) 59 59 - #define UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT 15 60 60 - #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT 16 61 61 - #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x0000000009UL 56 56 + #define cpubit_isset(cpu, bau_local_cpumask) \ 57 57 + test_bit((cpu), (bau_local_cpumask).bits) 58 58 + 62 59 /* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */ 63 63 - #define BAU_MISC_CONTROL_MULT_MASK 3 60 60 + /* 61 61 + * UV2: Bit 19 selects between 62 62 + * (0): 10 microsecond timebase and 63 63 + * (1): 80 microseconds 64 64 + * we're using 655us, similar to UV1: 65 units of 10us 65 65 + */ 66 66 + #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL) 67 67 + #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL) 64 68 65 65 - #define UVH_AGING_PRESCALE_SEL 0x000000b000UL 69 69 + #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \ 70 70 + UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \ 71 71 + UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD) 72 72 + 73 73 + #define BAU_MISC_CONTROL_MULT_MASK 3 74 74 + 75 75 + #define UVH_AGING_PRESCALE_SEL 0x000000b000UL 66 76 /* [30:28] URGENCY_7 an index into a table of times */ 67 67 - #define BAU_URGENCY_7_SHIFT 28 68 68 - #define BAU_URGENCY_7_MASK 7 77 77 + #define BAU_URGENCY_7_SHIFT 28 78 78 + #define BAU_URGENCY_7_MASK 7 69 79 70 70 - #define UVH_TRANSACTION_TIMEOUT 0x000000b200UL 80 80 + #define UVH_TRANSACTION_TIMEOUT 0x000000b200UL 71 81 /* [45:40] BAU - BAU transaction timeout select - a multiplier */ 72 72 - #define BAU_TRANS_SHIFT 40 73 73 - #define BAU_TRANS_MASK 0x3f 82 82 + #define BAU_TRANS_SHIFT 40 83 83 + #define BAU_TRANS_MASK 0x3f 84 84 + 85 85 + /* 86 86 + * shorten some awkward names 87 87 + */ 88 88 + #define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 89 89 + #define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 90 90 + #define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 91 91 + #define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 92 92 + #define write_gmmr uv_write_global_mmr64 93 93 + #define write_lmmr uv_write_local_mmr 94 94 + #define read_lmmr uv_read_local_mmr 95 95 + #define read_gmmr uv_read_global_mmr64 74 96 75 97 /* 76 98 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1 77 99 */ 78 78 - #define DESC_STATUS_IDLE 0 79 79 - #define DESC_STATUS_ACTIVE 1 80 80 - #define DESC_STATUS_DESTINATION_TIMEOUT 2 81 81 - #define DESC_STATUS_SOURCE_TIMEOUT 3 100 100 + #define DS_IDLE 0 101 101 + #define DS_ACTIVE 1 102 102 + #define DS_DESTINATION_TIMEOUT 2 103 103 + #define DS_SOURCE_TIMEOUT 3 104 104 + /* 105 105 + * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2 106 106 + * values 1 and 5 will not occur 107 107 + */ 108 108 + #define UV2H_DESC_IDLE 0 109 109 + #define UV2H_DESC_DEST_TIMEOUT 2 110 110 + #define UV2H_DESC_DEST_STRONG_NACK 3 111 111 + #define UV2H_DESC_BUSY 4 112 112 + #define UV2H_DESC_SOURCE_TIMEOUT 6 113 113 + #define UV2H_DESC_DEST_PUT_ERR 7 82 114 83 115 /* 84 116 * delay for 'plugged' timeout retries, in microseconds ··· 124 86 * threshholds at which to use IPI to free resources 125 87 */ 126 88 /* after this # consecutive 'plugged' timeouts, use IPI to release resources */ 127 127 - #define PLUGSB4RESET 100 89 89 + #define PLUGSB4RESET 100 128 90 /* after this many consecutive timeouts, use IPI to release resources */ 129 129 - #define TIMEOUTSB4RESET 1 91 91 + #define TIMEOUTSB4RESET 1 130 92 /* at this number uses of IPI to release resources, giveup the request */ 131 131 - #define IPI_RESET_LIMIT 1 93 93 + #define IPI_RESET_LIMIT 1 132 94 /* after this # consecutive successes, bump up the throttle if it was lowered */ 133 133 - #define COMPLETE_THRESHOLD 5 95 95 + #define COMPLETE_THRESHOLD 5 134 96 135 135 - #define UV_LB_SUBNODEID 0x10 97 97 + #define UV_LB_SUBNODEID 0x10 98 98 + 99 99 + /* these two are the same for UV1 and UV2: */ 100 100 + #define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 101 101 + #define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 102 102 + /* 4 bits of software ack period */ 103 103 + #define UV2_ACK_MASK 0x7UL 104 104 + #define UV2_ACK_UNITS_SHFT 3 105 105 + #define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 106 106 + #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 136 107 137 108 /* 138 109 * number of entries in the destination side payload queue ··· 162 115 /* 163 116 * tuning the action when the numalink network is extremely delayed 164 117 */ 165 165 - #define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in microseconds */ 166 166 - #define CONGESTED_REPS 10 /* long delays averaged over this many broadcasts */ 167 167 - #define CONGESTED_PERIOD 30 /* time for the bau to be disabled, in seconds */ 118 118 + #define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in 119 119 + microseconds */ 120 120 + #define CONGESTED_REPS 10 /* long delays averaged over 121 121 + this many broadcasts */ 122 122 + #define CONGESTED_PERIOD 30 /* time for the bau to be 123 123 + disabled, in seconds */ 124 124 + /* see msg_type: */ 125 125 + #define MSG_NOOP 0 126 126 + #define MSG_REGULAR 1 127 127 + #define MSG_RETRY 2 168 128 169 129 /* 170 130 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor) ··· 183 129 * 'base_dest_nasid' field of the header corresponds to the 184 130 * destination nodeID associated with that specified bit. 185 131 */ 186 186 - struct bau_target_uvhubmask { 187 187 - unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)]; 132 132 + struct bau_targ_hubmask { 133 133 + unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)]; 188 134 }; 189 135 190 136 /* ··· 193 139 * enough bits for max. cpu's per uvhub) 194 140 */ 195 141 struct bau_local_cpumask { 196 196 - unsigned long bits; 142 142 + unsigned long bits; 197 143 }; 198 144 199 145 /* ··· 214 160 * The payload is software-defined for INTD transactions 215 161 */ 216 162 struct bau_msg_payload { 217 217 - unsigned long address; /* signifies a page or all TLB's 218 218 - of the cpu */ 163 163 + unsigned long address; /* signifies a page or all 164 164 + TLB's of the cpu */ 219 165 /* 64 bits */ 220 220 - unsigned short sending_cpu; /* filled in by sender */ 166 166 + unsigned short sending_cpu; /* filled in by sender */ 221 167 /* 16 bits */ 222 222 - unsigned short acknowledge_count;/* filled in by destination */ 168 168 + unsigned short acknowledge_count; /* filled in by destination */ 223 169 /* 16 bits */ 224 224 - unsigned int reserved1:32; /* not usable */ 170 170 + unsigned int reserved1:32; /* not usable */ 225 171 }; 226 172 227 173 ··· 230 176 * see table 4.2.3.0.1 in broacast_assist spec. 231 177 */ 232 178 struct bau_msg_header { 233 233 - unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */ 179 179 + unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */ 234 180 /* bits 5:0 */ 235 235 - unsigned int base_dest_nasid:15; /* nasid of the */ 236 236 - /* bits 20:6 */ /* first bit in uvhub map */ 237 237 - unsigned int command:8; /* message type */ 181 181 + unsigned int base_dest_nasid:15; /* nasid of the first bit */ 182 182 + /* bits 20:6 */ /* in uvhub map */ 183 183 + unsigned int command:8; /* message type */ 238 184 /* bits 28:21 */ 239 239 - /* 0x38: SN3net EndPoint Message */ 240 240 - unsigned int rsvd_1:3; /* must be zero */ 185 185 + /* 0x38: SN3net EndPoint Message */ 186 186 + unsigned int rsvd_1:3; /* must be zero */ 241 187 /* bits 31:29 */ 242 242 - /* int will align on 32 bits */ 243 243 - unsigned int rsvd_2:9; /* must be zero */ 188 188 + /* int will align on 32 bits */ 189 189 + unsigned int rsvd_2:9; /* must be zero */ 244 190 /* bits 40:32 */ 245 245 - /* Suppl_A is 56-41 */ 246 246 - unsigned int sequence:16;/* message sequence number */ 247 247 - /* bits 56:41 */ /* becomes bytes 16-17 of msg */ 248 248 - /* Address field (96:57) is never used as an 249 249 - address (these are address bits 42:3) */ 191 191 + /* Suppl_A is 56-41 */ 192 192 + unsigned int sequence:16; /* message sequence number */ 193 193 + /* bits 56:41 */ /* becomes bytes 16-17 of msg */ 194 194 + /* Address field (96:57) is 195 195 + never used as an address 196 196 + (these are address bits 197 197 + 42:3) */ 250 198 251 251 - unsigned int rsvd_3:1; /* must be zero */ 199 199 + unsigned int rsvd_3:1; /* must be zero */ 252 200 /* bit 57 */ 253 253 - /* address bits 27:4 are payload */ 201 201 + /* address bits 27:4 are payload */ 254 202 /* these next 24 (58-81) bits become bytes 12-14 of msg */ 255 255 - 256 203 /* bits 65:58 land in byte 12 */ 257 257 - unsigned int replied_to:1;/* sent as 0 by the source to byte 12 */ 204 204 + unsigned int replied_to:1; /* sent as 0 by the source to 205 205 + byte 12 */ 258 206 /* bit 58 */ 259 259 - unsigned int msg_type:3; /* software type of the message*/ 207 207 + unsigned int msg_type:3; /* software type of the 208 208 + message */ 260 209 /* bits 61:59 */ 261 261 - unsigned int canceled:1; /* message canceled, resource to be freed*/ 210 210 + unsigned int canceled:1; /* message canceled, resource 211 211 + is to be freed*/ 262 212 /* bit 62 */ 263 263 - unsigned int payload_1a:1;/* not currently used */ 213 213 + unsigned int payload_1a:1; /* not currently used */ 264 214 /* bit 63 */ 265 265 - unsigned int payload_1b:2;/* not currently used */ 215 215 + unsigned int payload_1b:2; /* not currently used */ 266 216 /* bits 65:64 */ 267 217 268 218 /* bits 73:66 land in byte 13 */ 269 269 - unsigned int payload_1ca:6;/* not currently used */ 219 219 + unsigned int payload_1ca:6; /* not currently used */ 270 220 /* bits 71:66 */ 271 271 - unsigned int payload_1c:2;/* not currently used */ 221 221 + unsigned int payload_1c:2; /* not currently used */ 272 222 /* bits 73:72 */ 273 223 274 224 /* bits 81:74 land in byte 14 */ 275 275 - unsigned int payload_1d:6;/* not currently used */ 225 225 + unsigned int payload_1d:6; /* not currently used */ 276 226 /* bits 79:74 */ 277 277 - unsigned int payload_1e:2;/* not currently used */ 227 227 + unsigned int payload_1e:2; /* not currently used */ 278 228 /* bits 81:80 */ 279 229 280 280 - unsigned int rsvd_4:7; /* must be zero */ 230 230 + unsigned int rsvd_4:7; /* must be zero */ 281 231 /* bits 88:82 */ 282 282 - unsigned int sw_ack_flag:1;/* software acknowledge flag */ 232 232 + unsigned int swack_flag:1; /* software acknowledge flag */ 283 233 /* bit 89 */ 284 284 - /* INTD trasactions at destination are to 285 285 - wait for software acknowledge */ 286 286 - unsigned int rsvd_5:6; /* must be zero */ 234 234 + /* INTD trasactions at 235 235 + destination are to wait for 236 236 + software acknowledge */ 237 237 + unsigned int rsvd_5:6; /* must be zero */ 287 238 /* bits 95:90 */ 288 288 - unsigned int rsvd_6:5; /* must be zero */ 239 239 + unsigned int rsvd_6:5; /* must be zero */ 289 240 /* bits 100:96 */ 290 290 - unsigned int int_both:1;/* if 1, interrupt both sockets on the uvhub */ 241 241 + unsigned int int_both:1; /* if 1, interrupt both sockets 242 242 + on the uvhub */ 291 243 /* bit 101*/ 292 292 - unsigned int fairness:3;/* usually zero */ 244 244 + unsigned int fairness:3; /* usually zero */ 293 245 /* bits 104:102 */ 294 294 - unsigned int multilevel:1; /* multi-level multicast format */ 246 246 + unsigned int multilevel:1; /* multi-level multicast 247 247 + format */ 295 248 /* bit 105 */ 296 296 - /* 0 for TLB: endpoint multi-unicast messages */ 297 297 - unsigned int chaining:1;/* next descriptor is part of this activation*/ 249 249 + /* 0 for TLB: endpoint multi-unicast messages */ 250 250 + unsigned int chaining:1; /* next descriptor is part of 251 251 + this activation*/ 298 252 /* bit 106 */ 299 299 - unsigned int rsvd_7:21; /* must be zero */ 253 253 + unsigned int rsvd_7:21; /* must be zero */ 300 254 /* bits 127:107 */ 301 255 }; 302 302 - 303 303 - /* see msg_type: */ 304 304 - #define MSG_NOOP 0 305 305 - #define MSG_REGULAR 1 306 306 - #define MSG_RETRY 2 307 256 308 257 /* 309 258 * The activation descriptor: ··· 314 257 * Should be 64 bytes 315 258 */ 316 259 struct bau_desc { 317 317 - struct bau_target_uvhubmask distribution; 260 260 + struct bau_targ_hubmask distribution; 318 261 /* 319 262 * message template, consisting of header and payload: 320 263 */ 321 321 - struct bau_msg_header header; 322 322 - struct bau_msg_payload payload; 264 264 + struct bau_msg_header header; 265 265 + struct bau_msg_payload payload; 323 266 }; 324 267 /* 325 268 * -payload-- ---------header------ ··· 338 281 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17 339 282 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120) 340 283 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from 341 341 - * sw_ack_vector and payload_2) 284 284 + * swack_vec and payload_2) 342 285 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software 343 286 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload 344 287 * operation." 345 288 */ 346 346 - struct bau_payload_queue_entry { 347 347 - unsigned long address; /* signifies a page or all TLB's 348 348 - of the cpu */ 289 289 + struct bau_pq_entry { 290 290 + unsigned long address; /* signifies a page or all TLB's 291 291 + of the cpu */ 349 292 /* 64 bits, bytes 0-7 */ 350 350 - 351 351 - unsigned short sending_cpu; /* cpu that sent the message */ 293 293 + unsigned short sending_cpu; /* cpu that sent the message */ 352 294 /* 16 bits, bytes 8-9 */ 353 353 - 354 354 - unsigned short acknowledge_count; /* filled in by destination */ 295 295 + unsigned short acknowledge_count; /* filled in by destination */ 355 296 /* 16 bits, bytes 10-11 */ 356 356 - 357 297 /* these next 3 bytes come from bits 58-81 of the message header */ 358 358 - unsigned short replied_to:1; /* sent as 0 by the source */ 359 359 - unsigned short msg_type:3; /* software message type */ 360 360 - unsigned short canceled:1; /* sent as 0 by the source */ 361 361 - unsigned short unused1:3; /* not currently using */ 298 298 + unsigned short replied_to:1; /* sent as 0 by the source */ 299 299 + unsigned short msg_type:3; /* software message type */ 300 300 + unsigned short canceled:1; /* sent as 0 by the source */ 301 301 + unsigned short unused1:3; /* not currently using */ 362 302 /* byte 12 */ 363 363 - 364 364 - unsigned char unused2a; /* not currently using */ 303 303 + unsigned char unused2a; /* not currently using */ 365 304 /* byte 13 */ 366 366 - unsigned char unused2; /* not currently using */ 305 305 + unsigned char unused2; /* not currently using */ 367 306 /* byte 14 */ 368 368 - 369 369 - unsigned char sw_ack_vector; /* filled in by the hardware */ 307 307 + unsigned char swack_vec; /* filled in by the hardware */ 370 308 /* byte 15 (bits 127:120) */ 371 371 - 372 372 - unsigned short sequence; /* message sequence number */ 309 309 + unsigned short sequence; /* message sequence number */ 373 310 /* bytes 16-17 */ 374 374 - unsigned char unused4[2]; /* not currently using bytes 18-19 */ 311 311 + unsigned char unused4[2]; /* not currently using bytes 18-19 */ 375 312 /* bytes 18-19 */ 376 376 - 377 377 - int number_of_cpus; /* filled in at destination */ 313 313 + int number_of_cpus; /* filled in at destination */ 378 314 /* 32 bits, bytes 20-23 (aligned) */ 379 379 - 380 380 - unsigned char unused5[8]; /* not using */ 315 315 + unsigned char unused5[8]; /* not using */ 381 316 /* bytes 24-31 */ 382 317 }; 383 318 384 319 struct msg_desc { 385 385 - struct bau_payload_queue_entry *msg; 386 386 - int msg_slot; 387 387 - int sw_ack_slot; 388 388 - struct bau_payload_queue_entry *va_queue_first; 389 389 - struct bau_payload_queue_entry *va_queue_last; 320 320 + struct bau_pq_entry *msg; 321 321 + int msg_slot; 322 322 + int swack_slot; 323 323 + struct bau_pq_entry *queue_first; 324 324 + struct bau_pq_entry *queue_last; 390 325 }; 391 326 392 327 struct reset_args { 393 393 - int sender; 328 328 + int sender; 394 329 }; 395 330 396 331 /* ··· 390 341 */ 391 342 struct ptc_stats { 392 343 /* sender statistics */ 393 393 - unsigned long s_giveup; /* number of fall backs to IPI-style flushes */ 394 394 - unsigned long s_requestor; /* number of shootdown requests */ 395 395 - unsigned long s_stimeout; /* source side timeouts */ 396 396 - unsigned long s_dtimeout; /* destination side timeouts */ 397 397 - unsigned long s_time; /* time spent in sending side */ 398 398 - unsigned long s_retriesok; /* successful retries */ 399 399 - unsigned long s_ntargcpu; /* total number of cpu's targeted */ 400 400 - unsigned long s_ntargself; /* times the sending cpu was targeted */ 401 401 - unsigned long s_ntarglocals; /* targets of cpus on the local blade */ 402 402 - unsigned long s_ntargremotes; /* targets of cpus on remote blades */ 403 403 - unsigned long s_ntarglocaluvhub; /* targets of the local hub */ 404 404 - unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */ 405 405 - unsigned long s_ntarguvhub; /* total number of uvhubs targeted */ 406 406 - unsigned long s_ntarguvhub16; /* number of times target hubs >= 16*/ 407 407 - unsigned long s_ntarguvhub8; /* number of times target hubs >= 8 */ 408 408 - unsigned long s_ntarguvhub4; /* number of times target hubs >= 4 */ 409 409 - unsigned long s_ntarguvhub2; /* number of times target hubs >= 2 */ 410 410 - unsigned long s_ntarguvhub1; /* number of times target hubs == 1 */ 411 411 - unsigned long s_resets_plug; /* ipi-style resets from plug state */ 412 412 - unsigned long s_resets_timeout; /* ipi-style resets from timeouts */ 413 413 - unsigned long s_busy; /* status stayed busy past s/w timer */ 414 414 - unsigned long s_throttles; /* waits in throttle */ 415 415 - unsigned long s_retry_messages; /* retry broadcasts */ 416 416 - unsigned long s_bau_reenabled; /* for bau enable/disable */ 417 417 - unsigned long s_bau_disabled; /* for bau enable/disable */ 344 344 + unsigned long s_giveup; /* number of fall backs to 345 345 + IPI-style flushes */ 346 346 + unsigned long s_requestor; /* number of shootdown 347 347 + requests */ 348 348 + unsigned long s_stimeout; /* source side timeouts */ 349 349 + unsigned long s_dtimeout; /* destination side timeouts */ 350 350 + unsigned long s_time; /* time spent in sending side */ 351 351 + unsigned long s_retriesok; /* successful retries */ 352 352 + unsigned long s_ntargcpu; /* total number of cpu's 353 353 + targeted */ 354 354 + unsigned long s_ntargself; /* times the sending cpu was 355 355 + targeted */ 356 356 + unsigned long s_ntarglocals; /* targets of cpus on the local 357 357 + blade */ 358 358 + unsigned long s_ntargremotes; /* targets of cpus on remote 359 359 + blades */ 360 360 + unsigned long s_ntarglocaluvhub; /* targets of the local hub */ 361 361 + unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */ 362 362 + unsigned long s_ntarguvhub; /* total number of uvhubs 363 363 + targeted */ 364 364 + unsigned long s_ntarguvhub16; /* number of times target 365 365 + hubs >= 16*/ 366 366 + unsigned long s_ntarguvhub8; /* number of times target 367 367 + hubs >= 8 */ 368 368 + unsigned long s_ntarguvhub4; /* number of times target 369 369 + hubs >= 4 */ 370 370 + unsigned long s_ntarguvhub2; /* number of times target 371 371 + hubs >= 2 */ 372 372 + unsigned long s_ntarguvhub1; /* number of times target 373 373 + hubs == 1 */ 374 374 + unsigned long s_resets_plug; /* ipi-style resets from plug 375 375 + state */ 376 376 + unsigned long s_resets_timeout; /* ipi-style resets from 377 377 + timeouts */ 378 378 + unsigned long s_busy; /* status stayed busy past 379 379 + s/w timer */ 380 380 + unsigned long s_throttles; /* waits in throttle */ 381 381 + unsigned long s_retry_messages; /* retry broadcasts */ 382 382 + unsigned long s_bau_reenabled; /* for bau enable/disable */ 383 383 + unsigned long s_bau_disabled; /* for bau enable/disable */ 418 384 /* destination statistics */ 419 419 - unsigned long d_alltlb; /* times all tlb's on this cpu were flushed */ 420 420 - unsigned long d_onetlb; /* times just one tlb on this cpu was flushed */ 421 421 - unsigned long d_multmsg; /* interrupts with multiple messages */ 422 422 - unsigned long d_nomsg; /* interrupts with no message */ 423 423 - unsigned long d_time; /* time spent on destination side */ 424 424 - unsigned long d_requestee; /* number of messages processed */ 425 425 - unsigned long d_retries; /* number of retry messages processed */ 426 426 - unsigned long d_canceled; /* number of messages canceled by retries */ 427 427 - unsigned long d_nocanceled; /* retries that found nothing to cancel */ 428 428 - unsigned long d_resets; /* number of ipi-style requests processed */ 429 429 - unsigned long d_rcanceled; /* number of messages canceled by resets */ 385 385 + unsigned long d_alltlb; /* times all tlb's on this 386 386 + cpu were flushed */ 387 387 + unsigned long d_onetlb; /* times just one tlb on this 388 388 + cpu was flushed */ 389 389 + unsigned long d_multmsg; /* interrupts with multiple 390 390 + messages */ 391 391 + unsigned long d_nomsg; /* interrupts with no message */ 392 392 + unsigned long d_time; /* time spent on destination 393 393 + side */ 394 394 + unsigned long d_requestee; /* number of messages 395 395 + processed */ 396 396 + unsigned long d_retries; /* number of retry messages 397 397 + processed */ 398 398 + unsigned long d_canceled; /* number of messages canceled 399 399 + by retries */ 400 400 + unsigned long d_nocanceled; /* retries that found nothing 401 401 + to cancel */ 402 402 + unsigned long d_resets; /* number of ipi-style requests 403 403 + processed */ 404 404 + unsigned long d_rcanceled; /* number of messages canceled 405 405 + by resets */ 406 406 + }; 407 407 + 408 408 + struct tunables { 409 409 + int *tunp; 410 410 + int deflt; 430 411 }; 431 412 432 413 struct hub_and_pnode { 433 433 - short uvhub; 434 434 - short pnode; 414 414 + short uvhub; 415 415 + short pnode; 435 416 }; 417 417 + 418 418 + struct socket_desc { 419 419 + short num_cpus; 420 420 + short cpu_number[MAX_CPUS_PER_SOCKET]; 421 421 + }; 422 422 + 423 423 + struct uvhub_desc { 424 424 + unsigned short socket_mask; 425 425 + short num_cpus; 426 426 + short uvhub; 427 427 + short pnode; 428 428 + struct socket_desc socket[2]; 429 429 + }; 430 430 + 436 431 /* 437 432 * one per-cpu; to locate the software tables 438 433 */ 439 434 struct bau_control { 440 440 - struct bau_desc *descriptor_base; 441 441 - struct bau_payload_queue_entry *va_queue_first; 442 442 - struct bau_payload_queue_entry *va_queue_last; 443 443 - struct bau_payload_queue_entry *bau_msg_head; 444 444 - struct bau_control *uvhub_master; 445 445 - struct bau_control *socket_master; 446 446 - struct ptc_stats *statp; 447 447 - unsigned long timeout_interval; 448 448 - unsigned long set_bau_on_time; 449 449 - atomic_t active_descriptor_count; 450 450 - int plugged_tries; 451 451 - int timeout_tries; 452 452 - int ipi_attempts; 453 453 - int conseccompletes; 454 454 - int baudisabled; 455 455 - int set_bau_off; 456 456 - short cpu; 457 457 - short osnode; 458 458 - short uvhub_cpu; 459 459 - short uvhub; 460 460 - short cpus_in_socket; 461 461 - short cpus_in_uvhub; 462 462 - short partition_base_pnode; 463 463 - unsigned short message_number; 464 464 - unsigned short uvhub_quiesce; 465 465 - short socket_acknowledge_count[DEST_Q_SIZE]; 466 466 - cycles_t send_message; 467 467 - spinlock_t uvhub_lock; 468 468 - spinlock_t queue_lock; 435 435 + struct bau_desc *descriptor_base; 436 436 + struct bau_pq_entry *queue_first; 437 437 + struct bau_pq_entry *queue_last; 438 438 + struct bau_pq_entry *bau_msg_head; 439 439 + struct bau_control *uvhub_master; 440 440 + struct bau_control *socket_master; 441 441 + struct ptc_stats *statp; 442 442 + unsigned long timeout_interval; 443 443 + unsigned long set_bau_on_time; 444 444 + atomic_t active_descriptor_count; 445 445 + int plugged_tries; 446 446 + int timeout_tries; 447 447 + int ipi_attempts; 448 448 + int conseccompletes; 449 449 + int baudisabled; 450 450 + int set_bau_off; 451 451 + short cpu; 452 452 + short osnode; 453 453 + short uvhub_cpu; 454 454 + short uvhub; 455 455 + short cpus_in_socket; 456 456 + short cpus_in_uvhub; 457 457 + short partition_base_pnode; 458 458 + unsigned short message_number; 459 459 + unsigned short uvhub_quiesce; 460 460 + short socket_acknowledge_count[DEST_Q_SIZE]; 461 461 + cycles_t send_message; 462 462 + spinlock_t uvhub_lock; 463 463 + spinlock_t queue_lock; 469 464 /* tunables */ 470 470 - int max_bau_concurrent; 471 471 - int max_bau_concurrent_constant; 472 472 - int plugged_delay; 473 473 - int plugsb4reset; 474 474 - int timeoutsb4reset; 475 475 - int ipi_reset_limit; 476 476 - int complete_threshold; 477 477 - int congested_response_us; 478 478 - int congested_reps; 479 479 - int congested_period; 480 480 - cycles_t period_time; 481 481 - long period_requests; 482 482 - struct hub_and_pnode *target_hub_and_pnode; 465 465 + int max_concurr; 466 466 + int max_concurr_const; 467 467 + int plugged_delay; 468 468 + int plugsb4reset; 469 469 + int timeoutsb4reset; 470 470 + int ipi_reset_limit; 471 471 + int complete_threshold; 472 472 + int cong_response_us; 473 473 + int cong_reps; 474 474 + int cong_period; 475 475 + cycles_t period_time; 476 476 + long period_requests; 477 477 + struct hub_and_pnode *thp; 483 478 }; 484 479 485 485 - static inline int bau_uvhub_isset(int uvhub, struct bau_target_uvhubmask *dstp) 480 480 + static unsigned long read_mmr_uv2_status(void) 481 481 + { 482 482 + return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2); 483 483 + } 484 484 + 485 485 + static void write_mmr_data_broadcast(int pnode, unsigned long mmr_image) 486 486 + { 487 487 + write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image); 488 488 + } 489 489 + 490 490 + static void write_mmr_descriptor_base(int pnode, unsigned long mmr_image) 491 491 + { 492 492 + write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image); 493 493 + } 494 494 + 495 495 + static void write_mmr_activation(unsigned long index) 496 496 + { 497 497 + write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); 498 498 + } 499 499 + 500 500 + static void write_gmmr_activation(int pnode, unsigned long mmr_image) 501 501 + { 502 502 + write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image); 503 503 + } 504 504 + 505 505 + static void write_mmr_payload_first(int pnode, unsigned long mmr_image) 506 506 + { 507 507 + write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image); 508 508 + } 509 509 + 510 510 + static void write_mmr_payload_tail(int pnode, unsigned long mmr_image) 511 511 + { 512 512 + write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image); 513 513 + } 514 514 + 515 515 + static void write_mmr_payload_last(int pnode, unsigned long mmr_image) 516 516 + { 517 517 + write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image); 518 518 + } 519 519 + 520 520 + static void write_mmr_misc_control(int pnode, unsigned long mmr_image) 521 521 + { 522 522 + write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 523 523 + } 524 524 + 525 525 + static unsigned long read_mmr_misc_control(int pnode) 526 526 + { 527 527 + return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL); 528 528 + } 529 529 + 530 530 + static void write_mmr_sw_ack(unsigned long mr) 531 531 + { 532 532 + uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr); 533 533 + } 534 534 + 535 535 + static unsigned long read_mmr_sw_ack(void) 536 536 + { 537 537 + return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 538 538 + } 539 539 + 540 540 + static unsigned long read_gmmr_sw_ack(int pnode) 541 541 + { 542 542 + return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 543 543 + } 544 544 + 545 545 + static void write_mmr_data_config(int pnode, unsigned long mr) 546 546 + { 547 547 + uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr); 548 548 + } 549 549 + 550 550 + static inline int bau_uvhub_isset(int uvhub, struct bau_targ_hubmask *dstp) 486 551 { 487 552 return constant_test_bit(uvhub, &dstp->bits[0]); 488 553 } 489 489 - static inline void bau_uvhub_set(int pnode, struct bau_target_uvhubmask *dstp) 554 554 + static inline void bau_uvhub_set(int pnode, struct bau_targ_hubmask *dstp) 490 555 { 491 556 __set_bit(pnode, &dstp->bits[0]); 492 557 } 493 493 - static inline void bau_uvhubs_clear(struct bau_target_uvhubmask *dstp, 558 558 + static inline void bau_uvhubs_clear(struct bau_targ_hubmask *dstp, 494 559 int nbits) 495 560 { 496 561 bitmap_zero(&dstp->bits[0], nbits); 497 562 } 498 498 - static inline int bau_uvhub_weight(struct bau_target_uvhubmask *dstp) 563 563 + static inline int bau_uvhub_weight(struct bau_targ_hubmask *dstp) 499 564 { 500 565 return bitmap_weight((unsigned long *)&dstp->bits[0], 501 566 UV_DISTRIBUTION_SIZE); ··· 620 457 bitmap_zero(&dstp->bits, nbits); 621 458 } 622 459 623 623 - #define cpubit_isset(cpu, bau_local_cpumask) \ 624 624 - test_bit((cpu), (bau_local_cpumask).bits) 625 625 - 626 460 extern void uv_bau_message_intr1(void); 627 461 extern void uv_bau_timeout_intr1(void); 628 462 ··· 627 467 short counter; 628 468 }; 629 469 630 630 - /** 470 470 + /* 631 471 * atomic_read_short - read a short atomic variable 632 472 * @v: pointer of type atomic_short 633 473 * ··· 638 478 return v->counter; 639 479 } 640 480 641 641 - /** 642 642 - * atomic_add_short_return - add and return a short int 481 481 + /* 482 482 + * atom_asr - add and return a short int 643 483 * @i: short value to add 644 484 * @v: pointer of type atomic_short 645 485 * 646 486 * Atomically adds @i to @v and returns @i + @v 647 487 */ 648 648 - static inline int atomic_add_short_return(short i, struct atomic_short *v) 488 488 + static inline int atom_asr(short i, struct atomic_short *v) 649 489 { 650 490 short __i = i; 651 491 asm volatile(LOCK_PREFIX "xaddw %0, %1" 652 492 : "+r" (i), "+m" (v->counter) 653 493 : : "memory"); 654 494 return i + __i; 495 495 + } 496 496 + 497 497 + /* 498 498 + * conditionally add 1 to *v, unless *v is >= u 499 499 + * return 0 if we cannot add 1 to *v because it is >= u 500 500 + * return 1 if we can add 1 to *v because it is < u 501 501 + * the add is atomic 502 502 + * 503 503 + * This is close to atomic_add_unless(), but this allows the 'u' value 504 504 + * to be lowered below the current 'v'. atomic_add_unless can only stop 505 505 + * on equal. 506 506 + */ 507 507 + static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u) 508 508 + { 509 509 + spin_lock(lock); 510 510 + if (atomic_read(v) >= u) { 511 511 + spin_unlock(lock); 512 512 + return 0; 513 513 + } 514 514 + atomic_inc(v); 515 515 + spin_unlock(lock); 516 516 + return 1; 655 517 } 656 518 657 519 #endif /* _ASM_X86_UV_UV_BAU_H */

+58 -13

arch/x86/include/asm/uv/uv_hub.h

reviewed

··· 77 77 * 78 78 * 1111110000000000 79 79 * 5432109876543210 80 80 - * pppppppppplc0cch Nehalem-EX 81 81 - * ppppppppplcc0cch Westmere-EX 80 80 + * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 81 81 + * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 82 82 + * pppppppppppcccch SandyBridge (15 bits in hdw reg) 82 83 * sssssssssss 83 84 * 84 85 * p = pnode bits ··· 88 87 * h = hyperthread 89 88 * s = bits that are in the SOCKET_ID CSR 90 89 * 91 91 - * Note: Processor only supports 12 bits in the APICID register. The ACPI 90 90 + * Note: Processor may support fewer bits in the APICID register. The ACPI 92 91 * tables hold all 16 bits. Software needs to be aware of this. 93 92 * 94 93 * Unless otherwise specified, all references to APICID refer to ··· 139 138 unsigned long global_mmr_base; 140 139 unsigned long gpa_mask; 141 140 unsigned int gnode_extra; 141 141 + unsigned char hub_revision; 142 142 + unsigned char apic_pnode_shift; 142 143 unsigned long gnode_upper; 143 144 unsigned long lowmem_remap_top; 144 145 unsigned long lowmem_remap_base; ··· 152 149 unsigned char m_val; 153 150 unsigned char n_val; 154 151 struct uv_scir_s scir; 155 155 - unsigned char apic_pnode_shift; 156 152 }; 157 153 158 154 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 159 155 #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) 160 156 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 157 157 + 158 158 + /* 159 159 + * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2 160 160 + * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE. 161 161 + * This is a software convention - NOT the hardware revision numbers in 162 162 + * the hub chip. 163 163 + */ 164 164 + #define UV1_HUB_REVISION_BASE 1 165 165 + #define UV2_HUB_REVISION_BASE 3 166 166 + 167 167 + static inline int is_uv1_hub(void) 168 168 + { 169 169 + return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; 170 170 + } 171 171 + 172 172 + static inline int is_uv2_hub(void) 173 173 + { 174 174 + return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE; 175 175 + } 161 176 162 177 union uvh_apicid { 163 178 unsigned long v; ··· 201 180 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 202 181 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 203 182 204 204 - #define UV_LOCAL_MMR_BASE 0xf4000000UL 205 205 - #define UV_GLOBAL_MMR32_BASE 0xf8000000UL 183 183 + #define UV1_LOCAL_MMR_BASE 0xf4000000UL 184 184 + #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL 185 185 + #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 186 186 + #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 187 187 + 188 188 + #define UV2_LOCAL_MMR_BASE 0xfa000000UL 189 189 + #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 190 190 + #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 191 191 + #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 192 192 + 193 193 + #define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE \ 194 194 + : UV2_LOCAL_MMR_BASE) 195 195 + #define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE \ 196 196 + : UV2_GLOBAL_MMR32_BASE) 197 197 + #define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 198 198 + UV2_LOCAL_MMR_SIZE) 199 199 + #define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\ 200 200 + UV2_GLOBAL_MMR32_SIZE) 206 201 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 207 207 - #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 208 208 - #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 209 202 210 203 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 211 204 ··· 333 298 static inline int uv_apicid_to_pnode(int apicid) 334 299 { 335 300 return (apicid >> uv_hub_info->apic_pnode_shift); 301 301 + } 302 302 + 303 303 + /* 304 304 + * Convert an apicid to the socket number on the blade 305 305 + */ 306 306 + static inline int uv_apicid_to_socket(int apicid) 307 307 + { 308 308 + if (is_uv1_hub()) 309 309 + return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; 310 310 + else 311 311 + return 0; 336 312 } 337 313 338 314 /* ··· 565 519 566 520 /* 567 521 * Get the minimum revision number of the hub chips within the partition. 568 568 - * 1 - initial rev 1.0 silicon 569 569 - * 2 - rev 2.0 production silicon 522 522 + * 1 - UV1 rev 1.0 initial silicon 523 523 + * 2 - UV1 rev 2.0 production silicon 524 524 + * 3 - UV2 rev 1.0 initial silicon 570 525 */ 571 526 static inline int uv_get_min_hub_revision_id(void) 572 527 { 573 573 - extern int uv_min_hub_revision_id; 574 574 - 575 575 - return uv_min_hub_revision_id; 528 528 + return uv_hub_info->hub_revision; 576 529 } 577 530 578 531 #endif /* CONFIG_X86_64 */

+821 -189

arch/x86/include/asm/uv/uv_mmrs.h

reviewed

··· 11 11 #ifndef _ASM_X86_UV_UV_MMRS_H 12 12 #define _ASM_X86_UV_UV_MMRS_H 13 13 14 14 + /* 15 15 + * This file contains MMR definitions for both UV1 & UV2 hubs. 16 16 + * 17 17 + * In general, MMR addresses and structures are identical on both hubs. 18 18 + * These MMRs are identified as: 19 19 + * #define UVH_xxx <address> 20 20 + * union uvh_xxx { 21 21 + * unsigned long v; 22 22 + * struct uvh_int_cmpd_s { 23 23 + * } s; 24 24 + * }; 25 25 + * 26 26 + * If the MMR exists on both hub type but has different addresses or 27 27 + * contents, the MMR definition is similar to: 28 28 + * #define UV1H_xxx <uv1 address> 29 29 + * #define UV2H_xxx <uv2address> 30 30 + * #define UVH_xxx (is_uv1_hub() ? UV1H_xxx : UV2H_xxx) 31 31 + * union uvh_xxx { 32 32 + * unsigned long v; 33 33 + * struct uv1h_int_cmpd_s { (Common fields only) 34 34 + * } s; 35 35 + * struct uv1h_int_cmpd_s { (Full UV1 definition) 36 36 + * } s1; 37 37 + * struct uv2h_int_cmpd_s { (Full UV2 definition) 38 38 + * } s2; 39 39 + * }; 40 40 + * 41 41 + * Only essential difference are enumerated. For example, if the address is 42 42 + * the same for both UV1 & UV2, only a single #define is generated. Likewise, 43 43 + * if the contents is the same for both hubs, only the "s" structure is 44 44 + * generated. 45 45 + * 46 46 + * If the MMR exists on ONLY 1 type of hub, no generic definition is 47 47 + * generated: 48 48 + * #define UVnH_xxx <uvn address> 49 49 + * union uvnh_xxx { 50 50 + * unsigned long v; 51 51 + * struct uvh_int_cmpd_s { 52 52 + * } sn; 53 53 + * }; 54 54 + */ 55 55 + 14 56 #define UV_MMR_ENABLE (1UL << 63) 57 57 + 58 58 + #define UV1_HUB_PART_NUMBER 0x88a5 59 59 + #define UV2_HUB_PART_NUMBER 0x8eb8 60 60 + 61 61 + /* Compat: if this #define is present, UV headers support UV2 */ 62 62 + #define UV2_HUB_IS_SUPPORTED 1 63 63 + 64 64 + /* KABI compat: if this #define is present, KABI hacks are present */ 65 65 + #define UV2_HUB_KABI_HACKS 1 15 66 16 67 /* ========================================================================= */ 17 68 /* UVH_BAU_DATA_BROADCAST */ 18 69 /* ========================================================================= */ 19 70 #define UVH_BAU_DATA_BROADCAST 0x61688UL 20 20 - #define UVH_BAU_DATA_BROADCAST_32 0x0440 71 71 + #define UVH_BAU_DATA_BROADCAST_32 0x440 21 72 22 73 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 23 74 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL ··· 85 34 /* UVH_BAU_DATA_CONFIG */ 86 35 /* ========================================================================= */ 87 36 #define UVH_BAU_DATA_CONFIG 0x61680UL 88 88 - #define UVH_BAU_DATA_CONFIG_32 0x0438 37 37 + #define UVH_BAU_DATA_CONFIG_32 0x438 89 38 90 39 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 91 40 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL ··· 124 73 /* UVH_EVENT_OCCURRED0 */ 125 74 /* ========================================================================= */ 126 75 #define UVH_EVENT_OCCURRED0 0x70000UL 127 127 - #define UVH_EVENT_OCCURRED0_32 0x005e8 76 76 + #define UVH_EVENT_OCCURRED0_32 0x5e8 128 77 129 129 - #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 130 130 - #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 131 131 - #define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 132 132 - #define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 133 133 - #define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 134 134 - #define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 135 135 - #define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3 136 136 - #define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 137 137 - #define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4 138 138 - #define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL 139 139 - #define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5 140 140 - #define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL 141 141 - #define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6 142 142 - #define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL 143 143 - #define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 144 144 - #define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL 145 145 - #define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 146 146 - #define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 147 147 - #define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 148 148 - #define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 149 149 - #define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 150 150 - #define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 151 151 - #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 152 152 - #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 153 153 - #define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 154 154 - #define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 155 155 - #define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 156 156 - #define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 157 157 - #define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 158 158 - #define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 159 159 - #define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 160 160 - #define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL 161 161 - #define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 162 162 - #define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL 163 163 - #define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 164 164 - #define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL 165 165 - #define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 166 166 - #define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL 167 167 - #define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 168 168 - #define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL 169 169 - #define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 170 170 - #define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL 171 171 - #define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 172 172 - #define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL 173 173 - #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 174 174 - #define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 175 175 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 176 176 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL 177 177 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 178 178 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL 179 179 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 180 180 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL 181 181 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 182 182 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL 183 183 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 184 184 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL 185 185 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 186 186 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL 187 187 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 188 188 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL 189 189 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 190 190 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL 191 191 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 192 192 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL 193 193 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 194 194 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL 195 195 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 196 196 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL 197 197 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 198 198 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL 199 199 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 200 200 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL 201 201 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 202 202 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL 203 203 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 204 204 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL 205 205 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 206 206 - #define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL 207 207 - #define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 208 208 - #define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL 209 209 - #define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 210 210 - #define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL 211 211 - #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 212 212 - #define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL 213 213 - #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 214 214 - #define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL 215 215 - #define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43 216 216 - #define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL 217 217 - #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 218 218 - #define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 219 219 - #define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45 220 220 - #define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL 221 221 - #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 222 222 - #define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL 223 223 - #define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 224 224 - #define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL 225 225 - #define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 226 226 - #define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL 227 227 - #define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 228 228 - #define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL 229 229 - #define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 230 230 - #define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL 231 231 - #define UVH_EVENT_OCCURRED0_RTC0_SHFT 51 232 232 - #define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL 233 233 - #define UVH_EVENT_OCCURRED0_RTC1_SHFT 52 234 234 - #define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL 235 235 - #define UVH_EVENT_OCCURRED0_RTC2_SHFT 53 236 236 - #define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL 237 237 - #define UVH_EVENT_OCCURRED0_RTC3_SHFT 54 238 238 - #define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL 239 239 - #define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55 240 240 - #define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 241 241 - #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 242 242 - #define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 78 78 + #define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 79 79 + #define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 80 80 + #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 81 81 + #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 82 82 + #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 83 83 + #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 84 84 + #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3 85 85 + #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 86 86 + #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4 87 87 + #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL 88 88 + #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5 89 89 + #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL 90 90 + #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6 91 91 + #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL 92 92 + #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 93 93 + #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL 94 94 + #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 95 95 + #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 96 96 + #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 97 97 + #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 98 98 + #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 99 99 + #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 100 100 + #define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 101 101 + #define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 102 102 + #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 103 103 + #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 104 104 + #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 105 105 + #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 106 106 + #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 107 107 + #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 108 108 + #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 109 109 + #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL 110 110 + #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 111 111 + #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL 112 112 + #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 113 113 + #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL 114 114 + #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 115 115 + #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL 116 116 + #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 117 117 + #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL 118 118 + #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 119 119 + #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL 120 120 + #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 121 121 + #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL 122 122 + #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 123 123 + #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 124 124 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 125 125 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL 126 126 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 127 127 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL 128 128 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 129 129 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL 130 130 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 131 131 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL 132 132 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 133 133 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL 134 134 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 135 135 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL 136 136 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 137 137 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL 138 138 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 139 139 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL 140 140 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 141 141 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL 142 142 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 143 143 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL 144 144 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 145 145 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL 146 146 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 147 147 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL 148 148 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 149 149 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL 150 150 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 151 151 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL 152 152 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 153 153 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL 154 154 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 155 155 + #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL 156 156 + #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 157 157 + #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL 158 158 + #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 159 159 + #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL 160 160 + #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 161 161 + #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL 162 162 + #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 163 163 + #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL 164 164 + #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43 165 165 + #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL 166 166 + #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 167 167 + #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 168 168 + #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45 169 169 + #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL 170 170 + #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 171 171 + #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL 172 172 + #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 173 173 + #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL 174 174 + #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 175 175 + #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL 176 176 + #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 177 177 + #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL 178 178 + #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 179 179 + #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL 180 180 + #define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51 181 181 + #define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL 182 182 + #define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52 183 183 + #define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL 184 184 + #define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53 185 185 + #define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL 186 186 + #define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54 187 187 + #define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL 188 188 + #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55 189 189 + #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 190 190 + #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 191 191 + #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 192 192 + 193 193 + #define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 194 194 + #define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 195 195 + #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 196 196 + #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 197 197 + #define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2 198 198 + #define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 199 199 + #define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 200 200 + #define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 201 201 + #define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 202 202 + #define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL 203 203 + #define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 204 204 + #define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL 205 205 + #define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 206 206 + #define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL 207 207 + #define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 208 208 + #define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL 209 209 + #define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 210 210 + #define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 211 211 + #define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 212 212 + #define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 213 213 + #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 214 214 + #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 215 215 + #define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 216 216 + #define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 217 217 + #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 218 218 + #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 219 219 + #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 220 220 + #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 221 221 + #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 222 222 + #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 223 223 + #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 224 224 + #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL 225 225 + #define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 226 226 + #define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL 227 227 + #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 228 228 + #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 229 229 + #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 230 230 + #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 231 231 + #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 232 232 + #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 233 233 + #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 234 234 + #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 235 235 + #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 236 236 + #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 237 237 + #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 238 238 + #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 239 239 + #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 240 240 + #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 241 241 + #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 242 242 + #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 243 243 + #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 244 244 + #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 245 245 + #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 246 246 + #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 247 247 + #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 248 248 + #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 249 249 + #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 250 250 + #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 251 251 + #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 252 252 + #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 253 253 + #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 254 254 + #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 255 255 + #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 256 256 + #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 257 257 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 258 258 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 259 259 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 260 260 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 261 261 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 262 262 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 263 263 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 264 264 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 265 265 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 266 266 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 267 267 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 268 268 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 269 269 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 270 270 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 271 271 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 272 272 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 273 273 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 274 274 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 275 275 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 276 276 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 277 277 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 278 278 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 279 279 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 280 280 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 281 281 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 282 282 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 283 283 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 284 284 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 285 285 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 286 286 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 287 287 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 288 288 + #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 289 289 + #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 290 290 + #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 291 291 + #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 292 292 + #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 293 293 + #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 294 294 + #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 295 295 + #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 296 296 + #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 297 297 + #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 298 298 + #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 299 299 + #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53 300 300 + #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 301 301 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 302 302 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 303 303 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 304 304 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 305 305 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 306 306 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 307 307 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 308 308 + #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 309 309 + #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 310 310 + #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 311 311 + 243 312 union uvh_event_occurred0_u { 244 313 unsigned long v; 245 245 - struct uvh_event_occurred0_s { 314 314 + struct uv1h_event_occurred0_s { 246 315 unsigned long lb_hcerr : 1; /* RW, W1C */ 247 316 unsigned long gr0_hcerr : 1; /* RW, W1C */ 248 317 unsigned long gr1_hcerr : 1; /* RW, W1C */ ··· 421 250 unsigned long bau_data : 1; /* RW, W1C */ 422 251 unsigned long power_management_req : 1; /* RW, W1C */ 423 252 unsigned long rsvd_57_63 : 7; /* */ 424 424 - } s; 253 253 + } s1; 254 254 + struct uv2h_event_occurred0_s { 255 255 + unsigned long lb_hcerr : 1; /* RW */ 256 256 + unsigned long qp_hcerr : 1; /* RW */ 257 257 + unsigned long rh_hcerr : 1; /* RW */ 258 258 + unsigned long lh0_hcerr : 1; /* RW */ 259 259 + unsigned long lh1_hcerr : 1; /* RW */ 260 260 + unsigned long gr0_hcerr : 1; /* RW */ 261 261 + unsigned long gr1_hcerr : 1; /* RW */ 262 262 + unsigned long ni0_hcerr : 1; /* RW */ 263 263 + unsigned long ni1_hcerr : 1; /* RW */ 264 264 + unsigned long lb_aoerr0 : 1; /* RW */ 265 265 + unsigned long qp_aoerr0 : 1; /* RW */ 266 266 + unsigned long rh_aoerr0 : 1; /* RW */ 267 267 + unsigned long lh0_aoerr0 : 1; /* RW */ 268 268 + unsigned long lh1_aoerr0 : 1; /* RW */ 269 269 + unsigned long gr0_aoerr0 : 1; /* RW */ 270 270 + unsigned long gr1_aoerr0 : 1; /* RW */ 271 271 + unsigned long xb_aoerr0 : 1; /* RW */ 272 272 + unsigned long rt_aoerr0 : 1; /* RW */ 273 273 + unsigned long ni0_aoerr0 : 1; /* RW */ 274 274 + unsigned long ni1_aoerr0 : 1; /* RW */ 275 275 + unsigned long lb_aoerr1 : 1; /* RW */ 276 276 + unsigned long qp_aoerr1 : 1; /* RW */ 277 277 + unsigned long rh_aoerr1 : 1; /* RW */ 278 278 + unsigned long lh0_aoerr1 : 1; /* RW */ 279 279 + unsigned long lh1_aoerr1 : 1; /* RW */ 280 280 + unsigned long gr0_aoerr1 : 1; /* RW */ 281 281 + unsigned long gr1_aoerr1 : 1; /* RW */ 282 282 + unsigned long xb_aoerr1 : 1; /* RW */ 283 283 + unsigned long rt_aoerr1 : 1; /* RW */ 284 284 + unsigned long ni0_aoerr1 : 1; /* RW */ 285 285 + unsigned long ni1_aoerr1 : 1; /* RW */ 286 286 + unsigned long system_shutdown_int : 1; /* RW */ 287 287 + unsigned long lb_irq_int_0 : 1; /* RW */ 288 288 + unsigned long lb_irq_int_1 : 1; /* RW */ 289 289 + unsigned long lb_irq_int_2 : 1; /* RW */ 290 290 + unsigned long lb_irq_int_3 : 1; /* RW */ 291 291 + unsigned long lb_irq_int_4 : 1; /* RW */ 292 292 + unsigned long lb_irq_int_5 : 1; /* RW */ 293 293 + unsigned long lb_irq_int_6 : 1; /* RW */ 294 294 + unsigned long lb_irq_int_7 : 1; /* RW */ 295 295 + unsigned long lb_irq_int_8 : 1; /* RW */ 296 296 + unsigned long lb_irq_int_9 : 1; /* RW */ 297 297 + unsigned long lb_irq_int_10 : 1; /* RW */ 298 298 + unsigned long lb_irq_int_11 : 1; /* RW */ 299 299 + unsigned long lb_irq_int_12 : 1; /* RW */ 300 300 + unsigned long lb_irq_int_13 : 1; /* RW */ 301 301 + unsigned long lb_irq_int_14 : 1; /* RW */ 302 302 + unsigned long lb_irq_int_15 : 1; /* RW */ 303 303 + unsigned long l1_nmi_int : 1; /* RW */ 304 304 + unsigned long stop_clock : 1; /* RW */ 305 305 + unsigned long asic_to_l1 : 1; /* RW */ 306 306 + unsigned long l1_to_asic : 1; /* RW */ 307 307 + unsigned long la_seq_trigger : 1; /* RW */ 308 308 + unsigned long ipi_int : 1; /* RW */ 309 309 + unsigned long extio_int0 : 1; /* RW */ 310 310 + unsigned long extio_int1 : 1; /* RW */ 311 311 + unsigned long extio_int2 : 1; /* RW */ 312 312 + unsigned long extio_int3 : 1; /* RW */ 313 313 + unsigned long profile_int : 1; /* RW */ 314 314 + unsigned long rsvd_59_63 : 5; /* */ 315 315 + } s2; 425 316 }; 426 317 427 318 /* ========================================================================= */ 428 319 /* UVH_EVENT_OCCURRED0_ALIAS */ 429 320 /* ========================================================================= */ 430 321 #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL 431 431 - #define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0 322 322 + #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 432 323 433 324 /* ========================================================================= */ 434 325 /* UVH_GR0_TLB_INT0_CONFIG */ ··· 665 432 /* ========================================================================= */ 666 433 #define UVH_INT_CMPC 0x22100UL 667 434 668 668 - #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 669 669 - #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL 435 435 + #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 436 436 + #define UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 437 437 + #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT (is_uv1_hub() ? \ 438 438 + UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT : \ 439 439 + UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT) 440 440 + #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL 441 441 + #define UV2H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL 442 442 + #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK (is_uv1_hub() ? \ 443 443 + UV1H_INT_CMPC_REAL_TIME_CMPC_MASK : \ 444 444 + UV2H_INT_CMPC_REAL_TIME_CMPC_MASK) 670 445 671 446 union uvh_int_cmpc_u { 672 447 unsigned long v; ··· 689 448 /* ========================================================================= */ 690 449 #define UVH_INT_CMPD 0x22180UL 691 450 692 692 - #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 693 693 - #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL 451 451 + #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 452 452 + #define UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 453 453 + #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT (is_uv1_hub() ? \ 454 454 + UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT : \ 455 455 + UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT) 456 456 + #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL 457 457 + #define UV2H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL 458 458 + #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK (is_uv1_hub() ? \ 459 459 + UV1H_INT_CMPD_REAL_TIME_CMPD_MASK : \ 460 460 + UV2H_INT_CMPD_REAL_TIME_CMPD_MASK) 694 461 695 462 union uvh_int_cmpd_u { 696 463 unsigned long v; ··· 712 463 /* UVH_IPI_INT */ 713 464 /* ========================================================================= */ 714 465 #define UVH_IPI_INT 0x60500UL 715 715 - #define UVH_IPI_INT_32 0x0348 466 466 + #define UVH_IPI_INT_32 0x348 716 467 717 468 #define UVH_IPI_INT_VECTOR_SHFT 0 718 469 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL ··· 742 493 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 743 494 /* ========================================================================= */ 744 495 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 745 745 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0 496 496 + #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 746 497 747 498 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 748 499 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL ··· 764 515 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 765 516 /* ========================================================================= */ 766 517 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 767 767 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8 518 518 + #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 768 519 769 520 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 770 521 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL ··· 782 533 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 783 534 /* ========================================================================= */ 784 535 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 785 785 - #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0 536 536 + #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 786 537 787 538 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 788 539 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL ··· 800 551 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 801 552 /* ========================================================================= */ 802 553 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 803 803 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68 554 554 + #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 804 555 805 556 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 806 557 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL ··· 834 585 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 835 586 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 836 587 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 588 588 + 837 589 union uvh_lb_bau_intd_software_acknowledge_u { 838 590 unsigned long v; 839 591 struct uvh_lb_bau_intd_software_acknowledge_s { ··· 862 612 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 863 613 /* ========================================================================= */ 864 614 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL 865 865 - #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70 615 615 + #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 866 616 867 617 /* ========================================================================= */ 868 618 /* UVH_LB_BAU_MISC_CONTROL */ 869 619 /* ========================================================================= */ 870 620 #define UVH_LB_BAU_MISC_CONTROL 0x320170UL 871 871 - #define UVH_LB_BAU_MISC_CONTROL_32 0x00a10 621 621 + #define UVH_LB_BAU_MISC_CONTROL_32 0xa10 872 622 873 623 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 874 624 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL ··· 878 628 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 879 629 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 880 630 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 881 881 - #define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_SHFT 11 882 882 - #define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 631 631 + #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 632 632 + #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 883 633 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 884 634 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 885 635 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 ··· 900 650 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 901 651 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 902 652 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 903 903 - #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 904 904 - #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 653 653 + 654 654 + #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 655 655 + #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 656 656 + #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 657 657 + #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 658 658 + #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 659 659 + #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 660 660 + #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 661 661 + #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 662 662 + #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 663 663 + #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 664 664 + #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 665 665 + #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 666 666 + #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 667 667 + #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 668 668 + #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 669 669 + #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 670 670 + #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 671 671 + #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 672 672 + #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 673 673 + #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 674 674 + #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 675 675 + #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 676 676 + #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 677 677 + #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 678 678 + #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 679 679 + #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 680 680 + #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 681 681 + #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 682 682 + #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 683 683 + #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 684 684 + #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 685 685 + #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 686 686 + 687 687 + #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 688 688 + #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 689 689 + #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 690 690 + #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 691 691 + #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 692 692 + #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 693 693 + #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 694 694 + #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 695 695 + #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 696 696 + #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 697 697 + #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 698 698 + #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 699 699 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 700 700 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 701 701 + #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 702 702 + #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 703 703 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 704 704 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 705 705 + #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 706 706 + #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 707 707 + #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 708 708 + #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 709 709 + #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 710 710 + #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 711 711 + #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 712 712 + #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 713 713 + #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 714 714 + #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 715 715 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 716 716 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 717 717 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 718 718 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 719 719 + #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 720 720 + #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 721 721 + #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 722 722 + #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 723 723 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 724 724 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 725 725 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 726 726 + #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 727 727 + #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 728 728 + #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 729 729 + #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 730 730 + #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 731 731 + #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 732 732 + #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 905 733 906 734 union uvh_lb_bau_misc_control_u { 907 735 unsigned long v; ··· 988 660 unsigned long apic_mode : 1; /* RW */ 989 661 unsigned long force_broadcast : 1; /* RW */ 990 662 unsigned long force_lock_nop : 1; /* RW */ 991 991 - unsigned long csi_agent_presence_vector : 3; /* RW */ 663 663 + unsigned long qpi_agent_presence_vector : 3; /* RW */ 664 664 + unsigned long descriptor_fetch_mode : 1; /* RW */ 665 665 + unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 666 666 + unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 667 667 + unsigned long enable_dual_mapping_mode : 1; /* RW */ 668 668 + unsigned long vga_io_port_decode_enable : 1; /* RW */ 669 669 + unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 670 670 + unsigned long suppress_dest_registration : 1; /* RW */ 671 671 + unsigned long programmed_initial_priority : 3; /* RW */ 672 672 + unsigned long use_incoming_priority : 1; /* RW */ 673 673 + unsigned long enable_programmed_initial_priority : 1; /* RW */ 674 674 + unsigned long rsvd_29_63 : 35; 675 675 + } s; 676 676 + struct uv1h_lb_bau_misc_control_s { 677 677 + unsigned long rejection_delay : 8; /* RW */ 678 678 + unsigned long apic_mode : 1; /* RW */ 679 679 + unsigned long force_broadcast : 1; /* RW */ 680 680 + unsigned long force_lock_nop : 1; /* RW */ 681 681 + unsigned long qpi_agent_presence_vector : 3; /* RW */ 992 682 unsigned long descriptor_fetch_mode : 1; /* RW */ 993 683 unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 994 684 unsigned long intd_soft_ack_timeout_period : 4; /* RW */ ··· 1019 673 unsigned long enable_programmed_initial_priority : 1; /* RW */ 1020 674 unsigned long rsvd_29_47 : 19; /* */ 1021 675 unsigned long fun : 16; /* RW */ 1022 1022 - } s; 676 676 + } s1; 677 677 + struct uv2h_lb_bau_misc_control_s { 678 678 + unsigned long rejection_delay : 8; /* RW */ 679 679 + unsigned long apic_mode : 1; /* RW */ 680 680 + unsigned long force_broadcast : 1; /* RW */ 681 681 + unsigned long force_lock_nop : 1; /* RW */ 682 682 + unsigned long qpi_agent_presence_vector : 3; /* RW */ 683 683 + unsigned long descriptor_fetch_mode : 1; /* RW */ 684 684 + unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 685 685 + unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 686 686 + unsigned long enable_dual_mapping_mode : 1; /* RW */ 687 687 + unsigned long vga_io_port_decode_enable : 1; /* RW */ 688 688 + unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 689 689 + unsigned long suppress_dest_registration : 1; /* RW */ 690 690 + unsigned long programmed_initial_priority : 3; /* RW */ 691 691 + unsigned long use_incoming_priority : 1; /* RW */ 692 692 + unsigned long enable_programmed_initial_priority : 1; /* RW */ 693 693 + unsigned long enable_automatic_apic_mode_selection : 1; /* RW */ 694 694 + unsigned long apic_mode_status : 1; /* RO */ 695 695 + unsigned long suppress_interrupts_to_self : 1; /* RW */ 696 696 + unsigned long enable_lock_based_system_flush : 1; /* RW */ 697 697 + unsigned long enable_extended_sb_status : 1; /* RW */ 698 698 + unsigned long suppress_int_prio_udt_to_self : 1; /* RW */ 699 699 + unsigned long use_legacy_descriptor_formats : 1; /* RW */ 700 700 + unsigned long rsvd_36_47 : 12; /* */ 701 701 + unsigned long fun : 16; /* RW */ 702 702 + } s2; 1023 703 }; 1024 704 1025 705 /* ========================================================================= */ 1026 706 /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 1027 707 /* ========================================================================= */ 1028 708 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 1029 1029 - #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8 709 709 + #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 1030 710 1031 711 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 1032 712 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL ··· 1075 703 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 1076 704 /* ========================================================================= */ 1077 705 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 1078 1078 - #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0 706 706 + #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 1079 707 1080 708 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 1081 709 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL ··· 1091 719 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 1092 720 /* ========================================================================= */ 1093 721 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 1094 1094 - #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8 722 722 + #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 1095 723 1096 724 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 1097 725 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL ··· 1107 735 /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 1108 736 /* ========================================================================= */ 1109 737 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 1110 1110 - #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0 738 738 + #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 1111 739 1112 740 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 1113 741 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL ··· 1126 754 }; 1127 755 1128 756 /* ========================================================================= */ 1129 1129 - /* UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK */ 1130 1130 - /* ========================================================================= */ 1131 1131 - #define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL 1132 1132 - #define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x009f0 1133 1133 - 1134 1134 - #define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0 1135 1135 - #define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL 1136 1136 - 1137 1137 - union uvh_lb_target_physical_apic_id_mask_u { 1138 1138 - unsigned long v; 1139 1139 - struct uvh_lb_target_physical_apic_id_mask_s { 1140 1140 - unsigned long bit_enables : 32; /* RW */ 1141 1141 - unsigned long rsvd_32_63 : 32; /* */ 1142 1142 - } s; 1143 1143 - }; 1144 1144 - 1145 1145 - /* ========================================================================= */ 1146 757 /* UVH_NODE_ID */ 1147 758 /* ========================================================================= */ 1148 759 #define UVH_NODE_ID 0x0UL ··· 1140 785 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 1141 786 #define UVH_NODE_ID_NODE_ID_SHFT 32 1142 787 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 1143 1143 - #define UVH_NODE_ID_NODES_PER_BIT_SHFT 48 1144 1144 - #define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL 1145 1145 - #define UVH_NODE_ID_NI_PORT_SHFT 56 1146 1146 - #define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL 788 788 + 789 789 + #define UV1H_NODE_ID_FORCE1_SHFT 0 790 790 + #define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 791 791 + #define UV1H_NODE_ID_MANUFACTURER_SHFT 1 792 792 + #define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 793 793 + #define UV1H_NODE_ID_PART_NUMBER_SHFT 12 794 794 + #define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 795 795 + #define UV1H_NODE_ID_REVISION_SHFT 28 796 796 + #define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 797 797 + #define UV1H_NODE_ID_NODE_ID_SHFT 32 798 798 + #define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 799 799 + #define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48 800 800 + #define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL 801 801 + #define UV1H_NODE_ID_NI_PORT_SHFT 56 802 802 + #define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL 803 803 + 804 804 + #define UV2H_NODE_ID_FORCE1_SHFT 0 805 805 + #define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 806 806 + #define UV2H_NODE_ID_MANUFACTURER_SHFT 1 807 807 + #define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 808 808 + #define UV2H_NODE_ID_PART_NUMBER_SHFT 12 809 809 + #define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 810 810 + #define UV2H_NODE_ID_REVISION_SHFT 28 811 811 + #define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 812 812 + #define UV2H_NODE_ID_NODE_ID_SHFT 32 813 813 + #define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 814 814 + #define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50 815 815 + #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 816 816 + #define UV2H_NODE_ID_NI_PORT_SHFT 57 817 817 + #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 1147 818 1148 819 union uvh_node_id_u { 1149 820 unsigned long v; 1150 821 struct uvh_node_id_s { 822 822 + unsigned long force1 : 1; /* RO */ 823 823 + unsigned long manufacturer : 11; /* RO */ 824 824 + unsigned long part_number : 16; /* RO */ 825 825 + unsigned long revision : 4; /* RO */ 826 826 + unsigned long node_id : 15; /* RW */ 827 827 + unsigned long rsvd_47_63 : 17; 828 828 + } s; 829 829 + struct uv1h_node_id_s { 1151 830 unsigned long force1 : 1; /* RO */ 1152 831 unsigned long manufacturer : 11; /* RO */ 1153 832 unsigned long part_number : 16; /* RO */ ··· 1192 803 unsigned long rsvd_55 : 1; /* */ 1193 804 unsigned long ni_port : 4; /* RO */ 1194 805 unsigned long rsvd_60_63 : 4; /* */ 1195 1195 - } s; 806 806 + } s1; 807 807 + struct uv2h_node_id_s { 808 808 + unsigned long force1 : 1; /* RO */ 809 809 + unsigned long manufacturer : 11; /* RO */ 810 810 + unsigned long part_number : 16; /* RO */ 811 811 + unsigned long revision : 4; /* RO */ 812 812 + unsigned long node_id : 15; /* RW */ 813 813 + unsigned long rsvd_47_49 : 3; /* */ 814 814 + unsigned long nodes_per_bit : 7; /* RO */ 815 815 + unsigned long ni_port : 5; /* RO */ 816 816 + unsigned long rsvd_62_63 : 2; /* */ 817 817 + } s2; 1196 818 }; 1197 819 1198 820 /* ========================================================================= */ ··· 1354 954 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 1355 955 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 1356 956 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 1357 1357 - #define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 1358 1358 - #define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 957 957 + 958 958 + #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 959 959 + #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 960 960 + #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 961 961 + #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 962 962 + #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 963 963 + #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 964 964 + 965 965 + #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 966 966 + #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 967 967 + #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 968 968 + #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 1359 969 1360 970 union uvh_rh_gam_config_mmr_u { 1361 971 unsigned long v; 1362 972 struct uvh_rh_gam_config_mmr_s { 1363 973 unsigned long m_skt : 6; /* RW */ 1364 974 unsigned long n_skt : 4; /* RW */ 975 975 + unsigned long rsvd_10_63 : 54; 976 976 + } s; 977 977 + struct uv1h_rh_gam_config_mmr_s { 978 978 + unsigned long m_skt : 6; /* RW */ 979 979 + unsigned long n_skt : 4; /* RW */ 1365 980 unsigned long rsvd_10_11: 2; /* */ 1366 981 unsigned long mmiol_cfg : 1; /* RW */ 1367 982 unsigned long rsvd_13_63: 51; /* */ 1368 1368 - } s; 983 983 + } s1; 984 984 + struct uv2h_rh_gam_config_mmr_s { 985 985 + unsigned long m_skt : 6; /* RW */ 986 986 + unsigned long n_skt : 4; /* RW */ 987 987 + unsigned long rsvd_10_63: 54; /* */ 988 988 + } s2; 1369 989 }; 1370 990 1371 991 /* ========================================================================= */ ··· 1395 975 1396 976 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 1397 977 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 1398 1398 - #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 1399 1399 - #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL 1400 1400 - #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 1401 1401 - #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 1402 1402 - #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1403 1403 - #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 978 978 + 979 979 + #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 980 980 + #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 981 981 + #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 982 982 + #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL 983 983 + #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 984 984 + #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 985 985 + #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 986 986 + #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 987 987 + 988 988 + #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 989 989 + #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 990 990 + #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 991 991 + #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 992 992 + #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 993 993 + #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1404 994 1405 995 union uvh_rh_gam_gru_overlay_config_mmr_u { 1406 996 unsigned long v; 1407 997 struct uvh_rh_gam_gru_overlay_config_mmr_s { 998 998 + unsigned long rsvd_0_27: 28; /* */ 999 999 + unsigned long base : 18; /* RW */ 1000 1000 + unsigned long rsvd_46_62 : 17; 1001 1001 + unsigned long enable : 1; /* RW */ 1002 1002 + } s; 1003 1003 + struct uv1h_rh_gam_gru_overlay_config_mmr_s { 1408 1004 unsigned long rsvd_0_27: 28; /* */ 1409 1005 unsigned long base : 18; /* RW */ 1410 1006 unsigned long rsvd_46_47: 2; /* */ ··· 1429 993 unsigned long n_gru : 4; /* RW */ 1430 994 unsigned long rsvd_56_62: 7; /* */ 1431 995 unsigned long enable : 1; /* RW */ 1432 1432 - } s; 996 996 + } s1; 997 997 + struct uv2h_rh_gam_gru_overlay_config_mmr_s { 998 998 + unsigned long rsvd_0_27: 28; /* */ 999 999 + unsigned long base : 18; /* RW */ 1000 1000 + unsigned long rsvd_46_51: 6; /* */ 1001 1001 + unsigned long n_gru : 4; /* RW */ 1002 1002 + unsigned long rsvd_56_62: 7; /* */ 1003 1003 + unsigned long enable : 1; /* RW */ 1004 1004 + } s2; 1433 1005 }; 1434 1006 1435 1007 /* ========================================================================= */ ··· 1445 1001 /* ========================================================================= */ 1446 1002 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 1447 1003 1448 1448 - #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 1449 1449 - #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL 1450 1450 - #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 1451 1451 - #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 1452 1452 - #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 1453 1453 - #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 1454 1454 - #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1455 1455 - #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1004 1004 + #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 1005 1005 + #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL 1006 1006 + #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 1007 1007 + #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 1008 1008 + #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 1009 1009 + #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 1010 1010 + #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1011 1011 + #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1012 1012 + 1013 1013 + #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 1014 1014 + #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL 1015 1015 + #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 1016 1016 + #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 1017 1017 + #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 1018 1018 + #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 1019 1019 + #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1020 1020 + #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1456 1021 1457 1022 union uvh_rh_gam_mmioh_overlay_config_mmr_u { 1458 1023 unsigned long v; 1459 1459 - struct uvh_rh_gam_mmioh_overlay_config_mmr_s { 1024 1024 + struct uv1h_rh_gam_mmioh_overlay_config_mmr_s { 1460 1025 unsigned long rsvd_0_29: 30; /* */ 1461 1026 unsigned long base : 16; /* RW */ 1462 1027 unsigned long m_io : 6; /* RW */ 1463 1028 unsigned long n_io : 4; /* RW */ 1464 1029 unsigned long rsvd_56_62: 7; /* */ 1465 1030 unsigned long enable : 1; /* RW */ 1466 1466 - } s; 1031 1031 + } s1; 1032 1032 + struct uv2h_rh_gam_mmioh_overlay_config_mmr_s { 1033 1033 + unsigned long rsvd_0_26: 27; /* */ 1034 1034 + unsigned long base : 19; /* RW */ 1035 1035 + unsigned long m_io : 6; /* RW */ 1036 1036 + unsigned long n_io : 4; /* RW */ 1037 1037 + unsigned long rsvd_56_62: 7; /* */ 1038 1038 + unsigned long enable : 1; /* RW */ 1039 1039 + } s2; 1467 1040 }; 1468 1041 1469 1042 /* ========================================================================= */ ··· 1490 1029 1491 1030 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1492 1031 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 1493 1493 - #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 1494 1494 - #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL 1495 1495 - #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1496 1496 - #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1032 1032 + 1033 1033 + #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1034 1034 + #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 1035 1035 + #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 1036 1036 + #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL 1037 1037 + #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1038 1038 + #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1039 1039 + 1040 1040 + #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1041 1041 + #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 1042 1042 + #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1043 1043 + #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1497 1044 1498 1045 union uvh_rh_gam_mmr_overlay_config_mmr_u { 1499 1046 unsigned long v; 1500 1047 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 1501 1048 unsigned long rsvd_0_25: 26; /* */ 1502 1049 unsigned long base : 20; /* RW */ 1050 1050 + unsigned long rsvd_46_62 : 17; 1051 1051 + unsigned long enable : 1; /* RW */ 1052 1052 + } s; 1053 1053 + struct uv1h_rh_gam_mmr_overlay_config_mmr_s { 1054 1054 + unsigned long rsvd_0_25: 26; /* */ 1055 1055 + unsigned long base : 20; /* RW */ 1503 1056 unsigned long dual_hub : 1; /* RW */ 1504 1057 unsigned long rsvd_47_62: 16; /* */ 1505 1058 unsigned long enable : 1; /* RW */ 1506 1506 - } s; 1059 1059 + } s1; 1060 1060 + struct uv2h_rh_gam_mmr_overlay_config_mmr_s { 1061 1061 + unsigned long rsvd_0_25: 26; /* */ 1062 1062 + unsigned long base : 20; /* RW */ 1063 1063 + unsigned long rsvd_46_62: 17; /* */ 1064 1064 + unsigned long enable : 1; /* RW */ 1065 1065 + } s2; 1507 1066 }; 1508 1067 1509 1068 /* ========================================================================= */ ··· 1584 1103 /* UVH_SCRATCH5 */ 1585 1104 /* ========================================================================= */ 1586 1105 #define UVH_SCRATCH5 0x2d0200UL 1587 1587 - #define UVH_SCRATCH5_32 0x00778 1106 1106 + #define UVH_SCRATCH5_32 0x778 1588 1107 1589 1108 #define UVH_SCRATCH5_SCRATCH5_SHFT 0 1590 1109 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 1110 1110 + 1591 1111 union uvh_scratch5_u { 1592 1112 unsigned long v; 1593 1113 struct uvh_scratch5_s { 1594 1114 unsigned long scratch5 : 64; /* RW, W1CS */ 1595 1115 } s; 1596 1116 }; 1117 1117 + 1118 1118 + /* ========================================================================= */ 1119 1119 + /* UV2H_EVENT_OCCURRED2 */ 1120 1120 + /* ========================================================================= */ 1121 1121 + #define UV2H_EVENT_OCCURRED2 0x70100UL 1122 1122 + #define UV2H_EVENT_OCCURRED2_32 0xb68 1123 1123 + 1124 1124 + #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 1125 1125 + #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 1126 1126 + #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 1127 1127 + #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 1128 1128 + #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2 1129 1129 + #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 1130 1130 + #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3 1131 1131 + #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 1132 1132 + #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4 1133 1133 + #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 1134 1134 + #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5 1135 1135 + #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 1136 1136 + #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6 1137 1137 + #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 1138 1138 + #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7 1139 1139 + #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 1140 1140 + #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8 1141 1141 + #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 1142 1142 + #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9 1143 1143 + #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 1144 1144 + #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10 1145 1145 + #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 1146 1146 + #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11 1147 1147 + #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 1148 1148 + #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12 1149 1149 + #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 1150 1150 + #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13 1151 1151 + #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 1152 1152 + #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14 1153 1153 + #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 1154 1154 + #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15 1155 1155 + #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 1156 1156 + #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16 1157 1157 + #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 1158 1158 + #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17 1159 1159 + #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 1160 1160 + #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18 1161 1161 + #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 1162 1162 + #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19 1163 1163 + #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 1164 1164 + #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20 1165 1165 + #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 1166 1166 + #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21 1167 1167 + #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 1168 1168 + #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22 1169 1169 + #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 1170 1170 + #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23 1171 1171 + #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 1172 1172 + #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24 1173 1173 + #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 1174 1174 + #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25 1175 1175 + #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 1176 1176 + #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26 1177 1177 + #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 1178 1178 + #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27 1179 1179 + #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 1180 1180 + #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28 1181 1181 + #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 1182 1182 + #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29 1183 1183 + #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 1184 1184 + #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30 1185 1185 + #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 1186 1186 + #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31 1187 1187 + #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 1188 1188 + 1189 1189 + union uv2h_event_occurred2_u { 1190 1190 + unsigned long v; 1191 1191 + struct uv2h_event_occurred2_s { 1192 1192 + unsigned long rtc_0 : 1; /* RW */ 1193 1193 + unsigned long rtc_1 : 1; /* RW */ 1194 1194 + unsigned long rtc_2 : 1; /* RW */ 1195 1195 + unsigned long rtc_3 : 1; /* RW */ 1196 1196 + unsigned long rtc_4 : 1; /* RW */ 1197 1197 + unsigned long rtc_5 : 1; /* RW */ 1198 1198 + unsigned long rtc_6 : 1; /* RW */ 1199 1199 + unsigned long rtc_7 : 1; /* RW */ 1200 1200 + unsigned long rtc_8 : 1; /* RW */ 1201 1201 + unsigned long rtc_9 : 1; /* RW */ 1202 1202 + unsigned long rtc_10 : 1; /* RW */ 1203 1203 + unsigned long rtc_11 : 1; /* RW */ 1204 1204 + unsigned long rtc_12 : 1; /* RW */ 1205 1205 + unsigned long rtc_13 : 1; /* RW */ 1206 1206 + unsigned long rtc_14 : 1; /* RW */ 1207 1207 + unsigned long rtc_15 : 1; /* RW */ 1208 1208 + unsigned long rtc_16 : 1; /* RW */ 1209 1209 + unsigned long rtc_17 : 1; /* RW */ 1210 1210 + unsigned long rtc_18 : 1; /* RW */ 1211 1211 + unsigned long rtc_19 : 1; /* RW */ 1212 1212 + unsigned long rtc_20 : 1; /* RW */ 1213 1213 + unsigned long rtc_21 : 1; /* RW */ 1214 1214 + unsigned long rtc_22 : 1; /* RW */ 1215 1215 + unsigned long rtc_23 : 1; /* RW */ 1216 1216 + unsigned long rtc_24 : 1; /* RW */ 1217 1217 + unsigned long rtc_25 : 1; /* RW */ 1218 1218 + unsigned long rtc_26 : 1; /* RW */ 1219 1219 + unsigned long rtc_27 : 1; /* RW */ 1220 1220 + unsigned long rtc_28 : 1; /* RW */ 1221 1221 + unsigned long rtc_29 : 1; /* RW */ 1222 1222 + unsigned long rtc_30 : 1; /* RW */ 1223 1223 + unsigned long rtc_31 : 1; /* RW */ 1224 1224 + unsigned long rsvd_32_63: 32; /* */ 1225 1225 + } s1; 1226 1226 + }; 1227 1227 + 1228 1228 + /* ========================================================================= */ 1229 1229 + /* UV2H_EVENT_OCCURRED2_ALIAS */ 1230 1230 + /* ========================================================================= */ 1231 1231 + #define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL 1232 1232 + #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70 1233 1233 + 1234 1234 + /* ========================================================================= */ 1235 1235 + /* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */ 1236 1236 + /* ========================================================================= */ 1237 1237 + #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 1238 1238 + #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 1239 1239 + 1240 1240 + #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 1241 1241 + #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 1242 1242 + 1243 1243 + union uv2h_lb_bau_sb_activation_status_2_u { 1244 1244 + unsigned long v; 1245 1245 + struct uv2h_lb_bau_sb_activation_status_2_s { 1246 1246 + unsigned long aux_error : 64; /* RW */ 1247 1247 + } s1; 1248 1248 + }; 1249 1249 + 1250 1250 + /* ========================================================================= */ 1251 1251 + /* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */ 1252 1252 + /* ========================================================================= */ 1253 1253 + #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL 1254 1254 + #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0 1255 1255 + 1256 1256 + #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0 1257 1257 + #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL 1258 1258 + 1259 1259 + union uv1h_lb_target_physical_apic_id_mask_u { 1260 1260 + unsigned long v; 1261 1261 + struct uv1h_lb_target_physical_apic_id_mask_s { 1262 1262 + unsigned long bit_enables : 32; /* RW */ 1263 1263 + unsigned long rsvd_32_63 : 32; /* */ 1264 1264 + } s1; 1265 1265 + }; 1266 1266 + 1597 1267 1598 1268 #endif /* __ASM_UV_MMRS_X86_H__ */

+31 -9

arch/x86/kernel/apic/x2apic_uv_x.c

reviewed

··· 91 91 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); 92 92 uv_min_hub_revision_id = node_id.s.revision; 93 93 94 94 + if (node_id.s.part_number == UV2_HUB_PART_NUMBER) 95 95 + uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; 96 96 + 97 97 + uv_hub_info->hub_revision = uv_min_hub_revision_id; 94 98 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); 95 99 return pnode; 96 100 } ··· 116 112 */ 117 113 static void __init uv_set_apicid_hibit(void) 118 114 { 119 119 - union uvh_lb_target_physical_apic_id_mask_u apicid_mask; 115 115 + union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; 120 116 121 121 - apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK); 122 122 - uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK; 117 117 + if (is_uv1_hub()) { 118 118 + apicid_mask.v = 119 119 + uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); 120 120 + uv_apicid_hibits = 121 121 + apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; 122 122 + } 123 123 } 124 124 125 125 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 126 126 { 127 127 - int pnodeid; 127 127 + int pnodeid, is_uv1, is_uv2; 128 128 129 129 - if (!strcmp(oem_id, "SGI")) { 129 129 + is_uv1 = !strcmp(oem_id, "SGI"); 130 130 + is_uv2 = !strcmp(oem_id, "SGI2"); 131 131 + if (is_uv1 || is_uv2) { 132 132 + uv_hub_info->hub_revision = 133 133 + is_uv1 ? UV1_HUB_REVISION_BASE : UV2_HUB_REVISION_BASE; 130 134 pnodeid = early_get_pnodeid(); 131 135 early_get_apic_pnode_shift(); 132 136 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; ··· 496 484 static __init void map_mmioh_high(int max_pnode) 497 485 { 498 486 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 499 499 - int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 487 487 + int shift; 500 488 501 489 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); 502 502 - if (mmioh.s.enable) 503 503 - map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io, 490 490 + if (is_uv1_hub() && mmioh.s1.enable) { 491 491 + shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 492 492 + map_high("MMIOH", mmioh.s1.base, shift, mmioh.s1.m_io, 504 493 max_pnode, map_uc); 494 494 + } 495 495 + if (is_uv2_hub() && mmioh.s2.enable) { 496 496 + shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 497 497 + map_high("MMIOH", mmioh.s2.base, shift, mmioh.s2.m_io, 498 498 + max_pnode, map_uc); 499 499 + } 505 500 } 506 501 507 502 static __init void map_low_mmrs(void) ··· 755 736 unsigned long mmr_base, present, paddr; 756 737 unsigned short pnode_mask, pnode_io_mask; 757 738 739 739 + printk(KERN_INFO "UV: Found %s hub\n", is_uv1_hub() ? "UV1" : "UV2"); 758 740 map_low_mmrs(); 759 741 760 742 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); 761 743 m_val = m_n_config.s.m_skt; 762 744 n_val = m_n_config.s.n_skt; 763 745 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); 764 764 - n_io = mmioh.s.n_io; 746 746 + n_io = is_uv1_hub() ? mmioh.s1.n_io : mmioh.s2.n_io; 765 747 mmr_base = 766 748 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & 767 749 ~UV_MMR_ENABLE; ··· 831 811 */ 832 812 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; 833 813 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; 814 814 + uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision; 815 815 + 834 816 pnode = uv_apicid_to_pnode(apicid); 835 817 blade = boot_pnode_to_blade(pnode); 836 818 lcpu = uv_blade_info[blade].nr_possible_cpus;

+5 -2

arch/x86/kernel/cpu/amd.c

reviewed

··· 612 612 } 613 613 #endif 614 614 615 615 - /* As a rule processors have APIC timer running in deep C states */ 616 616 - if (c->x86 > 0xf && !cpu_has_amd_erratum(amd_erratum_400)) 615 615 + /* 616 616 + * Family 0x12 and above processors have APIC timer 617 617 + * running in deep C states. 618 618 + */ 619 619 + if (c->x86 > 0x11) 617 620 set_cpu_cap(c, X86_FEATURE_ARAT); 618 621 619 622 /*

-7

arch/x86/kernel/cpu/common.c

reviewed

··· 477 477 if (smp_num_siblings <= 1) 478 478 goto out; 479 479 480 480 - if (smp_num_siblings > nr_cpu_ids) { 481 481 - pr_warning("CPU: Unsupported number of siblings %d", 482 482 - smp_num_siblings); 483 483 - smp_num_siblings = 1; 484 484 - return; 485 485 - } 486 486 - 487 480 index_msb = get_count_order(smp_num_siblings); 488 481 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 489 482

+7

arch/x86/kernel/setup.c

reviewed

··· 910 910 memblock.current_limit = get_max_mapped(); 911 911 memblock_x86_fill(); 912 912 913 913 + /* 914 914 + * The EFI specification says that boot service code won't be called 915 915 + * after ExitBootServices(). This is, in fact, a lie. 916 916 + */ 917 917 + if (efi_enabled) 918 918 + efi_reserve_boot_services(); 919 919 + 913 920 /* preallocate 4k for mptable mpc */ 914 921 early_reserve_e820_mpc_new(); 915 922

+20 -15

arch/x86/mm/fault.c

reviewed

··· 823 823 force_sig_info_fault(SIGBUS, code, address, tsk, fault); 824 824 } 825 825 826 826 - static noinline void 826 826 + static noinline int 827 827 mm_fault_error(struct pt_regs *regs, unsigned long error_code, 828 828 unsigned long address, unsigned int fault) 829 829 { 830 830 + /* 831 831 + * Pagefault was interrupted by SIGKILL. We have no reason to 832 832 + * continue pagefault. 833 833 + */ 834 834 + if (fatal_signal_pending(current)) { 835 835 + if (!(fault & VM_FAULT_RETRY)) 836 836 + up_read(&current->mm->mmap_sem); 837 837 + if (!(error_code & PF_USER)) 838 838 + no_context(regs, error_code, address); 839 839 + return 1; 840 840 + } 841 841 + if (!(fault & VM_FAULT_ERROR)) 842 842 + return 0; 843 843 + 830 844 if (fault & VM_FAULT_OOM) { 831 845 /* Kernel mode? Handle exceptions or die: */ 832 846 if (!(error_code & PF_USER)) { 833 847 up_read(&current->mm->mmap_sem); 834 848 no_context(regs, error_code, address); 835 835 - return; 849 849 + return 1; 836 850 } 837 851 838 852 out_of_memory(regs, error_code, address); ··· 857 843 else 858 844 BUG(); 859 845 } 846 846 + return 1; 860 847 } 861 848 862 849 static int spurious_fault_check(unsigned long error_code, pte_t *pte) ··· 1148 1133 */ 1149 1134 fault = handle_mm_fault(mm, vma, address, flags); 1150 1135 1151 1151 - if (unlikely(fault & VM_FAULT_ERROR)) { 1152 1152 - mm_fault_error(regs, error_code, address, fault); 1153 1153 - return; 1154 1154 - } 1155 1155 - 1156 1156 - /* 1157 1157 - * Pagefault was interrupted by SIGKILL. We have no reason to 1158 1158 - * continue pagefault. 1159 1159 - */ 1160 1160 - if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) { 1161 1161 - if (!(error_code & PF_USER)) 1162 1162 - no_context(regs, error_code, address); 1163 1163 - return; 1136 1136 + if (unlikely(fault & (VM_FAULT_RETRY|VM_FAULT_ERROR))) { 1137 1137 + if (mm_fault_error(regs, error_code, address, fault)) 1138 1138 + return; 1164 1139 } 1165 1140 1166 1141 /*

+44 -1

arch/x86/platform/efi/efi.c

reviewed

··· 304 304 } 305 305 #endif /* EFI_DEBUG */ 306 306 307 307 + void __init efi_reserve_boot_services(void) 308 308 + { 309 309 + void *p; 310 310 + 311 311 + for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { 312 312 + efi_memory_desc_t *md = p; 313 313 + unsigned long long start = md->phys_addr; 314 314 + unsigned long long size = md->num_pages << EFI_PAGE_SHIFT; 315 315 + 316 316 + if (md->type != EFI_BOOT_SERVICES_CODE && 317 317 + md->type != EFI_BOOT_SERVICES_DATA) 318 318 + continue; 319 319 + 320 320 + memblock_x86_reserve_range(start, start + size, "EFI Boot"); 321 321 + } 322 322 + } 323 323 + 324 324 + static void __init efi_free_boot_services(void) 325 325 + { 326 326 + void *p; 327 327 + 328 328 + for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { 329 329 + efi_memory_desc_t *md = p; 330 330 + unsigned long long start = md->phys_addr; 331 331 + unsigned long long size = md->num_pages << EFI_PAGE_SHIFT; 332 332 + 333 333 + if (md->type != EFI_BOOT_SERVICES_CODE && 334 334 + md->type != EFI_BOOT_SERVICES_DATA) 335 335 + continue; 336 336 + 337 337 + free_bootmem_late(start, size); 338 338 + } 339 339 + } 340 340 + 307 341 void __init efi_init(void) 308 342 { 309 343 efi_config_table_t *config_tables; ··· 570 536 571 537 for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { 572 538 md = p; 573 573 - if (!(md->attribute & EFI_MEMORY_RUNTIME)) 539 539 + if (!(md->attribute & EFI_MEMORY_RUNTIME) && 540 540 + md->type != EFI_BOOT_SERVICES_CODE && 541 541 + md->type != EFI_BOOT_SERVICES_DATA) 574 542 continue; 575 543 576 544 size = md->num_pages << EFI_PAGE_SHIFT; ··· 627 591 "(status=%lx)!\n", status); 628 592 panic("EFI call to SetVirtualAddressMap() failed!"); 629 593 } 594 594 + 595 595 + /* 596 596 + * Thankfully, it does seem that no runtime services other than 597 597 + * SetVirtualAddressMap() will touch boot services code, so we can 598 598 + * get rid of it all at this point 599 599 + */ 600 600 + efi_free_boot_services(); 630 601 631 602 /* 632 603 * Now that EFI is in virtual mode, update the function

+3 -2

arch/x86/platform/efi/efi_64.c

reviewed

··· 49 49 if (!(__supported_pte_mask & _PAGE_NX)) 50 50 return; 51 51 52 52 - /* Make EFI runtime service code area executable */ 52 52 + /* Make EFI service code area executable */ 53 53 for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { 54 54 md = p; 55 55 - if (md->type == EFI_RUNTIME_SERVICES_CODE) 55 55 + if (md->type == EFI_RUNTIME_SERVICES_CODE || 56 56 + md->type == EFI_BOOT_SERVICES_CODE) 56 57 efi_set_executable(md, executable); 57 58 } 58 59 }

+825 -677

arch/x86/platform/uv/tlb_uv.c

reviewed

··· 1 1 /* 2 2 * SGI UltraViolet TLB flush routines. 3 3 * 4 4 - * (c) 2008-2010 Cliff Wickman <cpw@sgi.com>, SGI. 4 4 + * (c) 2008-2011 Cliff Wickman <cpw@sgi.com>, SGI. 5 5 * 6 6 * This code is released under the GNU General Public License version 2 or 7 7 * later. ··· 35 35 5242880, 36 36 167772160 37 37 }; 38 38 + 38 39 static int timeout_us; 39 40 static int nobau; 40 41 static int baudisabled; ··· 43 42 static cycles_t congested_cycles; 44 43 45 44 /* tunables: */ 46 46 - static int max_bau_concurrent = MAX_BAU_CONCURRENT; 47 47 - static int max_bau_concurrent_constant = MAX_BAU_CONCURRENT; 48 48 - static int plugged_delay = PLUGGED_DELAY; 49 49 - static int plugsb4reset = PLUGSB4RESET; 50 50 - static int timeoutsb4reset = TIMEOUTSB4RESET; 51 51 - static int ipi_reset_limit = IPI_RESET_LIMIT; 52 52 - static int complete_threshold = COMPLETE_THRESHOLD; 53 53 - static int congested_response_us = CONGESTED_RESPONSE_US; 54 54 - static int congested_reps = CONGESTED_REPS; 55 55 - static int congested_period = CONGESTED_PERIOD; 45 45 + static int max_concurr = MAX_BAU_CONCURRENT; 46 46 + static int max_concurr_const = MAX_BAU_CONCURRENT; 47 47 + static int plugged_delay = PLUGGED_DELAY; 48 48 + static int plugsb4reset = PLUGSB4RESET; 49 49 + static int timeoutsb4reset = TIMEOUTSB4RESET; 50 50 + static int ipi_reset_limit = IPI_RESET_LIMIT; 51 51 + static int complete_threshold = COMPLETE_THRESHOLD; 52 52 + static int congested_respns_us = CONGESTED_RESPONSE_US; 53 53 + static int congested_reps = CONGESTED_REPS; 54 54 + static int congested_period = CONGESTED_PERIOD; 55 55 + 56 56 + static struct tunables tunables[] = { 57 57 + {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */ 58 58 + {&plugged_delay, PLUGGED_DELAY}, 59 59 + {&plugsb4reset, PLUGSB4RESET}, 60 60 + {&timeoutsb4reset, TIMEOUTSB4RESET}, 61 61 + {&ipi_reset_limit, IPI_RESET_LIMIT}, 62 62 + {&complete_threshold, COMPLETE_THRESHOLD}, 63 63 + {&congested_respns_us, CONGESTED_RESPONSE_US}, 64 64 + {&congested_reps, CONGESTED_REPS}, 65 65 + {&congested_period, CONGESTED_PERIOD} 66 66 + }; 67 67 + 56 68 static struct dentry *tunables_dir; 57 69 static struct dentry *tunables_file; 58 70 59 59 - static int __init setup_nobau(char *arg) 71 71 + /* these correspond to the statistics printed by ptc_seq_show() */ 72 72 + static char *stat_description[] = { 73 73 + "sent: number of shootdown messages sent", 74 74 + "stime: time spent sending messages", 75 75 + "numuvhubs: number of hubs targeted with shootdown", 76 76 + "numuvhubs16: number times 16 or more hubs targeted", 77 77 + "numuvhubs8: number times 8 or more hubs targeted", 78 78 + "numuvhubs4: number times 4 or more hubs targeted", 79 79 + "numuvhubs2: number times 2 or more hubs targeted", 80 80 + "numuvhubs1: number times 1 hub targeted", 81 81 + "numcpus: number of cpus targeted with shootdown", 82 82 + "dto: number of destination timeouts", 83 83 + "retries: destination timeout retries sent", 84 84 + "rok: : destination timeouts successfully retried", 85 85 + "resetp: ipi-style resource resets for plugs", 86 86 + "resett: ipi-style resource resets for timeouts", 87 87 + "giveup: fall-backs to ipi-style shootdowns", 88 88 + "sto: number of source timeouts", 89 89 + "bz: number of stay-busy's", 90 90 + "throt: number times spun in throttle", 91 91 + "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE", 92 92 + "recv: shootdown messages received", 93 93 + "rtime: time spent processing messages", 94 94 + "all: shootdown all-tlb messages", 95 95 + "one: shootdown one-tlb messages", 96 96 + "mult: interrupts that found multiple messages", 97 97 + "none: interrupts that found no messages", 98 98 + "retry: number of retry messages processed", 99 99 + "canc: number messages canceled by retries", 100 100 + "nocan: number retries that found nothing to cancel", 101 101 + "reset: number of ipi-style reset requests processed", 102 102 + "rcan: number messages canceled by reset requests", 103 103 + "disable: number times use of the BAU was disabled", 104 104 + "enable: number times use of the BAU was re-enabled" 105 105 + }; 106 106 + 107 107 + static int __init 108 108 + setup_nobau(char *arg) 60 109 { 61 110 nobau = 1; 62 111 return 0; ··· 114 63 early_param("nobau", setup_nobau); 115 64 116 65 /* base pnode in this partition */ 117 117 - static int uv_partition_base_pnode __read_mostly; 66 66 + static int uv_base_pnode __read_mostly; 118 67 /* position of pnode (which is nasid>>1): */ 119 68 static int uv_nshift __read_mostly; 120 69 static unsigned long uv_mmask __read_mostly; ··· 160 109 * clear of the Timeout bit (as well) will free the resource. No reply will 161 110 * be sent (the hardware will only do one reply per message). 162 111 */ 163 163 - static inline void uv_reply_to_message(struct msg_desc *mdp, 164 164 - struct bau_control *bcp) 112 112 + static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp) 165 113 { 166 114 unsigned long dw; 167 167 - struct bau_payload_queue_entry *msg; 115 115 + struct bau_pq_entry *msg; 168 116 169 117 msg = mdp->msg; 170 118 if (!msg->canceled) { 171 171 - dw = (msg->sw_ack_vector << UV_SW_ACK_NPENDING) | 172 172 - msg->sw_ack_vector; 173 173 - uv_write_local_mmr( 174 174 - UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw); 119 119 + dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec; 120 120 + write_mmr_sw_ack(dw); 175 121 } 176 122 msg->replied_to = 1; 177 177 - msg->sw_ack_vector = 0; 123 123 + msg->swack_vec = 0; 178 124 } 179 125 180 126 /* 181 127 * Process the receipt of a RETRY message 182 128 */ 183 183 - static inline void uv_bau_process_retry_msg(struct msg_desc *mdp, 184 184 - struct bau_control *bcp) 129 129 + static void bau_process_retry_msg(struct msg_desc *mdp, 130 130 + struct bau_control *bcp) 185 131 { 186 132 int i; 187 133 int cancel_count = 0; 188 188 - int slot2; 189 134 unsigned long msg_res; 190 135 unsigned long mmr = 0; 191 191 - struct bau_payload_queue_entry *msg; 192 192 - struct bau_payload_queue_entry *msg2; 193 193 - struct ptc_stats *stat; 136 136 + struct bau_pq_entry *msg = mdp->msg; 137 137 + struct bau_pq_entry *msg2; 138 138 + struct ptc_stats *stat = bcp->statp; 194 139 195 195 - msg = mdp->msg; 196 196 - stat = bcp->statp; 197 140 stat->d_retries++; 198 141 /* 199 142 * cancel any message from msg+1 to the retry itself 200 143 */ 201 144 for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) { 202 202 - if (msg2 > mdp->va_queue_last) 203 203 - msg2 = mdp->va_queue_first; 145 145 + if (msg2 > mdp->queue_last) 146 146 + msg2 = mdp->queue_first; 204 147 if (msg2 == msg) 205 148 break; 206 149 207 207 - /* same conditions for cancellation as uv_do_reset */ 150 150 + /* same conditions for cancellation as do_reset */ 208 151 if ((msg2->replied_to == 0) && (msg2->canceled == 0) && 209 209 - (msg2->sw_ack_vector) && ((msg2->sw_ack_vector & 210 210 - msg->sw_ack_vector) == 0) && 152 152 + (msg2->swack_vec) && ((msg2->swack_vec & 153 153 + msg->swack_vec) == 0) && 211 154 (msg2->sending_cpu == msg->sending_cpu) && 212 155 (msg2->msg_type != MSG_NOOP)) { 213 213 - slot2 = msg2 - mdp->va_queue_first; 214 214 - mmr = uv_read_local_mmr 215 215 - (UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 216 216 - msg_res = msg2->sw_ack_vector; 156 156 + mmr = read_mmr_sw_ack(); 157 157 + msg_res = msg2->swack_vec; 217 158 /* 218 159 * This is a message retry; clear the resources held 219 160 * by the previous message only if they timed out. ··· 213 170 * situation to report. 214 171 */ 215 172 if (mmr & (msg_res << UV_SW_ACK_NPENDING)) { 173 173 + unsigned long mr; 216 174 /* 217 175 * is the resource timed out? 218 176 * make everyone ignore the cancelled message. ··· 221 177 msg2->canceled = 1; 222 178 stat->d_canceled++; 223 179 cancel_count++; 224 224 - uv_write_local_mmr( 225 225 - UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, 226 226 - (msg_res << UV_SW_ACK_NPENDING) | 227 227 - msg_res); 180 180 + mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; 181 181 + write_mmr_sw_ack(mr); 228 182 } 229 183 } 230 184 } ··· 234 192 * Do all the things a cpu should do for a TLB shootdown message. 235 193 * Other cpu's may come here at the same time for this message. 236 194 */ 237 237 - static void uv_bau_process_message(struct msg_desc *mdp, 238 238 - struct bau_control *bcp) 195 195 + static void bau_process_message(struct msg_desc *mdp, 196 196 + struct bau_control *bcp) 239 197 { 240 240 - int msg_ack_count; 241 198 short socket_ack_count = 0; 242 242 - struct ptc_stats *stat; 243 243 - struct bau_payload_queue_entry *msg; 199 199 + short *sp; 200 200 + struct atomic_short *asp; 201 201 + struct ptc_stats *stat = bcp->statp; 202 202 + struct bau_pq_entry *msg = mdp->msg; 244 203 struct bau_control *smaster = bcp->socket_master; 245 204 246 205 /* 247 206 * This must be a normal message, or retry of a normal message 248 207 */ 249 249 - msg = mdp->msg; 250 250 - stat = bcp->statp; 251 208 if (msg->address == TLB_FLUSH_ALL) { 252 209 local_flush_tlb(); 253 210 stat->d_alltlb++; ··· 263 222 * cpu number. 264 223 */ 265 224 if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master) 266 266 - uv_bau_process_retry_msg(mdp, bcp); 225 225 + bau_process_retry_msg(mdp, bcp); 267 226 268 227 /* 269 269 - * This is a sw_ack message, so we have to reply to it. 228 228 + * This is a swack message, so we have to reply to it. 270 229 * Count each responding cpu on the socket. This avoids 271 230 * pinging the count's cache line back and forth between 272 231 * the sockets. 273 232 */ 274 274 - socket_ack_count = atomic_add_short_return(1, (struct atomic_short *) 275 275 - &smaster->socket_acknowledge_count[mdp->msg_slot]); 233 233 + sp = &smaster->socket_acknowledge_count[mdp->msg_slot]; 234 234 + asp = (struct atomic_short *)sp; 235 235 + socket_ack_count = atom_asr(1, asp); 276 236 if (socket_ack_count == bcp->cpus_in_socket) { 237 237 + int msg_ack_count; 277 238 /* 278 239 * Both sockets dump their completed count total into 279 240 * the message's count. 280 241 */ 281 242 smaster->socket_acknowledge_count[mdp->msg_slot] = 0; 282 282 - msg_ack_count = atomic_add_short_return(socket_ack_count, 283 283 - (struct atomic_short *)&msg->acknowledge_count); 243 243 + asp = (struct atomic_short *)&msg->acknowledge_count; 244 244 + msg_ack_count = atom_asr(socket_ack_count, asp); 284 245 285 246 if (msg_ack_count == bcp->cpus_in_uvhub) { 286 247 /* 287 248 * All cpus in uvhub saw it; reply 288 249 */ 289 289 - uv_reply_to_message(mdp, bcp); 250 250 + reply_to_message(mdp, bcp); 290 251 } 291 252 } 292 253 ··· 311 268 * Last resort when we get a large number of destination timeouts is 312 269 * to clear resources held by a given cpu. 313 270 * Do this with IPI so that all messages in the BAU message queue 314 314 - * can be identified by their nonzero sw_ack_vector field. 271 271 + * can be identified by their nonzero swack_vec field. 315 272 * 316 273 * This is entered for a single cpu on the uvhub. 317 274 * The sender want's this uvhub to free a specific message's 318 318 - * sw_ack resources. 275 275 + * swack resources. 319 276 */ 320 320 - static void 321 321 - uv_do_reset(void *ptr) 277 277 + static void do_reset(void *ptr) 322 278 { 323 279 int i; 324 324 - int slot; 325 325 - int count = 0; 326 326 - unsigned long mmr; 327 327 - unsigned long msg_res; 328 328 - struct bau_control *bcp; 329 329 - struct reset_args *rap; 330 330 - struct bau_payload_queue_entry *msg; 331 331 - struct ptc_stats *stat; 280 280 + struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id()); 281 281 + struct reset_args *rap = (struct reset_args *)ptr; 282 282 + struct bau_pq_entry *msg; 283 283 + struct ptc_stats *stat = bcp->statp; 332 284 333 333 - bcp = &per_cpu(bau_control, smp_processor_id()); 334 334 - rap = (struct reset_args *)ptr; 335 335 - stat = bcp->statp; 336 285 stat->d_resets++; 337 337 - 338 286 /* 339 287 * We're looking for the given sender, and 340 340 - * will free its sw_ack resource. 288 288 + * will free its swack resource. 341 289 * If all cpu's finally responded after the timeout, its 342 290 * message 'replied_to' was set. 343 291 */ 344 344 - for (msg = bcp->va_queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) { 345 345 - /* uv_do_reset: same conditions for cancellation as 346 346 - uv_bau_process_retry_msg() */ 292 292 + for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) { 293 293 + unsigned long msg_res; 294 294 + /* do_reset: same conditions for cancellation as 295 295 + bau_process_retry_msg() */ 347 296 if ((msg->replied_to == 0) && 348 297 (msg->canceled == 0) && 349 298 (msg->sending_cpu == rap->sender) && 350 350 - (msg->sw_ack_vector) && 299 299 + (msg->swack_vec) && 351 300 (msg->msg_type != MSG_NOOP)) { 301 301 + unsigned long mmr; 302 302 + unsigned long mr; 352 303 /* 353 304 * make everyone else ignore this message 354 305 */ 355 306 msg->canceled = 1; 356 356 - slot = msg - bcp->va_queue_first; 357 357 - count++; 358 307 /* 359 308 * only reset the resource if it is still pending 360 309 */ 361 361 - mmr = uv_read_local_mmr 362 362 - (UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 363 363 - msg_res = msg->sw_ack_vector; 310 310 + mmr = read_mmr_sw_ack(); 311 311 + msg_res = msg->swack_vec; 312 312 + mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; 364 313 if (mmr & msg_res) { 365 314 stat->d_rcanceled++; 366 366 - uv_write_local_mmr( 367 367 - UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, 368 368 - (msg_res << UV_SW_ACK_NPENDING) | 369 369 - msg_res); 315 315 + write_mmr_sw_ack(mr); 370 316 } 371 317 } 372 318 } ··· 366 334 * Use IPI to get all target uvhubs to release resources held by 367 335 * a given sending cpu number. 368 336 */ 369 369 - static void uv_reset_with_ipi(struct bau_target_uvhubmask *distribution, 370 370 - int sender) 337 337 + static void reset_with_ipi(struct bau_targ_hubmask *distribution, int sender) 371 338 { 372 339 int uvhub; 373 373 - int cpu; 340 340 + int maskbits; 374 341 cpumask_t mask; 375 342 struct reset_args reset_args; 376 343 377 344 reset_args.sender = sender; 378 378 - 379 345 cpus_clear(mask); 380 346 /* find a single cpu for each uvhub in this distribution mask */ 381 381 - for (uvhub = 0; 382 382 - uvhub < sizeof(struct bau_target_uvhubmask) * BITSPERBYTE; 383 383 - uvhub++) { 347 347 + maskbits = sizeof(struct bau_targ_hubmask) * BITSPERBYTE; 348 348 + for (uvhub = 0; uvhub < maskbits; uvhub++) { 349 349 + int cpu; 384 350 if (!bau_uvhub_isset(uvhub, distribution)) 385 351 continue; 386 352 /* find a cpu for this uvhub */ 387 353 cpu = uvhub_to_first_cpu(uvhub); 388 354 cpu_set(cpu, mask); 389 355 } 390 390 - /* IPI all cpus; Preemption is already disabled */ 391 391 - smp_call_function_many(&mask, uv_do_reset, (void *)&reset_args, 1); 356 356 + 357 357 + /* IPI all cpus; preemption is already disabled */ 358 358 + smp_call_function_many(&mask, do_reset, (void *)&reset_args, 1); 392 359 return; 393 360 } 394 361 395 395 - static inline unsigned long 396 396 - cycles_2_us(unsigned long long cyc) 362 362 + static inline unsigned long cycles_2_us(unsigned long long cyc) 397 363 { 398 364 unsigned long long ns; 399 365 unsigned long us; 400 400 - ns = (cyc * per_cpu(cyc2ns, smp_processor_id())) 401 401 - >> CYC2NS_SCALE_FACTOR; 366 366 + int cpu = smp_processor_id(); 367 367 + 368 368 + ns = (cyc * per_cpu(cyc2ns, cpu)) >> CYC2NS_SCALE_FACTOR; 402 369 us = ns / 1000; 403 370 return us; 404 371 } ··· 407 376 * leaves uvhub_quiesce set so that no new broadcasts are started by 408 377 * bau_flush_send_and_wait() 409 378 */ 410 410 - static inline void 411 411 - quiesce_local_uvhub(struct bau_control *hmaster) 379 379 + static inline void quiesce_local_uvhub(struct bau_control *hmaster) 412 380 { 413 413 - atomic_add_short_return(1, (struct atomic_short *) 414 414 - &hmaster->uvhub_quiesce); 381 381 + atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce); 415 382 } 416 383 417 384 /* 418 385 * mark this quiet-requestor as done 419 386 */ 420 420 - static inline void 421 421 - end_uvhub_quiesce(struct bau_control *hmaster) 387 387 + static inline void end_uvhub_quiesce(struct bau_control *hmaster) 422 388 { 423 423 - atomic_add_short_return(-1, (struct atomic_short *) 424 424 - &hmaster->uvhub_quiesce); 389 389 + atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce); 390 390 + } 391 391 + 392 392 + static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift) 393 393 + { 394 394 + unsigned long descriptor_status; 395 395 + 396 396 + descriptor_status = uv_read_local_mmr(mmr_offset); 397 397 + descriptor_status >>= right_shift; 398 398 + descriptor_status &= UV_ACT_STATUS_MASK; 399 399 + return descriptor_status; 425 400 } 426 401 427 402 /* 428 403 * Wait for completion of a broadcast software ack message 429 404 * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP 430 405 */ 431 431 - static int uv_wait_completion(struct bau_desc *bau_desc, 432 432 - unsigned long mmr_offset, int right_shift, int this_cpu, 433 433 - struct bau_control *bcp, struct bau_control *smaster, long try) 406 406 + static int uv1_wait_completion(struct bau_desc *bau_desc, 407 407 + unsigned long mmr_offset, int right_shift, 408 408 + struct bau_control *bcp, long try) 434 409 { 435 410 unsigned long descriptor_status; 436 436 - cycles_t ttime; 411 411 + cycles_t ttm; 437 412 struct ptc_stats *stat = bcp->statp; 438 438 - struct bau_control *hmaster; 439 413 440 440 - hmaster = bcp->uvhub_master; 441 441 - 414 414 + descriptor_status = uv1_read_status(mmr_offset, right_shift); 442 415 /* spin on the status MMR, waiting for it to go idle */ 443 443 - while ((descriptor_status = (((unsigned long) 444 444 - uv_read_local_mmr(mmr_offset) >> 445 445 - right_shift) & UV_ACT_STATUS_MASK)) != 446 446 - DESC_STATUS_IDLE) { 416 416 + while ((descriptor_status != DS_IDLE)) { 447 417 /* 448 448 - * Our software ack messages may be blocked because there are 449 449 - * no swack resources available. As long as none of them 450 450 - * has timed out hardware will NACK our message and its 451 451 - * state will stay IDLE. 418 418 + * Our software ack messages may be blocked because 419 419 + * there are no swack resources available. As long 420 420 + * as none of them has timed out hardware will NACK 421 421 + * our message and its state will stay IDLE. 452 422 */ 453 453 - if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) { 423 423 + if (descriptor_status == DS_SOURCE_TIMEOUT) { 454 424 stat->s_stimeout++; 455 425 return FLUSH_GIVEUP; 456 456 - } else if (descriptor_status == 457 457 - DESC_STATUS_DESTINATION_TIMEOUT) { 426 426 + } else if (descriptor_status == DS_DESTINATION_TIMEOUT) { 458 427 stat->s_dtimeout++; 459 459 - ttime = get_cycles(); 428 428 + ttm = get_cycles(); 460 429 461 430 /* 462 431 * Our retries may be blocked by all destination ··· 464 433 * pending. In that case hardware returns the 465 434 * ERROR that looks like a destination timeout. 466 435 */ 467 467 - if (cycles_2_us(ttime - bcp->send_message) < 468 468 - timeout_us) { 436 436 + if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { 469 437 bcp->conseccompletes = 0; 470 438 return FLUSH_RETRY_PLUGGED; 471 439 } ··· 477 447 */ 478 448 cpu_relax(); 479 449 } 450 450 + descriptor_status = uv1_read_status(mmr_offset, right_shift); 480 451 } 481 452 bcp->conseccompletes++; 482 453 return FLUSH_COMPLETE; 483 454 } 484 455 485 485 - static inline cycles_t 486 486 - sec_2_cycles(unsigned long sec) 456 456 + /* 457 457 + * UV2 has an extra bit of status in the ACTIVATION_STATUS_2 register. 458 458 + */ 459 459 + static unsigned long uv2_read_status(unsigned long offset, int rshft, int cpu) 460 460 + { 461 461 + unsigned long descriptor_status; 462 462 + unsigned long descriptor_status2; 463 463 + 464 464 + descriptor_status = ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK); 465 465 + descriptor_status2 = (read_mmr_uv2_status() >> cpu) & 0x1UL; 466 466 + descriptor_status = (descriptor_status << 1) | descriptor_status2; 467 467 + return descriptor_status; 468 468 + } 469 469 + 470 470 + static int uv2_wait_completion(struct bau_desc *bau_desc, 471 471 + unsigned long mmr_offset, int right_shift, 472 472 + struct bau_control *bcp, long try) 473 473 + { 474 474 + unsigned long descriptor_stat; 475 475 + cycles_t ttm; 476 476 + int cpu = bcp->uvhub_cpu; 477 477 + struct ptc_stats *stat = bcp->statp; 478 478 + 479 479 + descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu); 480 480 + 481 481 + /* spin on the status MMR, waiting for it to go idle */ 482 482 + while (descriptor_stat != UV2H_DESC_IDLE) { 483 483 + /* 484 484 + * Our software ack messages may be blocked because 485 485 + * there are no swack resources available. As long 486 486 + * as none of them has timed out hardware will NACK 487 487 + * our message and its state will stay IDLE. 488 488 + */ 489 489 + if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) || 490 490 + (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) || 491 491 + (descriptor_stat == UV2H_DESC_DEST_PUT_ERR)) { 492 492 + stat->s_stimeout++; 493 493 + return FLUSH_GIVEUP; 494 494 + } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) { 495 495 + stat->s_dtimeout++; 496 496 + ttm = get_cycles(); 497 497 + /* 498 498 + * Our retries may be blocked by all destination 499 499 + * swack resources being consumed, and a timeout 500 500 + * pending. In that case hardware returns the 501 501 + * ERROR that looks like a destination timeout. 502 502 + */ 503 503 + if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { 504 504 + bcp->conseccompletes = 0; 505 505 + return FLUSH_RETRY_PLUGGED; 506 506 + } 507 507 + bcp->conseccompletes = 0; 508 508 + return FLUSH_RETRY_TIMEOUT; 509 509 + } else { 510 510 + /* 511 511 + * descriptor_stat is still BUSY 512 512 + */ 513 513 + cpu_relax(); 514 514 + } 515 515 + descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu); 516 516 + } 517 517 + bcp->conseccompletes++; 518 518 + return FLUSH_COMPLETE; 519 519 + } 520 520 + 521 521 + /* 522 522 + * There are 2 status registers; each and array[32] of 2 bits. Set up for 523 523 + * which register to read and position in that register based on cpu in 524 524 + * current hub. 525 525 + */ 526 526 + static int wait_completion(struct bau_desc *bau_desc, 527 527 + struct bau_control *bcp, long try) 528 528 + { 529 529 + int right_shift; 530 530 + unsigned long mmr_offset; 531 531 + int cpu = bcp->uvhub_cpu; 532 532 + 533 533 + if (cpu < UV_CPUS_PER_AS) { 534 534 + mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; 535 535 + right_shift = cpu * UV_ACT_STATUS_SIZE; 536 536 + } else { 537 537 + mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; 538 538 + right_shift = ((cpu - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE); 539 539 + } 540 540 + 541 541 + if (is_uv1_hub()) 542 542 + return uv1_wait_completion(bau_desc, mmr_offset, right_shift, 543 543 + bcp, try); 544 544 + else 545 545 + return uv2_wait_completion(bau_desc, mmr_offset, right_shift, 546 546 + bcp, try); 547 547 + } 548 548 + 549 549 + static inline cycles_t sec_2_cycles(unsigned long sec) 487 550 { 488 551 unsigned long ns; 489 552 cycles_t cyc; ··· 587 464 } 588 465 589 466 /* 590 590 - * conditionally add 1 to *v, unless *v is >= u 591 591 - * return 0 if we cannot add 1 to *v because it is >= u 592 592 - * return 1 if we can add 1 to *v because it is < u 593 593 - * the add is atomic 594 594 - * 595 595 - * This is close to atomic_add_unless(), but this allows the 'u' value 596 596 - * to be lowered below the current 'v'. atomic_add_unless can only stop 597 597 - * on equal. 598 598 - */ 599 599 - static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u) 600 600 - { 601 601 - spin_lock(lock); 602 602 - if (atomic_read(v) >= u) { 603 603 - spin_unlock(lock); 604 604 - return 0; 605 605 - } 606 606 - atomic_inc(v); 607 607 - spin_unlock(lock); 608 608 - return 1; 609 609 - } 610 610 - 611 611 - /* 612 612 - * Our retries are blocked by all destination swack resources being 467 467 + * Our retries are blocked by all destination sw ack resources being 613 468 * in use, and a timeout is pending. In that case hardware immediately 614 469 * returns the ERROR that looks like a destination timeout. 615 470 */ 616 616 - static void 617 617 - destination_plugged(struct bau_desc *bau_desc, struct bau_control *bcp, 471 471 + static void destination_plugged(struct bau_desc *bau_desc, 472 472 + struct bau_control *bcp, 618 473 struct bau_control *hmaster, struct ptc_stats *stat) 619 474 { 620 475 udelay(bcp->plugged_delay); 621 476 bcp->plugged_tries++; 477 477 + 622 478 if (bcp->plugged_tries >= bcp->plugsb4reset) { 623 479 bcp->plugged_tries = 0; 480 480 + 624 481 quiesce_local_uvhub(hmaster); 482 482 + 625 483 spin_lock(&hmaster->queue_lock); 626 626 - uv_reset_with_ipi(&bau_desc->distribution, bcp->cpu); 484 484 + reset_with_ipi(&bau_desc->distribution, bcp->cpu); 627 485 spin_unlock(&hmaster->queue_lock); 486 486 + 628 487 end_uvhub_quiesce(hmaster); 488 488 + 629 489 bcp->ipi_attempts++; 630 490 stat->s_resets_plug++; 631 491 } 632 492 } 633 493 634 634 - static void 635 635 - destination_timeout(struct bau_desc *bau_desc, struct bau_control *bcp, 636 636 - struct bau_control *hmaster, struct ptc_stats *stat) 494 494 + static void destination_timeout(struct bau_desc *bau_desc, 495 495 + struct bau_control *bcp, struct bau_control *hmaster, 496 496 + struct ptc_stats *stat) 637 497 { 638 638 - hmaster->max_bau_concurrent = 1; 498 498 + hmaster->max_concurr = 1; 639 499 bcp->timeout_tries++; 640 500 if (bcp->timeout_tries >= bcp->timeoutsb4reset) { 641 501 bcp->timeout_tries = 0; 502 502 + 642 503 quiesce_local_uvhub(hmaster); 504 504 + 643 505 spin_lock(&hmaster->queue_lock); 644 644 - uv_reset_with_ipi(&bau_desc->distribution, bcp->cpu); 506 506 + reset_with_ipi(&bau_desc->distribution, bcp->cpu); 645 507 spin_unlock(&hmaster->queue_lock); 508 508 + 646 509 end_uvhub_quiesce(hmaster); 510 510 + 647 511 bcp->ipi_attempts++; 648 512 stat->s_resets_timeout++; 649 513 } ··· 640 530 * Completions are taking a very long time due to a congested numalink 641 531 * network. 642 532 */ 643 643 - static void 644 644 - disable_for_congestion(struct bau_control *bcp, struct ptc_stats *stat) 533 533 + static void disable_for_congestion(struct bau_control *bcp, 534 534 + struct ptc_stats *stat) 645 535 { 646 646 - int tcpu; 647 647 - struct bau_control *tbcp; 648 648 - 649 536 /* let only one cpu do this disabling */ 650 537 spin_lock(&disable_lock); 538 538 + 651 539 if (!baudisabled && bcp->period_requests && 652 540 ((bcp->period_time / bcp->period_requests) > congested_cycles)) { 541 541 + int tcpu; 542 542 + struct bau_control *tbcp; 653 543 /* it becomes this cpu's job to turn on the use of the 654 544 BAU again */ 655 545 baudisabled = 1; 656 546 bcp->set_bau_off = 1; 657 657 - bcp->set_bau_on_time = get_cycles() + 658 658 - sec_2_cycles(bcp->congested_period); 547 547 + bcp->set_bau_on_time = get_cycles(); 548 548 + bcp->set_bau_on_time += sec_2_cycles(bcp->cong_period); 659 549 stat->s_bau_disabled++; 660 550 for_each_present_cpu(tcpu) { 661 551 tbcp = &per_cpu(bau_control, tcpu); 662 662 - tbcp->baudisabled = 1; 552 552 + tbcp->baudisabled = 1; 663 553 } 664 554 } 555 555 + 665 556 spin_unlock(&disable_lock); 666 557 } 667 558 668 668 - /** 669 669 - * uv_flush_send_and_wait 670 670 - * 559 559 + static void count_max_concurr(int stat, struct bau_control *bcp, 560 560 + struct bau_control *hmaster) 561 561 + { 562 562 + bcp->plugged_tries = 0; 563 563 + bcp->timeout_tries = 0; 564 564 + if (stat != FLUSH_COMPLETE) 565 565 + return; 566 566 + if (bcp->conseccompletes <= bcp->complete_threshold) 567 567 + return; 568 568 + if (hmaster->max_concurr >= hmaster->max_concurr_const) 569 569 + return; 570 570 + hmaster->max_concurr++; 571 571 + } 572 572 + 573 573 + static void record_send_stats(cycles_t time1, cycles_t time2, 574 574 + struct bau_control *bcp, struct ptc_stats *stat, 575 575 + int completion_status, int try) 576 576 + { 577 577 + cycles_t elapsed; 578 578 + 579 579 + if (time2 > time1) { 580 580 + elapsed = time2 - time1; 581 581 + stat->s_time += elapsed; 582 582 + 583 583 + if ((completion_status == FLUSH_COMPLETE) && (try == 1)) { 584 584 + bcp->period_requests++; 585 585 + bcp->period_time += elapsed; 586 586 + if ((elapsed > congested_cycles) && 587 587 + (bcp->period_requests > bcp->cong_reps)) 588 588 + disable_for_congestion(bcp, stat); 589 589 + } 590 590 + } else 591 591 + stat->s_requestor--; 592 592 + 593 593 + if (completion_status == FLUSH_COMPLETE && try > 1) 594 594 + stat->s_retriesok++; 595 595 + else if (completion_status == FLUSH_GIVEUP) 596 596 + stat->s_giveup++; 597 597 + } 598 598 + 599 599 + /* 600 600 + * Because of a uv1 hardware bug only a limited number of concurrent 601 601 + * requests can be made. 602 602 + */ 603 603 + static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat) 604 604 + { 605 605 + spinlock_t *lock = &hmaster->uvhub_lock; 606 606 + atomic_t *v; 607 607 + 608 608 + v = &hmaster->active_descriptor_count; 609 609 + if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) { 610 610 + stat->s_throttles++; 611 611 + do { 612 612 + cpu_relax(); 613 613 + } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)); 614 614 + } 615 615 + } 616 616 + 617 617 + /* 618 618 + * Handle the completion status of a message send. 619 619 + */ 620 620 + static void handle_cmplt(int completion_status, struct bau_desc *bau_desc, 621 621 + struct bau_control *bcp, struct bau_control *hmaster, 622 622 + struct ptc_stats *stat) 623 623 + { 624 624 + if (completion_status == FLUSH_RETRY_PLUGGED) 625 625 + destination_plugged(bau_desc, bcp, hmaster, stat); 626 626 + else if (completion_status == FLUSH_RETRY_TIMEOUT) 627 627 + destination_timeout(bau_desc, bcp, hmaster, stat); 628 628 + } 629 629 + 630 630 + /* 671 631 * Send a broadcast and wait for it to complete. 672 632 * 673 633 * The flush_mask contains the cpus the broadcast is to be sent to including ··· 748 568 * returned to the kernel. 749 569 */ 750 570 int uv_flush_send_and_wait(struct bau_desc *bau_desc, 751 751 - struct cpumask *flush_mask, struct bau_control *bcp) 571 571 + struct cpumask *flush_mask, struct bau_control *bcp) 752 572 { 753 753 - int right_shift; 754 754 - int completion_status = 0; 755 573 int seq_number = 0; 574 574 + int completion_stat = 0; 756 575 long try = 0; 757 757 - int cpu = bcp->uvhub_cpu; 758 758 - int this_cpu = bcp->cpu; 759 759 - unsigned long mmr_offset; 760 576 unsigned long index; 761 577 cycles_t time1; 762 578 cycles_t time2; 763 763 - cycles_t elapsed; 764 579 struct ptc_stats *stat = bcp->statp; 765 765 - struct bau_control *smaster = bcp->socket_master; 766 580 struct bau_control *hmaster = bcp->uvhub_master; 767 581 768 768 - if (!atomic_inc_unless_ge(&hmaster->uvhub_lock, 769 769 - &hmaster->active_descriptor_count, 770 770 - hmaster->max_bau_concurrent)) { 771 771 - stat->s_throttles++; 772 772 - do { 773 773 - cpu_relax(); 774 774 - } while (!atomic_inc_unless_ge(&hmaster->uvhub_lock, 775 775 - &hmaster->active_descriptor_count, 776 776 - hmaster->max_bau_concurrent)); 777 777 - } 582 582 + if (is_uv1_hub()) 583 583 + uv1_throttle(hmaster, stat); 584 584 + 778 585 while (hmaster->uvhub_quiesce) 779 586 cpu_relax(); 780 587 781 781 - if (cpu < UV_CPUS_PER_ACT_STATUS) { 782 782 - mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; 783 783 - right_shift = cpu * UV_ACT_STATUS_SIZE; 784 784 - } else { 785 785 - mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; 786 786 - right_shift = 787 787 - ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE); 788 788 - } 789 588 time1 = get_cycles(); 790 589 do { 791 590 if (try == 0) { ··· 774 615 bau_desc->header.msg_type = MSG_RETRY; 775 616 stat->s_retry_messages++; 776 617 } 777 777 - bau_desc->header.sequence = seq_number; 778 778 - index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) | 779 779 - bcp->uvhub_cpu; 780 780 - bcp->send_message = get_cycles(); 781 781 - uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); 782 782 - try++; 783 783 - completion_status = uv_wait_completion(bau_desc, mmr_offset, 784 784 - right_shift, this_cpu, bcp, smaster, try); 785 618 786 786 - if (completion_status == FLUSH_RETRY_PLUGGED) { 787 787 - destination_plugged(bau_desc, bcp, hmaster, stat); 788 788 - } else if (completion_status == FLUSH_RETRY_TIMEOUT) { 789 789 - destination_timeout(bau_desc, bcp, hmaster, stat); 790 790 - } 619 619 + bau_desc->header.sequence = seq_number; 620 620 + index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu; 621 621 + bcp->send_message = get_cycles(); 622 622 + 623 623 + write_mmr_activation(index); 624 624 + 625 625 + try++; 626 626 + completion_stat = wait_completion(bau_desc, bcp, try); 627 627 + 628 628 + handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat); 629 629 + 791 630 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) { 792 631 bcp->ipi_attempts = 0; 793 793 - completion_status = FLUSH_GIVEUP; 632 632 + completion_stat = FLUSH_GIVEUP; 794 633 break; 795 634 } 796 635 cpu_relax(); 797 797 - } while ((completion_status == FLUSH_RETRY_PLUGGED) || 798 798 - (completion_status == FLUSH_RETRY_TIMEOUT)); 636 636 + } while ((completion_stat == FLUSH_RETRY_PLUGGED) || 637 637 + (completion_stat == FLUSH_RETRY_TIMEOUT)); 638 638 + 799 639 time2 = get_cycles(); 800 800 - bcp->plugged_tries = 0; 801 801 - bcp->timeout_tries = 0; 802 802 - if ((completion_status == FLUSH_COMPLETE) && 803 803 - (bcp->conseccompletes > bcp->complete_threshold) && 804 804 - (hmaster->max_bau_concurrent < 805 805 - hmaster->max_bau_concurrent_constant)) 806 806 - hmaster->max_bau_concurrent++; 640 640 + 641 641 + count_max_concurr(completion_stat, bcp, hmaster); 642 642 + 807 643 while (hmaster->uvhub_quiesce) 808 644 cpu_relax(); 645 645 + 809 646 atomic_dec(&hmaster->active_descriptor_count); 810 810 - if (time2 > time1) { 811 811 - elapsed = time2 - time1; 812 812 - stat->s_time += elapsed; 813 813 - if ((completion_status == FLUSH_COMPLETE) && (try == 1)) { 814 814 - bcp->period_requests++; 815 815 - bcp->period_time += elapsed; 816 816 - if ((elapsed > congested_cycles) && 817 817 - (bcp->period_requests > bcp->congested_reps)) { 818 818 - disable_for_congestion(bcp, stat); 819 819 - } 820 820 - } 821 821 - } else 822 822 - stat->s_requestor--; 823 823 - if (completion_status == FLUSH_COMPLETE && try > 1) 824 824 - stat->s_retriesok++; 825 825 - else if (completion_status == FLUSH_GIVEUP) { 826 826 - stat->s_giveup++; 647 647 + 648 648 + record_send_stats(time1, time2, bcp, stat, completion_stat, try); 649 649 + 650 650 + if (completion_stat == FLUSH_GIVEUP) 827 651 return 1; 828 828 - } 829 652 return 0; 830 653 } 831 654 832 832 - /** 833 833 - * uv_flush_tlb_others - globally purge translation cache of a virtual 834 834 - * address or all TLB's 655 655 + /* 656 656 + * The BAU is disabled. When the disabled time period has expired, the cpu 657 657 + * that disabled it must re-enable it. 658 658 + * Return 0 if it is re-enabled for all cpus. 659 659 + */ 660 660 + static int check_enable(struct bau_control *bcp, struct ptc_stats *stat) 661 661 + { 662 662 + int tcpu; 663 663 + struct bau_control *tbcp; 664 664 + 665 665 + if (bcp->set_bau_off) { 666 666 + if (get_cycles() >= bcp->set_bau_on_time) { 667 667 + stat->s_bau_reenabled++; 668 668 + baudisabled = 0; 669 669 + for_each_present_cpu(tcpu) { 670 670 + tbcp = &per_cpu(bau_control, tcpu); 671 671 + tbcp->baudisabled = 0; 672 672 + tbcp->period_requests = 0; 673 673 + tbcp->period_time = 0; 674 674 + } 675 675 + return 0; 676 676 + } 677 677 + } 678 678 + return -1; 679 679 + } 680 680 + 681 681 + static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs, 682 682 + int remotes, struct bau_desc *bau_desc) 683 683 + { 684 684 + stat->s_requestor++; 685 685 + stat->s_ntargcpu += remotes + locals; 686 686 + stat->s_ntargremotes += remotes; 687 687 + stat->s_ntarglocals += locals; 688 688 + 689 689 + /* uvhub statistics */ 690 690 + hubs = bau_uvhub_weight(&bau_desc->distribution); 691 691 + if (locals) { 692 692 + stat->s_ntarglocaluvhub++; 693 693 + stat->s_ntargremoteuvhub += (hubs - 1); 694 694 + } else 695 695 + stat->s_ntargremoteuvhub += hubs; 696 696 + 697 697 + stat->s_ntarguvhub += hubs; 698 698 + 699 699 + if (hubs >= 16) 700 700 + stat->s_ntarguvhub16++; 701 701 + else if (hubs >= 8) 702 702 + stat->s_ntarguvhub8++; 703 703 + else if (hubs >= 4) 704 704 + stat->s_ntarguvhub4++; 705 705 + else if (hubs >= 2) 706 706 + stat->s_ntarguvhub2++; 707 707 + else 708 708 + stat->s_ntarguvhub1++; 709 709 + } 710 710 + 711 711 + /* 712 712 + * Translate a cpu mask to the uvhub distribution mask in the BAU 713 713 + * activation descriptor. 714 714 + */ 715 715 + static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp, 716 716 + struct bau_desc *bau_desc, int *localsp, int *remotesp) 717 717 + { 718 718 + int cpu; 719 719 + int pnode; 720 720 + int cnt = 0; 721 721 + struct hub_and_pnode *hpp; 722 722 + 723 723 + for_each_cpu(cpu, flush_mask) { 724 724 + /* 725 725 + * The distribution vector is a bit map of pnodes, relative 726 726 + * to the partition base pnode (and the partition base nasid 727 727 + * in the header). 728 728 + * Translate cpu to pnode and hub using a local memory array. 729 729 + */ 730 730 + hpp = &bcp->socket_master->thp[cpu]; 731 731 + pnode = hpp->pnode - bcp->partition_base_pnode; 732 732 + bau_uvhub_set(pnode, &bau_desc->distribution); 733 733 + cnt++; 734 734 + if (hpp->uvhub == bcp->uvhub) 735 735 + (*localsp)++; 736 736 + else 737 737 + (*remotesp)++; 738 738 + } 739 739 + if (!cnt) 740 740 + return 1; 741 741 + return 0; 742 742 + } 743 743 + 744 744 + /* 745 745 + * globally purge translation cache of a virtual address or all TLB's 835 746 * @cpumask: mask of all cpu's in which the address is to be removed 836 747 * @mm: mm_struct containing virtual address range 837 748 * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu) ··· 925 696 * done. The returned pointer is valid till preemption is re-enabled. 926 697 */ 927 698 const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, 928 928 - struct mm_struct *mm, 929 929 - unsigned long va, unsigned int cpu) 699 699 + struct mm_struct *mm, unsigned long va, 700 700 + unsigned int cpu) 930 701 { 931 702 int locals = 0; 932 703 int remotes = 0; 933 704 int hubs = 0; 934 934 - int tcpu; 935 935 - int tpnode; 936 705 struct bau_desc *bau_desc; 937 706 struct cpumask *flush_mask; 938 707 struct ptc_stats *stat; 939 708 struct bau_control *bcp; 940 940 - struct bau_control *tbcp; 941 941 - struct hub_and_pnode *hpp; 942 709 943 710 /* kernel was booted 'nobau' */ 944 711 if (nobau) ··· 945 720 946 721 /* bau was disabled due to slow response */ 947 722 if (bcp->baudisabled) { 948 948 - /* the cpu that disabled it must re-enable it */ 949 949 - if (bcp->set_bau_off) { 950 950 - if (get_cycles() >= bcp->set_bau_on_time) { 951 951 - stat->s_bau_reenabled++; 952 952 - baudisabled = 0; 953 953 - for_each_present_cpu(tcpu) { 954 954 - tbcp = &per_cpu(bau_control, tcpu); 955 955 - tbcp->baudisabled = 0; 956 956 - tbcp->period_requests = 0; 957 957 - tbcp->period_time = 0; 958 958 - } 959 959 - } 960 960 - } 961 961 - return cpumask; 723 723 + if (check_enable(bcp, stat)) 724 724 + return cpumask; 962 725 } 963 726 964 727 /* ··· 957 744 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu); 958 745 /* don't actually do a shootdown of the local cpu */ 959 746 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); 747 747 + 960 748 if (cpu_isset(cpu, *cpumask)) 961 749 stat->s_ntargself++; 962 750 963 751 bau_desc = bcp->descriptor_base; 964 964 - bau_desc += UV_ITEMS_PER_DESCRIPTOR * bcp->uvhub_cpu; 752 752 + bau_desc += ITEMS_PER_DESC * bcp->uvhub_cpu; 965 753 bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); 966 966 - 967 967 - for_each_cpu(tcpu, flush_mask) { 968 968 - /* 969 969 - * The distribution vector is a bit map of pnodes, relative 970 970 - * to the partition base pnode (and the partition base nasid 971 971 - * in the header). 972 972 - * Translate cpu to pnode and hub using an array stored 973 973 - * in local memory. 974 974 - */ 975 975 - hpp = &bcp->socket_master->target_hub_and_pnode[tcpu]; 976 976 - tpnode = hpp->pnode - bcp->partition_base_pnode; 977 977 - bau_uvhub_set(tpnode, &bau_desc->distribution); 978 978 - if (hpp->uvhub == bcp->uvhub) 979 979 - locals++; 980 980 - else 981 981 - remotes++; 982 982 - } 983 983 - if ((locals + remotes) == 0) 754 754 + if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) 984 755 return NULL; 985 985 - stat->s_requestor++; 986 986 - stat->s_ntargcpu += remotes + locals; 987 987 - stat->s_ntargremotes += remotes; 988 988 - stat->s_ntarglocals += locals; 989 989 - remotes = bau_uvhub_weight(&bau_desc->distribution); 990 756 991 991 - /* uvhub statistics */ 992 992 - hubs = bau_uvhub_weight(&bau_desc->distribution); 993 993 - if (locals) { 994 994 - stat->s_ntarglocaluvhub++; 995 995 - stat->s_ntargremoteuvhub += (hubs - 1); 996 996 - } else 997 997 - stat->s_ntargremoteuvhub += hubs; 998 998 - stat->s_ntarguvhub += hubs; 999 999 - if (hubs >= 16) 1000 1000 - stat->s_ntarguvhub16++; 1001 1001 - else if (hubs >= 8) 1002 1002 - stat->s_ntarguvhub8++; 1003 1003 - else if (hubs >= 4) 1004 1004 - stat->s_ntarguvhub4++; 1005 1005 - else if (hubs >= 2) 1006 1006 - stat->s_ntarguvhub2++; 1007 1007 - else 1008 1008 - stat->s_ntarguvhub1++; 757 757 + record_send_statistics(stat, locals, hubs, remotes, bau_desc); 1009 758 1010 759 bau_desc->payload.address = va; 1011 760 bau_desc->payload.sending_cpu = cpu; 1012 1012 - 1013 761 /* 1014 762 * uv_flush_send_and_wait returns 0 if all cpu's were messaged, 1015 763 * or 1 if it gave up and the original cpumask should be returned. ··· 999 825 { 1000 826 int count = 0; 1001 827 cycles_t time_start; 1002 1002 - struct bau_payload_queue_entry *msg; 828 828 + struct bau_pq_entry *msg; 1003 829 struct bau_control *bcp; 1004 830 struct ptc_stats *stat; 1005 831 struct msg_desc msgdesc; 1006 832 1007 833 time_start = get_cycles(); 834 834 + 1008 835 bcp = &per_cpu(bau_control, smp_processor_id()); 1009 836 stat = bcp->statp; 1010 1010 - msgdesc.va_queue_first = bcp->va_queue_first; 1011 1011 - msgdesc.va_queue_last = bcp->va_queue_last; 837 837 + 838 838 + msgdesc.queue_first = bcp->queue_first; 839 839 + msgdesc.queue_last = bcp->queue_last; 840 840 + 1012 841 msg = bcp->bau_msg_head; 1013 1013 - while (msg->sw_ack_vector) { 842 842 + while (msg->swack_vec) { 1014 843 count++; 1015 1015 - msgdesc.msg_slot = msg - msgdesc.va_queue_first; 1016 1016 - msgdesc.sw_ack_slot = ffs(msg->sw_ack_vector) - 1; 844 844 + 845 845 + msgdesc.msg_slot = msg - msgdesc.queue_first; 846 846 + msgdesc.swack_slot = ffs(msg->swack_vec) - 1; 1017 847 msgdesc.msg = msg; 1018 1018 - uv_bau_process_message(&msgdesc, bcp); 848 848 + bau_process_message(&msgdesc, bcp); 849 849 + 1019 850 msg++; 1020 1020 - if (msg > msgdesc.va_queue_last) 1021 1021 - msg = msgdesc.va_queue_first; 851 851 + if (msg > msgdesc.queue_last) 852 852 + msg = msgdesc.queue_first; 1022 853 bcp->bau_msg_head = msg; 1023 854 } 1024 855 stat->d_time += (get_cycles() - time_start); ··· 1031 852 stat->d_nomsg++; 1032 853 else if (count > 1) 1033 854 stat->d_multmsg++; 855 855 + 1034 856 ack_APIC_irq(); 1035 857 } 1036 858 1037 859 /* 1038 1038 - * uv_enable_timeouts 1039 1039 - * 1040 1040 - * Each target uvhub (i.e. a uvhub that has no cpu's) needs to have 860 860 + * Each target uvhub (i.e. a uvhub that has cpu's) needs to have 1041 861 * shootdown message timeouts enabled. The timeout does not cause 1042 862 * an interrupt, but causes an error message to be returned to 1043 863 * the sender. 1044 864 */ 1045 1045 - static void __init uv_enable_timeouts(void) 865 865 + static void __init enable_timeouts(void) 1046 866 { 1047 867 int uvhub; 1048 868 int nuvhubs; ··· 1055 877 continue; 1056 878 1057 879 pnode = uv_blade_to_pnode(uvhub); 1058 1058 - mmr_image = 1059 1059 - uv_read_global_mmr64(pnode, UVH_LB_BAU_MISC_CONTROL); 880 880 + mmr_image = read_mmr_misc_control(pnode); 1060 881 /* 1061 882 * Set the timeout period and then lock it in, in three 1062 883 * steps; captures and locks in the period. 1063 884 * 1064 885 * To program the period, the SOFT_ACK_MODE must be off. 1065 886 */ 1066 1066 - mmr_image &= ~((unsigned long)1 << 1067 1067 - UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT); 1068 1068 - uv_write_global_mmr64 1069 1069 - (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 887 887 + mmr_image &= ~(1L << SOFTACK_MSHIFT); 888 888 + write_mmr_misc_control(pnode, mmr_image); 1070 889 /* 1071 890 * Set the 4-bit period. 1072 891 */ 1073 1073 - mmr_image &= ~((unsigned long)0xf << 1074 1074 - UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT); 1075 1075 - mmr_image |= (UV_INTD_SOFT_ACK_TIMEOUT_PERIOD << 1076 1076 - UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT); 1077 1077 - uv_write_global_mmr64 1078 1078 - (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 892 892 + mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT); 893 893 + mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT); 894 894 + write_mmr_misc_control(pnode, mmr_image); 1079 895 /* 896 896 + * UV1: 1080 897 * Subsequent reversals of the timebase bit (3) cause an 1081 898 * immediate timeout of one or all INTD resources as 1082 899 * indicated in bits 2:0 (7 causes all of them to timeout). 1083 900 */ 1084 1084 - mmr_image |= ((unsigned long)1 << 1085 1085 - UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT); 1086 1086 - uv_write_global_mmr64 1087 1087 - (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 901 901 + mmr_image |= (1L << SOFTACK_MSHIFT); 902 902 + if (is_uv2_hub()) { 903 903 + mmr_image |= (1L << UV2_LEG_SHFT); 904 904 + mmr_image |= (1L << UV2_EXT_SHFT); 905 905 + } 906 906 + write_mmr_misc_control(pnode, mmr_image); 1088 907 } 1089 908 } 1090 909 1091 1091 - static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset) 910 910 + static void *ptc_seq_start(struct seq_file *file, loff_t *offset) 1092 911 { 1093 912 if (*offset < num_possible_cpus()) 1094 913 return offset; 1095 914 return NULL; 1096 915 } 1097 916 1098 1098 - static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset) 917 917 + static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset) 1099 918 { 1100 919 (*offset)++; 1101 920 if (*offset < num_possible_cpus()) ··· 1100 925 return NULL; 1101 926 } 1102 927 1103 1103 - static void uv_ptc_seq_stop(struct seq_file *file, void *data) 928 928 + static void ptc_seq_stop(struct seq_file *file, void *data) 1104 929 { 1105 930 } 1106 931 1107 1107 - static inline unsigned long long 1108 1108 - microsec_2_cycles(unsigned long microsec) 932 932 + static inline unsigned long long usec_2_cycles(unsigned long microsec) 1109 933 { 1110 934 unsigned long ns; 1111 935 unsigned long long cyc; ··· 1115 941 } 1116 942 1117 943 /* 1118 1118 - * Display the statistics thru /proc. 944 944 + * Display the statistics thru /proc/sgi_uv/ptc_statistics 1119 945 * 'data' points to the cpu number 946 946 + * Note: see the descriptions in stat_description[]. 1120 947 */ 1121 1121 - static int uv_ptc_seq_show(struct seq_file *file, void *data) 948 948 + static int ptc_seq_show(struct seq_file *file, void *data) 1122 949 { 1123 950 struct ptc_stats *stat; 1124 951 int cpu; 1125 952 1126 953 cpu = *(loff_t *)data; 1127 1127 - 1128 954 if (!cpu) { 1129 955 seq_printf(file, 1130 956 "# cpu sent stime self locals remotes ncpus localhub "); 1131 957 seq_printf(file, 1132 958 "remotehub numuvhubs numuvhubs16 numuvhubs8 "); 1133 959 seq_printf(file, 1134 1134 - "numuvhubs4 numuvhubs2 numuvhubs1 dto "); 960 960 + "numuvhubs4 numuvhubs2 numuvhubs1 dto retries rok "); 1135 961 seq_printf(file, 1136 1136 - "retries rok resetp resett giveup sto bz throt "); 962 962 + "resetp resett giveup sto bz throt swack recv rtime "); 1137 963 seq_printf(file, 1138 1138 - "sw_ack recv rtime all "); 1139 1139 - seq_printf(file, 1140 1140 - "one mult none retry canc nocan reset rcan "); 964 964 + "all one mult none retry canc nocan reset rcan "); 1141 965 seq_printf(file, 1142 966 "disable enable\n"); 1143 967 } ··· 1162 990 /* destination side statistics */ 1163 991 seq_printf(file, 1164 992 "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", 1165 1165 - uv_read_global_mmr64(uv_cpu_to_pnode(cpu), 1166 1166 - UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE), 993 993 + read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)), 1167 994 stat->d_requestee, cycles_2_us(stat->d_time), 1168 995 stat->d_alltlb, stat->d_onetlb, stat->d_multmsg, 1169 996 stat->d_nomsg, stat->d_retries, stat->d_canceled, ··· 1171 1000 seq_printf(file, "%ld %ld\n", 1172 1001 stat->s_bau_disabled, stat->s_bau_reenabled); 1173 1002 } 1174 1174 - 1175 1003 return 0; 1176 1004 } 1177 1005 ··· 1178 1008 * Display the tunables thru debugfs 1179 1009 */ 1180 1010 static ssize_t tunables_read(struct file *file, char __user *userbuf, 1181 1181 - size_t count, loff_t *ppos) 1011 1011 + size_t count, loff_t *ppos) 1182 1012 { 1183 1013 char *buf; 1184 1014 int ret; 1185 1015 1186 1016 buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n", 1187 1187 - "max_bau_concurrent plugged_delay plugsb4reset", 1017 1017 + "max_concur plugged_delay plugsb4reset", 1188 1018 "timeoutsb4reset ipi_reset_limit complete_threshold", 1189 1019 "congested_response_us congested_reps congested_period", 1190 1190 - max_bau_concurrent, plugged_delay, plugsb4reset, 1020 1020 + max_concurr, plugged_delay, plugsb4reset, 1191 1021 timeoutsb4reset, ipi_reset_limit, complete_threshold, 1192 1192 - congested_response_us, congested_reps, congested_period); 1022 1022 + congested_respns_us, congested_reps, congested_period); 1193 1023 1194 1024 if (!buf) 1195 1025 return -ENOMEM; ··· 1200 1030 } 1201 1031 1202 1032 /* 1203 1203 - * -1: resetf the statistics 1033 1033 + * handle a write to /proc/sgi_uv/ptc_statistics 1034 1034 + * -1: reset the statistics 1204 1035 * 0: display meaning of the statistics 1205 1036 */ 1206 1206 - static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user, 1207 1207 - size_t count, loff_t *data) 1037 1037 + static ssize_t ptc_proc_write(struct file *file, const char __user *user, 1038 1038 + size_t count, loff_t *data) 1208 1039 { 1209 1040 int cpu; 1041 1041 + int i; 1042 1042 + int elements; 1210 1043 long input_arg; 1211 1044 char optstr[64]; 1212 1045 struct ptc_stats *stat; ··· 1219 1046 if (copy_from_user(optstr, user, count)) 1220 1047 return -EFAULT; 1221 1048 optstr[count - 1] = '\0'; 1049 1049 + 1222 1050 if (strict_strtol(optstr, 10, &input_arg) < 0) { 1223 1051 printk(KERN_DEBUG "%s is invalid\n", optstr); 1224 1052 return -EINVAL; 1225 1053 } 1226 1054 1227 1055 if (input_arg == 0) { 1056 1056 + elements = sizeof(stat_description)/sizeof(*stat_description); 1228 1057 printk(KERN_DEBUG "# cpu: cpu number\n"); 1229 1058 printk(KERN_DEBUG "Sender statistics:\n"); 1230 1230 - printk(KERN_DEBUG 1231 1231 - "sent: number of shootdown messages sent\n"); 1232 1232 - printk(KERN_DEBUG 1233 1233 - "stime: time spent sending messages\n"); 1234 1234 - printk(KERN_DEBUG 1235 1235 - "numuvhubs: number of hubs targeted with shootdown\n"); 1236 1236 - printk(KERN_DEBUG 1237 1237 - "numuvhubs16: number times 16 or more hubs targeted\n"); 1238 1238 - printk(KERN_DEBUG 1239 1239 - "numuvhubs8: number times 8 or more hubs targeted\n"); 1240 1240 - printk(KERN_DEBUG 1241 1241 - "numuvhubs4: number times 4 or more hubs targeted\n"); 1242 1242 - printk(KERN_DEBUG 1243 1243 - "numuvhubs2: number times 2 or more hubs targeted\n"); 1244 1244 - printk(KERN_DEBUG 1245 1245 - "numuvhubs1: number times 1 hub targeted\n"); 1246 1246 - printk(KERN_DEBUG 1247 1247 - "numcpus: number of cpus targeted with shootdown\n"); 1248 1248 - printk(KERN_DEBUG 1249 1249 - "dto: number of destination timeouts\n"); 1250 1250 - printk(KERN_DEBUG 1251 1251 - "retries: destination timeout retries sent\n"); 1252 1252 - printk(KERN_DEBUG 1253 1253 - "rok: : destination timeouts successfully retried\n"); 1254 1254 - printk(KERN_DEBUG 1255 1255 - "resetp: ipi-style resource resets for plugs\n"); 1256 1256 - printk(KERN_DEBUG 1257 1257 - "resett: ipi-style resource resets for timeouts\n"); 1258 1258 - printk(KERN_DEBUG 1259 1259 - "giveup: fall-backs to ipi-style shootdowns\n"); 1260 1260 - printk(KERN_DEBUG 1261 1261 - "sto: number of source timeouts\n"); 1262 1262 - printk(KERN_DEBUG 1263 1263 - "bz: number of stay-busy's\n"); 1264 1264 - printk(KERN_DEBUG 1265 1265 - "throt: number times spun in throttle\n"); 1266 1266 - printk(KERN_DEBUG "Destination side statistics:\n"); 1267 1267 - printk(KERN_DEBUG 1268 1268 - "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n"); 1269 1269 - printk(KERN_DEBUG 1270 1270 - "recv: shootdown messages received\n"); 1271 1271 - printk(KERN_DEBUG 1272 1272 - "rtime: time spent processing messages\n"); 1273 1273 - printk(KERN_DEBUG 1274 1274 - "all: shootdown all-tlb messages\n"); 1275 1275 - printk(KERN_DEBUG 1276 1276 - "one: shootdown one-tlb messages\n"); 1277 1277 - printk(KERN_DEBUG 1278 1278 - "mult: interrupts that found multiple messages\n"); 1279 1279 - printk(KERN_DEBUG 1280 1280 - "none: interrupts that found no messages\n"); 1281 1281 - printk(KERN_DEBUG 1282 1282 - "retry: number of retry messages processed\n"); 1283 1283 - printk(KERN_DEBUG 1284 1284 - "canc: number messages canceled by retries\n"); 1285 1285 - printk(KERN_DEBUG 1286 1286 - "nocan: number retries that found nothing to cancel\n"); 1287 1287 - printk(KERN_DEBUG 1288 1288 - "reset: number of ipi-style reset requests processed\n"); 1289 1289 - printk(KERN_DEBUG 1290 1290 - "rcan: number messages canceled by reset requests\n"); 1291 1291 - printk(KERN_DEBUG 1292 1292 - "disable: number times use of the BAU was disabled\n"); 1293 1293 - printk(KERN_DEBUG 1294 1294 - "enable: number times use of the BAU was re-enabled\n"); 1059 1059 + for (i = 0; i < elements; i++) 1060 1060 + printk(KERN_DEBUG "%s\n", stat_description[i]); 1295 1061 } else if (input_arg == -1) { 1296 1062 for_each_present_cpu(cpu) { 1297 1063 stat = &per_cpu(ptcstats, cpu); ··· 1257 1145 } 1258 1146 1259 1147 /* 1260 1260 - * set the tunables 1261 1261 - * 0 values reset them to defaults 1148 1148 + * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables. 1149 1149 + * Zero values reset them to defaults. 1262 1150 */ 1263 1263 - static ssize_t tunables_write(struct file *file, const char __user *user, 1264 1264 - size_t count, loff_t *data) 1151 1151 + static int parse_tunables_write(struct bau_control *bcp, char *instr, 1152 1152 + int count) 1265 1153 { 1266 1266 - int cpu; 1267 1267 - int cnt = 0; 1268 1268 - int val; 1269 1154 char *p; 1270 1155 char *q; 1271 1271 - char instr[64]; 1272 1272 - struct bau_control *bcp; 1156 1156 + int cnt = 0; 1157 1157 + int val; 1158 1158 + int e = sizeof(tunables) / sizeof(*tunables); 1273 1159 1274 1274 - if (count == 0 || count > sizeof(instr)-1) 1275 1275 - return -EINVAL; 1276 1276 - if (copy_from_user(instr, user, count)) 1277 1277 - return -EFAULT; 1278 1278 - 1279 1279 - instr[count] = '\0'; 1280 1280 - /* count the fields */ 1281 1160 p = instr + strspn(instr, WHITESPACE); 1282 1161 q = p; 1283 1162 for (; *p; p = q + strspn(q, WHITESPACE)) { ··· 1277 1174 if (q == p) 1278 1175 break; 1279 1176 } 1280 1280 - if (cnt != 9) { 1281 1281 - printk(KERN_INFO "bau tunable error: should be 9 numbers\n"); 1177 1177 + if (cnt != e) { 1178 1178 + printk(KERN_INFO "bau tunable error: should be %d values\n", e); 1282 1179 return -EINVAL; 1283 1180 } 1284 1181 ··· 1290 1187 switch (cnt) { 1291 1188 case 0: 1292 1189 if (val == 0) { 1293 1293 - max_bau_concurrent = MAX_BAU_CONCURRENT; 1294 1294 - max_bau_concurrent_constant = 1295 1295 - MAX_BAU_CONCURRENT; 1190 1190 + max_concurr = MAX_BAU_CONCURRENT; 1191 1191 + max_concurr_const = MAX_BAU_CONCURRENT; 1296 1192 continue; 1297 1193 } 1298 1298 - bcp = &per_cpu(bau_control, smp_processor_id()); 1299 1194 if (val < 1 || val > bcp->cpus_in_uvhub) { 1300 1195 printk(KERN_DEBUG 1301 1196 "Error: BAU max concurrent %d is invalid\n", 1302 1197 val); 1303 1198 return -EINVAL; 1304 1199 } 1305 1305 - max_bau_concurrent = val; 1306 1306 - max_bau_concurrent_constant = val; 1200 1200 + max_concurr = val; 1201 1201 + max_concurr_const = val; 1307 1202 continue; 1308 1308 - case 1: 1203 1203 + default: 1309 1204 if (val == 0) 1310 1310 - plugged_delay = PLUGGED_DELAY; 1205 1205 + *tunables[cnt].tunp = tunables[cnt].deflt; 1311 1206 else 1312 1312 - plugged_delay = val; 1313 1313 - continue; 1314 1314 - case 2: 1315 1315 - if (val == 0) 1316 1316 - plugsb4reset = PLUGSB4RESET; 1317 1317 - else 1318 1318 - plugsb4reset = val; 1319 1319 - continue; 1320 1320 - case 3: 1321 1321 - if (val == 0) 1322 1322 - timeoutsb4reset = TIMEOUTSB4RESET; 1323 1323 - else 1324 1324 - timeoutsb4reset = val; 1325 1325 - continue; 1326 1326 - case 4: 1327 1327 - if (val == 0) 1328 1328 - ipi_reset_limit = IPI_RESET_LIMIT; 1329 1329 - else 1330 1330 - ipi_reset_limit = val; 1331 1331 - continue; 1332 1332 - case 5: 1333 1333 - if (val == 0) 1334 1334 - complete_threshold = COMPLETE_THRESHOLD; 1335 1335 - else 1336 1336 - complete_threshold = val; 1337 1337 - continue; 1338 1338 - case 6: 1339 1339 - if (val == 0) 1340 1340 - congested_response_us = CONGESTED_RESPONSE_US; 1341 1341 - else 1342 1342 - congested_response_us = val; 1343 1343 - continue; 1344 1344 - case 7: 1345 1345 - if (val == 0) 1346 1346 - congested_reps = CONGESTED_REPS; 1347 1347 - else 1348 1348 - congested_reps = val; 1349 1349 - continue; 1350 1350 - case 8: 1351 1351 - if (val == 0) 1352 1352 - congested_period = CONGESTED_PERIOD; 1353 1353 - else 1354 1354 - congested_period = val; 1207 1207 + *tunables[cnt].tunp = val; 1355 1208 continue; 1356 1209 } 1357 1210 if (q == p) 1358 1211 break; 1359 1212 } 1213 1213 + return 0; 1214 1214 + } 1215 1215 + 1216 1216 + /* 1217 1217 + * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables) 1218 1218 + */ 1219 1219 + static ssize_t tunables_write(struct file *file, const char __user *user, 1220 1220 + size_t count, loff_t *data) 1221 1221 + { 1222 1222 + int cpu; 1223 1223 + int ret; 1224 1224 + char instr[100]; 1225 1225 + struct bau_control *bcp; 1226 1226 + 1227 1227 + if (count == 0 || count > sizeof(instr)-1) 1228 1228 + return -EINVAL; 1229 1229 + if (copy_from_user(instr, user, count)) 1230 1230 + return -EFAULT; 1231 1231 + 1232 1232 + instr[count] = '\0'; 1233 1233 + 1234 1234 + bcp = &per_cpu(bau_control, smp_processor_id()); 1235 1235 + 1236 1236 + ret = parse_tunables_write(bcp, instr, count); 1237 1237 + if (ret) 1238 1238 + return ret; 1239 1239 + 1360 1240 for_each_present_cpu(cpu) { 1361 1241 bcp = &per_cpu(bau_control, cpu); 1362 1362 - bcp->max_bau_concurrent = max_bau_concurrent; 1363 1363 - bcp->max_bau_concurrent_constant = max_bau_concurrent; 1364 1364 - bcp->plugged_delay = plugged_delay; 1365 1365 - bcp->plugsb4reset = plugsb4reset; 1366 1366 - bcp->timeoutsb4reset = timeoutsb4reset; 1367 1367 - bcp->ipi_reset_limit = ipi_reset_limit; 1368 1368 - bcp->complete_threshold = complete_threshold; 1369 1369 - bcp->congested_response_us = congested_response_us; 1370 1370 - bcp->congested_reps = congested_reps; 1371 1371 - bcp->congested_period = congested_period; 1242 1242 + bcp->max_concurr = max_concurr; 1243 1243 + bcp->max_concurr_const = max_concurr; 1244 1244 + bcp->plugged_delay = plugged_delay; 1245 1245 + bcp->plugsb4reset = plugsb4reset; 1246 1246 + bcp->timeoutsb4reset = timeoutsb4reset; 1247 1247 + bcp->ipi_reset_limit = ipi_reset_limit; 1248 1248 + bcp->complete_threshold = complete_threshold; 1249 1249 + bcp->cong_response_us = congested_respns_us; 1250 1250 + bcp->cong_reps = congested_reps; 1251 1251 + bcp->cong_period = congested_period; 1372 1252 } 1373 1253 return count; 1374 1254 } 1375 1255 1376 1256 static const struct seq_operations uv_ptc_seq_ops = { 1377 1377 - .start = uv_ptc_seq_start, 1378 1378 - .next = uv_ptc_seq_next, 1379 1379 - .stop = uv_ptc_seq_stop, 1380 1380 - .show = uv_ptc_seq_show 1257 1257 + .start = ptc_seq_start, 1258 1258 + .next = ptc_seq_next, 1259 1259 + .stop = ptc_seq_stop, 1260 1260 + .show = ptc_seq_show 1381 1261 }; 1382 1262 1383 1383 - static int uv_ptc_proc_open(struct inode *inode, struct file *file) 1263 1263 + static int ptc_proc_open(struct inode *inode, struct file *file) 1384 1264 { 1385 1265 return seq_open(file, &uv_ptc_seq_ops); 1386 1266 } ··· 1374 1288 } 1375 1289 1376 1290 static const struct file_operations proc_uv_ptc_operations = { 1377 1377 - .open = uv_ptc_proc_open, 1291 1291 + .open = ptc_proc_open, 1378 1292 .read = seq_read, 1379 1379 - .write = uv_ptc_proc_write, 1293 1293 + .write = ptc_proc_write, 1380 1294 .llseek = seq_lseek, 1381 1295 .release = seq_release, 1382 1296 }; ··· 1410 1324 return -EINVAL; 1411 1325 } 1412 1326 tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600, 1413 1413 - tunables_dir, NULL, &tunables_fops); 1327 1327 + tunables_dir, NULL, &tunables_fops); 1414 1328 if (!tunables_file) { 1415 1329 printk(KERN_ERR "unable to create debugfs file %s\n", 1416 1330 UV_BAU_TUNABLES_FILE); ··· 1422 1336 /* 1423 1337 * Initialize the sending side's sending buffers. 1424 1338 */ 1425 1425 - static void 1426 1426 - uv_activation_descriptor_init(int node, int pnode, int base_pnode) 1339 1339 + static void activation_descriptor_init(int node, int pnode, int base_pnode) 1427 1340 { 1428 1341 int i; 1429 1342 int cpu; 1430 1343 unsigned long pa; 1431 1344 unsigned long m; 1432 1345 unsigned long n; 1346 1346 + size_t dsize; 1433 1347 struct bau_desc *bau_desc; 1434 1348 struct bau_desc *bd2; 1435 1349 struct bau_control *bcp; 1436 1350 1437 1351 /* 1438 1438 - * each bau_desc is 64 bytes; there are 8 (UV_ITEMS_PER_DESCRIPTOR) 1439 1439 - * per cpu; and one per cpu on the uvhub (UV_ADP_SIZE) 1352 1352 + * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC) 1353 1353 + * per cpu; and one per cpu on the uvhub (ADP_SZ) 1440 1354 */ 1441 1441 - bau_desc = kmalloc_node(sizeof(struct bau_desc) * UV_ADP_SIZE 1442 1442 - * UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node); 1355 1355 + dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC; 1356 1356 + bau_desc = kmalloc_node(dsize, GFP_KERNEL, node); 1443 1357 BUG_ON(!bau_desc); 1444 1358 1445 1359 pa = uv_gpa(bau_desc); /* need the real nasid*/ ··· 1447 1361 m = pa & uv_mmask; 1448 1362 1449 1363 /* the 14-bit pnode */ 1450 1450 - uv_write_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, 1451 1451 - (n << UV_DESC_BASE_PNODE_SHIFT | m)); 1364 1364 + write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m)); 1452 1365 /* 1453 1453 - * Initializing all 8 (UV_ITEMS_PER_DESCRIPTOR) descriptors for each 1366 1366 + * Initializing all 8 (ITEMS_PER_DESC) descriptors for each 1454 1367 * cpu even though we only use the first one; one descriptor can 1455 1368 * describe a broadcast to 256 uv hubs. 1456 1369 */ 1457 1457 - for (i = 0, bd2 = bau_desc; i < (UV_ADP_SIZE*UV_ITEMS_PER_DESCRIPTOR); 1458 1458 - i++, bd2++) { 1370 1370 + for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) { 1459 1371 memset(bd2, 0, sizeof(struct bau_desc)); 1460 1460 - bd2->header.sw_ack_flag = 1; 1372 1372 + bd2->header.swack_flag = 1; 1461 1373 /* 1462 1374 * The base_dest_nasid set in the message header is the nasid 1463 1375 * of the first uvhub in the partition. The bit map will 1464 1376 * indicate destination pnode numbers relative to that base. 1465 1377 * They may not be consecutive if nasid striding is being used. 1466 1378 */ 1467 1467 - bd2->header.base_dest_nasid = UV_PNODE_TO_NASID(base_pnode); 1468 1468 - bd2->header.dest_subnodeid = UV_LB_SUBNODEID; 1469 1469 - bd2->header.command = UV_NET_ENDPOINT_INTD; 1470 1470 - bd2->header.int_both = 1; 1379 1379 + bd2->header.base_dest_nasid = UV_PNODE_TO_NASID(base_pnode); 1380 1380 + bd2->header.dest_subnodeid = UV_LB_SUBNODEID; 1381 1381 + bd2->header.command = UV_NET_ENDPOINT_INTD; 1382 1382 + bd2->header.int_both = 1; 1471 1383 /* 1472 1384 * all others need to be set to zero: 1473 1385 * fairness chaining multilevel count replied_to ··· 1485 1401 * - node is first node (kernel memory notion) on the uvhub 1486 1402 * - pnode is the uvhub's physical identifier 1487 1403 */ 1488 1488 - static void 1489 1489 - uv_payload_queue_init(int node, int pnode) 1404 1404 + static void pq_init(int node, int pnode) 1490 1405 { 1491 1491 - int pn; 1492 1406 int cpu; 1407 1407 + size_t plsize; 1493 1408 char *cp; 1494 1494 - unsigned long pa; 1495 1495 - struct bau_payload_queue_entry *pqp; 1496 1496 - struct bau_payload_queue_entry *pqp_malloc; 1409 1409 + void *vp; 1410 1410 + unsigned long pn; 1411 1411 + unsigned long first; 1412 1412 + unsigned long pn_first; 1413 1413 + unsigned long last; 1414 1414 + struct bau_pq_entry *pqp; 1497 1415 struct bau_control *bcp; 1498 1416 1499 1499 - pqp = kmalloc_node((DEST_Q_SIZE + 1) 1500 1500 - * sizeof(struct bau_payload_queue_entry), 1501 1501 - GFP_KERNEL, node); 1417 1417 + plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry); 1418 1418 + vp = kmalloc_node(plsize, GFP_KERNEL, node); 1419 1419 + pqp = (struct bau_pq_entry *)vp; 1502 1420 BUG_ON(!pqp); 1503 1503 - pqp_malloc = pqp; 1504 1421 1505 1422 cp = (char *)pqp + 31; 1506 1506 - pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5); 1423 1423 + pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5); 1507 1424 1508 1425 for_each_present_cpu(cpu) { 1509 1426 if (pnode != uv_cpu_to_pnode(cpu)) 1510 1427 continue; 1511 1428 /* for every cpu on this pnode: */ 1512 1429 bcp = &per_cpu(bau_control, cpu); 1513 1513 - bcp->va_queue_first = pqp; 1514 1514 - bcp->bau_msg_head = pqp; 1515 1515 - bcp->va_queue_last = pqp + (DEST_Q_SIZE - 1); 1430 1430 + bcp->queue_first = pqp; 1431 1431 + bcp->bau_msg_head = pqp; 1432 1432 + bcp->queue_last = pqp + (DEST_Q_SIZE - 1); 1516 1433 } 1517 1434 /* 1518 1435 * need the pnode of where the memory was really allocated 1519 1436 */ 1520 1520 - pa = uv_gpa(pqp); 1521 1521 - pn = pa >> uv_nshift; 1522 1522 - uv_write_global_mmr64(pnode, 1523 1523 - UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, 1524 1524 - ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | 1525 1525 - uv_physnodeaddr(pqp)); 1526 1526 - uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, 1527 1527 - uv_physnodeaddr(pqp)); 1528 1528 - uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, 1529 1529 - (unsigned long) 1530 1530 - uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1))); 1437 1437 + pn = uv_gpa(pqp) >> uv_nshift; 1438 1438 + first = uv_physnodeaddr(pqp); 1439 1439 + pn_first = ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | first; 1440 1440 + last = uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1)); 1441 1441 + write_mmr_payload_first(pnode, pn_first); 1442 1442 + write_mmr_payload_tail(pnode, first); 1443 1443 + write_mmr_payload_last(pnode, last); 1444 1444 + 1531 1445 /* in effect, all msg_type's are set to MSG_NOOP */ 1532 1532 - memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE); 1446 1446 + memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE); 1533 1447 } 1534 1448 1535 1449 /* 1536 1450 * Initialization of each UV hub's structures 1537 1451 */ 1538 1538 - static void __init uv_init_uvhub(int uvhub, int vector, int base_pnode) 1452 1452 + static void __init init_uvhub(int uvhub, int vector, int base_pnode) 1539 1453 { 1540 1454 int node; 1541 1455 int pnode; ··· 1541 1459 1542 1460 node = uvhub_to_first_node(uvhub); 1543 1461 pnode = uv_blade_to_pnode(uvhub); 1544 1544 - uv_activation_descriptor_init(node, pnode, base_pnode); 1545 1545 - uv_payload_queue_init(node, pnode); 1462 1462 + 1463 1463 + activation_descriptor_init(node, pnode, base_pnode); 1464 1464 + 1465 1465 + pq_init(node, pnode); 1546 1466 /* 1547 1467 * The below initialization can't be in firmware because the 1548 1468 * messaging IRQ will be determined by the OS. 1549 1469 */ 1550 1470 apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits; 1551 1551 - uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, 1552 1552 - ((apicid << 32) | vector)); 1471 1471 + write_mmr_data_config(pnode, ((apicid << 32) | vector)); 1553 1472 } 1554 1473 1555 1474 /* 1556 1475 * We will set BAU_MISC_CONTROL with a timeout period. 1557 1476 * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT. 1558 1558 - * So the destination timeout period has be be calculated from them. 1477 1477 + * So the destination timeout period has to be calculated from them. 1559 1478 */ 1560 1560 - static int 1561 1561 - calculate_destination_timeout(void) 1479 1479 + static int calculate_destination_timeout(void) 1562 1480 { 1563 1481 unsigned long mmr_image; 1564 1482 int mult1; ··· 1568 1486 int ret; 1569 1487 unsigned long ts_ns; 1570 1488 1571 1571 - mult1 = UV_INTD_SOFT_ACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK; 1572 1572 - mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); 1573 1573 - index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK; 1574 1574 - mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT); 1575 1575 - mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK; 1576 1576 - base = timeout_base_ns[index]; 1577 1577 - ts_ns = base * mult1 * mult2; 1578 1578 - ret = ts_ns / 1000; 1489 1489 + if (is_uv1_hub()) { 1490 1490 + mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK; 1491 1491 + mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); 1492 1492 + index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK; 1493 1493 + mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT); 1494 1494 + mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK; 1495 1495 + base = timeout_base_ns[index]; 1496 1496 + ts_ns = base * mult1 * mult2; 1497 1497 + ret = ts_ns / 1000; 1498 1498 + } else { 1499 1499 + /* 4 bits 0/1 for 10/80us, 3 bits of multiplier */ 1500 1500 + mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); 1501 1501 + mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT; 1502 1502 + if (mmr_image & (1L << UV2_ACK_UNITS_SHFT)) 1503 1503 + mult1 = 80; 1504 1504 + else 1505 1505 + mult1 = 10; 1506 1506 + base = mmr_image & UV2_ACK_MASK; 1507 1507 + ret = mult1 * base; 1508 1508 + } 1579 1509 return ret; 1580 1510 } 1581 1511 1582 1582 - /* 1583 1583 - * initialize the bau_control structure for each cpu 1584 1584 - */ 1585 1585 - static int __init uv_init_per_cpu(int nuvhubs, int base_part_pnode) 1512 1512 + static void __init init_per_cpu_tunables(void) 1586 1513 { 1587 1587 - int i; 1588 1514 int cpu; 1589 1589 - int tcpu; 1515 1515 + struct bau_control *bcp; 1516 1516 + 1517 1517 + for_each_present_cpu(cpu) { 1518 1518 + bcp = &per_cpu(bau_control, cpu); 1519 1519 + bcp->baudisabled = 0; 1520 1520 + bcp->statp = &per_cpu(ptcstats, cpu); 1521 1521 + /* time interval to catch a hardware stay-busy bug */ 1522 1522 + bcp->timeout_interval = usec_2_cycles(2*timeout_us); 1523 1523 + bcp->max_concurr = max_concurr; 1524 1524 + bcp->max_concurr_const = max_concurr; 1525 1525 + bcp->plugged_delay = plugged_delay; 1526 1526 + bcp->plugsb4reset = plugsb4reset; 1527 1527 + bcp->timeoutsb4reset = timeoutsb4reset; 1528 1528 + bcp->ipi_reset_limit = ipi_reset_limit; 1529 1529 + bcp->complete_threshold = complete_threshold; 1530 1530 + bcp->cong_response_us = congested_respns_us; 1531 1531 + bcp->cong_reps = congested_reps; 1532 1532 + bcp->cong_period = congested_period; 1533 1533 + } 1534 1534 + } 1535 1535 + 1536 1536 + /* 1537 1537 + * Scan all cpus to collect blade and socket summaries. 1538 1538 + */ 1539 1539 + static int __init get_cpu_topology(int base_pnode, 1540 1540 + struct uvhub_desc *uvhub_descs, 1541 1541 + unsigned char *uvhub_mask) 1542 1542 + { 1543 1543 + int cpu; 1590 1544 int pnode; 1591 1545 int uvhub; 1592 1592 - int have_hmaster; 1593 1593 - short socket = 0; 1594 1594 - unsigned short socket_mask; 1595 1595 - unsigned char *uvhub_mask; 1546 1546 + int socket; 1596 1547 struct bau_control *bcp; 1597 1548 struct uvhub_desc *bdp; 1598 1549 struct socket_desc *sdp; 1599 1599 - struct bau_control *hmaster = NULL; 1600 1600 - struct bau_control *smaster = NULL; 1601 1601 - struct socket_desc { 1602 1602 - short num_cpus; 1603 1603 - short cpu_number[MAX_CPUS_PER_SOCKET]; 1604 1604 - }; 1605 1605 - struct uvhub_desc { 1606 1606 - unsigned short socket_mask; 1607 1607 - short num_cpus; 1608 1608 - short uvhub; 1609 1609 - short pnode; 1610 1610 - struct socket_desc socket[2]; 1611 1611 - }; 1612 1612 - struct uvhub_desc *uvhub_descs; 1613 1550 1614 1614 - timeout_us = calculate_destination_timeout(); 1615 1615 - 1616 1616 - uvhub_descs = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL); 1617 1617 - memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc)); 1618 1618 - uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL); 1619 1551 for_each_present_cpu(cpu) { 1620 1552 bcp = &per_cpu(bau_control, cpu); 1553 1553 + 1621 1554 memset(bcp, 0, sizeof(struct bau_control)); 1555 1555 + 1622 1556 pnode = uv_cpu_hub_info(cpu)->pnode; 1623 1623 - if ((pnode - base_part_pnode) >= UV_DISTRIBUTION_SIZE) { 1557 1557 + if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) { 1624 1558 printk(KERN_EMERG 1625 1559 "cpu %d pnode %d-%d beyond %d; BAU disabled\n", 1626 1626 - cpu, pnode, base_part_pnode, 1627 1627 - UV_DISTRIBUTION_SIZE); 1560 1560 + cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE); 1628 1561 return 1; 1629 1562 } 1563 1563 + 1630 1564 bcp->osnode = cpu_to_node(cpu); 1631 1631 - bcp->partition_base_pnode = uv_partition_base_pnode; 1565 1565 + bcp->partition_base_pnode = base_pnode; 1566 1566 + 1632 1567 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; 1633 1568 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8)); 1634 1569 bdp = &uvhub_descs[uvhub]; 1570 1570 + 1635 1571 bdp->num_cpus++; 1636 1572 bdp->uvhub = uvhub; 1637 1573 bdp->pnode = pnode; 1574 1574 + 1638 1575 /* kludge: 'assuming' one node per socket, and assuming that 1639 1576 disabling a socket just leaves a gap in node numbers */ 1640 1577 socket = bcp->osnode & 1; ··· 1662 1561 sdp->cpu_number[sdp->num_cpus] = cpu; 1663 1562 sdp->num_cpus++; 1664 1563 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) { 1665 1665 - printk(KERN_EMERG "%d cpus per socket invalid\n", sdp->num_cpus); 1564 1564 + printk(KERN_EMERG "%d cpus per socket invalid\n", 1565 1565 + sdp->num_cpus); 1666 1566 return 1; 1667 1567 } 1668 1568 } 1569 1569 + return 0; 1570 1570 + } 1571 1571 + 1572 1572 + /* 1573 1573 + * Each socket is to get a local array of pnodes/hubs. 1574 1574 + */ 1575 1575 + static void make_per_cpu_thp(struct bau_control *smaster) 1576 1576 + { 1577 1577 + int cpu; 1578 1578 + size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus(); 1579 1579 + 1580 1580 + smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode); 1581 1581 + memset(smaster->thp, 0, hpsz); 1582 1582 + for_each_present_cpu(cpu) { 1583 1583 + smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode; 1584 1584 + smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; 1585 1585 + } 1586 1586 + } 1587 1587 + 1588 1588 + /* 1589 1589 + * Initialize all the per_cpu information for the cpu's on a given socket, 1590 1590 + * given what has been gathered into the socket_desc struct. 1591 1591 + * And reports the chosen hub and socket masters back to the caller. 1592 1592 + */ 1593 1593 + static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp, 1594 1594 + struct bau_control **smasterp, 1595 1595 + struct bau_control **hmasterp) 1596 1596 + { 1597 1597 + int i; 1598 1598 + int cpu; 1599 1599 + struct bau_control *bcp; 1600 1600 + 1601 1601 + for (i = 0; i < sdp->num_cpus; i++) { 1602 1602 + cpu = sdp->cpu_number[i]; 1603 1603 + bcp = &per_cpu(bau_control, cpu); 1604 1604 + bcp->cpu = cpu; 1605 1605 + if (i == 0) { 1606 1606 + *smasterp = bcp; 1607 1607 + if (!(*hmasterp)) 1608 1608 + *hmasterp = bcp; 1609 1609 + } 1610 1610 + bcp->cpus_in_uvhub = bdp->num_cpus; 1611 1611 + bcp->cpus_in_socket = sdp->num_cpus; 1612 1612 + bcp->socket_master = *smasterp; 1613 1613 + bcp->uvhub = bdp->uvhub; 1614 1614 + bcp->uvhub_master = *hmasterp; 1615 1615 + bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id; 1616 1616 + if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { 1617 1617 + printk(KERN_EMERG "%d cpus per uvhub invalid\n", 1618 1618 + bcp->uvhub_cpu); 1619 1619 + return 1; 1620 1620 + } 1621 1621 + } 1622 1622 + return 0; 1623 1623 + } 1624 1624 + 1625 1625 + /* 1626 1626 + * Summarize the blade and socket topology into the per_cpu structures. 1627 1627 + */ 1628 1628 + static int __init summarize_uvhub_sockets(int nuvhubs, 1629 1629 + struct uvhub_desc *uvhub_descs, 1630 1630 + unsigned char *uvhub_mask) 1631 1631 + { 1632 1632 + int socket; 1633 1633 + int uvhub; 1634 1634 + unsigned short socket_mask; 1635 1635 + 1669 1636 for (uvhub = 0; uvhub < nuvhubs; uvhub++) { 1637 1637 + struct uvhub_desc *bdp; 1638 1638 + struct bau_control *smaster = NULL; 1639 1639 + struct bau_control *hmaster = NULL; 1640 1640 + 1670 1641 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8)))) 1671 1642 continue; 1672 1672 - have_hmaster = 0; 1643 1643 + 1673 1644 bdp = &uvhub_descs[uvhub]; 1674 1645 socket_mask = bdp->socket_mask; 1675 1646 socket = 0; 1676 1647 while (socket_mask) { 1677 1677 - if (!(socket_mask & 1)) 1678 1678 - goto nextsocket; 1679 1679 - sdp = &bdp->socket[socket]; 1680 1680 - for (i = 0; i < sdp->num_cpus; i++) { 1681 1681 - cpu = sdp->cpu_number[i]; 1682 1682 - bcp = &per_cpu(bau_control, cpu); 1683 1683 - bcp->cpu = cpu; 1684 1684 - if (i == 0) { 1685 1685 - smaster = bcp; 1686 1686 - if (!have_hmaster) { 1687 1687 - have_hmaster++; 1688 1688 - hmaster = bcp; 1689 1689 - } 1690 1690 - } 1691 1691 - bcp->cpus_in_uvhub = bdp->num_cpus; 1692 1692 - bcp->cpus_in_socket = sdp->num_cpus; 1693 1693 - bcp->socket_master = smaster; 1694 1694 - bcp->uvhub = bdp->uvhub; 1695 1695 - bcp->uvhub_master = hmaster; 1696 1696 - bcp->uvhub_cpu = uv_cpu_hub_info(cpu)-> 1697 1697 - blade_processor_id; 1698 1698 - if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { 1699 1699 - printk(KERN_EMERG 1700 1700 - "%d cpus per uvhub invalid\n", 1701 1701 - bcp->uvhub_cpu); 1648 1648 + struct socket_desc *sdp; 1649 1649 + if ((socket_mask & 1)) { 1650 1650 + sdp = &bdp->socket[socket]; 1651 1651 + if (scan_sock(sdp, bdp, &smaster, &hmaster)) 1702 1652 return 1; 1703 1703 - } 1704 1653 } 1705 1705 - nextsocket: 1706 1654 socket++; 1707 1655 socket_mask = (socket_mask >> 1); 1708 1708 - /* each socket gets a local array of pnodes/hubs */ 1709 1709 - bcp = smaster; 1710 1710 - bcp->target_hub_and_pnode = kmalloc_node( 1711 1711 - sizeof(struct hub_and_pnode) * 1712 1712 - num_possible_cpus(), GFP_KERNEL, bcp->osnode); 1713 1713 - memset(bcp->target_hub_and_pnode, 0, 1714 1714 - sizeof(struct hub_and_pnode) * 1715 1715 - num_possible_cpus()); 1716 1716 - for_each_present_cpu(tcpu) { 1717 1717 - bcp->target_hub_and_pnode[tcpu].pnode = 1718 1718 - uv_cpu_hub_info(tcpu)->pnode; 1719 1719 - bcp->target_hub_and_pnode[tcpu].uvhub = 1720 1720 - uv_cpu_hub_info(tcpu)->numa_blade_id; 1721 1721 - } 1656 1656 + make_per_cpu_thp(smaster); 1722 1657 } 1723 1658 } 1659 1659 + return 0; 1660 1660 + } 1661 1661 + 1662 1662 + /* 1663 1663 + * initialize the bau_control structure for each cpu 1664 1664 + */ 1665 1665 + static int __init init_per_cpu(int nuvhubs, int base_part_pnode) 1666 1666 + { 1667 1667 + unsigned char *uvhub_mask; 1668 1668 + void *vp; 1669 1669 + struct uvhub_desc *uvhub_descs; 1670 1670 + 1671 1671 + timeout_us = calculate_destination_timeout(); 1672 1672 + 1673 1673 + vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL); 1674 1674 + uvhub_descs = (struct uvhub_desc *)vp; 1675 1675 + memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc)); 1676 1676 + uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL); 1677 1677 + 1678 1678 + if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask)) 1679 1679 + return 1; 1680 1680 + 1681 1681 + if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask)) 1682 1682 + return 1; 1683 1683 + 1724 1684 kfree(uvhub_descs); 1725 1685 kfree(uvhub_mask); 1726 1726 - for_each_present_cpu(cpu) { 1727 1727 - bcp = &per_cpu(bau_control, cpu); 1728 1728 - bcp->baudisabled = 0; 1729 1729 - bcp->statp = &per_cpu(ptcstats, cpu); 1730 1730 - /* time interval to catch a hardware stay-busy bug */ 1731 1731 - bcp->timeout_interval = microsec_2_cycles(2*timeout_us); 1732 1732 - bcp->max_bau_concurrent = max_bau_concurrent; 1733 1733 - bcp->max_bau_concurrent_constant = max_bau_concurrent; 1734 1734 - bcp->plugged_delay = plugged_delay; 1735 1735 - bcp->plugsb4reset = plugsb4reset; 1736 1736 - bcp->timeoutsb4reset = timeoutsb4reset; 1737 1737 - bcp->ipi_reset_limit = ipi_reset_limit; 1738 1738 - bcp->complete_threshold = complete_threshold; 1739 1739 - bcp->congested_response_us = congested_response_us; 1740 1740 - bcp->congested_reps = congested_reps; 1741 1741 - bcp->congested_period = congested_period; 1742 1742 - } 1686 1686 + init_per_cpu_tunables(); 1743 1687 return 0; 1744 1688 } 1745 1689 ··· 1797 1651 int pnode; 1798 1652 int nuvhubs; 1799 1653 int cur_cpu; 1654 1654 + int cpus; 1800 1655 int vector; 1801 1801 - unsigned long mmr; 1656 1656 + cpumask_var_t *mask; 1802 1657 1803 1658 if (!is_uv_system()) 1804 1659 return 0; ··· 1807 1660 if (nobau) 1808 1661 return 0; 1809 1662 1810 1810 - for_each_possible_cpu(cur_cpu) 1811 1811 - zalloc_cpumask_var_node(&per_cpu(uv_flush_tlb_mask, cur_cpu), 1812 1812 - GFP_KERNEL, cpu_to_node(cur_cpu)); 1663 1663 + for_each_possible_cpu(cur_cpu) { 1664 1664 + mask = &per_cpu(uv_flush_tlb_mask, cur_cpu); 1665 1665 + zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu)); 1666 1666 + } 1813 1667 1814 1668 uv_nshift = uv_hub_info->m_val; 1815 1669 uv_mmask = (1UL << uv_hub_info->m_val) - 1; 1816 1670 nuvhubs = uv_num_possible_blades(); 1817 1671 spin_lock_init(&disable_lock); 1818 1818 - congested_cycles = microsec_2_cycles(congested_response_us); 1672 1672 + congested_cycles = usec_2_cycles(congested_respns_us); 1819 1673 1820 1820 - uv_partition_base_pnode = 0x7fffffff; 1674 1674 + uv_base_pnode = 0x7fffffff; 1821 1675 for (uvhub = 0; uvhub < nuvhubs; uvhub++) { 1822 1822 - if (uv_blade_nr_possible_cpus(uvhub) && 1823 1823 - (uv_blade_to_pnode(uvhub) < uv_partition_base_pnode)) 1824 1824 - uv_partition_base_pnode = uv_blade_to_pnode(uvhub); 1676 1676 + cpus = uv_blade_nr_possible_cpus(uvhub); 1677 1677 + if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode)) 1678 1678 + uv_base_pnode = uv_blade_to_pnode(uvhub); 1825 1679 } 1826 1680 1827 1827 - if (uv_init_per_cpu(nuvhubs, uv_partition_base_pnode)) { 1681 1681 + if (init_per_cpu(nuvhubs, uv_base_pnode)) { 1828 1682 nobau = 1; 1829 1683 return 0; 1830 1684 } ··· 1833 1685 vector = UV_BAU_MESSAGE; 1834 1686 for_each_possible_blade(uvhub) 1835 1687 if (uv_blade_nr_possible_cpus(uvhub)) 1836 1836 - uv_init_uvhub(uvhub, vector, uv_partition_base_pnode); 1688 1688 + init_uvhub(uvhub, vector, uv_base_pnode); 1837 1689 1838 1838 - uv_enable_timeouts(); 1690 1690 + enable_timeouts(); 1839 1691 alloc_intr_gate(vector, uv_bau_message_intr1); 1840 1692 1841 1693 for_each_possible_blade(uvhub) { 1842 1694 if (uv_blade_nr_possible_cpus(uvhub)) { 1695 1695 + unsigned long val; 1696 1696 + unsigned long mmr; 1843 1697 pnode = uv_blade_to_pnode(uvhub); 1844 1698 /* INIT the bau */ 1845 1845 - uv_write_global_mmr64(pnode, 1846 1846 - UVH_LB_BAU_SB_ACTIVATION_CONTROL, 1847 1847 - ((unsigned long)1 << 63)); 1699 1699 + val = 1L << 63; 1700 1700 + write_gmmr_activation(pnode, val); 1848 1701 mmr = 1; /* should be 1 to broadcast to both sockets */ 1849 1849 - uv_write_global_mmr64(pnode, UVH_BAU_DATA_BROADCAST, 1850 1850 - mmr); 1702 1702 + write_mmr_data_broadcast(pnode, mmr); 1851 1703 } 1852 1704 } 1853 1705

+12 -4

arch/x86/platform/uv/uv_time.c

reviewed

··· 99 99 /* Check for an RTC interrupt pending */ 100 100 static int uv_intr_pending(int pnode) 101 101 { 102 102 - return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) & 103 103 - UVH_EVENT_OCCURRED0_RTC1_MASK; 102 102 + if (is_uv1_hub()) 103 103 + return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) & 104 104 + UV1H_EVENT_OCCURRED0_RTC1_MASK; 105 105 + else 106 106 + return uv_read_global_mmr64(pnode, UV2H_EVENT_OCCURRED2) & 107 107 + UV2H_EVENT_OCCURRED2_RTC_1_MASK; 104 108 } 105 109 106 110 /* Setup interrupt and return non-zero if early expiration occurred. */ ··· 118 114 UVH_RTC1_INT_CONFIG_M_MASK); 119 115 uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L); 120 116 121 121 - uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS, 122 122 - UVH_EVENT_OCCURRED0_RTC1_MASK); 117 117 + if (is_uv1_hub()) 118 118 + uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS, 119 119 + UV1H_EVENT_OCCURRED0_RTC1_MASK); 120 120 + else 121 121 + uv_write_global_mmr64(pnode, UV2H_EVENT_OCCURRED2_ALIAS, 122 122 + UV2H_EVENT_OCCURRED2_RTC_1_MASK); 123 123 124 124 val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) | 125 125 ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);

+1

include/linux/efi.h

reviewed

··· 299 299 struct resource *data_resource, struct resource *bss_resource); 300 300 extern unsigned long efi_get_time(void); 301 301 extern int efi_set_rtc_mmss(unsigned long nowtime); 302 302 + extern void efi_reserve_boot_services(void); 302 303 extern struct efi_memory_map memmap; 303 304 304 305 /**