Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

+4 -13

arch/sh/Kconfig

··· 448 448 Select Dreamcast if configuring for a SEGA Dreamcast. 449 449 More information at <http://www.linux-sh.org> 450 450 451 - config SH_MPC1211 452 - bool "Interface MPC1211" 453 - depends on CPU_SUBTYPE_SH7751 && BROKEN 454 - help 455 - CTP/PCI-SH02 is a CPU module computer that is produced 456 - by Interface Corporation. 457 - More information at <http://www.interface.co.jp> 458 - 459 451 config SH_SH03 460 452 bool "Interface CTP/PCI-SH03" 461 453 depends on CPU_SUBTYPE_SH7751 ··· 649 657 endmenu 650 658 651 659 config ISA_DMA_API 652 - def_bool y 653 - depends on SH_MPC1211 660 + bool 654 661 655 662 menu "Kernel features" 656 663 ··· 657 666 658 667 config KEXEC 659 668 bool "kexec system call (EXPERIMENTAL)" 660 - depends on EXPERIMENTAL 669 + depends on SUPERH32 && EXPERIMENTAL 661 670 help 662 671 kexec is a system call that implements the ability to shutdown your 663 672 current kernel, and to start another kernel. It is like a reboot ··· 674 683 675 684 config CRASH_DUMP 676 685 bool "kernel crash dumps (EXPERIMENTAL)" 677 - depends on EXPERIMENTAL 686 + depends on SUPERH32 && EXPERIMENTAL 678 687 help 679 688 Generate crash dump after being started by kexec. 680 689 This should be normally only set in special crash dump kernels ··· 754 763 755 764 config ZERO_PAGE_OFFSET 756 765 hex "Zero page offset" 757 - default "0x00004000" if SH_MPC1211 || SH_SH03 766 + default "0x00004000" if SH_SH03 758 767 default "0x00010000" if PAGE_SIZE_64KB 759 768 default "0x00002000" if PAGE_SIZE_8KB 760 769 default "0x00001000"

+1

arch/sh/Kconfig.debug

··· 7 7 8 8 config SH_STANDARD_BIOS 9 9 bool "Use LinuxSH standard BIOS" 10 + depends on SUPERH32 10 11 help 11 12 Say Y here if your target has the gdb-sh-stub 12 13 package from www.m17n.org (or any conforming standard LinuxSH BIOS)

-1

arch/sh/Makefile

··· 110 110 machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE) += se/7721 111 111 machdir-$(CONFIG_SH_HP6XX) += hp6xx 112 112 machdir-$(CONFIG_SH_DREAMCAST) += dreamcast 113 - machdir-$(CONFIG_SH_MPC1211) += mpc1211 114 113 machdir-$(CONFIG_SH_SH03) += sh03 115 114 machdir-$(CONFIG_SH_SECUREEDGE5410) += snapgear 116 115 machdir-$(CONFIG_SH_RTS7751R2D) += renesas/rts7751r2d

-8

arch/sh/boards/mpc1211/Makefile

··· 1 - # 2 - # Makefile for the Interface (CTP/PCI/MPC-SH02) specific parts of the kernel 3 - # 4 - 5 - obj-y := setup.o rtc.o 6 - 7 - obj-$(CONFIG_PCI) += pci.o 8 -

-295

arch/sh/boards/mpc1211/pci.c

··· 1 - /* 2 - * Low-Level PCI Support for the MPC-1211(CTP/PCI/MPC-SH02) 3 - * 4 - * (c) 2002-2003 Saito.K & Jeanne 5 - * 6 - * Dustin McIntire (dustin@sensoria.com) 7 - * Derived from arch/i386/kernel/pci-*.c which bore the message: 8 - * (c) 1999--2000 Martin Mares <mj@ucw.cz> 9 - * 10 - * May be copied or modified under the terms of the GNU General Public 11 - * License. See linux/COPYING for more information. 12 - * 13 - */ 14 - #include <linux/types.h> 15 - #include <linux/kernel.h> 16 - #include <linux/init.h> 17 - #include <linux/delay.h> 18 - #include <linux/pci.h> 19 - #include <linux/sched.h> 20 - #include <linux/ioport.h> 21 - #include <linux/errno.h> 22 - #include <linux/irq.h> 23 - #include <linux/interrupt.h> 24 - 25 - #include <asm/machvec.h> 26 - #include <asm/io.h> 27 - #include <asm/mpc1211/pci.h> 28 - 29 - static struct resource mpcpci_io_resource = { 30 - "MPCPCI IO", 31 - 0x00000000, 32 - 0xffffffff, 33 - IORESOURCE_IO 34 - }; 35 - 36 - static struct resource mpcpci_mem_resource = { 37 - "MPCPCI mem", 38 - 0x00000000, 39 - 0xffffffff, 40 - IORESOURCE_MEM 41 - }; 42 - 43 - static struct pci_ops pci_direct_conf1; 44 - struct pci_channel board_pci_channels[] = { 45 - {&pci_direct_conf1, &mpcpci_io_resource, &mpcpci_mem_resource, 0, 256}, 46 - {NULL, NULL, NULL, 0, 0}, 47 - }; 48 - 49 - /* 50 - * Direct access to PCI hardware... 51 - */ 52 - 53 - 54 - #define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) 55 - 56 - /* 57 - * Functions for accessing PCI configuration space with type 1 accesses 58 - */ 59 - static int pci_conf1_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) 60 - { 61 - u32 word; 62 - unsigned long flags; 63 - 64 - /* 65 - * PCIPDR may only be accessed as 32 bit words, 66 - * so we must do byte alignment by hand 67 - */ 68 - local_irq_save(flags); 69 - writel(CONFIG_CMD(bus,devfn,where), PCIPAR); 70 - word = readl(PCIPDR); 71 - local_irq_restore(flags); 72 - 73 - switch (size) { 74 - case 1: 75 - switch (where & 0x3) { 76 - case 3: 77 - *value = (u8)(word >> 24); 78 - break; 79 - case 2: 80 - *value = (u8)(word >> 16); 81 - break; 82 - case 1: 83 - *value = (u8)(word >> 8); 84 - break; 85 - default: 86 - *value = (u8)word; 87 - break; 88 - } 89 - break; 90 - case 2: 91 - switch (where & 0x3) { 92 - case 3: 93 - *value = (u16)(word >> 24); 94 - local_irq_save(flags); 95 - writel(CONFIG_CMD(bus,devfn,(where+1)), PCIPAR); 96 - word = readl(PCIPDR); 97 - local_irq_restore(flags); 98 - *value |= ((word & 0xff) << 8); 99 - break; 100 - case 2: 101 - *value = (u16)(word >> 16); 102 - break; 103 - case 1: 104 - *value = (u16)(word >> 8); 105 - break; 106 - default: 107 - *value = (u16)word; 108 - break; 109 - } 110 - break; 111 - case 4: 112 - *value = word; 113 - break; 114 - } 115 - PCIDBG(4,"pci_conf1_read@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),*value); 116 - return PCIBIOS_SUCCESSFUL; 117 - } 118 - 119 - /* 120 - * Since MPC-1211 only does 32bit access we'll have to do a read,mask,write operation. 121 - * We'll allow an odd byte offset, though it should be illegal. 122 - */ 123 - static int pci_conf1_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) 124 - { 125 - u32 word,mask = 0; 126 - unsigned long flags; 127 - u32 shift = (where & 3) * 8; 128 - 129 - if(size == 1) { 130 - mask = ((1 << 8) - 1) << shift; // create the byte mask 131 - } else if(size == 2){ 132 - if(shift == 24) 133 - return PCIBIOS_BAD_REGISTER_NUMBER; 134 - mask = ((1 << 16) - 1) << shift; // create the word mask 135 - } 136 - local_irq_save(flags); 137 - writel(CONFIG_CMD(bus,devfn,where), PCIPAR); 138 - if(size == 4){ 139 - writel(value, PCIPDR); 140 - local_irq_restore(flags); 141 - PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),value); 142 - return PCIBIOS_SUCCESSFUL; 143 - } 144 - word = readl(PCIPDR); 145 - word &= ~mask; 146 - word |= ((value << shift) & mask); 147 - writel(word, PCIPDR); 148 - local_irq_restore(flags); 149 - PCIDBG(4,"pci_conf1_write@0x%08x=0x%x\n", CONFIG_CMD(bus,devfn,where),word); 150 - return PCIBIOS_SUCCESSFUL; 151 - } 152 - 153 - #undef CONFIG_CMD 154 - 155 - static struct pci_ops pci_direct_conf1 = { 156 - .read = pci_conf1_read, 157 - .write = pci_conf1_write, 158 - }; 159 - 160 - static void __devinit quirk_ali_ide_ports(struct pci_dev *dev) 161 - { 162 - dev->resource[0].start = 0x1f0; 163 - dev->resource[0].end = 0x1f7; 164 - dev->resource[0].flags = IORESOURCE_IO; 165 - dev->resource[1].start = 0x3f6; 166 - dev->resource[1].end = 0x3f6; 167 - dev->resource[1].flags = IORESOURCE_IO; 168 - dev->resource[2].start = 0x170; 169 - dev->resource[2].end = 0x177; 170 - dev->resource[2].flags = IORESOURCE_IO; 171 - dev->resource[3].start = 0x376; 172 - dev->resource[3].end = 0x376; 173 - dev->resource[3].flags = IORESOURCE_IO; 174 - dev->resource[4].start = 0xf000; 175 - dev->resource[4].end = 0xf00f; 176 - dev->resource[4].flags = IORESOURCE_IO; 177 - } 178 - DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, quirk_ali_ide_ports); 179 - 180 - char * __devinit pcibios_setup(char *str) 181 - { 182 - return str; 183 - } 184 - 185 - /* 186 - * Called after each bus is probed, but before its children 187 - * are examined. 188 - */ 189 - 190 - void __devinit pcibios_fixup_bus(struct pci_bus *b) 191 - { 192 - pci_read_bridge_bases(b); 193 - } 194 - 195 - /* 196 - * IRQ functions 197 - */ 198 - static inline u8 bridge_swizzle(u8 pin, u8 slot) 199 - { 200 - return (((pin-1) + slot) % 4) + 1; 201 - } 202 - 203 - static inline u8 bridge_swizzle_pci_1(u8 pin, u8 slot) 204 - { 205 - return (((pin-1) - slot) & 3) + 1; 206 - } 207 - 208 - static u8 __init mpc1211_swizzle(struct pci_dev *dev, u8 *pinp) 209 - { 210 - unsigned long flags; 211 - u8 pin = *pinp; 212 - u32 word; 213 - 214 - for ( ; dev->bus->self; dev = dev->bus->self) { 215 - if (!pin) 216 - continue; 217 - 218 - if (dev->bus->number == 1) { 219 - local_irq_save(flags); 220 - writel(0x80000000 | 0x2c, PCIPAR); 221 - word = readl(PCIPDR); 222 - local_irq_restore(flags); 223 - word >>= 16; 224 - 225 - if (word == 0x0001) 226 - pin = bridge_swizzle_pci_1(pin, PCI_SLOT(dev->devfn)); 227 - else 228 - pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); 229 - } else 230 - pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); 231 - } 232 - 233 - *pinp = pin; 234 - 235 - return PCI_SLOT(dev->devfn); 236 - } 237 - 238 - static int __init map_mpc1211_irq(struct pci_dev *dev, u8 slot, u8 pin) 239 - { 240 - int irq = -1; 241 - 242 - /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */ 243 - if (dev->bus->number == 0) { 244 - switch (slot) { 245 - case 13: irq = 9; break; /* USB */ 246 - case 22: irq = 10; break; /* LAN */ 247 - default: irq = 0; break; 248 - } 249 - } else { 250 - switch (pin) { 251 - case 0: irq = 0; break; 252 - case 1: irq = 7; break; 253 - case 2: irq = 9; break; 254 - case 3: irq = 10; break; 255 - case 4: irq = 11; break; 256 - } 257 - } 258 - 259 - if( irq < 0 ) { 260 - PCIDBG(3, "PCI: Error mapping IRQ on device %s\n", pci_name(dev)); 261 - return irq; 262 - } 263 - 264 - PCIDBG(2, "Setting IRQ for slot %s to %d\n", pci_name(dev), irq); 265 - 266 - return irq; 267 - } 268 - 269 - void __init pcibios_fixup_irqs(void) 270 - { 271 - pci_fixup_irqs(mpc1211_swizzle, map_mpc1211_irq); 272 - } 273 - 274 - void pcibios_align_resource(void *data, struct resource *res, 275 - resource_size_t size, resource_size_t align) 276 - { 277 - resource_size_t start = res->start; 278 - 279 - if (res->flags & IORESOURCE_IO) { 280 - if (start >= 0x10000UL) { 281 - if ((start & 0xffffUL) < 0x4000UL) { 282 - start = (start & 0xffff0000UL) + 0x4000UL; 283 - } else if ((start & 0xffffUL) >= 0xf000UL) { 284 - start = (start & 0xffff0000UL) + 0x10000UL; 285 - } 286 - res->start = start; 287 - } else { 288 - if (start & 0x300) { 289 - start = (start + 0x3ff) & ~0x3ff; 290 - res->start = start; 291 - } 292 - } 293 - } 294 - } 295 -

-136

arch/sh/boards/mpc1211/rtc.c

··· 1 - /* 2 - * linux/arch/sh/kernel/rtc-mpc1211.c -- MPC-1211 on-chip RTC support 3 - * 4 - * Copyright (C) 2002 Saito.K & Jeanne 5 - * 6 - */ 7 - 8 - #include <linux/init.h> 9 - #include <linux/kernel.h> 10 - #include <linux/sched.h> 11 - #include <linux/time.h> 12 - #include <linux/bcd.h> 13 - #include <linux/mc146818rtc.h> 14 - 15 - unsigned long get_cmos_time(void) 16 - { 17 - unsigned int year, mon, day, hour, min, sec; 18 - 19 - spin_lock(&rtc_lock); 20 - 21 - do { 22 - sec = CMOS_READ(RTC_SECONDS); 23 - min = CMOS_READ(RTC_MINUTES); 24 - hour = CMOS_READ(RTC_HOURS); 25 - day = CMOS_READ(RTC_DAY_OF_MONTH); 26 - mon = CMOS_READ(RTC_MONTH); 27 - year = CMOS_READ(RTC_YEAR); 28 - } while (sec != CMOS_READ(RTC_SECONDS)); 29 - 30 - if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { 31 - BCD_TO_BIN(sec); 32 - BCD_TO_BIN(min); 33 - BCD_TO_BIN(hour); 34 - BCD_TO_BIN(day); 35 - BCD_TO_BIN(mon); 36 - BCD_TO_BIN(year); 37 - } 38 - 39 - spin_unlock(&rtc_lock); 40 - 41 - year += 1900; 42 - if (year < 1970) 43 - year += 100; 44 - 45 - return mktime(year, mon, day, hour, min, sec); 46 - } 47 - 48 - void mpc1211_rtc_gettimeofday(struct timeval *tv) 49 - { 50 - 51 - tv->tv_sec = get_cmos_time(); 52 - tv->tv_usec = 0; 53 - } 54 - 55 - /* arc/i386/kernel/time.c */ 56 - /* 57 - * In order to set the CMOS clock precisely, set_rtc_mmss has to be 58 - * called 500 ms after the second nowtime has started, because when 59 - * nowtime is written into the registers of the CMOS clock, it will 60 - * jump to the next second precisely 500 ms later. Check the Motorola 61 - * MC146818A or Dallas DS12887 data sheet for details. 62 - * 63 - * BUG: This routine does not handle hour overflow properly; it just 64 - * sets the minutes. Usually you'll only notice that after reboot! 65 - */ 66 - static int set_rtc_mmss(unsigned long nowtime) 67 - { 68 - int retval = 0; 69 - int real_seconds, real_minutes, cmos_minutes; 70 - unsigned char save_control, save_freq_select; 71 - 72 - /* gets recalled with irq locally disabled */ 73 - spin_lock(&rtc_lock); 74 - save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */ 75 - CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); 76 - 77 - save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */ 78 - CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); 79 - 80 - cmos_minutes = CMOS_READ(RTC_MINUTES); 81 - if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) 82 - BCD_TO_BIN(cmos_minutes); 83 - 84 - /* 85 - * since we're only adjusting minutes and seconds, 86 - * don't interfere with hour overflow. This avoids 87 - * messing with unknown time zones but requires your 88 - * RTC not to be off by more than 15 minutes 89 - */ 90 - real_seconds = nowtime % 60; 91 - real_minutes = nowtime / 60; 92 - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) 93 - real_minutes += 30; /* correct for half hour time zone */ 94 - real_minutes %= 60; 95 - 96 - if (abs(real_minutes - cmos_minutes) < 30) { 97 - if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { 98 - BIN_TO_BCD(real_seconds); 99 - BIN_TO_BCD(real_minutes); 100 - } 101 - CMOS_WRITE(real_seconds,RTC_SECONDS); 102 - CMOS_WRITE(real_minutes,RTC_MINUTES); 103 - } else { 104 - printk(KERN_WARNING 105 - "set_rtc_mmss: can't update from %d to %d\n", 106 - cmos_minutes, real_minutes); 107 - retval = -1; 108 - } 109 - 110 - /* The following flags have to be released exactly in this order, 111 - * otherwise the DS12887 (popular MC146818A clone with integrated 112 - * battery and quartz) will not reset the oscillator and will not 113 - * update precisely 500 ms later. You won't find this mentioned in 114 - * the Dallas Semiconductor data sheets, but who believes data 115 - * sheets anyway ... -- Markus Kuhn 116 - */ 117 - CMOS_WRITE(save_control, RTC_CONTROL); 118 - CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); 119 - spin_unlock(&rtc_lock); 120 - 121 - return retval; 122 - } 123 - 124 - int mpc1211_rtc_settimeofday(const struct timeval *tv) 125 - { 126 - unsigned long nowtime = tv->tv_sec; 127 - 128 - return set_rtc_mmss(nowtime); 129 - } 130 - 131 - void mpc1211_time_init(void) 132 - { 133 - rtc_sh_get_time = mpc1211_rtc_gettimeofday; 134 - rtc_sh_set_time = mpc1211_rtc_settimeofday; 135 - } 136 -

-347

arch/sh/boards/mpc1211/setup.c

··· 1 - /* 2 - * linux/arch/sh/boards/mpc1211/setup.c 3 - * 4 - * Copyright (C) 2002 Saito.K & Jeanne, Fujii.Y 5 - * 6 - */ 7 - 8 - #include <linux/init.h> 9 - #include <linux/irq.h> 10 - #include <linux/hdreg.h> 11 - #include <linux/ide.h> 12 - #include <linux/interrupt.h> 13 - #include <linux/platform_device.h> 14 - #include <asm/io.h> 15 - #include <asm/machvec.h> 16 - #include <asm/mpc1211/mpc1211.h> 17 - #include <asm/mpc1211/pci.h> 18 - #include <asm/mpc1211/m1543c.h> 19 - 20 - /* ALI15X3 SMBus address offsets */ 21 - #define SMBHSTSTS (0 + 0x3100) 22 - #define SMBHSTCNT (1 + 0x3100) 23 - #define SMBHSTSTART (2 + 0x3100) 24 - #define SMBHSTCMD (7 + 0x3100) 25 - #define SMBHSTADD (3 + 0x3100) 26 - #define SMBHSTDAT0 (4 + 0x3100) 27 - #define SMBHSTDAT1 (5 + 0x3100) 28 - #define SMBBLKDAT (6 + 0x3100) 29 - 30 - /* Other settings */ 31 - #define MAX_TIMEOUT 500 /* times 1/100 sec */ 32 - 33 - /* ALI15X3 command constants */ 34 - #define ALI15X3_ABORT 0x04 35 - #define ALI15X3_T_OUT 0x08 36 - #define ALI15X3_QUICK 0x00 37 - #define ALI15X3_BYTE 0x10 38 - #define ALI15X3_BYTE_DATA 0x20 39 - #define ALI15X3_WORD_DATA 0x30 40 - #define ALI15X3_BLOCK_DATA 0x40 41 - #define ALI15X3_BLOCK_CLR 0x80 42 - 43 - /* ALI15X3 status register bits */ 44 - #define ALI15X3_STS_IDLE 0x04 45 - #define ALI15X3_STS_BUSY 0x08 46 - #define ALI15X3_STS_DONE 0x10 47 - #define ALI15X3_STS_DEV 0x20 /* device error */ 48 - #define ALI15X3_STS_COLL 0x40 /* collision or no response */ 49 - #define ALI15X3_STS_TERM 0x80 /* terminated by abort */ 50 - #define ALI15X3_STS_ERR 0xE0 /* all the bad error bits */ 51 - 52 - static void __init pci_write_config(unsigned long busNo, 53 - unsigned long devNo, 54 - unsigned long fncNo, 55 - unsigned long cnfAdd, 56 - unsigned long cnfData) 57 - { 58 - ctrl_outl((0x80000000 59 - + ((busNo & 0xff) << 16) 60 - + ((devNo & 0x1f) << 11) 61 - + ((fncNo & 0x07) << 8) 62 - + (cnfAdd & 0xfc)), PCIPAR); 63 - 64 - ctrl_outl(cnfData, PCIPDR); 65 - } 66 - 67 - /* 68 - Initialize IRQ setting 69 - */ 70 - 71 - static unsigned char m_irq_mask = 0xfb; 72 - static unsigned char s_irq_mask = 0xff; 73 - 74 - static void disable_mpc1211_irq(unsigned int irq) 75 - { 76 - if( irq < 8) { 77 - m_irq_mask |= (1 << irq); 78 - outb(m_irq_mask,I8259_M_MR); 79 - } else { 80 - s_irq_mask |= (1 << (irq - 8)); 81 - outb(s_irq_mask,I8259_S_MR); 82 - } 83 - 84 - } 85 - 86 - static void enable_mpc1211_irq(unsigned int irq) 87 - { 88 - if( irq < 8) { 89 - m_irq_mask &= ~(1 << irq); 90 - outb(m_irq_mask,I8259_M_MR); 91 - } else { 92 - s_irq_mask &= ~(1 << (irq - 8)); 93 - outb(s_irq_mask,I8259_S_MR); 94 - } 95 - } 96 - 97 - static inline int mpc1211_irq_real(unsigned int irq) 98 - { 99 - int value; 100 - int irqmask; 101 - 102 - if ( irq < 8) { 103 - irqmask = 1<<irq; 104 - outb(0x0b,I8259_M_CR); /* ISR register */ 105 - value = inb(I8259_M_CR) & irqmask; 106 - outb(0x0a,I8259_M_CR); /* back ro the IPR reg */ 107 - return value; 108 - } 109 - irqmask = 1<<(irq - 8); 110 - outb(0x0b,I8259_S_CR); /* ISR register */ 111 - value = inb(I8259_S_CR) & irqmask; 112 - outb(0x0a,I8259_S_CR); /* back ro the IPR reg */ 113 - return value; 114 - } 115 - 116 - static void mask_and_ack_mpc1211(unsigned int irq) 117 - { 118 - if(irq < 8) { 119 - if(m_irq_mask & (1<<irq)){ 120 - if(!mpc1211_irq_real(irq)){ 121 - atomic_inc(&irq_err_count) 122 - printk("spurious 8259A interrupt: IRQ %x\n",irq); 123 - } 124 - } else { 125 - m_irq_mask |= (1<<irq); 126 - } 127 - inb(I8259_M_MR); /* DUMMY */ 128 - outb(m_irq_mask,I8259_M_MR); /* disable */ 129 - outb(0x60+irq,I8259_M_CR); /* EOI */ 130 - 131 - } else { 132 - if(s_irq_mask & (1<<(irq - 8))){ 133 - if(!mpc1211_irq_real(irq)){ 134 - atomic_inc(&irq_err_count); 135 - printk("spurious 8259A interrupt: IRQ %x\n",irq); 136 - } 137 - } else { 138 - s_irq_mask |= (1<<(irq - 8)); 139 - } 140 - inb(I8259_S_MR); /* DUMMY */ 141 - outb(s_irq_mask,I8259_S_MR); /* disable */ 142 - outb(0x60+(irq-8),I8259_S_CR); /* EOI */ 143 - outb(0x60+2,I8259_M_CR); 144 - } 145 - } 146 - 147 - static void end_mpc1211_irq(unsigned int irq) 148 - { 149 - enable_mpc1211_irq(irq); 150 - } 151 - 152 - static unsigned int startup_mpc1211_irq(unsigned int irq) 153 - { 154 - enable_mpc1211_irq(irq); 155 - return 0; 156 - } 157 - 158 - static void shutdown_mpc1211_irq(unsigned int irq) 159 - { 160 - disable_mpc1211_irq(irq); 161 - } 162 - 163 - static struct hw_interrupt_type mpc1211_irq_type = { 164 - .typename = "MPC1211-IRQ", 165 - .startup = startup_mpc1211_irq, 166 - .shutdown = shutdown_mpc1211_irq, 167 - .enable = enable_mpc1211_irq, 168 - .disable = disable_mpc1211_irq, 169 - .ack = mask_and_ack_mpc1211, 170 - .end = end_mpc1211_irq 171 - }; 172 - 173 - static void make_mpc1211_irq(unsigned int irq) 174 - { 175 - irq_desc[irq].chip = &mpc1211_irq_type; 176 - irq_desc[irq].status = IRQ_DISABLED; 177 - irq_desc[irq].action = 0; 178 - irq_desc[irq].depth = 1; 179 - disable_mpc1211_irq(irq); 180 - } 181 - 182 - int mpc1211_irq_demux(int irq) 183 - { 184 - unsigned int poll; 185 - 186 - if( irq == 2 ) { 187 - outb(0x0c,I8259_M_CR); 188 - poll = inb(I8259_M_CR); 189 - if(poll & 0x80) { 190 - irq = (poll & 0x07); 191 - } 192 - if( irq == 2) { 193 - outb(0x0c,I8259_S_CR); 194 - poll = inb(I8259_S_CR); 195 - irq = (poll & 0x07) + 8; 196 - } 197 - } 198 - return irq; 199 - } 200 - 201 - static void __init init_mpc1211_IRQ(void) 202 - { 203 - int i; 204 - /* 205 - * Super I/O (Just mimic PC): 206 - * 1: keyboard 207 - * 3: serial 1 208 - * 4: serial 0 209 - * 5: printer 210 - * 6: floppy 211 - * 8: rtc 212 - * 10: lan 213 - * 12: mouse 214 - * 14: ide0 215 - * 15: ide1 216 - */ 217 - 218 - pci_write_config(0,0,0,0x54, 0xb0b0002d); 219 - outb(0x11, I8259_M_CR); /* mater icw1 edge trigger */ 220 - outb(0x11, I8259_S_CR); /* slave icw1 edge trigger */ 221 - outb(0x20, I8259_M_MR); /* m icw2 base vec 0x08 */ 222 - outb(0x28, I8259_S_MR); /* s icw2 base vec 0x70 */ 223 - outb(0x04, I8259_M_MR); /* m icw3 slave irq2 */ 224 - outb(0x02, I8259_S_MR); /* s icw3 slave id */ 225 - outb(0x01, I8259_M_MR); /* m icw4 non buf normal eoi*/ 226 - outb(0x01, I8259_S_MR); /* s icw4 non buf normal eo1*/ 227 - outb(0xfb, I8259_M_MR); /* disable irq0--irq7 */ 228 - outb(0xff, I8259_S_MR); /* disable irq8--irq15 */ 229 - 230 - for ( i=0; i < 16; i++) { 231 - if(i != 2) { 232 - make_mpc1211_irq(i); 233 - } 234 - } 235 - } 236 - 237 - static void delay1000(void) 238 - { 239 - int i; 240 - 241 - for (i=0; i<1000; i++) 242 - ctrl_delay(); 243 - } 244 - 245 - static int put_smb_blk(unsigned char *p, int address, int command, int no) 246 - { 247 - int temp; 248 - int timeout; 249 - int i; 250 - 251 - outb(0xff, SMBHSTSTS); 252 - temp = inb(SMBHSTSTS); 253 - for (timeout = 0; (timeout < MAX_TIMEOUT) && !(temp & ALI15X3_STS_IDLE); timeout++) { 254 - delay1000(); 255 - temp = inb(SMBHSTSTS); 256 - } 257 - if (timeout >= MAX_TIMEOUT){ 258 - return -1; 259 - } 260 - 261 - outb(((address & 0x7f) << 1), SMBHSTADD); 262 - outb(0xc0, SMBHSTCNT); 263 - outb(command & 0xff, SMBHSTCMD); 264 - outb(no & 0x1f, SMBHSTDAT0); 265 - 266 - for(i = 1; i <= no; i++) { 267 - outb(*p++, SMBBLKDAT); 268 - } 269 - outb(0xff, SMBHSTSTART); 270 - 271 - temp = inb(SMBHSTSTS); 272 - for (timeout = 0; (timeout < MAX_TIMEOUT) && !(temp & (ALI15X3_STS_ERR | ALI15X3_STS_DONE)); timeout++) { 273 - delay1000(); 274 - temp = inb(SMBHSTSTS); 275 - } 276 - if (timeout >= MAX_TIMEOUT) { 277 - return -2; 278 - } 279 - if ( temp & ALI15X3_STS_ERR ){ 280 - return -3; 281 - } 282 - return 0; 283 - } 284 - 285 - static struct resource heartbeat_resources[] = { 286 - [0] = { 287 - .start = 0xa2000000, 288 - .end = 0xa2000000, 289 - .flags = IORESOURCE_MEM, 290 - }, 291 - }; 292 - 293 - static struct platform_device heartbeat_device = { 294 - .name = "heartbeat", 295 - .id = -1, 296 - .num_resources = ARRAY_SIZE(heartbeat_resources), 297 - .resource = heartbeat_resources, 298 - }; 299 - 300 - static struct platform_device *mpc1211_devices[] __initdata = { 301 - &heartbeat_device, 302 - }; 303 - 304 - static int __init mpc1211_devices_setup(void) 305 - { 306 - return platform_add_devices(mpc1211_devices, 307 - ARRAY_SIZE(mpc1211_devices)); 308 - } 309 - __initcall(mpc1211_devices_setup); 310 - 311 - /* arch/sh/boards/mpc1211/rtc.c */ 312 - void mpc1211_time_init(void); 313 - 314 - static void __init mpc1211_setup(char **cmdline_p) 315 - { 316 - unsigned char spd_buf[128]; 317 - 318 - __set_io_port_base(PA_PCI_IO); 319 - 320 - pci_write_config(0,0,0,0x54, 0xb0b00000); 321 - 322 - do { 323 - outb(ALI15X3_ABORT, SMBHSTCNT); 324 - spd_buf[0] = 0x0c; 325 - spd_buf[1] = 0x43; 326 - spd_buf[2] = 0x7f; 327 - spd_buf[3] = 0x03; 328 - spd_buf[4] = 0x00; 329 - spd_buf[5] = 0x03; 330 - spd_buf[6] = 0x00; 331 - } while (put_smb_blk(spd_buf, 0x69, 0, 7) < 0); 332 - 333 - board_time_init = mpc1211_time_init; 334 - 335 - return 0; 336 - } 337 - 338 - /* 339 - * The Machine Vector 340 - */ 341 - static struct sh_machine_vector mv_mpc1211 __initmv = { 342 - .mv_name = "Interface MPC-1211(CTP/PCI/MPC-SH02)", 343 - .mv_setup = mpc1211_setup, 344 - .mv_nr_irqs = 48, 345 - .mv_irq_demux = mpc1211_irq_demux, 346 - .mv_init_irq = init_mpc1211_IRQ, 347 - };

+10 -1

arch/sh/boards/renesas/migor/setup.c

··· 14 14 #include <linux/mtd/physmap.h> 15 15 #include <linux/mtd/nand.h> 16 16 #include <linux/i2c.h> 17 + #include <linux/smc91x.h> 17 18 #include <asm/machvec.h> 18 19 #include <asm/io.h> 19 20 #include <asm/sh_keysc.h> ··· 28 27 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A) 29 28 */ 30 29 30 + static struct smc91x_platdata smc91x_info = { 31 + .flags = SMC91X_USE_16BIT, 32 + .irq_flags = IRQF_TRIGGER_HIGH, 33 + }; 34 + 31 35 static struct resource smc91x_eth_resources[] = { 32 36 [0] = { 33 37 .name = "SMC91C111" , ··· 42 36 }, 43 37 [1] = { 44 38 .start = 32, /* IRQ0 */ 45 - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, 39 + .flags = IORESOURCE_IRQ, 46 40 }, 47 41 }; 48 42 ··· 50 44 .name = "smc91x", 51 45 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 52 46 .resource = smc91x_eth_resources, 47 + .dev = { 48 + .platform_data = &smc91x_info, 49 + }, 53 50 }; 54 51 55 52 static struct sh_keysc_info sh_keysc_info = {

+1 -1

arch/sh/boards/renesas/r7780rp/irq-r7780mp.c

··· 62 62 static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors, 63 63 NULL, mask_registers, NULL, NULL); 64 64 65 - unsigned char * __init highlander_init_irq_r7780mp(void) 65 + unsigned char * __init highlander_plat_irq_setup(void) 66 66 { 67 67 if ((ctrl_inw(0xa4000700) & 0xf000) == 0x2000) { 68 68 printk(KERN_INFO "Using r7780mp interrupt controller.\n");

+1 -1

arch/sh/boards/renesas/r7780rp/irq-r7780rp.c

··· 55 55 static DECLARE_INTC_DESC(intc_desc, "r7780rp", vectors, 56 56 NULL, mask_registers, NULL, NULL); 57 57 58 - unsigned char * __init highlander_init_irq_r7780rp(void) 58 + unsigned char * __init highlander_plat_irq_setup(void) 59 59 { 60 60 if (ctrl_inw(0xa5000600)) { 61 61 printk(KERN_INFO "Using r7780rp interrupt controller.\n");

+1 -1

arch/sh/boards/renesas/r7780rp/irq-r7785rp.c

··· 64 64 static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors, 65 65 NULL, mask_registers, NULL, NULL); 66 66 67 - unsigned char * __init highlander_init_irq_r7785rp(void) 67 + unsigned char * __init highlander_plat_irq_setup(void) 68 68 { 69 69 if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000) 70 70 return NULL;

+3 -21

arch/sh/boards/renesas/r7780rp/setup.c

··· 316 316 317 317 static unsigned char irl2irq[HL_NR_IRL]; 318 318 319 - int highlander_irq_demux(int irq) 319 + static int highlander_irq_demux(int irq) 320 320 { 321 321 if (irq >= HL_NR_IRL || !irl2irq[irq]) 322 322 return irq; ··· 324 324 return irl2irq[irq]; 325 325 } 326 326 327 - void __init highlander_init_irq(void) 327 + static void __init highlander_init_irq(void) 328 328 { 329 - unsigned char *ucp = NULL; 330 - 331 - do { 332 - #ifdef CONFIG_SH_R7780MP 333 - ucp = highlander_init_irq_r7780mp(); 334 - if (ucp) 335 - break; 336 - #endif 337 - #ifdef CONFIG_SH_R7785RP 338 - ucp = highlander_init_irq_r7785rp(); 339 - if (ucp) 340 - break; 341 - #endif 342 - #ifdef CONFIG_SH_R7780RP 343 - ucp = highlander_init_irq_r7780rp(); 344 - if (ucp) 345 - break; 346 - #endif 347 - } while (0); 329 + unsigned char *ucp = highlander_plat_irq_setup(); 348 330 349 331 if (ucp) { 350 332 plat_irq_setup_pins(IRQ_MODE_IRL3210);

+2 -5

arch/sh/boards/renesas/rts7751r2d/setup.c

··· 109 109 .resource = heartbeat_resources, 110 110 }; 111 111 112 - #ifdef CONFIG_MFD_SM501 113 112 static struct plat_serial8250_port uart_platform_data[] = { 114 113 { 115 114 .membase = (void __iomem *)0xb3e30000, ··· 207 208 .resource = sm501_resources, 208 209 }; 209 210 210 - #endif /* CONFIG_MFD_SM501 */ 211 - 212 211 static struct platform_device *rts7751r2d_devices[] __initdata = { 213 - #ifdef CONFIG_MFD_SM501 214 212 &uart_device, 215 213 &sm501_device, 216 - #endif 217 214 &heartbeat_device, 218 215 &spi_sh_sci_device, 219 216 }; ··· 229 234 { 230 235 if (register_trapped_io(&cf_trapped_io) == 0) 231 236 platform_device_register(&cf_ide_device); 237 + 232 238 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus)); 239 + 233 240 return platform_add_devices(rts7751r2d_devices, 234 241 ARRAY_SIZE(rts7751r2d_devices)); 235 242 }

+14 -3

arch/sh/boards/se/7206/setup.c

··· 3 3 * linux/arch/sh/boards/se/7206/setup.c 4 4 * 5 5 * Copyright (C) 2006 Yoshinori Sato 6 - * Copyright (C) 2007 Paul Mundt 6 + * Copyright (C) 2007 - 2008 Paul Mundt 7 7 * 8 8 * Hitachi 7206 SolutionEngine Support. 9 9 */ 10 10 #include <linux/init.h> 11 11 #include <linux/platform_device.h> 12 + #include <linux/smc91x.h> 12 13 #include <asm/se7206.h> 13 14 #include <asm/io.h> 14 15 #include <asm/machvec.h> ··· 17 16 18 17 static struct resource smc91x_resources[] = { 19 18 [0] = { 20 - .start = 0x300, 21 - .end = 0x300 + 0x020 - 1, 19 + .name = "smc91x-regs", 20 + .start = PA_SMSC + 0x300, 21 + .end = PA_SMSC + 0x300 + 0x020 - 1, 22 22 .flags = IORESOURCE_MEM, 23 23 }, 24 24 [1] = { ··· 29 27 }, 30 28 }; 31 29 30 + static struct smc91x_platdata smc91x_info = { 31 + .flags = SMC91X_USE_16BIT, 32 + }; 33 + 32 34 static struct platform_device smc91x_device = { 33 35 .name = "smc91x", 34 36 .id = -1, 37 + .dev = { 38 + .dma_mask = NULL, 39 + .coherent_dma_mask = 0xffffffff, 40 + .platform_data = &smc91x_info, 41 + }, 35 42 .num_resources = ARRAY_SIZE(smc91x_resources), 36 43 .resource = smc91x_resources, 37 44 };

+6

arch/sh/boards/se/7722/setup.c

··· 14 14 #include <linux/platform_device.h> 15 15 #include <linux/ata_platform.h> 16 16 #include <linux/input.h> 17 + #include <linux/smc91x.h> 17 18 #include <asm/machvec.h> 18 19 #include <asm/se7722.h> 19 20 #include <asm/io.h> ··· 45 44 }; 46 45 47 46 /* SMC91x */ 47 + static struct smc91x_platdata smc91x_info = { 48 + .flags = SMC91X_USE_16BIT, 49 + }; 50 + 48 51 static struct resource smc91x_eth_resources[] = { 49 52 [0] = { 50 53 .name = "smc91x-regs" , ··· 69 64 .dev = { 70 65 .dma_mask = NULL, /* don't use dma */ 71 66 .coherent_dma_mask = 0xffffffff, 67 + .platform_data = &smc91x_info, 72 68 }, 73 69 .num_resources = ARRAY_SIZE(smc91x_eth_resources), 74 70 .resource = smc91x_eth_resources,

-1

arch/sh/boot/compressed/Makefile_32

··· 6 6 7 7 targets := vmlinux vmlinux.bin vmlinux.bin.gz \ 8 8 head_32.o misc_32.o piggy.o 9 - EXTRA_AFLAGS := -traditional 10 9 11 10 OBJECTS = $(obj)/head_32.o $(obj)/misc_32.o 12 11

-1

arch/sh/boot/compressed/Makefile_64

··· 13 13 14 14 targets := vmlinux vmlinux.bin vmlinux.bin.gz \ 15 15 head_64.o misc_64.o cache.o piggy.o 16 - EXTRA_AFLAGS := -traditional 17 16 18 17 OBJECTS := $(obj)/vmlinux_64.lds $(obj)/head_64.o $(obj)/misc_64.o \ 19 18 $(obj)/cache.o

+37 -34

arch/sh/kernel/cpu/irq/intc-sh5.c

··· 184 184 185 185 void __init plat_irq_setup(void) 186 186 { 187 - unsigned long long __dummy0, __dummy1=~0x00000000100000f0; 187 + unsigned long long __dummy0, __dummy1=~0x00000000100000f0; 188 188 unsigned long reg; 189 - unsigned long data; 190 189 int i; 191 190 192 191 intc_virt = onchip_remap(INTC_BASE, 1024, "INTC"); ··· 195 196 196 197 197 198 /* Set default: per-line enable/disable, priority driven ack/eoi */ 198 - for (i = 0; i < NR_INTC_IRQS; i++) { 199 - if (platform_int_priority[i] != NO_PRIORITY) { 200 - irq_desc[i].chip = &intc_irq_type; 201 - } 202 - } 199 + for (i = 0; i < NR_INTC_IRQS; i++) 200 + irq_desc[i].chip = &intc_irq_type; 203 201 204 202 205 203 /* Disable all interrupts and set all priorities to 0 to avoid trouble */ ··· 207 211 ctrl_outl( NO_PRIORITY, reg); 208 212 209 213 210 - /* Set IRLM */ 211 - /* If all the priorities are set to 'no priority', then 212 - * assume we are using encoded mode. 213 - */ 214 - irlm = platform_int_priority[IRQ_IRL0] + platform_int_priority[IRQ_IRL1] + \ 215 - platform_int_priority[IRQ_IRL2] + platform_int_priority[IRQ_IRL3]; 214 + #ifdef CONFIG_SH_CAYMAN 215 + { 216 + unsigned long data; 216 217 217 - if (irlm == NO_PRIORITY) { 218 - /* IRLM = 0 */ 219 - reg = INTC_ICR_CLEAR; 220 - i = IRQ_INTA; 221 - printk("Trying to use encoded IRL0-3. IRLs unsupported.\n"); 222 - } else { 223 - /* IRLM = 1 */ 224 - reg = INTC_ICR_SET; 225 - i = IRQ_IRL0; 226 - } 227 - ctrl_outl(INTC_ICR_IRLM, reg); 228 - 229 - /* Set interrupt priorities according to platform description */ 230 - for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) { 231 - data |= platform_int_priority[i] << ((i % INTC_INTPRI_PPREG) * 4); 232 - if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) { 233 - /* Upon the 7th, set Priority Register */ 234 - ctrl_outl(data, reg); 235 - data = 0; 236 - reg += 8; 218 + /* Set IRLM */ 219 + /* If all the priorities are set to 'no priority', then 220 + * assume we are using encoded mode. 221 + */ 222 + irlm = platform_int_priority[IRQ_IRL0] + 223 + platform_int_priority[IRQ_IRL1] + 224 + platform_int_priority[IRQ_IRL2] + 225 + platform_int_priority[IRQ_IRL3]; 226 + if (irlm == NO_PRIORITY) { 227 + /* IRLM = 0 */ 228 + reg = INTC_ICR_CLEAR; 229 + i = IRQ_INTA; 230 + printk("Trying to use encoded IRL0-3. IRLs unsupported.\n"); 231 + } else { 232 + /* IRLM = 1 */ 233 + reg = INTC_ICR_SET; 234 + i = IRQ_IRL0; 237 235 } 238 - } 236 + ctrl_outl(INTC_ICR_IRLM, reg); 237 + 238 + /* Set interrupt priorities according to platform description */ 239 + for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) { 240 + data |= platform_int_priority[i] << 241 + ((i % INTC_INTPRI_PPREG) * 4); 242 + if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) { 243 + /* Upon the 7th, set Priority Register */ 244 + ctrl_outl(data, reg); 245 + data = 0; 246 + reg += 8; 247 + } 248 + } 249 + #endif 239 250 240 251 /* 241 252 * And now let interrupts come in.

+90 -3

arch/sh/kernel/cpu/irq/intc.c

··· 1 1 /* 2 2 * Shared interrupt handling code for IPR and INTC2 types of IRQs. 3 3 * 4 - * Copyright (C) 2007 Magnus Damm 4 + * Copyright (C) 2007, 2008 Magnus Damm 5 5 * 6 6 * Based on intc2.c and ipr.c 7 7 * ··· 62 62 #endif 63 63 64 64 static unsigned int intc_prio_level[NR_IRQS]; /* for now */ 65 + #ifdef CONFIG_CPU_SH3 66 + static unsigned long ack_handle[NR_IRQS]; 67 + #endif 65 68 66 69 static inline struct intc_desc_int *get_intc_desc(unsigned int irq) 67 70 { ··· 101 98 102 99 static void modify_8(unsigned long addr, unsigned long h, unsigned long data) 103 100 { 101 + unsigned long flags; 102 + local_irq_save(flags); 104 103 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr); 104 + local_irq_restore(flags); 105 105 } 106 106 107 107 static void modify_16(unsigned long addr, unsigned long h, unsigned long data) 108 108 { 109 + unsigned long flags; 110 + local_irq_save(flags); 109 111 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr); 112 + local_irq_restore(flags); 110 113 } 111 114 112 115 static void modify_32(unsigned long addr, unsigned long h, unsigned long data) 113 116 { 117 + unsigned long flags; 118 + local_irq_save(flags); 114 119 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr); 120 + local_irq_restore(flags); 115 121 } 116 122 117 123 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 }; ··· 231 219 } 232 220 } 233 221 222 + #ifdef CONFIG_CPU_SH3 223 + static void intc_mask_ack(unsigned int irq) 224 + { 225 + struct intc_desc_int *d = get_intc_desc(irq); 226 + unsigned long handle = ack_handle[irq]; 227 + unsigned long addr; 228 + 229 + intc_disable(irq); 230 + 231 + /* read register and write zero only to the assocaited bit */ 232 + 233 + if (handle) { 234 + addr = INTC_REG(d, _INTC_ADDR_D(handle), 0); 235 + ctrl_inb(addr); 236 + ctrl_outb(0x3f ^ set_field(0, 1, handle), addr); 237 + } 238 + } 239 + #endif 240 + 234 241 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp, 235 242 unsigned int nr_hp, 236 243 unsigned int irq) ··· 311 280 [IRQ_TYPE_EDGE_FALLING] = VALID(0), 312 281 [IRQ_TYPE_EDGE_RISING] = VALID(1), 313 282 [IRQ_TYPE_LEVEL_LOW] = VALID(2), 283 + /* SH7706, SH7707 and SH7709 do not support high level triggered */ 284 + #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \ 285 + !defined(CONFIG_CPU_SUBTYPE_SH7707) && \ 286 + !defined(CONFIG_CPU_SUBTYPE_SH7709) 314 287 [IRQ_TYPE_LEVEL_HIGH] = VALID(3), 288 + #endif 315 289 }; 316 290 317 291 static int intc_set_sense(unsigned int irq, unsigned int type) ··· 466 430 return 0; 467 431 } 468 432 433 + #ifdef CONFIG_CPU_SH3 434 + static unsigned int __init intc_ack_data(struct intc_desc *desc, 435 + struct intc_desc_int *d, 436 + intc_enum enum_id) 437 + { 438 + struct intc_mask_reg *mr = desc->ack_regs; 439 + unsigned int i, j, fn, mode; 440 + unsigned long reg_e, reg_d; 441 + 442 + for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) { 443 + mr = desc->ack_regs + i; 444 + 445 + for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { 446 + if (mr->enum_ids[j] != enum_id) 447 + continue; 448 + 449 + fn = REG_FN_MODIFY_BASE; 450 + mode = MODE_ENABLE_REG; 451 + reg_e = mr->set_reg; 452 + reg_d = mr->set_reg; 453 + 454 + fn += (mr->reg_width >> 3) - 1; 455 + return _INTC_MK(fn, mode, 456 + intc_get_reg(d, reg_e), 457 + intc_get_reg(d, reg_d), 458 + 1, 459 + (mr->reg_width - 1) - j); 460 + } 461 + } 462 + 463 + return 0; 464 + } 465 + #endif 466 + 469 467 static unsigned int __init intc_sense_data(struct intc_desc *desc, 470 468 struct intc_desc_int *d, 471 469 intc_enum enum_id) ··· 600 530 601 531 /* irq should be disabled by default */ 602 532 d->chip.mask(irq); 533 + 534 + #ifdef CONFIG_CPU_SH3 535 + if (desc->ack_regs) 536 + ack_handle[irq] = intc_ack_data(desc, d, enum_id); 537 + #endif 603 538 } 604 539 605 540 static unsigned int __init save_reg(struct intc_desc_int *d, ··· 635 560 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0; 636 561 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0; 637 562 563 + #ifdef CONFIG_CPU_SH3 564 + d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0; 565 + #endif 638 566 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg)); 639 567 #ifdef CONFIG_SMP 640 568 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp)); ··· 670 592 } 671 593 } 672 594 673 - BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ 674 - 675 595 d->chip.name = desc->name; 676 596 d->chip.mask = intc_disable; 677 597 d->chip.unmask = intc_enable; 678 598 d->chip.mask_ack = intc_disable; 679 599 d->chip.set_type = intc_set_sense; 600 + 601 + #ifdef CONFIG_CPU_SH3 602 + if (desc->ack_regs) { 603 + for (i = 0; i < desc->nr_ack_regs; i++) 604 + k += save_reg(d, k, desc->ack_regs[i].set_reg, 0); 605 + 606 + d->chip.mask_ack = intc_mask_ack; 607 + } 608 + #endif 609 + 610 + BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ 680 611 681 612 for (i = 0; i < desc->nr_vectors; i++) { 682 613 struct intc_vect *vect = desc->vectors + i;

+2 -2

arch/sh/kernel/cpu/sh2a/fpu.c

··· 300 300 iy = hy & 0x7fffffff; 301 301 if (iy < 0x00800000) { 302 302 ix = denormal_subf1(ix, iy); 303 - if (ix < 0) { 303 + if ((int) ix < 0) { 304 304 ix = -ix; 305 305 sign ^= 0x80000000; 306 306 } ··· 385 385 iy = hy & 0x7fffffffffffffffLL; 386 386 if (iy < 0x0010000000000000LL) { 387 387 ix = denormal_subd1(ix, iy); 388 - if (ix < 0) { 388 + if ((int) ix < 0) { 389 389 ix = -ix; 390 390 sign ^= 0x8000000000000000LL; 391 391 }

+1 -1

arch/sh/kernel/cpu/sh3/Makefile

··· 2 2 # Makefile for the Linux/SuperH SH-3 backends. 3 3 # 4 4 5 - obj-y := ex.o probe.o entry.o 5 + obj-y := ex.o probe.o entry.o setup-sh3.o 6 6 7 7 # CPU subtype setup 8 8 obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o

+71

arch/sh/kernel/cpu/sh3/setup-sh3.c

··· 1 + /* 2 + * Shared SH3 Setup code 3 + * 4 + * Copyright (C) 2008 Magnus Damm 5 + * 6 + * This file is subject to the terms and conditions of the GNU General Public 7 + * License. See the file "COPYING" in the main directory of this archive 8 + * for more details. 9 + */ 10 + 11 + #include <linux/init.h> 12 + #include <linux/irq.h> 13 + #include <linux/io.h> 14 + 15 + /* All SH3 devices are equipped with IRQ0->5 (except sh7708) */ 16 + 17 + enum { 18 + UNUSED = 0, 19 + 20 + /* interrupt sources */ 21 + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 22 + }; 23 + 24 + static struct intc_vect vectors_irq0123[] __initdata = { 25 + INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 26 + INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 27 + }; 28 + 29 + static struct intc_vect vectors_irq45[] __initdata = { 30 + INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 31 + }; 32 + 33 + static struct intc_prio_reg prio_registers[] __initdata = { 34 + { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 35 + { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 36 + }; 37 + 38 + static struct intc_mask_reg ack_registers[] __initdata = { 39 + { 0xa4000004, 0, 8, /* IRR0 */ 40 + { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } }, 41 + }; 42 + 43 + static struct intc_sense_reg sense_registers[] __initdata = { 44 + { 0xa4000010, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } }, 45 + }; 46 + 47 + static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh3-irq0123", 48 + vectors_irq0123, NULL, NULL, 49 + prio_registers, sense_registers, ack_registers); 50 + 51 + static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45", 52 + vectors_irq45, NULL, NULL, 53 + prio_registers, sense_registers, ack_registers); 54 + 55 + #define INTC_ICR1 0xa4000010UL 56 + #define INTC_ICR1_IRQLVL (1<<14) 57 + 58 + void __init plat_irq_setup_pins(int mode) 59 + { 60 + if (mode == IRQ_MODE_IRQ) { 61 + ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1); 62 + register_intc_controller(&intc_desc_irq0123); 63 + return; 64 + } 65 + BUG(); 66 + } 67 + 68 + void __init plat_irq_setup_sh3(void) 69 + { 70 + register_intc_controller(&intc_desc_irq45); 71 + }

+3 -19

arch/sh/kernel/cpu/sh3/setup-sh7705.c

··· 37 37 }; 38 38 39 39 static struct intc_vect vectors[] __initdata = { 40 - INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 40 + /* IRQ0->5 are handled in setup-sh3.c */ 41 41 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 42 42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 43 43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), ··· 48 48 INTC_VECT(ADC_ADI, 0x980), 49 49 INTC_VECT(USB_USI0, 0xa20), INTC_VECT(USB_USI1, 0xa40), 50 50 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20), 51 - INTC_VECT(TPU3, 0xc80), INTC_VECT(TPU1, 0xca0), 51 + INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0), 52 52 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 53 53 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 54 54 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), ··· 79 79 }; 80 80 81 81 static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups, 82 - NULL, prio_registers, NULL); 83 - 84 - static struct intc_vect vectors_irq[] __initdata = { 85 - INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 86 - INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 87 - }; 88 - 89 - static DECLARE_INTC_DESC(intc_desc_irq, "sh7705-irq", vectors_irq, NULL, 90 82 NULL, prio_registers, NULL); 91 83 92 84 static struct plat_sci_port sci_platform_data[] = { ··· 151 159 } 152 160 __initcall(sh7705_devices_setup); 153 161 154 - void __init plat_irq_setup_pins(int mode) 155 - { 156 - if (mode == IRQ_MODE_IRQ) { 157 - register_intc_controller(&intc_desc_irq); 158 - return; 159 - } 160 - BUG(); 161 - } 162 - 163 162 void __init plat_irq_setup(void) 164 163 { 165 164 register_intc_controller(&intc_desc); 165 + plat_irq_setup_sh3(); 166 166 }

+6 -30

arch/sh/kernel/cpu/sh3/setup-sh770x.c

··· 52 52 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 53 53 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 54 54 defined(CONFIG_CPU_SUBTYPE_SH7709) 55 - INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 55 + /* IRQ0->5 are handled in setup-sh3.c */ 56 56 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 57 57 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 58 58 INTC_VECT(ADC_ADI, 0x980), ··· 103 103 104 104 static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups, 105 105 NULL, prio_registers, NULL); 106 - 107 - #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 108 - defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 109 - defined(CONFIG_CPU_SUBTYPE_SH7709) 110 - static struct intc_vect vectors_irq[] __initdata = { 111 - INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 112 - INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 113 - }; 114 - 115 - static DECLARE_INTC_DESC(intc_desc_irq, "sh770x-irq", vectors_irq, NULL, 116 - NULL, prio_registers, NULL); 117 - #endif 118 106 119 107 static struct resource rtc_resources[] = { 120 108 [0] = { ··· 182 194 } 183 195 __initcall(sh770x_devices_setup); 184 196 185 - #define INTC_ICR1 0xa4000010UL 186 - #define INTC_ICR1_IRQLVL (1<<14) 187 - 188 - void __init plat_irq_setup_pins(int mode) 189 - { 190 - if (mode == IRQ_MODE_IRQ) { 191 - #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 192 - defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 193 - defined(CONFIG_CPU_SUBTYPE_SH7709) 194 - ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1); 195 - register_intc_controller(&intc_desc_irq); 196 - return; 197 - #endif 198 - } 199 - BUG(); 200 - } 201 - 202 197 void __init plat_irq_setup(void) 203 198 { 204 199 register_intc_controller(&intc_desc); 200 + #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 201 + defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 202 + defined(CONFIG_CPU_SUBTYPE_SH7709) 203 + plat_irq_setup_sh3(); 204 + #endif 205 205 }

+3 -22

arch/sh/kernel/cpu/sh3/setup-sh7710.c

··· 38 38 }; 39 39 40 40 static struct intc_vect vectors[] __initdata = { 41 - INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 41 + /* IRQ0->5 are handled in setup-sh3.c */ 42 42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 43 43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 44 44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), ··· 79 79 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 80 80 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 81 81 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, 82 - { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } }, 83 - #ifdef CONFIG_CPU_SUBTYPE_SH7710 84 - { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } }, 85 - #endif 82 + { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } }, 86 83 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, 87 84 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, 88 85 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 89 86 }; 90 87 91 88 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, 92 - NULL, prio_registers, NULL); 93 - 94 - static struct intc_vect vectors_irq[] __initdata = { 95 - INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 96 - INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 97 - }; 98 - 99 - static DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq, NULL, 100 89 NULL, prio_registers, NULL); 101 90 102 91 static struct resource rtc_resources[] = { ··· 159 170 } 160 171 __initcall(sh7710_devices_setup); 161 172 162 - void __init plat_irq_setup_pins(int mode) 163 - { 164 - if (mode == IRQ_MODE_IRQ) { 165 - register_intc_controller(&intc_desc_irq); 166 - return; 167 - } 168 - BUG(); 169 - } 170 - 171 173 void __init plat_irq_setup(void) 172 174 { 173 175 register_intc_controller(&intc_desc); 176 + plat_irq_setup_sh3(); 174 177 }

+2 -33

arch/sh/kernel/cpu/sh3/setup-sh7720.c

··· 19 19 #include <linux/serial_sci.h> 20 20 #include <asm/rtc.h> 21 21 22 - #define INTC_ICR1 0xA4140010UL 23 - #define INTC_ICR_IRLM 0x4000 24 - #define INTC_ICR_IRQ (~INTC_ICR_IRLM) 25 - 26 22 static struct resource rtc_resources[] = { 27 23 [0] = { 28 24 .start = 0xa413fec0, ··· 166 170 }; 167 171 168 172 static struct intc_vect vectors[] __initdata = { 173 + /* IRQ0->5 are handled in setup-sh3.c */ 169 174 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 170 175 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480), 171 176 INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0), ··· 211 214 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 212 215 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 213 216 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 214 - #if defined(CONFIG_CPU_SUBTYPE_SH7720) 215 217 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 216 - #else 217 - { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } }, 218 - #endif 219 218 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 220 219 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 221 220 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, ··· 222 229 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups, 223 230 NULL, prio_registers, NULL); 224 231 225 - static struct intc_sense_reg sense_registers[] __initdata = { 226 - { INTC_ICR1, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } }, 227 - }; 228 - 229 - static struct intc_vect vectors_irq[] __initdata = { 230 - INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 231 - INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 232 - INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 233 - }; 234 - 235 - static DECLARE_INTC_DESC(intc_irq_desc, "sh7720-irq", vectors_irq, 236 - NULL, NULL, prio_registers, sense_registers); 237 - 238 - void __init plat_irq_setup_pins(int mode) 239 - { 240 - switch (mode) { 241 - case IRQ_MODE_IRQ: 242 - ctrl_outw(ctrl_inw(INTC_ICR1) & INTC_ICR_IRQ, INTC_ICR1); 243 - register_intc_controller(&intc_irq_desc); 244 - break; 245 - default: 246 - BUG(); 247 - } 248 - } 249 - 250 232 void __init plat_irq_setup(void) 251 233 { 252 234 register_intc_controller(&intc_desc); 235 + plat_irq_setup_sh3(); 253 236 }

+28

arch/sh/kernel/cpu/sh5/entry.S

··· 143 143 trap_jtable: 144 144 .long do_exception_error /* 0x000 */ 145 145 .long do_exception_error /* 0x020 */ 146 + #ifdef CONFIG_MMU 146 147 .long tlb_miss_load /* 0x040 */ 147 148 .long tlb_miss_store /* 0x060 */ 149 + #else 150 + .long do_exception_error 151 + .long do_exception_error 152 + #endif 148 153 ! ARTIFICIAL pseudo-EXPEVT setting 149 154 .long do_debug_interrupt /* 0x080 */ 155 + #ifdef CONFIG_MMU 150 156 .long tlb_miss_load /* 0x0A0 */ 151 157 .long tlb_miss_store /* 0x0C0 */ 158 + #else 159 + .long do_exception_error 160 + .long do_exception_error 161 + #endif 152 162 .long do_address_error_load /* 0x0E0 */ 153 163 .long do_address_error_store /* 0x100 */ 154 164 #ifdef CONFIG_SH_FPU ··· 195 185 .endr 196 186 .long do_IRQ /* 0xA00 */ 197 187 .long do_IRQ /* 0xA20 */ 188 + #ifdef CONFIG_MMU 198 189 .long itlb_miss_or_IRQ /* 0xA40 */ 190 + #else 191 + .long do_IRQ 192 + #endif 199 193 .long do_IRQ /* 0xA60 */ 200 194 .long do_IRQ /* 0xA80 */ 195 + #ifdef CONFIG_MMU 201 196 .long itlb_miss_or_IRQ /* 0xAA0 */ 197 + #else 198 + .long do_IRQ 199 + #endif 202 200 .long do_exception_error /* 0xAC0 */ 203 201 .long do_address_error_exec /* 0xAE0 */ 204 202 .rept 8 ··· 292 274 * Instead of '.space 1024-TEXT_SIZE' place the RESVEC 293 275 * block making sure the final alignment is correct. 294 276 */ 277 + #ifdef CONFIG_MMU 295 278 tlb_miss: 296 279 synco /* TAKum03020 (but probably a good idea anyway.) */ 297 280 putcon SP, KCR1 ··· 396 377 getcon KCR1, SP 397 378 pta handle_exception, tr0 398 379 blink tr0, ZERO 380 + #else /* CONFIG_MMU */ 381 + .balign 256 382 + #endif 399 383 400 384 /* NB TAKE GREAT CARE HERE TO ENSURE THAT THE INTERRUPT CODE 401 385 DOES END UP AT VBR+0x600 */ ··· 1125 1103 * fpu_error_or_IRQ? is a helper to deflect to the right cause. 1126 1104 * 1127 1105 */ 1106 + #ifdef CONFIG_MMU 1128 1107 tlb_miss_load: 1129 1108 or SP, ZERO, r2 1130 1109 or ZERO, ZERO, r3 /* Read */ ··· 1155 1132 movi do_page_fault, r6 1156 1133 ptabs r6, tr0 1157 1134 blink tr0, ZERO 1135 + #endif /* CONFIG_MMU */ 1158 1136 1159 1137 fpu_error_or_IRQA: 1160 1138 pta its_IRQ, tr0 ··· 1505 1481 ptabs LINK, tr0 1506 1482 blink tr0, r63 1507 1483 1484 + #ifdef CONFIG_MMU 1508 1485 /* 1509 1486 * --- User Access Handling Section 1510 1487 */ ··· 1629 1604 ptabs LINK, tr0 1630 1605 blink tr0, ZERO 1631 1606 1607 + #endif /* CONFIG_MMU */ 1632 1608 1633 1609 /* 1634 1610 * int __strncpy_from_user(unsigned long __dest, unsigned long __src, ··· 2040 2014 .global asm_uaccess_start /* Just a marker */ 2041 2015 asm_uaccess_start: 2042 2016 2017 + #ifdef CONFIG_MMU 2043 2018 .long ___copy_user1, ___copy_user_exit 2044 2019 .long ___copy_user2, ___copy_user_exit 2045 2020 .long ___clear_user1, ___clear_user_exit 2021 + #endif 2046 2022 .long ___strncpy_from_user1, ___strncpy_from_user_exit 2047 2023 .long ___strnlen_user1, ___strnlen_user_exit 2048 2024 .long ___get_user_asm_b1, ___get_user_asm_b_exit

+4

arch/sh/kernel/cpu/sh5/probe.c

··· 15 15 #include <linux/string.h> 16 16 #include <asm/processor.h> 17 17 #include <asm/cache.h> 18 + #include <asm/tlb.h> 18 19 19 20 int __init detect_cpu_and_cache_system(void) 20 21 { ··· 67 66 #elif defined(CONFIG_CACHE_WRITEBACK) 68 67 set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags)); 69 68 #endif 69 + 70 + /* Setup some I/D TLB defaults */ 71 + sh64_tlb_init(); 70 72 71 73 return 0; 72 74 }

+18 -10

arch/sh/kernel/early_printk.c

··· 141 141 */ 142 142 static void scif_sercon_init(char *s) 143 143 { 144 + struct uart_port *port = &scif_port; 144 145 unsigned baud = DEFAULT_BAUD; 146 + unsigned int status; 145 147 char *e; 146 148 147 149 if (*s == ',') ··· 162 160 baud = DEFAULT_BAUD; 163 161 } 164 162 165 - ctrl_outw(0, scif_port.mapbase + 8); 166 - ctrl_outw(0, scif_port.mapbase); 163 + do { 164 + status = sci_in(port, SCxSR); 165 + } while (!(status & SCxSR_TEND(port))); 166 + 167 + sci_out(port, SCSCR, 0); /* TE=0, RE=0 */ 168 + sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 169 + sci_out(port, SCSMR, 0); 167 170 168 171 /* Set baud rate */ 169 - ctrl_outb((CONFIG_SH_PCLK_FREQ + 16 * baud) / 170 - (32 * baud) - 1, scif_port.mapbase + 4); 172 + sci_out(port, SCBRR, (CONFIG_SH_PCLK_FREQ + 16 * baud) / 173 + (32 * baud) - 1); 174 + udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ 171 175 172 - ctrl_outw(12, scif_port.mapbase + 24); 173 - ctrl_outw(8, scif_port.mapbase + 24); 174 - ctrl_outw(0, scif_port.mapbase + 32); 175 - ctrl_outw(0x60, scif_port.mapbase + 16); 176 - ctrl_outw(0, scif_port.mapbase + 36); 177 - ctrl_outw(0x30, scif_port.mapbase + 8); 176 + sci_out(port, SCSPTR, 0); 177 + sci_out(port, SCxSR, 0x60); 178 + sci_out(port, SCLSR, 0); 179 + 180 + sci_out(port, SCFCR, 0); 181 + sci_out(port, SCSCR, 0x30); /* TE=1, RE=1 */ 178 182 } 179 183 #endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */ 180 184 #endif /* !defined(CONFIG_SH_STANDARD_BIOS) */

+45 -1

arch/sh/kernel/setup.c

··· 53 53 * sh_mv= on the command line, prior to .machvec.init teardown. 54 54 */ 55 55 struct sh_machine_vector sh_mv = { .mv_name = "generic", }; 56 + EXPORT_SYMBOL(sh_mv); 56 57 57 58 #ifdef CONFIG_VT 58 59 struct screen_info screen_info; ··· 77 76 .flags = IORESOURCE_BUSY | IORESOURCE_MEM, 78 77 }; 79 78 79 + static struct resource bss_resource = { 80 + .name = "Kernel bss", 81 + .flags = IORESOURCE_BUSY | IORESOURCE_MEM, 82 + }; 83 + 80 84 unsigned long memory_start; 81 85 EXPORT_SYMBOL(memory_start); 82 86 unsigned long memory_end = 0; 83 87 EXPORT_SYMBOL(memory_end); 88 + 89 + static struct resource mem_resources[MAX_NUMNODES]; 84 90 85 91 int l1i_cache_shape, l1d_cache_shape, l2_cache_shape; 86 92 ··· 177 169 {} 178 170 #endif 179 171 172 + void __init __add_active_range(unsigned int nid, unsigned long start_pfn, 173 + unsigned long end_pfn) 174 + { 175 + struct resource *res = &mem_resources[nid]; 176 + 177 + WARN_ON(res->name); /* max one active range per node for now */ 178 + 179 + res->name = "System RAM"; 180 + res->start = start_pfn << PAGE_SHIFT; 181 + res->end = (end_pfn << PAGE_SHIFT) - 1; 182 + res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 183 + if (request_resource(&iomem_resource, res)) { 184 + pr_err("unable to request memory_resource 0x%lx 0x%lx\n", 185 + start_pfn, end_pfn); 186 + return; 187 + } 188 + 189 + /* 190 + * We don't know which RAM region contains kernel data, 191 + * so we try it repeatedly and let the resource manager 192 + * test it. 193 + */ 194 + request_resource(res, &code_resource); 195 + request_resource(res, &data_resource); 196 + request_resource(res, &bss_resource); 197 + 198 + #ifdef CONFIG_KEXEC 199 + if (crashk_res.start != crashk_res.end) 200 + request_resource(res, &crashk_res); 201 + #endif 202 + 203 + add_active_range(nid, start_pfn, end_pfn); 204 + } 205 + 180 206 void __init setup_bootmem_allocator(unsigned long free_pfn) 181 207 { 182 208 unsigned long bootmap_size; ··· 223 181 bootmap_size = init_bootmem_node(NODE_DATA(0), free_pfn, 224 182 min_low_pfn, max_low_pfn); 225 183 226 - add_active_range(0, min_low_pfn, max_low_pfn); 184 + __add_active_range(0, min_low_pfn, max_low_pfn); 227 185 register_bootmem_low_pages(); 228 186 229 187 node_set_online(0); ··· 309 267 code_resource.end = virt_to_phys(_etext)-1; 310 268 data_resource.start = virt_to_phys(_etext); 311 269 data_resource.end = virt_to_phys(_edata)-1; 270 + bss_resource.start = virt_to_phys(__bss_start); 271 + bss_resource.end = virt_to_phys(_ebss)-1; 312 272 313 273 memory_start = (unsigned long)__va(__MEMORY_START); 314 274 if (!memory_end)

-2

arch/sh/kernel/sh_ksyms_32.c

··· 20 20 extern int dump_fpu(struct pt_regs *, elf_fpregset_t *); 21 21 extern struct hw_interrupt_type no_irq_type; 22 22 23 - EXPORT_SYMBOL(sh_mv); 24 - 25 23 /* platform dependent support */ 26 24 EXPORT_SYMBOL(dump_fpu); 27 25 EXPORT_SYMBOL(kernel_thread);

+26

arch/sh/kernel/sh_ksyms_64.c

··· 16 16 #include <linux/in6.h> 17 17 #include <linux/interrupt.h> 18 18 #include <linux/screen_info.h> 19 + #include <asm/cacheflush.h> 19 20 #include <asm/processor.h> 20 21 #include <asm/uaccess.h> 21 22 #include <asm/checksum.h> ··· 30 29 EXPORT_SYMBOL(dump_fpu); 31 30 EXPORT_SYMBOL(kernel_thread); 32 31 32 + #if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) 33 + EXPORT_SYMBOL(clear_user_page); 34 + #endif 35 + 36 + #ifndef CONFIG_CACHE_OFF 37 + EXPORT_SYMBOL(flush_dcache_page); 38 + #endif 39 + 33 40 /* Networking helper routines. */ 41 + EXPORT_SYMBOL(csum_partial); 34 42 EXPORT_SYMBOL(csum_partial_copy_nocheck); 43 + #ifdef CONFIG_IPV6 44 + EXPORT_SYMBOL(csum_ipv6_magic); 45 + #endif 35 46 36 47 #ifdef CONFIG_VT 37 48 EXPORT_SYMBOL(screen_info); 38 49 #endif 39 50 51 + EXPORT_SYMBOL(__put_user_asm_b); 52 + EXPORT_SYMBOL(__put_user_asm_w); 40 53 EXPORT_SYMBOL(__put_user_asm_l); 54 + EXPORT_SYMBOL(__put_user_asm_q); 55 + EXPORT_SYMBOL(__get_user_asm_b); 56 + EXPORT_SYMBOL(__get_user_asm_w); 41 57 EXPORT_SYMBOL(__get_user_asm_l); 58 + EXPORT_SYMBOL(__get_user_asm_q); 59 + EXPORT_SYMBOL(__strnlen_user); 60 + EXPORT_SYMBOL(__strncpy_from_user); 61 + EXPORT_SYMBOL(clear_page); 62 + EXPORT_SYMBOL(__clear_user); 42 63 EXPORT_SYMBOL(copy_page); 43 64 EXPORT_SYMBOL(__copy_user); 44 65 EXPORT_SYMBOL(empty_zero_page); 45 66 EXPORT_SYMBOL(memcpy); 46 67 EXPORT_SYMBOL(__udelay); 47 68 EXPORT_SYMBOL(__ndelay); 69 + EXPORT_SYMBOL(__const_udelay); 48 70 49 71 /* Ugh. These come in from libgcc.a at link time. */ 50 72 #define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name) 51 73 52 74 DECLARE_EXPORT(__sdivsi3); 75 + DECLARE_EXPORT(__sdivsi3_2); 53 76 DECLARE_EXPORT(__muldi3); 54 77 DECLARE_EXPORT(__udivsi3); 78 + DECLARE_EXPORT(__div_table);

+3 -2

arch/sh/kernel/time_64.c

··· 172 172 tv->tv_sec = sec; 173 173 tv->tv_usec = usec; 174 174 } 175 + EXPORT_SYMBOL(do_gettimeofday); 175 176 176 177 int do_settimeofday(struct timespec *tv) 177 178 { ··· 241 240 * the irq version of write_lock because as just said we have irq 242 241 * locally disabled. -arca 243 242 */ 244 - write_lock(&xtime_lock); 243 + write_seqlock(&xtime_lock); 245 244 asm ("getcon cr62, %0" : "=r" (current_ctc)); 246 245 ctc_last_interrupt = (unsigned long) current_ctc; 247 246 ··· 267 266 /* do it again in 60 s */ 268 267 last_rtc_update = xtime.tv_sec - 600; 269 268 } 270 - write_unlock(&xtime_lock); 269 + write_sequnlock(&xtime_lock); 271 270 272 271 #ifndef CONFIG_SMP 273 272 update_process_times(user_mode(get_irq_regs()));

+1 -1

arch/sh/lib64/dbg.c

··· 186 186 rr->pc = regs->pc; 187 187 188 188 if (sp < stack_bottom + 3092) { 189 - printk("evt_debug : stack underflow report\n"); 190 189 int i, j; 190 + printk("evt_debug : stack underflow report\n"); 191 191 for (j=0, i = event_ptr; j<16; j++) { 192 192 rr = event_ring + i; 193 193 printk("evt=%08x event=%08x tra=%08x pid=%5d sp=%08lx pc=%08lx\n",

+4 -3

arch/sh/mm/Makefile_64

··· 2 2 # Makefile for the Linux SuperH-specific parts of the memory manager. 3 3 # 4 4 5 - obj-y := init.o extable_64.o consistent.o 5 + obj-y := init.o consistent.o 6 6 7 - mmu-y := tlb-nommu.o pg-nommu.o 8 - mmu-$(CONFIG_MMU) := fault_64.o ioremap_64.o tlbflush_64.o tlb-sh5.o 7 + mmu-y := tlb-nommu.o pg-nommu.o extable_32.o 8 + mmu-$(CONFIG_MMU) := fault_64.o ioremap_64.o tlbflush_64.o tlb-sh5.o \ 9 + extable_64.o 9 10 10 11 ifndef CONFIG_CACHE_OFF 11 12 obj-y += cache-sh5.o

+2

arch/sh/mm/cache-sh5.c

··· 714 714 sh64_icache_inv_current_user_range(vaddr, end); 715 715 } 716 716 717 + #ifdef CONFIG_MMU 717 718 /* 718 719 * These *MUST* lie in an area of virtual address space that's otherwise 719 720 * unused. ··· 831 830 else 832 831 sh64_clear_user_page_coloured(to, address); 833 832 } 833 + #endif

+2

arch/sh/mm/ioremap_64.c

··· 343 343 344 344 return shmedia_alloc_io(phys, size, name); 345 345 } 346 + EXPORT_SYMBOL(onchip_remap); 346 347 347 348 void onchip_unmap(unsigned long vaddr) 348 349 { ··· 371 370 kfree(res); 372 371 } 373 372 } 373 + EXPORT_SYMBOL(onchip_unmap); 374 374 375 375 #ifdef CONFIG_PROC_FS 376 376 static int

+1 -1

arch/sh/mm/numa.c

··· 59 59 free_pfn = start_pfn = start >> PAGE_SHIFT; 60 60 end_pfn = end >> PAGE_SHIFT; 61 61 62 - add_active_range(nid, start_pfn, end_pfn); 62 + __add_active_range(nid, start_pfn, end_pfn); 63 63 64 64 /* Node-local pgdat */ 65 65 NODE_DATA(nid) = pfn_to_kaddr(free_pfn);

-1

arch/sh/tools/mach-types

··· 28 28 7751SYSTEMH SH_7751_SYSTEMH 29 29 HP6XX SH_HP6XX 30 30 DREAMCAST SH_DREAMCAST 31 - MPC1211 SH_MPC1211 32 31 SNAPGEAR SH_SECUREEDGE5410 33 32 EDOSK7705 SH_EDOSK7705 34 33 SH4202_MICRODEV SH_SH4202_MICRODEV

+1 -1

drivers/input/serio/i8042-io.h

··· 25 25 #elif defined(__arm__) 26 26 /* defined in include/asm-arm/arch-xxx/irqs.h */ 27 27 #include <asm/irq.h> 28 - #elif defined(CONFIG_SUPERH64) 28 + #elif defined(CONFIG_SH_CAYMAN) 29 29 #include <asm/irq.h> 30 30 #else 31 31 # define I8042_KBD_IRQ 1

+1 -8

drivers/mtd/maps/Kconfig

··· 374 374 375 375 config MTD_SOLUTIONENGINE 376 376 tristate "CFI Flash device mapped on Hitachi SolutionEngine" 377 - depends on SUPERH && MTD_CFI && MTD_REDBOOT_PARTS 377 + depends on SUPERH && SOLUTION_ENGINE && MTD_CFI && MTD_REDBOOT_PARTS 378 378 help 379 379 This enables access to the flash chips on the Hitachi SolutionEngine and 380 380 similar boards. Say 'Y' if you are building a kernel for such a board. ··· 478 478 depends on MTD_CFI && ( ARCH_H7201 || ARCH_H7202 ) 479 479 help 480 480 This enables access to the flash chips on the Hynix evaluation boards. 481 - If you have such a board, say 'Y'. 482 - 483 - config MTD_MPC1211 484 - tristate "CFI Flash device mapped on Interface MPC-1211" 485 - depends on SH_MPC1211 && MTD_CFI 486 - help 487 - This enables access to the flash chips on the Interface MPC-1211(CTP/PCI/MPC-SH02). 488 481 If you have such a board, say 'Y'. 489 482 490 483 config MTD_OMAP_NOR

-1

drivers/mtd/maps/Makefile

··· 58 58 obj-$(CONFIG_MTD_H720X) += h720x-flash.o 59 59 obj-$(CONFIG_MTD_SBC8240) += sbc8240.o 60 60 obj-$(CONFIG_MTD_NOR_TOTO) += omap-toto-flash.o 61 - obj-$(CONFIG_MTD_MPC1211) += mpc1211.o 62 61 obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o 63 62 obj-$(CONFIG_MTD_IXP2000) += ixp2000.o 64 63 obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o

-80

drivers/mtd/maps/mpc1211.c

··· 1 - /* 2 - * Flash on MPC-1211 3 - * 4 - * $Id: mpc1211.c,v 1.4 2004/09/16 23:27:13 gleixner Exp $ 5 - * 6 - * (C) 2002 Interface, Saito.K & Jeanne 7 - * 8 - * GPL'd 9 - */ 10 - 11 - #include <linux/module.h> 12 - #include <linux/types.h> 13 - #include <linux/kernel.h> 14 - #include <asm/io.h> 15 - #include <linux/mtd/mtd.h> 16 - #include <linux/mtd/map.h> 17 - #include <linux/mtd/partitions.h> 18 - 19 - static struct mtd_info *flash_mtd; 20 - static struct mtd_partition *parsed_parts; 21 - 22 - struct map_info mpc1211_flash_map = { 23 - .name = "MPC-1211 FLASH", 24 - .size = 0x80000, 25 - .bankwidth = 1, 26 - }; 27 - 28 - static struct mtd_partition mpc1211_partitions[] = { 29 - { 30 - .name = "IPL & ETH-BOOT", 31 - .offset = 0x00000000, 32 - .size = 0x10000, 33 - }, 34 - { 35 - .name = "Flash FS", 36 - .offset = 0x00010000, 37 - .size = MTDPART_SIZ_FULL, 38 - } 39 - }; 40 - 41 - static int __init init_mpc1211_maps(void) 42 - { 43 - int nr_parts; 44 - 45 - mpc1211_flash_map.phys = 0; 46 - mpc1211_flash_map.virt = (void __iomem *)P2SEGADDR(0); 47 - 48 - simple_map_init(&mpc1211_flash_map); 49 - 50 - printk(KERN_NOTICE "Probing for flash chips at 0x00000000:\n"); 51 - flash_mtd = do_map_probe("jedec_probe", &mpc1211_flash_map); 52 - if (!flash_mtd) { 53 - printk(KERN_NOTICE "Flash chips not detected at either possible location.\n"); 54 - return -ENXIO; 55 - } 56 - printk(KERN_NOTICE "MPC-1211: Flash at 0x%08lx\n", mpc1211_flash_map.virt & 0x1fffffff); 57 - flash_mtd->module = THIS_MODULE; 58 - 59 - parsed_parts = mpc1211_partitions; 60 - nr_parts = ARRAY_SIZE(mpc1211_partitions); 61 - 62 - add_mtd_partitions(flash_mtd, parsed_parts, nr_parts); 63 - return 0; 64 - } 65 - 66 - static void __exit cleanup_mpc1211_maps(void) 67 - { 68 - if (parsed_parts) 69 - del_mtd_partitions(flash_mtd); 70 - else 71 - del_mtd_device(flash_mtd); 72 - map_destroy(flash_mtd); 73 - } 74 - 75 - module_init(init_mpc1211_maps); 76 - module_exit(cleanup_mpc1211_maps); 77 - 78 - MODULE_LICENSE("GPL"); 79 - MODULE_AUTHOR("Saito.K & Jeanne <ksaito@interface.co.jp>"); 80 - MODULE_DESCRIPTION("MTD map driver for MPC-1211 boards. Interface");

+9 -5

drivers/rtc/rtc-sh.c

··· 616 616 goto err_badres; 617 617 } 618 618 619 - rtc->regbase = (void __iomem *)rtc->res->start; 619 + rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize); 620 620 if (unlikely(!rtc->regbase)) { 621 621 ret = -EINVAL; 622 622 goto err_badmap; ··· 626 626 &sh_rtc_ops, THIS_MODULE); 627 627 if (IS_ERR(rtc->rtc_dev)) { 628 628 ret = PTR_ERR(rtc->rtc_dev); 629 - goto err_badmap; 629 + goto err_unmap; 630 630 } 631 631 632 632 rtc->capabilities = RTC_DEF_CAPABILITIES; ··· 653 653 dev_err(&pdev->dev, 654 654 "request period IRQ failed with %d, IRQ %d\n", ret, 655 655 rtc->periodic_irq); 656 - goto err_badmap; 656 + goto err_unmap; 657 657 } 658 658 659 659 ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED, ··· 663 663 "request carry IRQ failed with %d, IRQ %d\n", ret, 664 664 rtc->carry_irq); 665 665 free_irq(rtc->periodic_irq, rtc); 666 - goto err_badmap; 666 + goto err_unmap; 667 667 } 668 668 669 669 ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED, ··· 674 674 rtc->alarm_irq); 675 675 free_irq(rtc->carry_irq, rtc); 676 676 free_irq(rtc->periodic_irq, rtc); 677 - goto err_badmap; 677 + goto err_unmap; 678 678 } 679 679 680 680 tmp = readb(rtc->regbase + RCR1); ··· 684 684 685 685 return 0; 686 686 687 + err_unmap: 688 + iounmap(rtc->regbase); 687 689 err_badmap: 688 690 release_resource(rtc->res); 689 691 err_badres: ··· 709 707 free_irq(rtc->alarm_irq, rtc); 710 708 711 709 release_resource(rtc->res); 710 + 711 + iounmap(rtc->regbase); 712 712 713 713 platform_set_drvdata(pdev, NULL); 714 714

+14 -18

drivers/serial/sh-sci.c

··· 42 42 #include <linux/console.h> 43 43 #include <linux/platform_device.h> 44 44 #include <linux/serial_sci.h> 45 - 46 - #ifdef CONFIG_CPU_FREQ 47 45 #include <linux/notifier.h> 48 46 #include <linux/cpufreq.h> 49 - #endif 50 - 51 - #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) 47 + #include <linux/clk.h> 52 48 #include <linux/ctype.h> 49 + 50 + #ifdef CONFIG_SUPERH 53 51 #include <asm/clock.h> 54 52 #include <asm/sh_bios.h> 55 53 #include <asm/kgdb.h> ··· 78 80 struct timer_list break_timer; 79 81 int break_flag; 80 82 81 - #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) 83 + #ifdef CONFIG_SUPERH 82 84 /* Port clock */ 83 85 struct clk *clk; 84 86 #endif ··· 363 365 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 364 366 { 365 367 unsigned int fcr_val = 0; 368 + unsigned short data; 366 369 367 - if (cflag & CRTSCTS) { 368 - fcr_val |= SCFCR_MCE; 370 + if (port->mapbase == 0xffe00000) { 371 + data = ctrl_inw(PSCR); 372 + data &= ~0x03cf; 373 + if (cflag & CRTSCTS) 374 + fcr_val |= SCFCR_MCE; 375 + else 376 + data |= 0x0340; 369 377 370 - ctrl_outw(0x0000, PORT_PSCR); 371 - } else { 372 - unsigned short data; 373 - 374 - data = ctrl_inw(PORT_PSCR); 375 - data &= 0x033f; 376 - data |= 0x0400; 377 - ctrl_outw(data, PORT_PSCR); 378 - 379 - ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0); 378 + ctrl_outw(data, PSCR); 380 379 } 380 + /* SCIF1 and SCIF2 should be setup by board code */ 381 381 382 382 sci_out(port, SCFCR, fcr_val); 383 383 }

+22 -5

drivers/serial/sh-sci.h

··· 76 76 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 77 77 # define SCIF_ONLY 78 78 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) 79 - # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 80 - # define SCSPTR0 SCPDR0 79 + # define PADR 0xA4050120 80 + # define PSDR 0xA405013e 81 + # define PWDR 0xA4050166 82 + # define PSCR 0xA405011E 81 83 # define SCIF_ORER 0x0001 /* overrun error bit */ 82 84 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 83 85 # define SCIF_ONLY 84 - # define PORT_PSCR 0xA405011E 85 86 #elif defined(CONFIG_CPU_SUBTYPE_SH7366) 86 87 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 87 88 # define SCSPTR0 SCPDR0 ··· 321 320 unsigned int addr = port->mapbase + (offset); \ 322 321 if ((size) == 8) { \ 323 322 ctrl_outb(value, addr); \ 324 - } else { \ 323 + } else if ((size) == 16) { \ 325 324 ctrl_outw(value, addr); \ 326 325 } 327 326 ··· 452 451 SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 453 452 #else 454 453 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 454 + #if defined(CONFIG_CPU_SUBTYPE_SH7722) 455 + SCIF_FNS(SCSPTR, 0, 0, 0, 0) 456 + #else 455 457 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 458 + #endif 456 459 SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 457 460 #endif 458 461 #endif ··· 598 593 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 599 594 return 1; 600 595 } 601 - #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366) 596 + #elif defined(CONFIG_CPU_SUBTYPE_SH7366) 602 597 static inline int sci_rxd_in(struct uart_port *port) 603 598 { 604 599 if (port->mapbase == 0xffe00000) 605 600 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ 601 + return 1; 602 + } 603 + #elif defined(CONFIG_CPU_SUBTYPE_SH7722) 604 + static inline int sci_rxd_in(struct uart_port *port) 605 + { 606 + if (port->mapbase == 0xffe00000) 607 + return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ 608 + if (port->mapbase == 0xffe10000) 609 + return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ 610 + if (port->mapbase == 0xffe20000) 611 + return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ 612 + 606 613 return 1; 607 614 } 608 615 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)

+5 -5

include/asm-sh/cpu-sh3/dma.h

··· 3 3 4 4 5 5 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 6 - defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 7 - defined(CONFIG_CPU_SUBTYPE_SH7709) 6 + defined(CONFIG_CPU_SUBTYPE_SH7721) 8 7 #define SH_DMAC_BASE 0xa4010020 8 + #else 9 + #define SH_DMAC_BASE 0xa4000020 10 + #endif 9 11 12 + #if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709) 10 13 #define DMTE0_IRQ 48 11 14 #define DMTE1_IRQ 49 12 15 #define DMTE2_IRQ 50 13 16 #define DMTE3_IRQ 51 14 17 #define DMTE4_IRQ 76 15 18 #define DMTE5_IRQ 77 16 - 17 - #else 18 - #define SH_DMAC_BASE 0xa4000020 19 19 #endif 20 20 21 21 /* Definitions for the SuperH DMAC */

+19

include/asm-sh/hw_irq.h

··· 79 79 struct intc_sense_reg *sense_regs; 80 80 unsigned int nr_sense_regs; 81 81 char *name; 82 + #ifdef CONFIG_CPU_SH3 83 + struct intc_mask_reg *ack_regs; 84 + unsigned int nr_ack_regs; 85 + #endif 82 86 }; 83 87 84 88 #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) ··· 95 91 chipname, \ 96 92 } 97 93 94 + #ifdef CONFIG_CPU_SH3 95 + #define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \ 96 + mask_regs, prio_regs, sense_regs, ack_regs) \ 97 + struct intc_desc symbol __initdata = { \ 98 + _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ 99 + _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ 100 + _INTC_ARRAY(sense_regs), \ 101 + chipname, \ 102 + _INTC_ARRAY(ack_regs), \ 103 + } 104 + #endif 105 + 98 106 void __init register_intc_controller(struct intc_desc *desc); 99 107 int intc_set_priority(unsigned int irq, unsigned int prio); 100 108 101 109 void __init plat_irq_setup(void); 110 + #ifdef CONFIG_CPU_SH3 111 + void __init plat_irq_setup_sh3(void); 112 + #endif 102 113 103 114 enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210, 104 115 IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,

+7 -5

include/asm-sh/io.h

··· 268 268 unsigned long long poke_real_address_q(unsigned long long addr, 269 269 unsigned long long val); 270 270 271 - /* arch/sh/mm/ioremap_64.c */ 272 - unsigned long onchip_remap(unsigned long addr, unsigned long size, 273 - const char *name); 274 - extern void onchip_unmap(unsigned long vaddr); 275 - 276 271 #if !defined(CONFIG_MMU) 277 272 #define virt_to_phys(address) ((unsigned long)(address)) 278 273 #define phys_to_virt(address) ((void *)(address)) ··· 297 302 void __iomem *__ioremap(unsigned long offset, unsigned long size, 298 303 unsigned long flags); 299 304 void __iounmap(void __iomem *addr); 305 + 306 + /* arch/sh/mm/ioremap_64.c */ 307 + unsigned long onchip_remap(unsigned long addr, unsigned long size, 308 + const char *name); 309 + extern void onchip_unmap(unsigned long vaddr); 300 310 #else 301 311 #define __ioremap(offset, size, flags) ((void __iomem *)(offset)) 302 312 #define __iounmap(addr) do { } while (0) 313 + #define onchip_remap(addr, size, name) (addr) 314 + #define onchip_unmap(addr) do { } while (0) 303 315 #endif /* CONFIG_MMU */ 304 316 305 317 static inline void __iomem *

-13

include/asm-sh/keyboard.h

··· 1 - #ifndef __ASM_SH_KEYBOARD_H 2 - #define __ASM_SH_KEYBOARD_H 3 - /* 4 - * $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $ 5 - */ 6 - 7 - #include <linux/kd.h> 8 - #include <asm/machvec.h> 9 - 10 - #ifdef CONFIG_SH_MPC1211 11 - #include <asm/mpc1211/keyboard-mpc1211.h> 12 - #endif 13 - #endif

+3 -1

include/asm-sh/mmu_context.h

··· 27 27 /* ASID is 8-bit value, so it can't be 0x100 */ 28 28 #define MMU_NO_ASID 0x100 29 29 30 + #ifdef CONFIG_MMU 30 31 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 31 32 #define cpu_context(cpu, mm) ((mm)->context.id[cpu]) 32 33 ··· 39 38 */ 40 39 #define MMU_VPN_MASK 0xfffff000 41 40 42 - #ifdef CONFIG_MMU 43 41 #if defined(CONFIG_SUPERH32) 44 42 #include "mmu_context_32.h" 45 43 #else ··· 129 129 #define destroy_context(mm) do { } while (0) 130 130 #define set_asid(asid) do { } while (0) 131 131 #define get_asid() (0) 132 + #define cpu_asid(cpu, mm) ({ (void)cpu; 0; }) 133 + #define switch_and_save_asid(asid) (0) 132 134 #define set_TTB(pgd) do { } while (0) 133 135 #define get_TTB() (0) 134 136 #define activate_context(mm,cpu) do { } while (0)

+2

include/asm-sh/mmzone.h

··· 41 41 42 42 /* arch/sh/kernel/setup.c */ 43 43 void __init setup_bootmem_allocator(unsigned long start_pfn); 44 + void __init __add_active_range(unsigned int nid, unsigned long start_pfn, 45 + unsigned long end_pfn); 44 46 45 47 #endif /* __KERNEL__ */ 46 48 #endif /* __ASM_SH_MMZONE_H */

-303

include/asm-sh/mpc1211/dma.h

··· 1 - /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $ 2 - * linux/include/asm/dma.h: Defines for using and allocating dma channels. 3 - * Written by Hennus Bergman, 1992. 4 - * High DMA channel support & info by Hannu Savolainen 5 - * and John Boyd, Nov. 1992. 6 - */ 7 - 8 - #ifndef _ASM_MPC1211_DMA_H 9 - #define _ASM_MPC1211_DMA_H 10 - 11 - #include <linux/spinlock.h> /* And spinlocks */ 12 - #include <asm/io.h> /* need byte IO */ 13 - #include <linux/delay.h> 14 - 15 - 16 - #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER 17 - #define dma_outb outb_p 18 - #else 19 - #define dma_outb outb 20 - #endif 21 - 22 - #define dma_inb inb 23 - 24 - /* 25 - * NOTES about DMA transfers: 26 - * 27 - * controller 1: channels 0-3, byte operations, ports 00-1F 28 - * controller 2: channels 4-7, word operations, ports C0-DF 29 - * 30 - * - ALL registers are 8 bits only, regardless of transfer size 31 - * - channel 4 is not used - cascades 1 into 2. 32 - * - channels 0-3 are byte - addresses/counts are for physical bytes 33 - * - channels 5-7 are word - addresses/counts are for physical words 34 - * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries 35 - * - transfer count loaded to registers is 1 less than actual count 36 - * - controller 2 offsets are all even (2x offsets for controller 1) 37 - * - page registers for 5-7 don't use data bit 0, represent 128K pages 38 - * - page registers for 0-3 use bit 0, represent 64K pages 39 - * 40 - * DMA transfers are limited to the lower 16MB of _physical_ memory. 41 - * Note that addresses loaded into registers must be _physical_ addresses, 42 - * not logical addresses (which may differ if paging is active). 43 - * 44 - * Address mapping for channels 0-3: 45 - * 46 - * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) 47 - * | ... | | ... | | ... | 48 - * | ... | | ... | | ... | 49 - * | ... | | ... | | ... | 50 - * P7 ... P0 A7 ... A0 A7 ... A0 51 - * | Page | Addr MSB | Addr LSB | (DMA registers) 52 - * 53 - * Address mapping for channels 5-7: 54 - * 55 - * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) 56 - * | ... | \ \ ... \ \ \ ... \ \ 57 - * | ... | \ \ ... \ \ \ ... \ (not used) 58 - * | ... | \ \ ... \ \ \ ... \ 59 - * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 60 - * | Page | Addr MSB | Addr LSB | (DMA registers) 61 - * 62 - * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses 63 - * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at 64 - * the hardware level, so odd-byte transfers aren't possible). 65 - * 66 - * Transfer count (_not # bytes_) is limited to 64K, represented as actual 67 - * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, 68 - * and up to 128K bytes may be transferred on channels 5-7 in one operation. 69 - * 70 - */ 71 - 72 - #define MAX_DMA_CHANNELS 8 73 - 74 - /* The maximum address that we can perform a DMA transfer to on this platform */ 75 - #define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000) 76 - 77 - /* 8237 DMA controllers */ 78 - #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 79 - #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 80 - 81 - /* DMA controller registers */ 82 - #define DMA1_CMD_REG 0x08 /* command register (w) */ 83 - #define DMA1_STAT_REG 0x08 /* status register (r) */ 84 - #define DMA1_REQ_REG 0x09 /* request register (w) */ 85 - #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 86 - #define DMA1_MODE_REG 0x0B /* mode register (w) */ 87 - #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 88 - #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 89 - #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 90 - #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 91 - #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 92 - 93 - #define DMA2_CMD_REG 0xD0 /* command register (w) */ 94 - #define DMA2_STAT_REG 0xD0 /* status register (r) */ 95 - #define DMA2_REQ_REG 0xD2 /* request register (w) */ 96 - #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 97 - #define DMA2_MODE_REG 0xD6 /* mode register (w) */ 98 - #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 99 - #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 100 - #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 101 - #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 102 - #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 103 - 104 - #define DMA_ADDR_0 0x00 /* DMA address registers */ 105 - #define DMA_ADDR_1 0x02 106 - #define DMA_ADDR_2 0x04 107 - #define DMA_ADDR_3 0x06 108 - #define DMA_ADDR_4 0xC0 109 - #define DMA_ADDR_5 0xC4 110 - #define DMA_ADDR_6 0xC8 111 - #define DMA_ADDR_7 0xCC 112 - 113 - #define DMA_CNT_0 0x01 /* DMA count registers */ 114 - #define DMA_CNT_1 0x03 115 - #define DMA_CNT_2 0x05 116 - #define DMA_CNT_3 0x07 117 - #define DMA_CNT_4 0xC2 118 - #define DMA_CNT_5 0xC6 119 - #define DMA_CNT_6 0xCA 120 - #define DMA_CNT_7 0xCE 121 - 122 - #define DMA_PAGE_0 0x87 /* DMA page registers */ 123 - #define DMA_PAGE_1 0x83 124 - #define DMA_PAGE_2 0x81 125 - #define DMA_PAGE_3 0x82 126 - #define DMA_PAGE_5 0x8B 127 - #define DMA_PAGE_6 0x89 128 - #define DMA_PAGE_7 0x8A 129 - 130 - #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ 131 - #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ 132 - #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 133 - 134 - #define DMA_AUTOINIT 0x10 135 - 136 - 137 - extern spinlock_t dma_spin_lock; 138 - 139 - static __inline__ unsigned long claim_dma_lock(void) 140 - { 141 - unsigned long flags; 142 - spin_lock_irqsave(&dma_spin_lock, flags); 143 - return flags; 144 - } 145 - 146 - static __inline__ void release_dma_lock(unsigned long flags) 147 - { 148 - spin_unlock_irqrestore(&dma_spin_lock, flags); 149 - } 150 - 151 - /* enable/disable a specific DMA channel */ 152 - static __inline__ void enable_dma(unsigned int dmanr) 153 - { 154 - if (dmanr<=3) 155 - dma_outb(dmanr, DMA1_MASK_REG); 156 - else 157 - dma_outb(dmanr & 3, DMA2_MASK_REG); 158 - } 159 - 160 - static __inline__ void disable_dma(unsigned int dmanr) 161 - { 162 - if (dmanr<=3) 163 - dma_outb(dmanr | 4, DMA1_MASK_REG); 164 - else 165 - dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 166 - } 167 - 168 - /* Clear the 'DMA Pointer Flip Flop'. 169 - * Write 0 for LSB/MSB, 1 for MSB/LSB access. 170 - * Use this once to initialize the FF to a known state. 171 - * After that, keep track of it. :-) 172 - * --- In order to do that, the DMA routines below should --- 173 - * --- only be used while holding the DMA lock ! --- 174 - */ 175 - static __inline__ void clear_dma_ff(unsigned int dmanr) 176 - { 177 - if (dmanr<=3) 178 - dma_outb(0, DMA1_CLEAR_FF_REG); 179 - else 180 - dma_outb(0, DMA2_CLEAR_FF_REG); 181 - } 182 - 183 - /* set mode (above) for a specific DMA channel */ 184 - static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 185 - { 186 - if (dmanr<=3) 187 - dma_outb(mode | dmanr, DMA1_MODE_REG); 188 - else 189 - dma_outb(mode | (dmanr&3), DMA2_MODE_REG); 190 - } 191 - 192 - /* Set only the page register bits of the transfer address. 193 - * This is used for successive transfers when we know the contents of 194 - * the lower 16 bits of the DMA current address register, but a 64k boundary 195 - * may have been crossed. 196 - */ 197 - static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr) 198 - { 199 - switch(dmanr) { 200 - case 0: 201 - dma_outb( pagenr & 0xff, DMA_PAGE_0); 202 - dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400); 203 - break; 204 - case 1: 205 - dma_outb( pagenr & 0xff, DMA_PAGE_1); 206 - dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400); 207 - break; 208 - case 2: 209 - dma_outb( pagenr & 0xff, DMA_PAGE_2); 210 - dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400); 211 - break; 212 - case 3: 213 - dma_outb( pagenr & 0xff, DMA_PAGE_3); 214 - dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400); 215 - break; 216 - case 5: 217 - dma_outb( pagenr & 0xfe, DMA_PAGE_5); 218 - dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400); 219 - break; 220 - case 6: 221 - dma_outb( pagenr & 0xfe, DMA_PAGE_6); 222 - dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400); 223 - break; 224 - case 7: 225 - dma_outb( pagenr & 0xfe, DMA_PAGE_7); 226 - dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400); 227 - break; 228 - } 229 - } 230 - 231 - 232 - /* Set transfer address & page bits for specific DMA channel. 233 - * Assumes dma flipflop is clear. 234 - */ 235 - static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) 236 - { 237 - set_dma_page(dmanr, a>>16); 238 - if (dmanr <= 3) { 239 - dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 240 - dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 241 - } else { 242 - dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 243 - dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 244 - } 245 - } 246 - 247 - 248 - /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for 249 - * a specific DMA channel. 250 - * You must ensure the parameters are valid. 251 - * NOTE: from a manual: "the number of transfers is one more 252 - * than the initial word count"! This is taken into account. 253 - * Assumes dma flip-flop is clear. 254 - * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 255 - */ 256 - static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 257 - { 258 - count--; 259 - if (dmanr <= 3) { 260 - dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 261 - dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 262 - } else { 263 - dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 264 - dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 265 - } 266 - } 267 - 268 - 269 - /* Get DMA residue count. After a DMA transfer, this 270 - * should return zero. Reading this while a DMA transfer is 271 - * still in progress will return unpredictable results. 272 - * If called before the channel has been used, it may return 1. 273 - * Otherwise, it returns the number of _bytes_ left to transfer. 274 - * 275 - * Assumes DMA flip-flop is clear. 276 - */ 277 - static __inline__ int get_dma_residue(unsigned int dmanr) 278 - { 279 - unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE 280 - : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; 281 - 282 - /* using short to get 16-bit wrap around */ 283 - unsigned short count; 284 - 285 - count = 1 + dma_inb(io_port); 286 - count += dma_inb(io_port) << 8; 287 - return (dmanr<=3)? count : (count<<1); 288 - } 289 - 290 - 291 - /* These are in kernel/dma.c: */ 292 - extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ 293 - extern void free_dma(unsigned int dmanr); /* release it again */ 294 - 295 - /* From PCI */ 296 - 297 - #ifdef CONFIG_PCI 298 - extern int isa_dma_bridge_buggy; 299 - #else 300 - #define isa_dma_bridge_buggy (0) 301 - #endif 302 - 303 - #endif /* _ASM_MPC1211_DMA_H */

-22

include/asm-sh/mpc1211/io.h

··· 1 - /* 2 - * include/asm-sh/mpc1211/io.h 3 - * 4 - * Copyright 2001 Saito.K & Jeanne 5 - * 6 - * IO functions for an Interface MPC-1211 7 - */ 8 - 9 - #ifndef _ASM_SH_IO_MPC1211_H 10 - #define _ASM_SH_IO_MPC1211_H 11 - 12 - #include <linux/time.h> 13 - 14 - extern int mpc1211_irq_demux(int irq); 15 - 16 - extern void init_mpc1211_IRQ(void); 17 - extern void heartbeat_mpc1211(void); 18 - 19 - extern void mpc1211_rtc_gettimeofday(struct timeval *tv); 20 - extern int mpc1211_rtc_settimeofday(const struct timeval *tv); 21 - 22 - #endif /* _ASM_SH_IO_MPC1211_H */

-60

include/asm-sh/mpc1211/keyboard.h

··· 1 - /* 2 - * MPC1211 specific keybord definitions 3 - * Taken from the old asm-i386/keybord.h for PC/AT-style definitions 4 - * created 3 Nov 1996 by Geert Uytterhoeven. 5 - */ 6 - 7 - #ifdef __KERNEL__ 8 - 9 - #include <linux/kernel.h> 10 - #include <linux/ioport.h> 11 - #include <linux/kd.h> 12 - #include <linux/pm.h> 13 - #include <asm/io.h> 14 - 15 - #define KEYBOARD_IRQ 1 16 - #define DISABLE_KBD_DURING_INTERRUPTS 0 17 - 18 - extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode); 19 - extern int pckbd_getkeycode(unsigned int scancode); 20 - extern int pckbd_translate(unsigned char scancode, unsigned char *keycode, 21 - char raw_mode); 22 - extern char pckbd_unexpected_up(unsigned char keycode); 23 - extern void pckbd_leds(unsigned char leds); 24 - extern void pckbd_init_hw(void); 25 - extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *); 26 - extern pm_callback pm_kbd_request_override; 27 - 28 - #define kbd_setkeycode pckbd_setkeycode 29 - #define kbd_getkeycode pckbd_getkeycode 30 - #define kbd_translate pckbd_translate 31 - #define kbd_unexpected_up pckbd_unexpected_up 32 - #define kbd_leds pckbd_leds 33 - #define kbd_init_hw pckbd_init_hw 34 - 35 - /* resource allocation */ 36 - #define kbd_request_region() 37 - #define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \ 38 - "keyboard", NULL) 39 - 40 - /* How to access the keyboard macros on this platform. */ 41 - #define kbd_read_input() inb(KBD_DATA_REG) 42 - #define kbd_read_status() inb(KBD_STATUS_REG) 43 - #define kbd_write_output(val) outb(val, KBD_DATA_REG) 44 - #define kbd_write_command(val) outb(val, KBD_CNTL_REG) 45 - 46 - /* Some stoneage hardware needs delays after some operations. */ 47 - #define kbd_pause() do { } while(0) 48 - 49 - /* 50 - * Machine specific bits for the PS/2 driver 51 - */ 52 - 53 - #define AUX_IRQ 12 54 - 55 - #define aux_request_irq(hand, dev_id) \ 56 - request_irq(AUX_IRQ, hand, IRQF_SHARED, "PS2 Mouse", dev_id) 57 - 58 - #define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id) 59 - 60 - #endif /* __KERNEL__ */

-200

include/asm-sh/mpc1211/m1543c.h

··· 1 - #ifndef __ASM_SH_M1543C_H 2 - #define __ASM_SH_M1543C_H 3 - 4 - /* 5 - * linux/include/asm-sh/m1543c.h 6 - * Copyright (C) 2001 Nobuhiro Sakawa 7 - * M1543C:PCI-ISA Bus Bridge with Super IO Chip support 8 - * 9 - * from 10 - * 11 - * linux/include/asm-sh/smc37c93x.h 12 - * 13 - * Copyright (C) 2000 Kazumoto Kojima 14 - * 15 - * SMSC 37C93x Super IO Chip support 16 - */ 17 - 18 - /* Default base I/O address */ 19 - #define FDC_PRIMARY_BASE 0x3f0 20 - #define IDE1_PRIMARY_BASE 0x1f0 21 - #define IDE1_SECONDARY_BASE 0x170 22 - #define PARPORT_PRIMARY_BASE 0x378 23 - #define COM1_PRIMARY_BASE 0x2f8 24 - #define COM2_PRIMARY_BASE 0x3f8 25 - #define COM3_PRIMARY_BASE 0x3e8 26 - #define RTC_PRIMARY_BASE 0x070 27 - #define KBC_PRIMARY_BASE 0x060 28 - #define AUXIO_PRIMARY_BASE 0x000 /* XXX */ 29 - #define I8259_M_CR 0x20 30 - #define I8259_M_MR 0x21 31 - #define I8259_S_CR 0xa0 32 - #define I8259_S_MR 0xa1 33 - 34 - /* Logical device number */ 35 - #define LDN_FDC 0 36 - #define LDN_IDE1 1 37 - #define LDN_IDE2 2 38 - #define LDN_PARPORT 3 39 - #define LDN_COM1 4 40 - #define LDN_COM2 5 41 - #define LDN_COM3 11 42 - #define LDN_RTC 6 43 - #define LDN_KBC 7 44 - 45 - /* Configuration port and key */ 46 - #define CONFIG_PORT 0x3f0 47 - #define INDEX_PORT CONFIG_PORT 48 - #define DATA_PORT 0x3f1 49 - #define CONFIG_ENTER1 0x51 50 - #define CONFIG_ENTER2 0x23 51 - #define CONFIG_EXIT 0xbb 52 - 53 - /* Configuration index */ 54 - #define CURRENT_LDN_INDEX 0x07 55 - #define POWER_CONTROL_INDEX 0x22 56 - #define ACTIVATE_INDEX 0x30 57 - #define IO_BASE_HI_INDEX 0x60 58 - #define IO_BASE_LO_INDEX 0x61 59 - #define IRQ_SELECT_INDEX 0x70 60 - #define PS2_IRQ_INDEX 0x72 61 - #define DMA_SELECT_INDEX 0x74 62 - 63 - /* UART stuff. Only for debugging. */ 64 - /* UART Register */ 65 - 66 - #define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */ 67 - #define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */ 68 - #define UART_IER 0x2 /* Interrupt Enable Register */ 69 - #define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */ 70 - #define UART_FCR 0x4 /* FIFO Control Register (Write Only) */ 71 - #define UART_LCR 0x6 /* Line Control Register */ 72 - #define UART_MCR 0x8 /* MODEM Control Register */ 73 - #define UART_LSR 0xa /* Line Status Register */ 74 - #define UART_MSR 0xc /* MODEM Status Register */ 75 - #define UART_SCR 0xe /* Scratch Register */ 76 - #define UART_DLL 0x0 /* Divisor Latch (LS) */ 77 - #define UART_DLM 0x2 /* Divisor Latch (MS) */ 78 - 79 - #ifndef __ASSEMBLY__ 80 - typedef struct uart_reg { 81 - volatile __u16 rbr; 82 - volatile __u16 ier; 83 - volatile __u16 iir; 84 - volatile __u16 lcr; 85 - volatile __u16 mcr; 86 - volatile __u16 lsr; 87 - volatile __u16 msr; 88 - volatile __u16 scr; 89 - } uart_reg; 90 - #endif /* ! __ASSEMBLY__ */ 91 - 92 - /* Alias for Write Only Register */ 93 - 94 - #define thr rbr 95 - #define tcr iir 96 - 97 - /* Alias for Divisor Latch Register */ 98 - 99 - #define dll rbr 100 - #define dlm ier 101 - #define fcr iir 102 - 103 - /* Interrupt Enable Register */ 104 - 105 - #define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */ 106 - #define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */ 107 - #define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */ 108 - #define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */ 109 - 110 - /* Interrupt Ident Register */ 111 - 112 - #define IIR_IP 0x0100 /* "0" if Interrupt Pending */ 113 - #define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */ 114 - #define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */ 115 - #define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */ 116 - #define IIR_FIFO 0xc000 /* FIFOs enabled */ 117 - 118 - /* FIFO Control Register */ 119 - 120 - #define FCR_FEN 0x0100 /* FIFO enable */ 121 - #define FCR_RFRES 0x0200 /* Receiver FIFO reset */ 122 - #define FCR_TFRES 0x0400 /* Transmitter FIFO reset */ 123 - #define FCR_DMA 0x0800 /* DMA mode select */ 124 - #define FCR_RTL 0x4000 /* Receiver triger (LSB) */ 125 - #define FCR_RTM 0x8000 /* Receiver triger (MSB) */ 126 - 127 - /* Line Control Register */ 128 - 129 - #define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */ 130 - #define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */ 131 - #define LCR_STB 0x0400 /* Number of Stop Bits */ 132 - #define LCR_PEN 0x0800 /* Parity Enable */ 133 - #define LCR_EPS 0x1000 /* Even Parity Select */ 134 - #define LCR_SP 0x2000 /* Stick Parity */ 135 - #define LCR_SB 0x4000 /* Set Break */ 136 - #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */ 137 - 138 - /* MODEM Control Register */ 139 - 140 - #define MCR_DTR 0x0100 /* Data Terminal Ready */ 141 - #define MCR_RTS 0x0200 /* Request to Send */ 142 - #define MCR_OUT1 0x0400 /* Out 1 */ 143 - #define MCR_IRQEN 0x0800 /* IRQ Enable */ 144 - #define MCR_LOOP 0x1000 /* Loop */ 145 - 146 - /* Line Status Register */ 147 - 148 - #define LSR_DR 0x0100 /* Data Ready */ 149 - #define LSR_OE 0x0200 /* Overrun Error */ 150 - #define LSR_PE 0x0400 /* Parity Error */ 151 - #define LSR_FE 0x0800 /* Framing Error */ 152 - #define LSR_BI 0x1000 /* Break Interrupt */ 153 - #define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */ 154 - #define LSR_TEMT 0x4000 /* Transmitter Empty */ 155 - #define LSR_FIFOE 0x8000 /* Receiver FIFO error */ 156 - 157 - /* MODEM Status Register */ 158 - 159 - #define MSR_DCTS 0x0100 /* Delta Clear to Send */ 160 - #define MSR_DDSR 0x0200 /* Delta Data Set Ready */ 161 - #define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */ 162 - #define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */ 163 - #define MSR_CTS 0x1000 /* Clear to Send */ 164 - #define MSR_DSR 0x2000 /* Data Set Ready */ 165 - #define MSR_RI 0x4000 /* Ring Indicator */ 166 - #define MSR_DCD 0x8000 /* Data Carrier Detect */ 167 - 168 - /* Baud Rate Divisor */ 169 - 170 - #define UART_CLK (1843200) /* 1.8432 MHz */ 171 - #define UART_BAUD(x) (UART_CLK / (16 * (x))) 172 - 173 - /* RTC register definition */ 174 - #define RTC_SECONDS 0 175 - #define RTC_SECONDS_ALARM 1 176 - #define RTC_MINUTES 2 177 - #define RTC_MINUTES_ALARM 3 178 - #define RTC_HOURS 4 179 - #define RTC_HOURS_ALARM 5 180 - #define RTC_DAY_OF_WEEK 6 181 - #define RTC_DAY_OF_MONTH 7 182 - #define RTC_MONTH 8 183 - #define RTC_YEAR 9 184 - #define RTC_FREQ_SELECT 10 185 - # define RTC_UIP 0x80 186 - # define RTC_DIV_CTL 0x70 187 - /* This RTC can work under 32.768KHz clock only. */ 188 - # define RTC_OSC_ENABLE 0x20 189 - # define RTC_OSC_DISABLE 0x00 190 - #define RTC_CONTROL 11 191 - # define RTC_SET 0x80 192 - # define RTC_PIE 0x40 193 - # define RTC_AIE 0x20 194 - # define RTC_UIE 0x10 195 - # define RTC_SQWE 0x08 196 - # define RTC_DM_BINARY 0x04 197 - # define RTC_24H 0x02 198 - # define RTC_DST_EN 0x01 199 - 200 - #endif /* __ASM_SH_M1543C_H */

-6

include/asm-sh/mpc1211/mc146818rtc.h

··· 1 - /* 2 - * MPC1211 uses PC/AT style RTC definitions. 3 - */ 4 - #include <asm-x86/mc146818rtc_32.h> 5 - 6 -

-18

include/asm-sh/mpc1211/mpc1211.h

··· 1 - #ifndef __ASM_SH_MPC1211_H 2 - #define __ASM_SH_MPC1211_H 3 - 4 - /* 5 - * linux/include/asm-sh/mpc1211.h 6 - * 7 - * Copyright (C) 2001 Saito.K & Jeanne 8 - * 9 - * Interface MPC-1211 support 10 - */ 11 - 12 - #define PA_PCI_IO (0xa4000000) /* PCI I/O space */ 13 - #define PA_PCI_MEM (0xb0000000) /* PCI MEM space */ 14 - 15 - #define PCIPAR (0xa4000cf8) /* PCI Config address */ 16 - #define PCIPDR (0xa4000cfc) /* PCI Config data */ 17 - 18 - #endif /* __ASM_SH_MPC1211_H */

-38

include/asm-sh/mpc1211/pci.h

··· 1 - /* 2 - * Low-Level PCI Support for MPC-1211 3 - * 4 - * (c) 2002 Saito.K & Jeanne 5 - * 6 - */ 7 - 8 - #ifndef _PCI_MPC1211_H_ 9 - #define _PCI_MPC1211_H_ 10 - 11 - #include <linux/pci.h> 12 - 13 - /* set debug level 4=verbose...1=terse */ 14 - //#define DEBUG_PCI 3 15 - #undef DEBUG_PCI 16 - 17 - #ifdef DEBUG_PCI 18 - #define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); } 19 - #else 20 - #define PCIDBG(n, x...) 21 - #endif 22 - 23 - /* startup values */ 24 - #define PCI_PROBE_BIOS 1 25 - #define PCI_PROBE_CONF1 2 26 - #define PCI_PROBE_CONF2 4 27 - #define PCI_NO_CHECKS 0x400 28 - #define PCI_ASSIGN_ROMS 0x1000 29 - #define PCI_BIOS_IRQ_SCAN 0x2000 30 - 31 - /* MPC-1211 Specific Values */ 32 - #define PCIPAR (0xa4000cf8) /* PCI Config address */ 33 - #define PCIPDR (0xa4000cfc) /* PCI Config data */ 34 - 35 - #define PA_PCI_IO (0xa4000000) /* PCI I/O space */ 36 - #define PA_PCI_MEM (0xb0000000) /* PCI MEM space */ 37 - 38 - #endif /* _PCI_MPC1211_H_ */

+1 -3

include/asm-sh/r7780rp.h

··· 193 193 #define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15) 194 194 #define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16) 195 195 196 - unsigned char *highlander_init_irq_r7780mp(void); 197 - unsigned char *highlander_init_irq_r7780rp(void); 198 - unsigned char *highlander_init_irq_r7785rp(void); 196 + unsigned char *highlander_plat_irq_setup(void); 199 197 200 198 #endif /* __ASM_SH_RENESAS_R7780RP */

+9 -1

include/asm-sh/tlb_64.h

··· 56 56 __asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot)); 57 57 } 58 58 59 + #ifdef CONFIG_MMU 59 60 /* arch/sh64/mm/tlb.c */ 60 61 int sh64_tlb_init(void); 61 62 unsigned long long sh64_next_free_dtlb_entry(void); ··· 65 64 void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr, 66 65 unsigned long asid, unsigned long paddr); 67 66 void sh64_teardown_tlb_slot(unsigned long long config_addr); 68 - 67 + #else 68 + #define sh64_tlb_init() do { } while (0) 69 + #define sh64_next_free_dtlb_entry() (0) 70 + #define sh64_get_wired_dtlb_entry() (0) 71 + #define sh64_put_wired_dtlb_entry(entry) do { } while (0) 72 + #define sh64_setup_tlb_slot(conf, virt, asid, phys) do { } while (0) 73 + #define sh64_teardown_tlb_slot(addr) do { } while (0) 74 + #endif /* CONFIG_MMU */ 69 75 #endif /* __ASSEMBLY__ */ 70 76 #endif /* __ASM_SH_TLB_64_H */

+11

include/asm-sh/topology.h

··· 29 29 .nr_balance_failed = 0, \ 30 30 } 31 31 32 + #define cpu_to_node(cpu) ((void)(cpu),0) 33 + #define parent_node(node) ((void)(node),0) 34 + 35 + #define node_to_cpumask(node) ((void)node, cpu_online_map) 36 + #define node_to_first_cpu(node) ((void)(node),0) 37 + 38 + #define pcibus_to_node(bus) ((void)(bus), -1) 39 + #define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \ 40 + CPU_MASK_ALL : \ 41 + node_to_cpumask(pcibus_to_node(bus)) \ 42 + ) 32 43 #endif 33 44 34 45 #include <asm-generic/topology.h>

+2

include/asm-sh/uaccess_64.h

··· 274 274 unsigned long insn, fixup; 275 275 }; 276 276 277 + #ifdef CONFIG_MMU 277 278 #define ARCH_HAS_SEARCH_EXTABLE 279 + #endif 278 280 279 281 /* Returns 0 if exception not found and fixup.unit otherwise. */ 280 282 extern unsigned long search_exception_table(unsigned long addr);

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