tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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crypto: qat - add adf_rl_get_num_svc_aes() in rate limiting

Enhance the rate limiting (RL) infrastructure by adding
adf_rl_get_num_svc_aes() which can be used to fetch the number of engines
associated with the service type. Expand the structure adf_rl_hw_data
with an array that contains the number of AEs per service.

Implement adf_gen4_init_num_svc_aes() for QAT GEN4 devices to calculate
the total number of acceleration engines dedicated to a specific service.

Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Suman Kumar Chakraborty and committed by
Herbert Xu a9552153 fdf31c75

+40 -1
+2
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
··· 301 301 rl_data->max_tp[SVC_DC] = ADF_420XX_RL_MAX_TP_DC; 302 302 rl_data->scan_interval = ADF_420XX_RL_SCANS_PER_SEC; 303 303 rl_data->scale_ref = ADF_420XX_RL_SLICE_REF; 304 + 305 + adf_gen4_init_num_svc_aes(rl_data); 304 306 } 305 307 306 308 static int get_rp_group(struct adf_accel_dev *accel_dev, u32 ae_mask)
+2
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
··· 227 227 rl_data->max_tp[SVC_DC] = ADF_4XXX_RL_MAX_TP_DC; 228 228 rl_data->scan_interval = ADF_4XXX_RL_SCANS_PER_SEC; 229 229 rl_data->scale_ref = ADF_4XXX_RL_SLICE_REF; 230 + 231 + adf_gen4_init_num_svc_aes(rl_data); 230 232 } 231 233 232 234 static u32 uof_get_num_objs(struct adf_accel_dev *accel_dev)
+22
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
··· 558 558 dc_ops->build_decomp_block = adf_gen4_build_decomp_block; 559 559 } 560 560 EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops); 561 + 562 + void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data) 563 + { 564 + struct adf_hw_device_data *hw_data; 565 + unsigned int i; 566 + u32 ae_cnt; 567 + 568 + hw_data = container_of(device_data, struct adf_hw_device_data, rl_data); 569 + ae_cnt = hweight32(hw_data->get_ae_mask(hw_data)); 570 + if (!ae_cnt) 571 + return; 572 + 573 + for (i = 0; i < SVC_BASE_COUNT; i++) 574 + device_data->svc_ae_mask[i] = ae_cnt - 1; 575 + 576 + /* 577 + * The decompression service is not supported on QAT GEN4 devices. 578 + * Therefore, set svc_ae_mask to 0. 579 + */ 580 + device_data->svc_ae_mask[SVC_DECOMP] = 0; 581 + } 582 + EXPORT_SYMBOL_GPL(adf_gen4_init_num_svc_aes);
+1
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
··· 175 175 u32 bank_number); 176 176 bool adf_gen4_services_supported(unsigned long service_mask); 177 177 void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops); 178 + void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data); 178 179 179 180 #endif
+12 -1
drivers/crypto/intel/qat/qat_common/adf_rl.c
··· 552 552 return allocated_tokens; 553 553 } 554 554 555 + static u32 adf_rl_get_num_svc_aes(struct adf_accel_dev *accel_dev, 556 + enum adf_base_services svc) 557 + { 558 + struct adf_rl_hw_data *device_data = &accel_dev->hw_device->rl_data; 559 + 560 + if (svc >= SVC_BASE_COUNT) 561 + return 0; 562 + 563 + return device_data->svc_ae_mask[svc]; 564 + } 565 + 555 566 u32 adf_rl_calculate_ae_cycles(struct adf_accel_dev *accel_dev, u32 sla_val, 556 567 enum adf_base_services svc_type) 557 568 { ··· 574 563 return 0; 575 564 576 565 avail_ae_cycles = hw_data->clock_frequency; 577 - avail_ae_cycles *= hw_data->get_num_aes(hw_data) - 1; 566 + avail_ae_cycles *= adf_rl_get_num_svc_aes(accel_dev, svc_type); 578 567 do_div(avail_ae_cycles, device_data->scan_interval); 579 568 580 569 sla_val *= device_data->max_tp[svc_type];
+1
drivers/crypto/intel/qat/qat_common/adf_rl.h
··· 89 89 u32 pcie_scale_div; 90 90 u32 dcpr_correction; 91 91 u32 max_tp[RL_ROOT_MAX]; 92 + u32 svc_ae_mask[SVC_BASE_COUNT]; 92 93 struct rl_slice_cnt slices; 93 94 }; 94 95