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iio: adc: ad4030: Add SPI offload support

AD4030 and similar ADCs can capture data at sample rates up to 2 mega
samples per second (MSPS). Not all SPI controllers are able to achieve such
high throughputs and even when the controller is fast enough to run
transfers at the required speed, it may be costly to the CPU to handle
transfer data at such high sample rates. Add SPI offload support for AD4030
and similar ADCs to enable data capture at maximum sample rates.

Note that a pair of PWM devices are used for the supported setup. One of
the PWM goes to the ADC CNV pin to initiate conversions while the other PWM
is connected to the SPI offload trigger to signal when to fetch data from
the peripheral. Note also that the PWMs must be somewhat synchronized such
to make the controller run transfers only when ADC sample data is
available. See Documentation/iio/ad4030.rst for details.

Reviewed-by: David Lechner <dlechner@baylibre.com>
Co-developed-by: Trevor Gamblin <tgamblin@baylibre.com>
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
Co-developed-by: Axel Haslam <ahaslam@baylibre.com>
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Marcelo Schmitt and committed by
Jonathan Cameron a98edf7d 5e0d71dc

+396 -18
+5
drivers/iio/adc/Kconfig
··· 60 60 tristate "Analog Devices AD4030 ADC Driver" 61 61 depends on SPI 62 62 depends on GPIOLIB 63 + depends on PWM 63 64 select REGMAP 64 65 select IIO_BUFFER 66 + select IIO_BUFFER_DMA 67 + select IIO_BUFFER_DMAENGINE 65 68 select IIO_TRIGGERED_BUFFER 69 + select SPI_OFFLOAD 70 + select SPI_OFFLOAD_TRIGGER_PWM 66 71 help 67 72 Say yes here to build support for Analog Devices AD4030 and AD4630 high speed 68 73 SPI analog to digital converters (ADC).
+391 -18
drivers/iio/adc/ad4030.c
··· 14 14 */ 15 15 16 16 #include <linux/bitfield.h> 17 + #include <linux/cleanup.h> 17 18 #include <linux/clk.h> 18 - #include <linux/iio/iio.h> 19 - #include <linux/iio/trigger_consumer.h> 20 - #include <linux/iio/triggered_buffer.h> 19 + #include <linux/dmaengine.h> 20 + #include <linux/limits.h> 21 + #include <linux/log2.h> 22 + #include <linux/math64.h> 23 + #include <linux/minmax.h> 24 + #include <linux/pwm.h> 21 25 #include <linux/regmap.h> 22 26 #include <linux/regulator/consumer.h> 27 + #include <linux/spi/offload/consumer.h> 23 28 #include <linux/spi/spi.h> 24 29 #include <linux/unaligned.h> 25 30 #include <linux/units.h> 31 + #include <linux/types.h> 32 + 33 + #include <linux/iio/buffer-dmaengine.h> 34 + #include <linux/iio/iio.h> 35 + #include <linux/iio/trigger_consumer.h> 36 + #include <linux/iio/triggered_buffer.h> 26 37 27 38 #define AD4030_REG_INTERFACE_CONFIG_A 0x00 28 39 #define AD4030_REG_INTERFACE_CONFIG_A_SW_RESET (BIT(0) | BIT(7)) ··· 122 111 #define AD4632_TCYC_NS 2000 123 112 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS) 124 113 #define AD4030_TRESET_COM_DELAY_MS 750 114 + /* Datasheet says 9.8ns, so use the closest integer value */ 115 + #define AD4030_TQUIET_CNV_DELAY_NS 10 125 116 126 117 enum ad4030_out_mode { 127 118 AD4030_OUT_DATA_MD_DIFF, ··· 149 136 const char *name; 150 137 const unsigned long *available_masks; 151 138 const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB]; 139 + const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; 152 140 u8 grade; 153 141 u8 precision_bits; 154 142 /* Number of hardware channels */ 155 143 int num_voltage_inputs; 156 144 unsigned int tcyc_ns; 145 + unsigned int max_sample_rate_hz; 157 146 }; 158 147 159 148 struct ad4030_state { ··· 168 153 int offset_avail[3]; 169 154 unsigned int avg_log2; 170 155 enum ad4030_out_mode mode; 156 + /* Offload sampling */ 157 + struct spi_transfer offload_xfer; 158 + struct spi_message offload_msg; 159 + struct spi_offload *offload; 160 + struct spi_offload_trigger *offload_trigger; 161 + struct spi_offload_trigger_config offload_trigger_config; 162 + struct pwm_device *cnv_trigger; 163 + struct pwm_waveform cnv_wf; 171 164 172 165 /* 173 166 * DMA (thus cache coherency maintenance) requires the transfer buffers ··· 232 209 * - voltage0-voltage1 233 210 * - voltage2-voltage3 234 211 */ 235 - #define AD4030_CHAN_DIFF(_idx, _scan_type) { \ 212 + #define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload) { \ 236 213 .info_mask_shared_by_all = \ 214 + (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ 237 215 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 238 216 .info_mask_shared_by_all_available = \ 239 217 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ ··· 256 232 .num_ext_scan_type = ARRAY_SIZE(_scan_type), \ 257 233 } 258 234 235 + #define AD4030_CHAN_DIFF(_idx, _scan_type) \ 236 + __AD4030_CHAN_DIFF(_idx, _scan_type, 0) 237 + 238 + #define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ 239 + __AD4030_CHAN_DIFF(_idx, _scan_type, 1) 240 + 259 241 /* 260 242 * AD4030 can average over 2^N samples, where N = 1, 2, 3, ..., 16. 261 243 * We use N = 0 to mean no sample averaging. ··· 272 242 BIT(5), BIT(6), BIT(7), BIT(8), 273 243 BIT(9), BIT(10), BIT(11), BIT(12), 274 244 BIT(13), BIT(14), BIT(15), BIT(16), 245 + }; 246 + 247 + static const struct spi_offload_config ad4030_offload_config = { 248 + .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 249 + SPI_OFFLOAD_CAP_RX_STREAM_DMA, 275 250 }; 276 251 277 252 static int ad4030_enter_config_mode(struct ad4030_state *st) ··· 492 457 } 493 458 } 494 459 460 + static void ad4030_get_sampling_freq(struct ad4030_state *st, int *freq) 461 + { 462 + struct spi_offload_trigger_config *config = &st->offload_trigger_config; 463 + 464 + /* 465 + * Conversion data is fetched from the device when the offload transfer 466 + * is triggered. Thus, provide the SPI offload trigger frequency as the 467 + * sampling frequency. 468 + */ 469 + *freq = config->periodic.frequency_hz; 470 + } 471 + 472 + static int ad4030_update_conversion_rate(struct ad4030_state *st, 473 + unsigned int freq_hz, unsigned int avg_log2) 474 + { 475 + struct spi_offload_trigger_config *config = &st->offload_trigger_config; 476 + unsigned int offload_period_ns, cnv_rate_hz; 477 + struct pwm_waveform cnv_wf = { }; 478 + u64 target = AD4030_TCNVH_NS; 479 + u64 offload_offset_ns; 480 + int ret; 481 + 482 + /* 483 + * When averaging/oversampling over N samples, we fire the offload 484 + * trigger once at every N pulses of the CNV signal. Conversely, the CNV 485 + * signal needs to be N times faster than the offload trigger. Take that 486 + * into account to correctly re-evaluate both the PWM waveform connected 487 + * to CNV and the SPI offload trigger. 488 + */ 489 + cnv_rate_hz = freq_hz << avg_log2; 490 + 491 + cnv_wf.period_length_ns = DIV_ROUND_CLOSEST(NSEC_PER_SEC, cnv_rate_hz); 492 + /* 493 + * The datasheet lists a minimum time of 9.8 ns, but no maximum. If the 494 + * rounded PWM's value is less than 10, increase the target value by 10 495 + * and attempt to round the waveform again, until the value is at least 496 + * 10 ns. Use a separate variable to represent the target in case the 497 + * rounding is severe enough to keep putting the first few results under 498 + * the minimum 10ns condition checked by the while loop. 499 + */ 500 + do { 501 + cnv_wf.duty_length_ns = target; 502 + ret = pwm_round_waveform_might_sleep(st->cnv_trigger, &cnv_wf); 503 + if (ret) 504 + return ret; 505 + target += AD4030_TCNVH_NS; 506 + } while (cnv_wf.duty_length_ns < AD4030_TCNVH_NS); 507 + 508 + /* 509 + * The CNV waveform period (period_length_ns) might get rounded down by 510 + * pwm_round_waveform_might_sleep(). Check the resultant PWM period 511 + * is not smaller than the minimum data conversion cycle time. 512 + */ 513 + if (!in_range(cnv_wf.period_length_ns, AD4030_TCYC_NS, INT_MAX)) 514 + return -EINVAL; 515 + 516 + offload_period_ns = DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq_hz); 517 + 518 + config->periodic.frequency_hz = DIV_ROUND_UP(HZ_PER_GHZ, offload_period_ns); 519 + 520 + /* 521 + * The hardware does the capture on zone 2 (when SPI trigger PWM 522 + * is used). This means that the SPI trigger signal should happen at 523 + * tsync + tquiet_con_delay being tsync the conversion signal period 524 + * and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly. 525 + * 526 + * The PWM waveform API only supports nanosecond resolution right now, 527 + * so round this setting to the closest available value. 528 + */ 529 + offload_offset_ns = AD4030_TQUIET_CNV_DELAY_NS; 530 + do { 531 + config->periodic.offset_ns = offload_offset_ns; 532 + ret = spi_offload_trigger_validate(st->offload_trigger, config); 533 + if (ret) 534 + return ret; 535 + offload_offset_ns += AD4030_TQUIET_CNV_DELAY_NS; 536 + } while (config->periodic.offset_ns < AD4030_TQUIET_CNV_DELAY_NS); 537 + 538 + st->cnv_wf = cnv_wf; 539 + 540 + return 0; 541 + } 542 + 543 + static int ad4030_set_sampling_freq(struct iio_dev *indio_dev, int freq_hz) 544 + { 545 + struct ad4030_state *st = iio_priv(indio_dev); 546 + 547 + if (freq_hz == 0) 548 + return -EINVAL; 549 + 550 + if (!in_range(freq_hz, 0, st->chip->max_sample_rate_hz)) 551 + return -ERANGE; 552 + 553 + return ad4030_update_conversion_rate(st, freq_hz, st->avg_log2); 554 + } 555 + 495 556 static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev, 496 557 struct iio_chan_spec const *chan, 497 558 int gain_int, ··· 647 516 struct ad4030_state *st = iio_priv(dev); 648 517 unsigned int avg_log2 = ilog2(avg_val); 649 518 unsigned int last_avg_idx = ARRAY_SIZE(ad4030_average_modes) - 1; 519 + int freq_hz; 650 520 int ret; 651 521 652 522 if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx]) 653 523 return -EINVAL; 524 + 525 + if (st->offload_trigger) { 526 + /* 527 + * The sample averaging and sampling frequency configurations 528 + * are mutually dependent on each other. That's because the 529 + * effective data sample rate is fCNV / 2^N, where N is the 530 + * number of samples being averaged. 531 + * 532 + * When SPI offload is supported and we have control over the 533 + * sample rate, the conversion start signal (CNV) and the SPI 534 + * offload trigger frequencies must be re-evaluated so data is 535 + * fetched only after 'avg_val' conversions. 536 + */ 537 + ad4030_get_sampling_freq(st, &freq_hz); 538 + ret = ad4030_update_conversion_rate(st, freq_hz, avg_log2); 539 + if (ret) 540 + return ret; 541 + } 654 542 655 543 ret = regmap_write(st->regmap, AD4030_REG_AVG, 656 544 AD4030_REG_AVG_MASK_AVG_SYNC | ··· 923 773 *val = BIT(st->avg_log2); 924 774 return IIO_VAL_INT; 925 775 776 + case IIO_CHAN_INFO_SAMP_FREQ: 777 + ad4030_get_sampling_freq(st, val); 778 + return IIO_VAL_INT; 779 + 926 780 default: 927 781 return -EINVAL; 928 782 } ··· 966 812 967 813 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 968 814 return ad4030_set_avg_frame_len(indio_dev, val); 815 + 816 + case IIO_CHAN_INFO_SAMP_FREQ: 817 + return ad4030_set_sampling_freq(indio_dev, val); 969 818 970 819 default: 971 820 return -EINVAL; ··· 1059 902 .validate_scan_mask = ad4030_validate_scan_mask, 1060 903 }; 1061 904 905 + static void ad4030_prepare_offload_msg(struct iio_dev *indio_dev) 906 + { 907 + struct ad4030_state *st = iio_priv(indio_dev); 908 + u8 offload_bpw; 909 + 910 + if (st->mode == AD4030_OUT_DATA_MD_30_AVERAGED_DIFF) 911 + offload_bpw = 32; 912 + else 913 + offload_bpw = st->chip->precision_bits; 914 + 915 + st->offload_xfer.bits_per_word = offload_bpw; 916 + st->offload_xfer.len = spi_bpw_to_bytes(offload_bpw); 917 + st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 918 + spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); 919 + } 920 + 921 + static int ad4030_offload_buffer_postenable(struct iio_dev *indio_dev) 922 + { 923 + struct ad4030_state *st = iio_priv(indio_dev); 924 + unsigned int reg_modes; 925 + int ret; 926 + 927 + /* 928 + * When data from 2 analog input channels is output through a single 929 + * bus line (interleaved mode (LANE_MD == 0b11)) and gets pushed through 930 + * DMA, extra hardware is required to do the de-interleaving. While we 931 + * don't support such hardware configurations, disallow interleaved mode 932 + * when using SPI offload. 933 + */ 934 + ret = regmap_read(st->regmap, AD4030_REG_MODES, &reg_modes); 935 + if (ret) 936 + return ret; 937 + 938 + if (st->chip->num_voltage_inputs > 1 && 939 + FIELD_GET(AD4030_REG_MODES_MASK_LANE_MODE, reg_modes) == AD4030_LANE_MD_INTERLEAVED) 940 + return -EINVAL; 941 + 942 + ad4030_prepare_offload_msg(indio_dev); 943 + st->offload_msg.offload = st->offload; 944 + ret = spi_optimize_message(st->spi, &st->offload_msg); 945 + if (ret) 946 + return ret; 947 + 948 + ret = pwm_set_waveform_might_sleep(st->cnv_trigger, &st->cnv_wf, false); 949 + if (ret) 950 + goto out_unoptimize; 951 + 952 + ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, 953 + &st->offload_trigger_config); 954 + if (ret) 955 + goto out_pwm_disable; 956 + 957 + return 0; 958 + 959 + out_pwm_disable: 960 + pwm_disable(st->cnv_trigger); 961 + out_unoptimize: 962 + spi_unoptimize_message(&st->offload_msg); 963 + 964 + return ret; 965 + } 966 + 967 + static int ad4030_offload_buffer_predisable(struct iio_dev *indio_dev) 968 + { 969 + struct ad4030_state *st = iio_priv(indio_dev); 970 + 971 + spi_offload_trigger_disable(st->offload, st->offload_trigger); 972 + 973 + pwm_disable(st->cnv_trigger); 974 + 975 + spi_unoptimize_message(&st->offload_msg); 976 + 977 + return 0; 978 + } 979 + 980 + static const struct iio_buffer_setup_ops ad4030_offload_buffer_setup_ops = { 981 + .postenable = &ad4030_offload_buffer_postenable, 982 + .predisable = &ad4030_offload_buffer_predisable, 983 + }; 984 + 1062 985 static int ad4030_regulators_get(struct ad4030_state *st) 1063 986 { 1064 987 struct device *dev = &st->spi->dev; ··· 1208 971 return 0; 1209 972 } 1210 973 974 + static int ad4030_pwm_get(struct ad4030_state *st) 975 + { 976 + struct device *dev = &st->spi->dev; 977 + 978 + st->cnv_trigger = devm_pwm_get(dev, NULL); 979 + if (IS_ERR(st->cnv_trigger)) 980 + return dev_err_probe(dev, PTR_ERR(st->cnv_trigger), 981 + "Failed to get CNV PWM\n"); 982 + 983 + /* 984 + * Preemptively disable the PWM, since we only want to enable it with 985 + * the buffer. 986 + */ 987 + pwm_disable(st->cnv_trigger); 988 + 989 + return 0; 990 + } 991 + 1211 992 static int ad4030_config(struct ad4030_state *st) 1212 993 { 1213 994 int ret; ··· 1251 996 AD4030_REG_IO_MASK_IO2X); 1252 997 1253 998 return 0; 999 + } 1000 + 1001 + static int ad4030_spi_offload_setup(struct iio_dev *indio_dev, 1002 + struct ad4030_state *st) 1003 + { 1004 + struct device *dev = &st->spi->dev; 1005 + struct dma_chan *rx_dma; 1006 + 1007 + indio_dev->setup_ops = &ad4030_offload_buffer_setup_ops; 1008 + 1009 + st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 1010 + SPI_OFFLOAD_TRIGGER_PERIODIC); 1011 + if (IS_ERR(st->offload_trigger)) 1012 + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1013 + "failed to get offload trigger\n"); 1014 + 1015 + st->offload_trigger_config.type = SPI_OFFLOAD_TRIGGER_PERIODIC; 1016 + 1017 + rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 1018 + if (IS_ERR(rx_dma)) 1019 + return dev_err_probe(dev, PTR_ERR(rx_dma), 1020 + "failed to get offload RX DMA\n"); 1021 + 1022 + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, 1023 + IIO_BUFFER_DIRECTION_IN); 1254 1024 } 1255 1025 1256 1026 static int ad4030_probe(struct spi_device *spi) ··· 1329 1049 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), 1330 1050 "Failed to get cnv gpio\n"); 1331 1051 1332 - /* 1333 - * One hardware channel is split in two software channels when using 1334 - * common byte mode. Add one more channel for the timestamp. 1335 - */ 1336 - indio_dev->num_channels = 2 * st->chip->num_voltage_inputs + 1; 1337 1052 indio_dev->name = st->chip->name; 1338 1053 indio_dev->modes = INDIO_DIRECT_MODE; 1339 1054 indio_dev->info = &ad4030_iio_info; 1340 - indio_dev->channels = st->chip->channels; 1341 1055 indio_dev->available_scan_masks = st->chip->available_masks; 1342 1056 1343 - ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1344 - iio_pollfunc_store_time, 1345 - ad4030_trigger_handler, 1346 - &ad4030_buffer_setup_ops); 1347 - if (ret) 1348 - return dev_err_probe(dev, ret, 1349 - "Failed to setup triggered buffer\n"); 1057 + st->offload = devm_spi_offload_get(dev, spi, &ad4030_offload_config); 1058 + ret = PTR_ERR_OR_ZERO(st->offload); 1059 + /* Fall back to low speed usage when no SPI offload is available. */ 1060 + if (ret == -ENODEV) { 1061 + /* 1062 + * One hardware channel is split in two software channels when 1063 + * using common byte mode. Add one more channel for the timestamp. 1064 + */ 1065 + indio_dev->num_channels = 2 * st->chip->num_voltage_inputs + 1; 1066 + indio_dev->channels = st->chip->channels; 1067 + 1068 + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1069 + iio_pollfunc_store_time, 1070 + ad4030_trigger_handler, 1071 + &ad4030_buffer_setup_ops); 1072 + if (ret) 1073 + return dev_err_probe(dev, ret, 1074 + "Failed to setup triggered buffer\n"); 1075 + } else if (ret) { 1076 + return dev_err_probe(dev, ret, "failed to get offload\n"); 1077 + } else { 1078 + /* 1079 + * Offloaded SPI transfers can't support software timestamp so 1080 + * no additional timestamp channel is added. 1081 + */ 1082 + indio_dev->num_channels = st->chip->num_voltage_inputs; 1083 + indio_dev->channels = st->chip->offload_channels; 1084 + ret = ad4030_spi_offload_setup(indio_dev, st); 1085 + if (ret) 1086 + return dev_err_probe(dev, ret, 1087 + "Failed to setup SPI offload\n"); 1088 + 1089 + ret = ad4030_pwm_get(st); 1090 + if (ret) 1091 + return dev_err_probe(dev, ret, "Failed to get PWM\n"); 1092 + 1093 + /* 1094 + * Start with a slower sampling rate so there is some room for 1095 + * adjusting the sample averaging and the sampling frequency 1096 + * without hitting the maximum conversion rate. 1097 + */ 1098 + ret = ad4030_update_conversion_rate(st, st->chip->max_sample_rate_hz >> 4, 1099 + st->avg_log2); 1100 + if (ret) 1101 + return dev_err_probe(dev, ret, 1102 + "Failed to set offload samp freq\n"); 1103 + } 1350 1104 1351 1105 return devm_iio_device_register(dev, indio_dev); 1352 1106 } ··· 1418 1104 }, 1419 1105 }; 1420 1106 1107 + static const struct iio_scan_type ad4030_24_offload_scan_types[] = { 1108 + [AD4030_SCAN_TYPE_NORMAL] = { 1109 + .sign = 's', 1110 + .realbits = 24, 1111 + .storagebits = 32, 1112 + .shift = 0, 1113 + .endianness = IIO_CPU, 1114 + }, 1115 + [AD4030_SCAN_TYPE_AVG] = { 1116 + .sign = 's', 1117 + .realbits = 30, 1118 + .storagebits = 32, 1119 + .shift = 2, 1120 + .endianness = IIO_CPU, 1121 + }, 1122 + }; 1123 + 1421 1124 static const struct iio_scan_type ad4030_16_scan_types[] = { 1422 1125 [AD4030_SCAN_TYPE_NORMAL] = { 1423 1126 .sign = 's', 1424 - .storagebits = 32, 1425 1127 .realbits = 16, 1128 + .storagebits = 32, 1426 1129 .shift = 16, 1427 1130 .endianness = IIO_BE, 1428 1131 }, ··· 1452 1121 } 1453 1122 }; 1454 1123 1124 + static const struct iio_scan_type ad4030_16_offload_scan_types[] = { 1125 + [AD4030_SCAN_TYPE_NORMAL] = { 1126 + .sign = 's', 1127 + .realbits = 16, 1128 + .storagebits = 32, 1129 + .shift = 0, 1130 + .endianness = IIO_CPU, 1131 + }, 1132 + [AD4030_SCAN_TYPE_AVG] = { 1133 + .sign = 's', 1134 + .realbits = 30, 1135 + .storagebits = 32, 1136 + .shift = 2, 1137 + .endianness = IIO_CPU, 1138 + }, 1139 + }; 1140 + 1455 1141 static const struct ad4030_chip_info ad4030_24_chip_info = { 1456 1142 .name = "ad4030-24", 1457 1143 .available_masks = ad4030_channel_masks, ··· 1477 1129 AD4030_CHAN_CMO(1, 0), 1478 1130 IIO_CHAN_SOFT_TIMESTAMP(2), 1479 1131 }, 1132 + .offload_channels = { 1133 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1134 + }, 1480 1135 .grade = AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, 1481 1136 .precision_bits = 24, 1482 1137 .num_voltage_inputs = 1, 1483 1138 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1139 + .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1484 1140 }; 1485 1141 1486 1142 static const struct ad4030_chip_info ad4630_16_chip_info = { ··· 1497 1145 AD4030_CHAN_CMO(3, 1), 1498 1146 IIO_CHAN_SOFT_TIMESTAMP(4), 1499 1147 }, 1148 + .offload_channels = { 1149 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), 1150 + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), 1151 + }, 1500 1152 .grade = AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, 1501 1153 .precision_bits = 16, 1502 1154 .num_voltage_inputs = 2, 1503 1155 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1156 + .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1504 1157 }; 1505 1158 1506 1159 static const struct ad4030_chip_info ad4630_24_chip_info = { ··· 1518 1161 AD4030_CHAN_CMO(3, 1), 1519 1162 IIO_CHAN_SOFT_TIMESTAMP(4), 1520 1163 }, 1164 + .offload_channels = { 1165 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1166 + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), 1167 + }, 1521 1168 .grade = AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, 1522 1169 .precision_bits = 24, 1523 1170 .num_voltage_inputs = 2, 1524 1171 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS, 1172 + .max_sample_rate_hz = 2 * HZ_PER_MHZ, 1525 1173 }; 1526 1174 1527 1175 static const struct ad4030_chip_info ad4632_16_chip_info = { ··· 1539 1177 AD4030_CHAN_CMO(3, 1), 1540 1178 IIO_CHAN_SOFT_TIMESTAMP(4), 1541 1179 }, 1180 + .offload_channels = { 1181 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_offload_scan_types), 1182 + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_offload_scan_types), 1183 + }, 1542 1184 .grade = AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, 1543 1185 .precision_bits = 16, 1544 1186 .num_voltage_inputs = 2, 1545 1187 .tcyc_ns = AD4632_TCYC_ADJUSTED_NS, 1188 + .max_sample_rate_hz = 500 * HZ_PER_KHZ, 1546 1189 }; 1547 1190 1548 1191 static const struct ad4030_chip_info ad4632_24_chip_info = { ··· 1560 1193 AD4030_CHAN_CMO(3, 1), 1561 1194 IIO_CHAN_SOFT_TIMESTAMP(4), 1562 1195 }, 1196 + .offload_channels = { 1197 + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_offload_scan_types), 1198 + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_offload_scan_types), 1199 + }, 1563 1200 .grade = AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, 1564 1201 .precision_bits = 24, 1565 1202 .num_voltage_inputs = 2, 1566 1203 .tcyc_ns = AD4632_TCYC_ADJUSTED_NS, 1204 + .max_sample_rate_hz = 500 * HZ_PER_KHZ, 1567 1205 }; 1568 1206 1569 1207 static const struct spi_device_id ad4030_id_table[] = { ··· 1604 1232 MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>"); 1605 1233 MODULE_DESCRIPTION("Analog Devices AD4630 ADC family driver"); 1606 1234 MODULE_LICENSE("GPL"); 1235 + MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");