tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'pci-v6.13-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull PCI fixes from Krzysztof Wilczyński:
"Two small patches that are important for fixing boot time hang on
Intel JHL7540 'Titan Ridge' platforms equipped with a Thunderbolt
controller.

The boot time issue manifests itself when a PCI Express bandwidth
control is unnecessarily enabled on the Thunderbolt controller
downstream ports, which only supports a link speed of 2.5 GT/s in
accordance with USB4 v2 specification (p. 671, sec. 11.2.1, "PCIe
Physical Layer Logical Sub-block").

As such, there is no need to enable bandwidth control on such
downstream port links, which also works around the issue.

Both patches were tested by the original reporter on the hardware on
which the failure origin golly manifested itself. Both fixes were
proven to resolve the reported boot hang issue, and both patches have
been in linux-next this week with no reported problems"

* tag 'pci-v6.13-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
PCI/bwctrl: Enable only if more than one speed is supported
PCI: Honor Max Link Speed when determining supported speeds

Linus Torvalds a99b4a36 78b13461

+7 -3
+4 -2
drivers/pci/pci.c
··· 6232 6232 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); 6233 6233 speeds = lnkcap2 & PCI_EXP_LNKCAP2_SLS; 6234 6234 6235 + /* Ignore speeds higher than Max Link Speed */ 6236 + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 6237 + speeds &= GENMASK(lnkcap & PCI_EXP_LNKCAP_SLS, 0); 6238 + 6235 6239 /* PCIe r3.0-compliant */ 6236 6240 if (speeds) 6237 6241 return speeds; 6238 - 6239 - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 6240 6242 6241 6243 /* Synthesize from the Max Link Speed field */ 6242 6244 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
+3 -1
drivers/pci/pcie/portdrv.c
··· 265 265 (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER))) 266 266 services |= PCIE_PORT_SERVICE_DPC; 267 267 268 + /* Enable bandwidth control if more than one speed is supported. */ 268 269 if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM || 269 270 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { 270 271 u32 linkcap; 271 272 272 273 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &linkcap); 273 - if (linkcap & PCI_EXP_LNKCAP_LBNC) 274 + if (linkcap & PCI_EXP_LNKCAP_LBNC && 275 + hweight8(dev->supported_speeds) > 1) 274 276 services |= PCIE_PORT_SERVICE_BWCTRL; 275 277 } 276 278