Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86_bugs_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 CPU mitigation updates from Borislav Petkov:
- Convert the tsx= cmdline parsing to use early_param()
- Cleanup forward declarations gunk in bugs.c
* tag 'x86_bugs_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/bugs: Get rid of the forward declarations
x86/tsx: Get the tsx= command line parameter with early_param()
x86/tsx: Make tsx_ctrl_state static
+126
-174
+93
-140
arch/x86/kernel/cpu/bugs.c
+93
-140
arch/x86/kernel/cpu/bugs.c
···
53
53
* mitigation option.
54
54
*/
55
55
56
-
static void __init spectre_v1_select_mitigation(void);
57
-
static void __init spectre_v1_apply_mitigation(void);
58
-
static void __init spectre_v2_select_mitigation(void);
59
-
static void __init spectre_v2_update_mitigation(void);
60
-
static void __init spectre_v2_apply_mitigation(void);
61
-
static void __init retbleed_select_mitigation(void);
62
-
static void __init retbleed_update_mitigation(void);
63
-
static void __init retbleed_apply_mitigation(void);
64
-
static void __init spectre_v2_user_select_mitigation(void);
65
-
static void __init spectre_v2_user_update_mitigation(void);
66
-
static void __init spectre_v2_user_apply_mitigation(void);
67
-
static void __init ssb_select_mitigation(void);
68
-
static void __init ssb_apply_mitigation(void);
69
-
static void __init l1tf_select_mitigation(void);
70
-
static void __init l1tf_apply_mitigation(void);
71
-
static void __init mds_select_mitigation(void);
72
-
static void __init mds_update_mitigation(void);
73
-
static void __init mds_apply_mitigation(void);
74
-
static void __init taa_select_mitigation(void);
75
-
static void __init taa_update_mitigation(void);
76
-
static void __init taa_apply_mitigation(void);
77
-
static void __init mmio_select_mitigation(void);
78
-
static void __init mmio_update_mitigation(void);
79
-
static void __init mmio_apply_mitigation(void);
80
-
static void __init rfds_select_mitigation(void);
81
-
static void __init rfds_update_mitigation(void);
82
-
static void __init rfds_apply_mitigation(void);
83
-
static void __init srbds_select_mitigation(void);
84
-
static void __init srbds_apply_mitigation(void);
85
-
static void __init l1d_flush_select_mitigation(void);
86
-
static void __init srso_select_mitigation(void);
87
-
static void __init srso_update_mitigation(void);
88
-
static void __init srso_apply_mitigation(void);
89
-
static void __init gds_select_mitigation(void);
90
-
static void __init gds_apply_mitigation(void);
91
-
static void __init bhi_select_mitigation(void);
92
-
static void __init bhi_update_mitigation(void);
93
-
static void __init bhi_apply_mitigation(void);
94
-
static void __init its_select_mitigation(void);
95
-
static void __init its_update_mitigation(void);
96
-
static void __init its_apply_mitigation(void);
97
-
static void __init tsa_select_mitigation(void);
98
-
static void __init tsa_apply_mitigation(void);
99
-
static void __init vmscape_select_mitigation(void);
100
-
static void __init vmscape_update_mitigation(void);
101
-
static void __init vmscape_apply_mitigation(void);
102
-
103
56
/* The base value of the SPEC_CTRL MSR without task-specific bits set */
104
57
u64 x86_spec_ctrl_base;
105
58
EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
···
184
231
case SMT_MITIGATIONS_ON:
185
232
pr_cont("on\n");
186
233
}
187
-
}
188
-
189
-
void __init cpu_select_mitigations(void)
190
-
{
191
-
/*
192
-
* Read the SPEC_CTRL MSR to account for reserved bits which may
193
-
* have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
194
-
* init code as it is not enumerated and depends on the family.
195
-
*/
196
-
if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
197
-
rdmsrq(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
198
-
199
-
/*
200
-
* Previously running kernel (kexec), may have some controls
201
-
* turned ON. Clear them and let the mitigations setup below
202
-
* rediscover them based on configuration.
203
-
*/
204
-
x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
205
-
}
206
-
207
-
x86_arch_cap_msr = x86_read_arch_cap_msr();
208
-
209
-
cpu_print_attack_vectors();
210
-
211
-
/* Select the proper CPU mitigations before patching alternatives: */
212
-
spectre_v1_select_mitigation();
213
-
spectre_v2_select_mitigation();
214
-
retbleed_select_mitigation();
215
-
spectre_v2_user_select_mitigation();
216
-
ssb_select_mitigation();
217
-
l1tf_select_mitigation();
218
-
mds_select_mitigation();
219
-
taa_select_mitigation();
220
-
mmio_select_mitigation();
221
-
rfds_select_mitigation();
222
-
srbds_select_mitigation();
223
-
l1d_flush_select_mitigation();
224
-
srso_select_mitigation();
225
-
gds_select_mitigation();
226
-
its_select_mitigation();
227
-
bhi_select_mitigation();
228
-
tsa_select_mitigation();
229
-
vmscape_select_mitigation();
230
-
231
-
/*
232
-
* After mitigations are selected, some may need to update their
233
-
* choices.
234
-
*/
235
-
spectre_v2_update_mitigation();
236
-
/*
237
-
* retbleed_update_mitigation() relies on the state set by
238
-
* spectre_v2_update_mitigation(); specifically it wants to know about
239
-
* spectre_v2=ibrs.
240
-
*/
241
-
retbleed_update_mitigation();
242
-
/*
243
-
* its_update_mitigation() depends on spectre_v2_update_mitigation()
244
-
* and retbleed_update_mitigation().
245
-
*/
246
-
its_update_mitigation();
247
-
248
-
/*
249
-
* spectre_v2_user_update_mitigation() depends on
250
-
* retbleed_update_mitigation(), specifically the STIBP
251
-
* selection is forced for UNRET or IBPB.
252
-
*/
253
-
spectre_v2_user_update_mitigation();
254
-
mds_update_mitigation();
255
-
taa_update_mitigation();
256
-
mmio_update_mitigation();
257
-
rfds_update_mitigation();
258
-
bhi_update_mitigation();
259
-
/* srso_update_mitigation() depends on retbleed_update_mitigation(). */
260
-
srso_update_mitigation();
261
-
vmscape_update_mitigation();
262
-
263
-
spectre_v1_apply_mitigation();
264
-
spectre_v2_apply_mitigation();
265
-
retbleed_apply_mitigation();
266
-
spectre_v2_user_apply_mitigation();
267
-
ssb_apply_mitigation();
268
-
l1tf_apply_mitigation();
269
-
mds_apply_mitigation();
270
-
taa_apply_mitigation();
271
-
mmio_apply_mitigation();
272
-
rfds_apply_mitigation();
273
-
srbds_apply_mitigation();
274
-
srso_apply_mitigation();
275
-
gds_apply_mitigation();
276
-
its_apply_mitigation();
277
-
bhi_apply_mitigation();
278
-
tsa_apply_mitigation();
279
-
vmscape_apply_mitigation();
280
234
}
281
235
282
236
/*
···
3229
3369
}
3230
3370
3231
3371
mutex_unlock(&spec_ctrl_mutex);
3372
+
}
3373
+
3374
+
void __init cpu_select_mitigations(void)
3375
+
{
3376
+
/*
3377
+
* Read the SPEC_CTRL MSR to account for reserved bits which may
3378
+
* have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
3379
+
* init code as it is not enumerated and depends on the family.
3380
+
*/
3381
+
if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
3382
+
rdmsrq(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
3383
+
3384
+
/*
3385
+
* Previously running kernel (kexec), may have some controls
3386
+
* turned ON. Clear them and let the mitigations setup below
3387
+
* rediscover them based on configuration.
3388
+
*/
3389
+
x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
3390
+
}
3391
+
3392
+
x86_arch_cap_msr = x86_read_arch_cap_msr();
3393
+
3394
+
cpu_print_attack_vectors();
3395
+
3396
+
/* Select the proper CPU mitigations before patching alternatives: */
3397
+
spectre_v1_select_mitigation();
3398
+
spectre_v2_select_mitigation();
3399
+
retbleed_select_mitigation();
3400
+
spectre_v2_user_select_mitigation();
3401
+
ssb_select_mitigation();
3402
+
l1tf_select_mitigation();
3403
+
mds_select_mitigation();
3404
+
taa_select_mitigation();
3405
+
mmio_select_mitigation();
3406
+
rfds_select_mitigation();
3407
+
srbds_select_mitigation();
3408
+
l1d_flush_select_mitigation();
3409
+
srso_select_mitigation();
3410
+
gds_select_mitigation();
3411
+
its_select_mitigation();
3412
+
bhi_select_mitigation();
3413
+
tsa_select_mitigation();
3414
+
vmscape_select_mitigation();
3415
+
3416
+
/*
3417
+
* After mitigations are selected, some may need to update their
3418
+
* choices.
3419
+
*/
3420
+
spectre_v2_update_mitigation();
3421
+
/*
3422
+
* retbleed_update_mitigation() relies on the state set by
3423
+
* spectre_v2_update_mitigation(); specifically it wants to know about
3424
+
* spectre_v2=ibrs.
3425
+
*/
3426
+
retbleed_update_mitigation();
3427
+
/*
3428
+
* its_update_mitigation() depends on spectre_v2_update_mitigation()
3429
+
* and retbleed_update_mitigation().
3430
+
*/
3431
+
its_update_mitigation();
3432
+
3433
+
/*
3434
+
* spectre_v2_user_update_mitigation() depends on
3435
+
* retbleed_update_mitigation(), specifically the STIBP
3436
+
* selection is forced for UNRET or IBPB.
3437
+
*/
3438
+
spectre_v2_user_update_mitigation();
3439
+
mds_update_mitigation();
3440
+
taa_update_mitigation();
3441
+
mmio_update_mitigation();
3442
+
rfds_update_mitigation();
3443
+
bhi_update_mitigation();
3444
+
/* srso_update_mitigation() depends on retbleed_update_mitigation(). */
3445
+
srso_update_mitigation();
3446
+
vmscape_update_mitigation();
3447
+
3448
+
spectre_v1_apply_mitigation();
3449
+
spectre_v2_apply_mitigation();
3450
+
retbleed_apply_mitigation();
3451
+
spectre_v2_user_apply_mitigation();
3452
+
ssb_apply_mitigation();
3453
+
l1tf_apply_mitigation();
3454
+
mds_apply_mitigation();
3455
+
taa_apply_mitigation();
3456
+
mmio_apply_mitigation();
3457
+
rfds_apply_mitigation();
3458
+
srbds_apply_mitigation();
3459
+
srso_apply_mitigation();
3460
+
gds_apply_mitigation();
3461
+
its_apply_mitigation();
3462
+
bhi_apply_mitigation();
3463
+
tsa_apply_mitigation();
3464
+
vmscape_apply_mitigation();
3232
3465
}
3233
3466
3234
3467
#ifdef CONFIG_SYSFS
-9
arch/x86/kernel/cpu/cpu.h
-9
arch/x86/kernel/cpu/cpu.h
···
42
42
*const __x86_cpu_dev_end[];
43
43
44
44
#ifdef CONFIG_CPU_SUP_INTEL
45
-
enum tsx_ctrl_states {
46
-
TSX_CTRL_ENABLE,
47
-
TSX_CTRL_DISABLE,
48
-
TSX_CTRL_RTM_ALWAYS_ABORT,
49
-
TSX_CTRL_NOT_SUPPORTED,
50
-
};
51
-
52
-
extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
53
-
54
45
extern void __init tsx_init(void);
55
46
void tsx_ap_init(void);
56
47
void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c);
+33
-25
arch/x86/kernel/cpu/tsx.c
+33
-25
arch/x86/kernel/cpu/tsx.c
···
19
19
#undef pr_fmt
20
20
#define pr_fmt(fmt) "tsx: " fmt
21
21
22
-
enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED;
22
+
enum tsx_ctrl_states {
23
+
TSX_CTRL_AUTO,
24
+
TSX_CTRL_ENABLE,
25
+
TSX_CTRL_DISABLE,
26
+
TSX_CTRL_RTM_ALWAYS_ABORT,
27
+
TSX_CTRL_NOT_SUPPORTED,
28
+
};
29
+
30
+
static enum tsx_ctrl_states tsx_ctrl_state __ro_after_init =
31
+
IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO) ? TSX_CTRL_AUTO :
32
+
IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF) ? TSX_CTRL_DISABLE : TSX_CTRL_ENABLE;
23
33
24
34
static void tsx_disable(void)
25
35
{
···
166
156
}
167
157
}
168
158
159
+
static int __init tsx_parse_cmdline(char *str)
160
+
{
161
+
if (!str)
162
+
return -EINVAL;
163
+
164
+
if (!strcmp(str, "on")) {
165
+
tsx_ctrl_state = TSX_CTRL_ENABLE;
166
+
} else if (!strcmp(str, "off")) {
167
+
tsx_ctrl_state = TSX_CTRL_DISABLE;
168
+
} else if (!strcmp(str, "auto")) {
169
+
tsx_ctrl_state = TSX_CTRL_AUTO;
170
+
} else {
171
+
tsx_ctrl_state = TSX_CTRL_DISABLE;
172
+
pr_err("invalid option, defaulting to off\n");
173
+
}
174
+
175
+
return 0;
176
+
}
177
+
early_param("tsx", tsx_parse_cmdline);
178
+
169
179
void __init tsx_init(void)
170
180
{
171
-
char arg[5] = {};
172
-
int ret;
173
-
174
181
tsx_dev_mode_disable();
175
182
176
183
/*
···
221
194
return;
222
195
}
223
196
224
-
ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
225
-
if (ret >= 0) {
226
-
if (!strcmp(arg, "on")) {
227
-
tsx_ctrl_state = TSX_CTRL_ENABLE;
228
-
} else if (!strcmp(arg, "off")) {
229
-
tsx_ctrl_state = TSX_CTRL_DISABLE;
230
-
} else if (!strcmp(arg, "auto")) {
231
-
tsx_ctrl_state = x86_get_tsx_auto_mode();
232
-
} else {
233
-
tsx_ctrl_state = TSX_CTRL_DISABLE;
234
-
pr_err("invalid option, defaulting to off\n");
235
-
}
236
-
} else {
237
-
/* tsx= not provided */
238
-
if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO))
239
-
tsx_ctrl_state = x86_get_tsx_auto_mode();
240
-
else if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF))
241
-
tsx_ctrl_state = TSX_CTRL_DISABLE;
242
-
else
243
-
tsx_ctrl_state = TSX_CTRL_ENABLE;
244
-
}
197
+
if (tsx_ctrl_state == TSX_CTRL_AUTO)
198
+
tsx_ctrl_state = x86_get_tsx_auto_mode();
245
199
246
200
if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
247
201
tsx_disable();