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clk: imx8mp: Fix clkout1/2 support

The CLKOUTn may be fed from PLL1/2/3, but the PLL1/2/3 has to be enabled
first by setting PLL_CLKE bit 11 in CCM_ANALOG_SYS_PLLn_GEN_CTRL register.
The CCM_ANALOG_SYS_PLLn_GEN_CTRL bit 11 is modeled by plln_out clock. Fix
the clock tree and place the clkout1/2 under plln_sel instead of plain plln
to let the clock subsystem correctly control the bit 11 and enable the PLL
in case the CLKOUTn is supplied by PLL1/2/3.

Fixes: 43896f56b59e ("clk: imx8mp: add clkout1/2 support")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20241112013718.333771-1-marex@denx.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

authored by

Marek Vasut and committed by
Abel Vesa a9b7c84d 40384c84

+3 -2
+3 -2
drivers/clk/imx/clk-imx8mp.c
··· 399 399 400 400 static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", 401 401 "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", 402 - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", 403 - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; 402 + "arm_pll_out", "sys_pll1_out", "sys_pll2_out", 403 + "sys_pll3_out", "dummy", "dummy", "osc_24m", 404 + "dummy", "osc_32k"}; 404 405 405 406 static struct clk_hw **hws; 406 407 static struct clk_hw_onecell_data *clk_hw_data;