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ASoC: mediatek: mt8183-afe-pcm: Shorten source code
Merge series from Chen-Yu Tsai <wenst@chromium.org>:
This series is meant as an example on how to use macros and range cases
to shorten the MediaTek audio frontend drivers. The drivers have large
tables describing the registers and register fields for every supported
audio DMA interface. (Some are actually skipped!) There's a lot of
duplication which can be eliminated using macros. This should serve as
a reference for the MT8196 AFE driver that I had commented on.
The three patches tackle separate tables in the driver. The remaining
one that could be tackled is the list of DAIs; but that one has more
differences between each entry, so I haven't done it yet.
+127
-444
+127
-444
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
+127
-444
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
···
424
424
.name = "mt8183-afe-pcm-dai",
425
425
};
426
426
427
+
#define MT8183_MEMIF_BASE(_id, _en_reg, _fs_reg, _mono_reg) \
428
+
[MT8183_MEMIF_##_id] = { \
429
+
.name = #_id, \
430
+
.id = MT8183_MEMIF_##_id, \
431
+
.reg_ofs_base = AFE_##_id##_BASE, \
432
+
.reg_ofs_cur = AFE_##_id##_CUR, \
433
+
.reg_ofs_end = AFE_##_id##_END, \
434
+
.fs_reg = (_fs_reg), \
435
+
.fs_shift = _id##_MODE_SFT, \
436
+
.fs_maskbit = _id##_MODE_MASK, \
437
+
.mono_reg = (_mono_reg), \
438
+
.mono_shift = _id##_DATA_SFT, \
439
+
.enable_reg = (_en_reg), \
440
+
.enable_shift = _id##_ON_SFT, \
441
+
.hd_reg = AFE_MEMIF_HD_MODE, \
442
+
.hd_align_reg = AFE_MEMIF_HDALIGN, \
443
+
.hd_shift = _id##_HD_SFT, \
444
+
.hd_align_mshift = _id##_HD_ALIGN_SFT, \
445
+
.agent_disable_reg = -1, \
446
+
.agent_disable_shift = -1, \
447
+
.msb_reg = -1, \
448
+
.msb_shift = -1, \
449
+
}
450
+
451
+
#define MT8183_MEMIF(_id, _fs_reg, _mono_reg) \
452
+
MT8183_MEMIF_BASE(_id, AFE_DAC_CON0, _fs_reg, _mono_reg)
453
+
454
+
/* For convenience with macros: missing register fields */
455
+
#define MOD_DAI_DATA_SFT -1
456
+
#define HDMI_MODE_SFT -1
457
+
#define HDMI_MODE_MASK -1
458
+
#define HDMI_DATA_SFT -1
459
+
#define HDMI_ON_SFT -1
460
+
461
+
/* For convenience with macros: register name differences */
462
+
#define AFE_VUL12_BASE AFE_VUL_D2_BASE
463
+
#define AFE_VUL12_CUR AFE_VUL_D2_CUR
464
+
#define AFE_VUL12_END AFE_VUL_D2_END
465
+
#define AWB2_HD_ALIGN_SFT AWB2_ALIGN_SFT
466
+
#define VUL12_DATA_SFT VUL12_MONO_SFT
467
+
#define AFE_HDMI_BASE AFE_HDMI_OUT_BASE
468
+
#define AFE_HDMI_CUR AFE_HDMI_OUT_CUR
469
+
#define AFE_HDMI_END AFE_HDMI_OUT_END
470
+
427
471
static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
428
-
[MT8183_MEMIF_DL1] = {
429
-
.name = "DL1",
430
-
.id = MT8183_MEMIF_DL1,
431
-
.reg_ofs_base = AFE_DL1_BASE,
432
-
.reg_ofs_cur = AFE_DL1_CUR,
433
-
.fs_reg = AFE_DAC_CON1,
434
-
.fs_shift = DL1_MODE_SFT,
435
-
.fs_maskbit = DL1_MODE_MASK,
436
-
.mono_reg = AFE_DAC_CON1,
437
-
.mono_shift = DL1_DATA_SFT,
438
-
.enable_reg = AFE_DAC_CON0,
439
-
.enable_shift = DL1_ON_SFT,
440
-
.hd_reg = AFE_MEMIF_HD_MODE,
441
-
.hd_align_reg = AFE_MEMIF_HDALIGN,
442
-
.hd_shift = DL1_HD_SFT,
443
-
.hd_align_mshift = DL1_HD_ALIGN_SFT,
444
-
.agent_disable_reg = -1,
445
-
.agent_disable_shift = -1,
446
-
.msb_reg = -1,
447
-
.msb_shift = -1,
448
-
},
449
-
[MT8183_MEMIF_DL2] = {
450
-
.name = "DL2",
451
-
.id = MT8183_MEMIF_DL2,
452
-
.reg_ofs_base = AFE_DL2_BASE,
453
-
.reg_ofs_cur = AFE_DL2_CUR,
454
-
.fs_reg = AFE_DAC_CON1,
455
-
.fs_shift = DL2_MODE_SFT,
456
-
.fs_maskbit = DL2_MODE_MASK,
457
-
.mono_reg = AFE_DAC_CON1,
458
-
.mono_shift = DL2_DATA_SFT,
459
-
.enable_reg = AFE_DAC_CON0,
460
-
.enable_shift = DL2_ON_SFT,
461
-
.hd_reg = AFE_MEMIF_HD_MODE,
462
-
.hd_align_reg = AFE_MEMIF_HDALIGN,
463
-
.hd_shift = DL2_HD_SFT,
464
-
.hd_align_mshift = DL2_HD_ALIGN_SFT,
465
-
.agent_disable_reg = -1,
466
-
.agent_disable_shift = -1,
467
-
.msb_reg = -1,
468
-
.msb_shift = -1,
469
-
},
470
-
[MT8183_MEMIF_DL3] = {
471
-
.name = "DL3",
472
-
.id = MT8183_MEMIF_DL3,
473
-
.reg_ofs_base = AFE_DL3_BASE,
474
-
.reg_ofs_cur = AFE_DL3_CUR,
475
-
.fs_reg = AFE_DAC_CON2,
476
-
.fs_shift = DL3_MODE_SFT,
477
-
.fs_maskbit = DL3_MODE_MASK,
478
-
.mono_reg = AFE_DAC_CON1,
479
-
.mono_shift = DL3_DATA_SFT,
480
-
.enable_reg = AFE_DAC_CON0,
481
-
.enable_shift = DL3_ON_SFT,
482
-
.hd_reg = AFE_MEMIF_HD_MODE,
483
-
.hd_align_reg = AFE_MEMIF_HDALIGN,
484
-
.hd_shift = DL3_HD_SFT,
485
-
.hd_align_mshift = DL3_HD_ALIGN_SFT,
486
-
.agent_disable_reg = -1,
487
-
.agent_disable_shift = -1,
488
-
.msb_reg = -1,
489
-
.msb_shift = -1,
490
-
},
491
-
[MT8183_MEMIF_VUL2] = {
492
-
.name = "VUL2",
493
-
.id = MT8183_MEMIF_VUL2,
494
-
.reg_ofs_base = AFE_VUL2_BASE,
495
-
.reg_ofs_cur = AFE_VUL2_CUR,
496
-
.fs_reg = AFE_DAC_CON2,
497
-
.fs_shift = VUL2_MODE_SFT,
498
-
.fs_maskbit = VUL2_MODE_MASK,
499
-
.mono_reg = AFE_DAC_CON2,
500
-
.mono_shift = VUL2_DATA_SFT,
501
-
.enable_reg = AFE_DAC_CON0,
502
-
.enable_shift = VUL2_ON_SFT,
503
-
.hd_reg = AFE_MEMIF_HD_MODE,
504
-
.hd_align_reg = AFE_MEMIF_HDALIGN,
505
-
.hd_shift = VUL2_HD_SFT,
506
-
.hd_align_mshift = VUL2_HD_ALIGN_SFT,
507
-
.agent_disable_reg = -1,
508
-
.agent_disable_shift = -1,
509
-
.msb_reg = -1,
510
-
.msb_shift = -1,
511
-
},
512
-
[MT8183_MEMIF_AWB] = {
513
-
.name = "AWB",
514
-
.id = MT8183_MEMIF_AWB,
515
-
.reg_ofs_base = AFE_AWB_BASE,
516
-
.reg_ofs_cur = AFE_AWB_CUR,
517
-
.fs_reg = AFE_DAC_CON1,
518
-
.fs_shift = AWB_MODE_SFT,
519
-
.fs_maskbit = AWB_MODE_MASK,
520
-
.mono_reg = AFE_DAC_CON1,
521
-
.mono_shift = AWB_DATA_SFT,
522
-
.enable_reg = AFE_DAC_CON0,
523
-
.enable_shift = AWB_ON_SFT,
524
-
.hd_reg = AFE_MEMIF_HD_MODE,
525
-
.hd_align_reg = AFE_MEMIF_HDALIGN,
526
-
.hd_shift = AWB_HD_SFT,
527
-
.hd_align_mshift = AWB_HD_ALIGN_SFT,
528
-
.agent_disable_reg = -1,
529
-
.agent_disable_shift = -1,
530
-
.msb_reg = -1,
531
-
.msb_shift = -1,
532
-
},
533
-
[MT8183_MEMIF_AWB2] = {
534
-
.name = "AWB2",
535
-
.id = MT8183_MEMIF_AWB2,
536
-
.reg_ofs_base = AFE_AWB2_BASE,
537
-
.reg_ofs_cur = AFE_AWB2_CUR,
538
-
.fs_reg = AFE_DAC_CON2,
539
-
.fs_shift = AWB2_MODE_SFT,
540
-
.fs_maskbit = AWB2_MODE_MASK,
541
-
.mono_reg = AFE_DAC_CON2,
542
-
.mono_shift = AWB2_DATA_SFT,
543
-
.enable_reg = AFE_DAC_CON0,
544
-
.enable_shift = AWB2_ON_SFT,
545
-
.hd_reg = AFE_MEMIF_HD_MODE,
546
-
.hd_align_reg = AFE_MEMIF_HDALIGN,
547
-
.hd_shift = AWB2_HD_SFT,
548
-
.hd_align_mshift = AWB2_ALIGN_SFT,
549
-
.agent_disable_reg = -1,
550
-
.agent_disable_shift = -1,
551
-
.msb_reg = -1,
552
-
.msb_shift = -1,
553
-
},
554
-
[MT8183_MEMIF_VUL12] = {
555
-
.name = "VUL12",
556
-
.id = MT8183_MEMIF_VUL12,
557
-
.reg_ofs_base = AFE_VUL_D2_BASE,
558
-
.reg_ofs_cur = AFE_VUL_D2_CUR,
559
-
.fs_reg = AFE_DAC_CON0,
560
-
.fs_shift = VUL12_MODE_SFT,
561
-
.fs_maskbit = VUL12_MODE_MASK,
562
-
.mono_reg = AFE_DAC_CON0,
563
-
.mono_shift = VUL12_MONO_SFT,
564
-
.enable_reg = AFE_DAC_CON0,
565
-
.enable_shift = VUL12_ON_SFT,
566
-
.hd_reg = AFE_MEMIF_HD_MODE,
567
-
.hd_align_reg = AFE_MEMIF_HDALIGN,
568
-
.hd_shift = VUL12_HD_SFT,
569
-
.hd_align_mshift = VUL12_HD_ALIGN_SFT,
570
-
.agent_disable_reg = -1,
571
-
.agent_disable_shift = -1,
572
-
.msb_reg = -1,
573
-
.msb_shift = -1,
574
-
},
575
-
[MT8183_MEMIF_MOD_DAI] = {
576
-
.name = "MOD_DAI",
577
-
.id = MT8183_MEMIF_MOD_DAI,
578
-
.reg_ofs_base = AFE_MOD_DAI_BASE,
579
-
.reg_ofs_cur = AFE_MOD_DAI_CUR,
580
-
.fs_reg = AFE_DAC_CON1,
581
-
.fs_shift = MOD_DAI_MODE_SFT,
582
-
.fs_maskbit = MOD_DAI_MODE_MASK,
583
-
.mono_reg = -1,
584
-
.mono_shift = 0,
585
-
.enable_reg = AFE_DAC_CON0,
586
-
.enable_shift = MOD_DAI_ON_SFT,
587
-
.hd_reg = AFE_MEMIF_HD_MODE,
588
-
.hd_align_reg = AFE_MEMIF_HDALIGN,
589
-
.hd_shift = MOD_DAI_HD_SFT,
590
-
.hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,
591
-
.agent_disable_reg = -1,
592
-
.agent_disable_shift = -1,
593
-
.msb_reg = -1,
594
-
.msb_shift = -1,
595
-
},
596
-
[MT8183_MEMIF_HDMI] = {
597
-
.name = "HDMI",
598
-
.id = MT8183_MEMIF_HDMI,
599
-
.reg_ofs_base = AFE_HDMI_OUT_BASE,
600
-
.reg_ofs_cur = AFE_HDMI_OUT_CUR,
601
-
.fs_reg = -1,
602
-
.fs_shift = -1,
603
-
.fs_maskbit = -1,
604
-
.mono_reg = -1,
605
-
.mono_shift = -1,
606
-
.enable_reg = -1, /* control in tdm for sync start */
607
-
.enable_shift = -1,
608
-
.hd_reg = AFE_MEMIF_HD_MODE,
609
-
.hd_align_reg = AFE_MEMIF_HDALIGN,
610
-
.hd_shift = HDMI_HD_SFT,
611
-
.hd_align_mshift = HDMI_HD_ALIGN_SFT,
612
-
.agent_disable_reg = -1,
613
-
.agent_disable_shift = -1,
614
-
.msb_reg = -1,
615
-
.msb_shift = -1,
616
-
},
472
+
MT8183_MEMIF(DL1, AFE_DAC_CON1, AFE_DAC_CON1),
473
+
MT8183_MEMIF(DL2, AFE_DAC_CON1, AFE_DAC_CON1),
474
+
MT8183_MEMIF(DL3, AFE_DAC_CON2, AFE_DAC_CON1),
475
+
MT8183_MEMIF(VUL2, AFE_DAC_CON2, AFE_DAC_CON2),
476
+
MT8183_MEMIF(AWB, AFE_DAC_CON1, AFE_DAC_CON1),
477
+
MT8183_MEMIF(AWB2, AFE_DAC_CON2, AFE_DAC_CON2),
478
+
MT8183_MEMIF(VUL12, AFE_DAC_CON0, AFE_DAC_CON0),
479
+
MT8183_MEMIF(MOD_DAI, AFE_DAC_CON1, -1),
480
+
/* enable control in tdm for sync start */
481
+
MT8183_MEMIF_BASE(HDMI, -1, -1, -1),
617
482
};
618
483
484
+
#define MT8183_AFE_IRQ_BASE(_id, _fs_reg, _fs_shift, _fs_maskbit) \
485
+
[MT8183_IRQ_##_id] = { \
486
+
.id = MT8183_IRQ_##_id, \
487
+
.irq_cnt_reg = AFE_IRQ_MCU_CNT##_id, \
488
+
.irq_cnt_shift = 0, \
489
+
.irq_cnt_maskbit = 0x3ffff, \
490
+
.irq_fs_reg = _fs_reg, \
491
+
.irq_fs_shift = _fs_shift, \
492
+
.irq_fs_maskbit = _fs_maskbit, \
493
+
.irq_en_reg = AFE_IRQ_MCU_CON0, \
494
+
.irq_en_shift = IRQ##_id##_MCU_ON_SFT, \
495
+
.irq_clr_reg = AFE_IRQ_MCU_CLR, \
496
+
.irq_clr_shift = IRQ##_id##_MCU_CLR_SFT, \
497
+
}
498
+
499
+
#define MT8183_AFE_IRQ(_id) \
500
+
MT8183_AFE_IRQ_BASE(_id, AFE_IRQ_MCU_CON1 + _id / 8 * 4, \
501
+
IRQ##_id##_MCU_MODE_SFT, \
502
+
IRQ##_id##_MCU_MODE_MASK)
503
+
504
+
#define MT8183_AFE_IRQ_NOFS(_id) MT8183_AFE_IRQ_BASE(_id, -1, -1, -1)
505
+
619
506
static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
620
-
[MT8183_IRQ_0] = {
621
-
.id = MT8183_IRQ_0,
622
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT0,
623
-
.irq_cnt_shift = 0,
624
-
.irq_cnt_maskbit = 0x3ffff,
625
-
.irq_fs_reg = AFE_IRQ_MCU_CON1,
626
-
.irq_fs_shift = IRQ0_MCU_MODE_SFT,
627
-
.irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
628
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
629
-
.irq_en_shift = IRQ0_MCU_ON_SFT,
630
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
631
-
.irq_clr_shift = IRQ0_MCU_CLR_SFT,
632
-
},
633
-
[MT8183_IRQ_1] = {
634
-
.id = MT8183_IRQ_1,
635
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT1,
636
-
.irq_cnt_shift = 0,
637
-
.irq_cnt_maskbit = 0x3ffff,
638
-
.irq_fs_reg = AFE_IRQ_MCU_CON1,
639
-
.irq_fs_shift = IRQ1_MCU_MODE_SFT,
640
-
.irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
641
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
642
-
.irq_en_shift = IRQ1_MCU_ON_SFT,
643
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
644
-
.irq_clr_shift = IRQ1_MCU_CLR_SFT,
645
-
},
646
-
[MT8183_IRQ_2] = {
647
-
.id = MT8183_IRQ_2,
648
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT2,
649
-
.irq_cnt_shift = 0,
650
-
.irq_cnt_maskbit = 0x3ffff,
651
-
.irq_fs_reg = AFE_IRQ_MCU_CON1,
652
-
.irq_fs_shift = IRQ2_MCU_MODE_SFT,
653
-
.irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
654
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
655
-
.irq_en_shift = IRQ2_MCU_ON_SFT,
656
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
657
-
.irq_clr_shift = IRQ2_MCU_CLR_SFT,
658
-
},
659
-
[MT8183_IRQ_3] = {
660
-
.id = MT8183_IRQ_3,
661
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT3,
662
-
.irq_cnt_shift = 0,
663
-
.irq_cnt_maskbit = 0x3ffff,
664
-
.irq_fs_reg = AFE_IRQ_MCU_CON1,
665
-
.irq_fs_shift = IRQ3_MCU_MODE_SFT,
666
-
.irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
667
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
668
-
.irq_en_shift = IRQ3_MCU_ON_SFT,
669
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
670
-
.irq_clr_shift = IRQ3_MCU_CLR_SFT,
671
-
},
672
-
[MT8183_IRQ_4] = {
673
-
.id = MT8183_IRQ_4,
674
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT4,
675
-
.irq_cnt_shift = 0,
676
-
.irq_cnt_maskbit = 0x3ffff,
677
-
.irq_fs_reg = AFE_IRQ_MCU_CON1,
678
-
.irq_fs_shift = IRQ4_MCU_MODE_SFT,
679
-
.irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
680
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
681
-
.irq_en_shift = IRQ4_MCU_ON_SFT,
682
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
683
-
.irq_clr_shift = IRQ4_MCU_CLR_SFT,
684
-
},
685
-
[MT8183_IRQ_5] = {
686
-
.id = MT8183_IRQ_5,
687
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT5,
688
-
.irq_cnt_shift = 0,
689
-
.irq_cnt_maskbit = 0x3ffff,
690
-
.irq_fs_reg = AFE_IRQ_MCU_CON1,
691
-
.irq_fs_shift = IRQ5_MCU_MODE_SFT,
692
-
.irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
693
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
694
-
.irq_en_shift = IRQ5_MCU_ON_SFT,
695
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
696
-
.irq_clr_shift = IRQ5_MCU_CLR_SFT,
697
-
},
698
-
[MT8183_IRQ_6] = {
699
-
.id = MT8183_IRQ_6,
700
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT6,
701
-
.irq_cnt_shift = 0,
702
-
.irq_cnt_maskbit = 0x3ffff,
703
-
.irq_fs_reg = AFE_IRQ_MCU_CON1,
704
-
.irq_fs_shift = IRQ6_MCU_MODE_SFT,
705
-
.irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
706
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
707
-
.irq_en_shift = IRQ6_MCU_ON_SFT,
708
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
709
-
.irq_clr_shift = IRQ6_MCU_CLR_SFT,
710
-
},
711
-
[MT8183_IRQ_7] = {
712
-
.id = MT8183_IRQ_7,
713
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT7,
714
-
.irq_cnt_shift = 0,
715
-
.irq_cnt_maskbit = 0x3ffff,
716
-
.irq_fs_reg = AFE_IRQ_MCU_CON1,
717
-
.irq_fs_shift = IRQ7_MCU_MODE_SFT,
718
-
.irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
719
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
720
-
.irq_en_shift = IRQ7_MCU_ON_SFT,
721
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
722
-
.irq_clr_shift = IRQ7_MCU_CLR_SFT,
723
-
},
724
-
[MT8183_IRQ_8] = {
725
-
.id = MT8183_IRQ_8,
726
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT8,
727
-
.irq_cnt_shift = 0,
728
-
.irq_cnt_maskbit = 0x3ffff,
729
-
.irq_fs_reg = -1,
730
-
.irq_fs_shift = -1,
731
-
.irq_fs_maskbit = -1,
732
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
733
-
.irq_en_shift = IRQ8_MCU_ON_SFT,
734
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
735
-
.irq_clr_shift = IRQ8_MCU_CLR_SFT,
736
-
},
737
-
[MT8183_IRQ_11] = {
738
-
.id = MT8183_IRQ_11,
739
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT11,
740
-
.irq_cnt_shift = 0,
741
-
.irq_cnt_maskbit = 0x3ffff,
742
-
.irq_fs_reg = AFE_IRQ_MCU_CON2,
743
-
.irq_fs_shift = IRQ11_MCU_MODE_SFT,
744
-
.irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
745
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
746
-
.irq_en_shift = IRQ11_MCU_ON_SFT,
747
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
748
-
.irq_clr_shift = IRQ11_MCU_CLR_SFT,
749
-
},
750
-
[MT8183_IRQ_12] = {
751
-
.id = MT8183_IRQ_12,
752
-
.irq_cnt_reg = AFE_IRQ_MCU_CNT12,
753
-
.irq_cnt_shift = 0,
754
-
.irq_cnt_maskbit = 0x3ffff,
755
-
.irq_fs_reg = AFE_IRQ_MCU_CON2,
756
-
.irq_fs_shift = IRQ12_MCU_MODE_SFT,
757
-
.irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
758
-
.irq_en_reg = AFE_IRQ_MCU_CON0,
759
-
.irq_en_shift = IRQ12_MCU_ON_SFT,
760
-
.irq_clr_reg = AFE_IRQ_MCU_CLR,
761
-
.irq_clr_shift = IRQ12_MCU_CLR_SFT,
762
-
},
507
+
MT8183_AFE_IRQ(0),
508
+
MT8183_AFE_IRQ(1),
509
+
MT8183_AFE_IRQ(2),
510
+
MT8183_AFE_IRQ(3),
511
+
MT8183_AFE_IRQ(4),
512
+
MT8183_AFE_IRQ(5),
513
+
MT8183_AFE_IRQ(6),
514
+
MT8183_AFE_IRQ(7),
515
+
MT8183_AFE_IRQ_NOFS(8),
516
+
MT8183_AFE_IRQ(11),
517
+
MT8183_AFE_IRQ(12),
763
518
};
764
519
765
520
static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
···
522
767
/* these auto-gen reg has read-only bit, so put it as volatile */
523
768
/* volatile reg cannot be cached, so cannot be set when power off */
524
769
switch (reg) {
525
-
case AUDIO_TOP_CON0: /* reg bit controlled by CCF */
526
-
case AUDIO_TOP_CON1: /* reg bit controlled by CCF */
770
+
case AUDIO_TOP_CON0 ... AUDIO_TOP_CON1: /* reg bit controlled by CCF */
527
771
case AUDIO_TOP_CON3:
528
-
case AFE_DL1_CUR:
529
-
case AFE_DL1_END:
530
-
case AFE_DL2_CUR:
531
-
case AFE_DL2_END:
532
-
case AFE_AWB_END:
533
-
case AFE_AWB_CUR:
534
-
case AFE_VUL_END:
535
-
case AFE_VUL_CUR:
536
-
case AFE_MEMIF_MON0:
537
-
case AFE_MEMIF_MON1:
538
-
case AFE_MEMIF_MON2:
539
-
case AFE_MEMIF_MON3:
540
-
case AFE_MEMIF_MON4:
541
-
case AFE_MEMIF_MON5:
542
-
case AFE_MEMIF_MON6:
543
-
case AFE_MEMIF_MON7:
544
-
case AFE_MEMIF_MON8:
545
-
case AFE_MEMIF_MON9:
546
-
case AFE_ADDA_SRC_DEBUG_MON0:
547
-
case AFE_ADDA_SRC_DEBUG_MON1:
548
-
case AFE_ADDA_UL_SRC_MON0:
549
-
case AFE_ADDA_UL_SRC_MON1:
772
+
case AFE_DL1_CUR ... AFE_DL1_END:
773
+
case AFE_DL2_CUR ... AFE_DL2_END:
774
+
case AFE_AWB_END ... AFE_AWB_CUR:
775
+
case AFE_VUL_END ... AFE_VUL_CUR:
776
+
case AFE_MEMIF_MON0 ... AFE_MEMIF_MON9:
777
+
case AFE_ADDA_SRC_DEBUG_MON0 ... AFE_ADDA_SRC_DEBUG_MON1:
778
+
case AFE_ADDA_UL_SRC_MON0 ... AFE_ADDA_UL_SRC_MON1:
550
779
case AFE_SIDETONE_MON:
551
-
case AFE_SIDETONE_CON0:
552
-
case AFE_SIDETONE_COEFF:
780
+
case AFE_SIDETONE_CON0 ... AFE_SIDETONE_COEFF:
553
781
case AFE_BUS_MON0:
554
-
case AFE_MRGIF_MON0:
555
-
case AFE_MRGIF_MON1:
556
-
case AFE_MRGIF_MON2:
557
-
case AFE_I2S_MON:
782
+
case AFE_MRGIF_MON0 ... AFE_I2S_MON:
558
783
case AFE_DAC_MON:
559
-
case AFE_VUL2_END:
560
-
case AFE_VUL2_CUR:
561
-
case AFE_IRQ0_MCU_CNT_MON:
562
-
case AFE_IRQ6_MCU_CNT_MON:
563
-
case AFE_MOD_DAI_END:
564
-
case AFE_MOD_DAI_CUR:
565
-
case AFE_VUL_D2_END:
566
-
case AFE_VUL_D2_CUR:
567
-
case AFE_DL3_CUR:
568
-
case AFE_DL3_END:
784
+
case AFE_VUL2_END ... AFE_VUL2_CUR:
785
+
case AFE_IRQ0_MCU_CNT_MON ... AFE_IRQ6_MCU_CNT_MON:
786
+
case AFE_MOD_DAI_END ... AFE_MOD_DAI_CUR:
787
+
case AFE_VUL_D2_END ... AFE_VUL_D2_CUR:
788
+
case AFE_DL3_CUR ... AFE_DL3_END:
569
789
case AFE_HDMI_OUT_CON0:
570
-
case AFE_HDMI_OUT_CUR:
571
-
case AFE_HDMI_OUT_END:
572
-
case AFE_IRQ3_MCU_CNT_MON:
573
-
case AFE_IRQ4_MCU_CNT_MON:
574
-
case AFE_IRQ_MCU_STATUS:
575
-
case AFE_IRQ_MCU_CLR:
790
+
case AFE_HDMI_OUT_CUR ... AFE_HDMI_OUT_END:
791
+
case AFE_IRQ3_MCU_CNT_MON... AFE_IRQ4_MCU_CNT_MON:
792
+
case AFE_IRQ_MCU_STATUS ... AFE_IRQ_MCU_CLR:
576
793
case AFE_IRQ_MCU_MON2:
577
-
case AFE_IRQ1_MCU_CNT_MON:
578
-
case AFE_IRQ2_MCU_CNT_MON:
579
-
case AFE_IRQ1_MCU_EN_CNT_MON:
580
-
case AFE_IRQ5_MCU_CNT_MON:
794
+
case AFE_IRQ1_MCU_CNT_MON ... AFE_IRQ5_MCU_CNT_MON:
581
795
case AFE_IRQ7_MCU_CNT_MON:
582
796
case AFE_GAIN1_CUR:
583
797
case AFE_GAIN2_CUR:
584
798
case AFE_SRAM_DELSEL_CON0:
585
-
case AFE_SRAM_DELSEL_CON2:
586
-
case AFE_SRAM_DELSEL_CON3:
587
-
case AFE_ASRC_2CH_CON12:
588
-
case AFE_ASRC_2CH_CON13:
799
+
case AFE_SRAM_DELSEL_CON2 ... AFE_SRAM_DELSEL_CON3:
800
+
case AFE_ASRC_2CH_CON12 ... AFE_ASRC_2CH_CON13:
589
801
case PCM_INTF_CON2:
590
-
case FPGA_CFG0:
591
-
case FPGA_CFG1:
592
-
case FPGA_CFG2:
593
-
case FPGA_CFG3:
594
-
case AUDIO_TOP_DBG_MON0:
595
-
case AUDIO_TOP_DBG_MON1:
596
-
case AFE_IRQ8_MCU_CNT_MON:
597
-
case AFE_IRQ11_MCU_CNT_MON:
598
-
case AFE_IRQ12_MCU_CNT_MON:
802
+
case FPGA_CFG0 ... FPGA_CFG1:
803
+
case FPGA_CFG2 ... FPGA_CFG3:
804
+
case AUDIO_TOP_DBG_MON0 ... AUDIO_TOP_DBG_MON1:
805
+
case AFE_IRQ8_MCU_CNT_MON ... AFE_IRQ12_MCU_CNT_MON:
599
806
case AFE_CBIP_MON0:
600
-
case AFE_CBIP_SLV_MUX_MON0:
601
-
case AFE_CBIP_SLV_DECODER_MON0:
807
+
case AFE_CBIP_SLV_MUX_MON0 ... AFE_CBIP_SLV_DECODER_MON0:
602
808
case AFE_ADDA6_SRC_DEBUG_MON0:
603
-
case AFE_ADD6A_UL_SRC_MON0:
604
-
case AFE_ADDA6_UL_SRC_MON1:
809
+
case AFE_ADD6A_UL_SRC_MON0... AFE_ADDA6_UL_SRC_MON1:
605
810
case AFE_DL1_CUR_MSB:
606
811
case AFE_DL2_CUR_MSB:
607
812
case AFE_AWB_CUR_MSB:
···
571
856
case AFE_VUL_D2_CUR_MSB:
572
857
case AFE_DL3_CUR_MSB:
573
858
case AFE_HDMI_OUT_CUR_MSB:
574
-
case AFE_AWB2_END:
575
-
case AFE_AWB2_CUR:
859
+
case AFE_AWB2_END ... AFE_AWB2_CUR:
576
860
case AFE_AWB2_CUR_MSB:
577
-
case AFE_ADDA_DL_SDM_FIFO_MON:
578
-
case AFE_ADDA_DL_SRC_LCH_MON:
579
-
case AFE_ADDA_DL_SRC_RCH_MON:
580
-
case AFE_ADDA_DL_SDM_OUT_MON:
581
-
case AFE_CONNSYS_I2S_MON:
582
-
case AFE_ASRC_2CH_CON0:
583
-
case AFE_ASRC_2CH_CON2:
584
-
case AFE_ASRC_2CH_CON3:
585
-
case AFE_ASRC_2CH_CON4:
586
-
case AFE_ASRC_2CH_CON5:
587
-
case AFE_ASRC_2CH_CON7:
588
-
case AFE_ASRC_2CH_CON8:
589
-
case AFE_MEMIF_MON12:
590
-
case AFE_MEMIF_MON13:
591
-
case AFE_MEMIF_MON14:
592
-
case AFE_MEMIF_MON15:
593
-
case AFE_MEMIF_MON16:
594
-
case AFE_MEMIF_MON17:
595
-
case AFE_MEMIF_MON18:
596
-
case AFE_MEMIF_MON19:
597
-
case AFE_MEMIF_MON20:
598
-
case AFE_MEMIF_MON21:
599
-
case AFE_MEMIF_MON22:
600
-
case AFE_MEMIF_MON23:
601
-
case AFE_MEMIF_MON24:
602
-
case AFE_ADDA_MTKAIF_MON0:
603
-
case AFE_ADDA_MTKAIF_MON1:
861
+
case AFE_ADDA_DL_SDM_FIFO_MON ... AFE_ADDA_DL_SDM_OUT_MON:
862
+
case AFE_CONNSYS_I2S_MON ... AFE_ASRC_2CH_CON0:
863
+
case AFE_ASRC_2CH_CON2 ... AFE_ASRC_2CH_CON5:
864
+
case AFE_ASRC_2CH_CON7 ... AFE_ASRC_2CH_CON8:
865
+
case AFE_MEMIF_MON12 ... AFE_MEMIF_MON24:
866
+
case AFE_ADDA_MTKAIF_MON0 ... AFE_ADDA_MTKAIF_MON1:
604
867
case AFE_AUD_PAD_TOP:
605
868
case AFE_GENERAL1_ASRC_2CH_CON0:
606
-
case AFE_GENERAL1_ASRC_2CH_CON2:
607
-
case AFE_GENERAL1_ASRC_2CH_CON3:
608
-
case AFE_GENERAL1_ASRC_2CH_CON4:
609
-
case AFE_GENERAL1_ASRC_2CH_CON5:
610
-
case AFE_GENERAL1_ASRC_2CH_CON7:
611
-
case AFE_GENERAL1_ASRC_2CH_CON8:
612
-
case AFE_GENERAL1_ASRC_2CH_CON12:
613
-
case AFE_GENERAL1_ASRC_2CH_CON13:
869
+
case AFE_GENERAL1_ASRC_2CH_CON2 ... AFE_GENERAL1_ASRC_2CH_CON5:
870
+
case AFE_GENERAL1_ASRC_2CH_CON7 ... AFE_GENERAL1_ASRC_2CH_CON8:
871
+
case AFE_GENERAL1_ASRC_2CH_CON12 ... AFE_GENERAL1_ASRC_2CH_CON13:
614
872
case AFE_GENERAL2_ASRC_2CH_CON0:
615
-
case AFE_GENERAL2_ASRC_2CH_CON2:
616
-
case AFE_GENERAL2_ASRC_2CH_CON3:
617
-
case AFE_GENERAL2_ASRC_2CH_CON4:
618
-
case AFE_GENERAL2_ASRC_2CH_CON5:
619
-
case AFE_GENERAL2_ASRC_2CH_CON7:
620
-
case AFE_GENERAL2_ASRC_2CH_CON8:
621
-
case AFE_GENERAL2_ASRC_2CH_CON12:
622
-
case AFE_GENERAL2_ASRC_2CH_CON13:
873
+
case AFE_GENERAL2_ASRC_2CH_CON2 ... AFE_GENERAL2_ASRC_2CH_CON5:
874
+
case AFE_GENERAL2_ASRC_2CH_CON7 ... AFE_GENERAL2_ASRC_2CH_CON8:
875
+
case AFE_GENERAL2_ASRC_2CH_CON12 ... AFE_GENERAL2_ASRC_2CH_CON13:
623
876
return true;
624
877
default:
625
878
return false;