Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: PCI: Convert Rockchip RK3399 PCIe to DT schema
Convert the Rockchip RK3399 PCIe Host/Endpoint controller to DT schema
format. Like most dual mode PCI controllers, we need to split the schema
into common, host and endpoint schemas.
Link: https://lore.kernel.org/r/20221219191209.1975834-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
+270
-198
+69
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-common.yaml
+69
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-common.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip AXI PCIe Bridge Common Properties
8
+
9
+
maintainers:
10
+
- Shawn Lin <shawn.lin@rock-chips.com>
11
+
12
+
properties:
13
+
reg:
14
+
maxItems: 2
15
+
16
+
clocks:
17
+
maxItems: 4
18
+
19
+
clock-names:
20
+
items:
21
+
- const: aclk
22
+
- const: aclk-perf
23
+
- const: hclk
24
+
- const: pm
25
+
26
+
num-lanes:
27
+
maximum: 4
28
+
29
+
phys:
30
+
oneOf:
31
+
- maxItems: 1
32
+
- maxItems: 4
33
+
34
+
phy-names:
35
+
oneOf:
36
+
- const: pcie-phy
37
+
- items:
38
+
- const: pcie-phy-0
39
+
- const: pcie-phy-1
40
+
- const: pcie-phy-2
41
+
- const: pcie-phy-3
42
+
43
+
resets:
44
+
maxItems: 7
45
+
46
+
reset-names:
47
+
items:
48
+
- const: core
49
+
- const: mgmt
50
+
- const: mgmt-sticky
51
+
- const: pipe
52
+
- const: pm
53
+
- const: pclk
54
+
- const: aclk
55
+
56
+
required:
57
+
- compatible
58
+
- reg
59
+
- reg-names
60
+
- clocks
61
+
- clock-names
62
+
- phys
63
+
- phy-names
64
+
- resets
65
+
- reset-names
66
+
67
+
additionalProperties: true
68
+
69
+
...
+68
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
+68
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip AXI PCIe Endpoint
8
+
9
+
maintainers:
10
+
- Shawn Lin <shawn.lin@rock-chips.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/pci/pci-ep.yaml#
14
+
- $ref: rockchip,rk3399-pcie-common.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
const: rockchip,rk3399-pcie-ep
19
+
20
+
reg: true
21
+
22
+
reg-names:
23
+
items:
24
+
- const: apb-base
25
+
- const: mem-base
26
+
27
+
rockchip,max-outbound-regions:
28
+
description: Maximum number of outbound regions
29
+
$ref: /schemas/types.yaml#/definitions/uint32
30
+
maximum: 32
31
+
default: 32
32
+
33
+
required:
34
+
- rockchip,max-outbound-regions
35
+
36
+
unevaluatedProperties: false
37
+
38
+
examples:
39
+
- |
40
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
41
+
#include <dt-bindings/gpio/gpio.h>
42
+
#include <dt-bindings/clock/rk3399-cru.h>
43
+
44
+
bus {
45
+
#address-cells = <2>;
46
+
#size-cells = <2>;
47
+
48
+
pcie-ep@f8000000 {
49
+
compatible = "rockchip,rk3399-pcie-ep";
50
+
reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
51
+
reg-names = "apb-base", "mem-base";
52
+
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
53
+
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
54
+
clock-names = "aclk", "aclk-perf",
55
+
"hclk", "pm";
56
+
max-functions = /bits/ 8 <8>;
57
+
num-lanes = <4>;
58
+
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
59
+
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
60
+
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
61
+
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
62
+
"pm", "pclk", "aclk";
63
+
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
64
+
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
65
+
rockchip,max-outbound-regions = <16>;
66
+
};
67
+
};
68
+
...
+132
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
+132
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip AXI PCIe Root Port Bridge Host
8
+
9
+
maintainers:
10
+
- Shawn Lin <shawn.lin@rock-chips.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/pci/pci-bus.yaml#
14
+
- $ref: rockchip,rk3399-pcie-common.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
const: rockchip,rk3399-pcie
19
+
20
+
reg: true
21
+
22
+
reg-names:
23
+
items:
24
+
- const: axi-base
25
+
- const: apb-base
26
+
27
+
interrupts:
28
+
maxItems: 3
29
+
30
+
interrupt-names:
31
+
items:
32
+
- const: sys
33
+
- const: legacy
34
+
- const: client
35
+
36
+
aspm-no-l0s:
37
+
description: This property is needed if using 24MHz OSC for RC's PHY.
38
+
39
+
ep-gpios:
40
+
description: pre-reset GPIO
41
+
42
+
vpcie12v-supply:
43
+
description: The 12v regulator to use for PCIe.
44
+
45
+
vpcie3v3-supply:
46
+
description: The 3.3v regulator to use for PCIe.
47
+
48
+
vpcie1v8-supply:
49
+
description: The 1.8v regulator to use for PCIe.
50
+
51
+
vpcie0v9-supply:
52
+
description: The 0.9v regulator to use for PCIe.
53
+
54
+
interrupt-controller:
55
+
type: object
56
+
additionalProperties: false
57
+
58
+
properties:
59
+
'#address-cells':
60
+
const: 0
61
+
62
+
'#interrupt-cells':
63
+
const: 1
64
+
65
+
interrupt-controller: true
66
+
67
+
required:
68
+
- ranges
69
+
- "#interrupt-cells"
70
+
- interrupts
71
+
- interrupt-controller
72
+
- interrupt-map
73
+
- interrupt-map-mask
74
+
- msi-map
75
+
76
+
unevaluatedProperties: false
77
+
78
+
examples:
79
+
- |
80
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
81
+
#include <dt-bindings/gpio/gpio.h>
82
+
#include <dt-bindings/clock/rk3399-cru.h>
83
+
84
+
bus {
85
+
#address-cells = <2>;
86
+
#size-cells = <2>;
87
+
88
+
pcie@f8000000 {
89
+
compatible = "rockchip,rk3399-pcie";
90
+
device_type = "pci";
91
+
#address-cells = <3>;
92
+
#size-cells = <2>;
93
+
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
94
+
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
95
+
clock-names = "aclk", "aclk-perf",
96
+
"hclk", "pm";
97
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
98
+
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
99
+
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
100
+
interrupt-names = "sys", "legacy", "client";
101
+
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
102
+
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
103
+
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
104
+
num-lanes = <4>;
105
+
msi-map = <0x0 &its 0x0 0x1000>;
106
+
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
107
+
reg-names = "axi-base", "apb-base";
108
+
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
109
+
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
110
+
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
111
+
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
112
+
"pm", "pclk", "aclk";
113
+
/* deprecated legacy PHY model */
114
+
phys = <&pcie_phy>;
115
+
phy-names = "pcie-phy";
116
+
pinctrl-names = "default";
117
+
pinctrl-0 = <&pcie_clkreq>;
118
+
#interrupt-cells = <1>;
119
+
interrupt-map-mask = <0 0 0 7>;
120
+
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
121
+
<0 0 0 2 &pcie0_intc 1>,
122
+
<0 0 0 3 &pcie0_intc 2>,
123
+
<0 0 0 4 &pcie0_intc 3>;
124
+
125
+
pcie0_intc: interrupt-controller {
126
+
interrupt-controller;
127
+
#address-cells = <0>;
128
+
#interrupt-cells = <1>;
129
+
};
130
+
};
131
+
};
132
+
...
-62
Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
-62
Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
···
1
-
* Rockchip AXI PCIe Endpoint Controller DT description
2
-
3
-
Required properties:
4
-
- compatible: Should contain "rockchip,rk3399-pcie-ep"
5
-
- reg: Two register ranges as listed in the reg-names property
6
-
- reg-names: Must include the following names
7
-
- "apb-base"
8
-
- "mem-base"
9
-
- clocks: Must contain an entry for each entry in clock-names.
10
-
See ../clocks/clock-bindings.txt for details.
11
-
- clock-names: Must include the following entries:
12
-
- "aclk"
13
-
- "aclk-perf"
14
-
- "hclk"
15
-
- "pm"
16
-
- resets: Must contain seven entries for each entry in reset-names.
17
-
See ../reset/reset.txt for details.
18
-
- reset-names: Must include the following names
19
-
- "core"
20
-
- "mgmt"
21
-
- "mgmt-sticky"
22
-
- "pipe"
23
-
- "pm"
24
-
- "aclk"
25
-
- "pclk"
26
-
- pinctrl-names : The pin control state names
27
-
- pinctrl-0: The "default" pinctrl state
28
-
- phys: Must contain an phandle to a PHY for each entry in phy-names.
29
-
- phy-names: Must include 4 entries for all 4 lanes even if some of
30
-
them won't be used for your cases. Entries are of the form "pcie-phy-N":
31
-
where N ranges from 0 to 3.
32
-
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
33
-
for changing the #phy-cells of phy node to support it)
34
-
- rockchip,max-outbound-regions: Maximum number of outbound regions
35
-
36
-
Optional Property:
37
-
- num-lanes: number of lanes to use
38
-
- max-functions: Maximum number of functions that can be configured (default 1).
39
-
40
-
pcie0-ep: pcie@f8000000 {
41
-
compatible = "rockchip,rk3399-pcie-ep";
42
-
#address-cells = <3>;
43
-
#size-cells = <2>;
44
-
rockchip,max-outbound-regions = <16>;
45
-
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
46
-
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
47
-
clock-names = "aclk", "aclk-perf",
48
-
"hclk", "pm";
49
-
max-functions = /bits/ 8 <8>;
50
-
num-lanes = <4>;
51
-
reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
52
-
reg-names = "apb-base", "mem-base";
53
-
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
54
-
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
55
-
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
56
-
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
57
-
"pm", "pclk", "aclk";
58
-
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
59
-
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
60
-
pinctrl-names = "default";
61
-
pinctrl-0 = <&pcie_clkreq>;
62
-
};
-135
Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt
-135
Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt
···
1
-
* Rockchip AXI PCIe Root Port Bridge DT description
2
-
3
-
Required properties:
4
-
- #address-cells: Address representation for root ports, set to <3>
5
-
- #size-cells: Size representation for root ports, set to <2>
6
-
- #interrupt-cells: specifies the number of cells needed to encode an
7
-
interrupt source. The value must be 1.
8
-
- compatible: Should contain "rockchip,rk3399-pcie"
9
-
- reg: Two register ranges as listed in the reg-names property
10
-
- reg-names: Must include the following names
11
-
- "axi-base"
12
-
- "apb-base"
13
-
- clocks: Must contain an entry for each entry in clock-names.
14
-
See ../clocks/clock-bindings.txt for details.
15
-
- clock-names: Must include the following entries:
16
-
- "aclk"
17
-
- "aclk-perf"
18
-
- "hclk"
19
-
- "pm"
20
-
- msi-map: Maps a Requester ID to an MSI controller and associated
21
-
msi-specifier data. See ./pci-msi.txt
22
-
- interrupts: Three interrupt entries must be specified.
23
-
- interrupt-names: Must include the following names
24
-
- "sys"
25
-
- "legacy"
26
-
- "client"
27
-
- resets: Must contain seven entries for each entry in reset-names.
28
-
See ../reset/reset.txt for details.
29
-
- reset-names: Must include the following names
30
-
- "core"
31
-
- "mgmt"
32
-
- "mgmt-sticky"
33
-
- "pipe"
34
-
- "pm"
35
-
- "aclk"
36
-
- "pclk"
37
-
- pinctrl-names : The pin control state names
38
-
- pinctrl-0: The "default" pinctrl state
39
-
- #interrupt-cells: specifies the number of cells needed to encode an
40
-
interrupt source. The value must be 1.
41
-
- interrupt-map-mask and interrupt-map: standard PCI properties
42
-
43
-
Required properties for legacy PHY model (deprecated):
44
-
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
45
-
- phy-names: MUST be "pcie-phy".
46
-
47
-
Required properties for per-lane PHY model (preferred):
48
-
- phys: Must contain an phandle to a PHY for each entry in phy-names.
49
-
- phy-names: Must include 4 entries for all 4 lanes even if some of
50
-
them won't be used for your cases. Entries are of the form "pcie-phy-N":
51
-
where N ranges from 0 to 3.
52
-
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
53
-
for changing the #phy-cells of phy node to support it)
54
-
55
-
Optional Property:
56
-
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
57
-
using 24MHz OSC for RC's PHY.
58
-
- ep-gpios: contain the entry for pre-reset GPIO
59
-
- num-lanes: number of lanes to use
60
-
- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
61
-
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
62
-
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
63
-
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
64
-
65
-
*Interrupt controller child node*
66
-
The core controller provides a single interrupt for legacy INTx. The PCIe node
67
-
should contain an interrupt controller node as a target for the PCI
68
-
'interrupt-map' property. This node represents the domain at which the four
69
-
INTx interrupts are decoded and routed.
70
-
71
-
72
-
Required properties for Interrupt controller child node:
73
-
- interrupt-controller: identifies the node as an interrupt controller
74
-
- #address-cells: specifies the number of cells needed to encode an
75
-
address. The value must be 0.
76
-
- #interrupt-cells: specifies the number of cells needed to encode an
77
-
interrupt source. The value must be 1.
78
-
79
-
Example:
80
-
81
-
pcie0: pcie@f8000000 {
82
-
compatible = "rockchip,rk3399-pcie";
83
-
#address-cells = <3>;
84
-
#size-cells = <2>;
85
-
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
86
-
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
87
-
clock-names = "aclk", "aclk-perf",
88
-
"hclk", "pm";
89
-
bus-range = <0x0 0x1>;
90
-
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
91
-
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
92
-
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
93
-
interrupt-names = "sys", "legacy", "client";
94
-
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
95
-
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
96
-
assigned-clock-rates = <100000000>;
97
-
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
98
-
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
99
-
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
100
-
num-lanes = <4>;
101
-
msi-map = <0x0 &its 0x0 0x1000>;
102
-
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
103
-
reg-names = "axi-base", "apb-base";
104
-
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
105
-
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
106
-
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
107
-
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
108
-
"pm", "pclk", "aclk";
109
-
/* deprecated legacy PHY model */
110
-
phys = <&pcie_phy>;
111
-
phy-names = "pcie-phy";
112
-
pinctrl-names = "default";
113
-
pinctrl-0 = <&pcie_clkreq>;
114
-
#interrupt-cells = <1>;
115
-
interrupt-map-mask = <0 0 0 7>;
116
-
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
117
-
<0 0 0 2 &pcie0_intc 1>,
118
-
<0 0 0 3 &pcie0_intc 2>,
119
-
<0 0 0 4 &pcie0_intc 3>;
120
-
pcie0_intc: interrupt-controller {
121
-
interrupt-controller;
122
-
#address-cells = <0>;
123
-
#interrupt-cells = <1>;
124
-
};
125
-
};
126
-
127
-
pcie0: pcie@f8000000 {
128
-
...
129
-
130
-
/* preferred per-lane PHY model */
131
-
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
132
-
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
133
-
134
-
...
135
-
};
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
16307
16307
L: linux-pci@vger.kernel.org
16308
16308
L: linux-rockchip@lists.infradead.org
16309
16309
S: Maintained
16310
-
F: Documentation/devicetree/bindings/pci/rockchip-pcie*
16310
+
F: Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie*
16311
16311
F: drivers/pci/controller/pcie-rockchip*
16312
16312
16313
16313
PCIE DRIVER FOR SOCIONEXT UNIPHIER