Merge branch 'for-linus/i2c-33' of git://git.fluff.org/bjdooks/linux

+30

Documentation/devicetree/bindings/i2c/omap-i2c.txt

··· 1 + I2C for OMAP platforms 2 + 3 + Required properties : 4 + - compatible : Must be "ti,omap3-i2c" or "ti,omap4-i2c" 5 + - ti,hwmods : Must be "i2c<n>", n being the instance number (1-based) 6 + - #address-cells = <1>; 7 + - #size-cells = <0>; 8 + 9 + Recommended properties : 10 + - clock-frequency : Desired I2C bus clock frequency in Hz. Otherwise 11 + the default 100 kHz frequency will be used. 12 + 13 + Optional properties: 14 + - Child nodes conforming to i2c bus binding 15 + 16 + Note: Current implementation will fetch base address, irq and dma 17 + from omap hwmod data base during device registration. 18 + Future plan is to migrate hwmod data base contents into device tree 19 + blob so that, all the required data will be used from device tree dts 20 + file. 21 + 22 + Examples : 23 + 24 + i2c1: i2c@0 { 25 + compatible = "ti,omap3-i2c"; 26 + #address-cells = <1>; 27 + #size-cells = <0>; 28 + ti,hwmods = "i2c1"; 29 + clock-frequency = <400000>; 30 + };

+7 -7

drivers/i2c/busses/Kconfig

··· 682 682 will be called xilinx_i2c. 683 683 684 684 config I2C_EG20T 685 - tristate "Intel EG20T PCH / OKI SEMICONDUCTOR IOH(ML7213/ML7223)" 685 + tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) I2C" 686 686 depends on PCI 687 687 help 688 688 This driver is for PCH(Platform controller Hub) I2C of EG20T which 689 689 is an IOH(Input/Output Hub) for x86 embedded processor. 690 690 This driver can access PCH I2C bus device. 691 691 692 - This driver also can be used for OKI SEMICONDUCTOR IOH(Input/ 693 - Output Hub), ML7213 and ML7223. 694 - ML7213 IOH is for IVI(In-Vehicle Infotainment) use and ML7223 IOH is 695 - for MP(Media Phone) use. 696 - ML7213/ML7223 is companion chip for Intel Atom E6xx series. 697 - ML7213/ML7223 is completely compatible for Intel EG20T PCH. 692 + This driver also can be used for LAPIS Semiconductor IOH(Input/ 693 + Output Hub), ML7213, ML7223 and ML7831. 694 + ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is 695 + for MP(Media Phone) use and ML7831 IOH is for general purpose use. 696 + ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. 697 + ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. 698 698 699 699 comment "External I2C/SMBus adapter drivers" 700 700

+12 -7

drivers/i2c/busses/i2c-eg20t.c

··· 1 1 /* 2 - * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. 2 + * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 3 * 4 4 * This program is free software; you can redistribute it and/or modify 5 5 * it under the terms of the GNU General Public License as published by ··· 136 136 /* 137 137 Set the number of I2C instance max 138 138 Intel EG20T PCH : 1ch 139 - OKI SEMICONDUCTOR ML7213 IOH : 2ch 139 + LAPIS Semiconductor ML7213 IOH : 2ch 140 + LAPIS Semiconductor ML7831 IOH : 1ch 140 141 */ 141 142 #define PCH_I2C_MAX_DEV 2 142 143 ··· 181 180 static wait_queue_head_t pch_event; 182 181 static DEFINE_MUTEX(pch_mutex); 183 182 184 - /* Definition for ML7213 by OKI SEMICONDUCTOR */ 183 + /* Definition for ML7213 by LAPIS Semiconductor */ 185 184 #define PCI_VENDOR_ID_ROHM 0x10DB 186 185 #define PCI_DEVICE_ID_ML7213_I2C 0x802D 187 186 #define PCI_DEVICE_ID_ML7223_I2C 0x8010 187 + #define PCI_DEVICE_ID_ML7831_I2C 0x8817 188 188 189 189 static DEFINE_PCI_DEVICE_TABLE(pch_pcidev_id) = { 190 190 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, }, 191 191 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, }, 192 192 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, }, 193 + { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, }, 193 194 {0,} 194 195 }; 195 196 ··· 246 243 if (pch_clk > PCH_MAX_CLK) 247 244 pch_clk = 62500; 248 245 249 - pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8; 246 + pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8); 250 247 /* Set transfer speed in I2CBC */ 251 248 iowrite32(pch_i2cbc, p + PCH_I2CBC); 252 249 ··· 921 918 pch_adap->dev.parent = &pdev->dev; 922 919 923 920 pch_i2c_init(&adap_info->pch_data[i]); 924 - ret = i2c_add_adapter(pch_adap); 921 + 922 + pch_adap->nr = i; 923 + ret = i2c_add_numbered_adapter(pch_adap); 925 924 if (ret) { 926 925 pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i); 927 926 goto err_add_adapter; ··· 1063 1058 } 1064 1059 module_exit(pch_pci_exit); 1065 1060 1066 - MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH I2C Driver"); 1061 + MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C"); 1067 1062 MODULE_LICENSE("GPL"); 1068 - MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>"); 1063 + MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.lapis-semi.com>"); 1069 1064 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR)); 1070 1065 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));

+70 -40

drivers/i2c/busses/i2c-omap.c

··· 37 37 #include <linux/platform_device.h> 38 38 #include <linux/clk.h> 39 39 #include <linux/io.h> 40 + #include <linux/of.h> 41 + #include <linux/of_i2c.h> 42 + #include <linux/of_device.h> 40 43 #include <linux/slab.h> 41 44 #include <linux/i2c-omap.h> 42 45 #include <linux/pm_runtime.h> ··· 185 182 u32 latency; /* maximum mpu wkup latency */ 186 183 void (*set_mpu_wkup_lat)(struct device *dev, 187 184 long latency); 188 - u32 speed; /* Speed of bus in Khz */ 185 + u32 speed; /* Speed of bus in kHz */ 186 + u32 dtrev; /* extra revision from DT */ 187 + u32 flags; 189 188 u16 cmd_err; 190 189 u8 *buf; 191 190 u8 *regs; ··· 240 235 [OMAP_I2C_BUF_REG] = 0x94, 241 236 [OMAP_I2C_CNT_REG] = 0x98, 242 237 [OMAP_I2C_DATA_REG] = 0x9c, 243 - [OMAP_I2C_SYSC_REG] = 0x20, 238 + [OMAP_I2C_SYSC_REG] = 0x10, 244 239 [OMAP_I2C_CON_REG] = 0xa4, 245 240 [OMAP_I2C_OA_REG] = 0xa8, 246 241 [OMAP_I2C_SA_REG] = 0xac, ··· 271 266 272 267 static void omap_i2c_unidle(struct omap_i2c_dev *dev) 273 268 { 274 - struct omap_i2c_bus_platform_data *pdata; 275 - 276 - pdata = dev->dev->platform_data; 277 - 278 - if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 269 + if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 279 270 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 280 271 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); 281 272 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); ··· 292 291 293 292 static void omap_i2c_idle(struct omap_i2c_dev *dev) 294 293 { 295 - struct omap_i2c_bus_platform_data *pdata; 296 294 u16 iv; 297 295 298 - pdata = dev->dev->platform_data; 299 - 300 296 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 301 - if (pdata->rev == OMAP_I2C_IP_VERSION_2) 297 + if (dev->dtrev == OMAP_I2C_IP_VERSION_2) 302 298 omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1); 303 299 else 304 300 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); ··· 318 320 unsigned long timeout; 319 321 unsigned long internal_clk = 0; 320 322 struct clk *fclk; 321 - struct omap_i2c_bus_platform_data *pdata; 322 - 323 - pdata = dev->dev->platform_data; 324 323 325 324 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { 326 325 /* Disable I2C controller before soft reset */ ··· 368 373 } 369 374 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 370 375 371 - if (pdata->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { 376 + if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { 372 377 /* 373 378 * The I2C functional clock is the armxor_ck, so there's 374 379 * no need to get "armxor_ck" separately. Now, if OMAP2420 ··· 392 397 psc = fclk_rate / 12000000; 393 398 } 394 399 395 - if (!(pdata->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { 400 + if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { 396 401 397 402 /* 398 403 * HSI2C controller internal clk rate should be 19.2 Mhz for ··· 401 406 * The filter is iclk (fclk for HS) period. 402 407 */ 403 408 if (dev->speed > 400 || 404 - pdata->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) 409 + dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) 405 410 internal_clk = 19200; 406 411 else if (dev->speed > 100) 407 412 internal_clk = 9600; ··· 470 475 471 476 dev->errata = 0; 472 477 473 - if (pdata->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207) 478 + if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207) 474 479 dev->errata |= I2C_OMAP_ERRATA_I207; 475 480 476 481 /* Enable interrupts */ ··· 479 484 OMAP_I2C_IE_AL) | ((dev->fifo_size) ? 480 485 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); 481 486 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); 482 - if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 487 + if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 483 488 dev->pscstate = psc; 484 489 dev->scllstate = scll; 485 490 dev->sclhstate = sclh; ··· 799 804 u16 bits; 800 805 u16 stat, w; 801 806 int err, count = 0; 802 - struct omap_i2c_bus_platform_data *pdata; 803 - 804 - pdata = dev->dev->platform_data; 805 807 806 808 if (pm_runtime_suspended(dev->dev)) 807 809 return IRQ_NONE; ··· 822 830 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | 823 831 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); 824 832 825 - if (stat & OMAP_I2C_STAT_NACK) { 833 + if (stat & OMAP_I2C_STAT_NACK) 826 834 err |= OMAP_I2C_STAT_NACK; 827 - omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 828 - OMAP_I2C_CON_STP); 829 - } 835 + 830 836 if (stat & OMAP_I2C_STAT_AL) { 831 837 dev_err(dev->dev, "Arbitration lost\n"); 832 838 err |= OMAP_I2C_STAT_AL; ··· 865 875 * Data reg in 2430, omap3 and 866 876 * omap4 is 8 bit wide 867 877 */ 868 - if (pdata->flags & 878 + if (dev->flags & 869 879 OMAP_I2C_FLAG_16BIT_DATA_REG) { 870 880 if (dev->buf_len) { 871 881 *dev->buf++ = w >> 8; ··· 908 918 * Data reg in 2430, omap3 and 909 919 * omap4 is 8 bit wide 910 920 */ 911 - if (pdata->flags & 921 + if (dev->flags & 912 922 OMAP_I2C_FLAG_16BIT_DATA_REG) { 913 923 if (dev->buf_len) { 914 924 w |= *dev->buf++ << 8; ··· 955 965 .functionality = omap_i2c_func, 956 966 }; 957 967 968 + #ifdef CONFIG_OF 969 + static struct omap_i2c_bus_platform_data omap3_pdata = { 970 + .rev = OMAP_I2C_IP_VERSION_1, 971 + .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 972 + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | 973 + OMAP_I2C_FLAG_BUS_SHIFT_2, 974 + }; 975 + 976 + static struct omap_i2c_bus_platform_data omap4_pdata = { 977 + .rev = OMAP_I2C_IP_VERSION_2, 978 + }; 979 + 980 + static const struct of_device_id omap_i2c_of_match[] = { 981 + { 982 + .compatible = "ti,omap4-i2c", 983 + .data = &omap4_pdata, 984 + }, 985 + { 986 + .compatible = "ti,omap3-i2c", 987 + .data = &omap3_pdata, 988 + }, 989 + { }, 990 + }; 991 + MODULE_DEVICE_TABLE(of, omap_i2c_of_match); 992 + #endif 993 + 958 994 static int __devinit 959 995 omap_i2c_probe(struct platform_device *pdev) 960 996 { ··· 988 972 struct i2c_adapter *adap; 989 973 struct resource *mem, *irq, *ioarea; 990 974 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data; 975 + struct device_node *node = pdev->dev.of_node; 976 + const struct of_device_id *match; 991 977 irq_handler_t isr; 992 978 int r; 993 - u32 speed = 0; 994 979 995 980 /* NOTE: driver uses the static register mapping */ 996 981 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ··· 1018 1001 goto err_release_region; 1019 1002 } 1020 1003 1021 - if (pdata != NULL) { 1022 - speed = pdata->clkrate; 1004 + match = of_match_device(omap_i2c_of_match, &pdev->dev); 1005 + if (match) { 1006 + u32 freq = 100000; /* default to 100000 Hz */ 1007 + 1008 + pdata = match->data; 1009 + dev->dtrev = pdata->rev; 1010 + dev->flags = pdata->flags; 1011 + 1012 + of_property_read_u32(node, "clock-frequency", &freq); 1013 + /* convert DT freq value in Hz into kHz for speed */ 1014 + dev->speed = freq / 1000; 1015 + } else if (pdata != NULL) { 1016 + dev->speed = pdata->clkrate; 1017 + dev->flags = pdata->flags; 1023 1018 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; 1024 - } else { 1025 - speed = 100; /* Default speed */ 1026 - dev->set_mpu_wkup_lat = NULL; 1019 + dev->dtrev = pdata->rev; 1027 1020 } 1028 1021 1029 - dev->speed = speed; 1030 1022 dev->dev = &pdev->dev; 1031 1023 dev->irq = irq->start; 1032 1024 dev->base = ioremap(mem->start, resource_size(mem)); ··· 1046 1020 1047 1021 platform_set_drvdata(pdev, dev); 1048 1022 1049 - dev->reg_shift = (pdata->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; 1023 + dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; 1050 1024 1051 - if (pdata->rev == OMAP_I2C_IP_VERSION_2) 1025 + if (dev->dtrev == OMAP_I2C_IP_VERSION_2) 1052 1026 dev->regs = (u8 *)reg_map_ip_v2; 1053 1027 else 1054 1028 dev->regs = (u8 *)reg_map_ip_v1; ··· 1061 1035 if (dev->rev <= OMAP_I2C_REV_ON_3430) 1062 1036 dev->errata |= I2C_OMAP3_1P153; 1063 1037 1064 - if (!(pdata->flags & OMAP_I2C_FLAG_NO_FIFO)) { 1038 + if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { 1065 1039 u16 s; 1066 1040 1067 1041 /* Set up the fifo size - Get total size */ ··· 1084 1058 /* calculate wakeup latency constraint for MPU */ 1085 1059 if (dev->set_mpu_wkup_lat != NULL) 1086 1060 dev->latency = (1000000 * dev->fifo_size) / 1087 - (1000 * speed / 8); 1061 + (1000 * dev->speed / 8); 1088 1062 } 1089 1063 1090 1064 /* reset ASAP, clearing any IRQs */ ··· 1100 1074 } 1101 1075 1102 1076 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id, 1103 - pdata->rev, dev->rev >> 4, dev->rev & 0xf, dev->speed); 1077 + dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed); 1104 1078 1105 1079 pm_runtime_put(dev->dev); 1106 1080 ··· 1111 1085 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); 1112 1086 adap->algo = &omap_i2c_algo; 1113 1087 adap->dev.parent = &pdev->dev; 1088 + adap->dev.of_node = pdev->dev.of_node; 1114 1089 1115 1090 /* i2c device drivers may be active on return from add_adapter() */ 1116 1091 adap->nr = pdev->id; ··· 1120 1093 dev_err(dev->dev, "failure adding adapter\n"); 1121 1094 goto err_free_irq; 1122 1095 } 1096 + 1097 + of_i2c_register_devices(adap); 1123 1098 1124 1099 return 0; 1125 1100 ··· 1195 1166 .name = "omap_i2c", 1196 1167 .owner = THIS_MODULE, 1197 1168 .pm = OMAP_I2C_PM_OPS, 1169 + .of_match_table = of_match_ptr(omap_i2c_of_match), 1198 1170 }, 1199 1171 }; 1200 1172

Configure Feed

Configure Feed