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ARM: dts: rockchip: Enable Ethernet on rv1126 Neu2-IO

Rockchip RV1126 has GMAC 10/100/1000M ethernet controller.
Enable ethernet node on Neu2-IO board.

Co-Developed-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Link: https://lore.kernel.org/r/20230111172437.5295-4-anand@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Anand Moon and committed by
Heiko Stuebner
aa3555c5 594a76a4

+37
+37
arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts
··· 22 22 }; 23 23 }; 24 24 25 + &gmac { 26 + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 27 + <&cru CLK_GMAC_ETHERNET_OUT>; 28 + assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 29 + assigned-clock-rates = <125000000>, <0>, <25000000>; 30 + clock_in_out = "input"; 31 + phy-handle = <&phy>; 32 + phy-mode = "rgmii"; 33 + phy-supply = <&vcc_3v3>; 34 + pinctrl-names = "default"; 35 + pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 36 + tx_delay = <0x2a>; 37 + rx_delay = <0x1a>; 38 + status = "okay"; 39 + }; 40 + 41 + &mdio { 42 + phy: ethernet-phy@0 { 43 + compatible = "ethernet-phy-id001c.c916", 44 + "ethernet-phy-ieee802.3-c22"; 45 + reg = <0x0>; 46 + pinctrl-names = "default"; 47 + pinctrl-0 = <&eth_phy_rst>; 48 + reset-assert-us = <20000>; 49 + reset-deassert-us = <100000>; 50 + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; 51 + }; 52 + }; 53 + 54 + &pinctrl { 55 + ethernet { 56 + eth_phy_rst: eth-phy-rst { 57 + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; 58 + }; 59 + }; 60 + }; 61 + 25 62 &sdmmc { 26 63 bus-width = <4>; 27 64 cap-mmc-highspeed;