tjh.dev / kernel
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Merge tag 'powerpc-4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc fixes from Michael Ellerman:

- An implementation for the newly added hv_ops->flush() for the OPAL
hvc console driver backends, I forgot to apply this after merging the
hvc driver changes before the merge window.

- Enable all PCI bridges at boot on powernv, to avoid races when
multiple children of a bridge try to enable it simultaneously. This
is a workaround until the PCI core can be enhanced to fix the races.

- A fix to query PowerVM for the correct system topology at boot before
initialising sched domains, seen in some configurations to cause
broken scheduling etc.

- A fix for pte_access_permitted() on "nohash" platforms.

- Two commits to fix SIGBUS when using remap_pfn_range() seen on Power9
due to a workaround when using the nest MMU (GPUs, accelerators).

- Another fix to the VFIO code used by KVM, the previous fix had some
bugs which caused guests to not start in some configurations.

- A handful of other minor fixes.

Thanks to: Aneesh Kumar K.V, Benjamin Herrenschmidt, Christophe Leroy,
Hari Bathini, Luke Dashjr, Mahesh Salgaonkar, Nicholas Piggin, Paul
Mackerras, Srikar Dronamraju.

* tag 'powerpc-4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/mce: Fix SLB rebolting during MCE recovery path.
KVM: PPC: Book3S: Fix guest DMA when guest partially backed by THP pages
powerpc/mm/radix: Only need the Nest MMU workaround for R -> RW transition
powerpc/mm/books3s: Add new pte bit to mark pte temporarily invalid.
powerpc/nohash: fix pte_access_permitted()
powerpc/topology: Get topology for shared processors at boot
powerpc64/ftrace: Include ftrace.h needed for enable/disable calls
powerpc/powernv/pci: Work around races in PCI bridge enabling
powerpc/fadump: cleanup crash memory ranges support
powerpc/powernv: provide a console flush operation for opal hvc driver
powerpc/traps: Avoid rate limit messages from show unhandled signals
powerpc/64s: Fix PACA_IRQ_HARD_DIS accounting in idle_power4()

Linus Torvalds aa5b1054 e1dbc5a4

+173 -78
+17 -1
arch/powerpc/include/asm/book3s/64/pgtable.h
··· 44 44 45 45 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 46 46 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 47 + /* 48 + * We need to mark a pmd pte invalid while splitting. We can do that by clearing 49 + * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 50 + * differentiate between two use a SW field when invalidating. 51 + * 52 + * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 53 + * 54 + * This is used only when _PAGE_PRESENT is cleared. 55 + */ 56 + #define _PAGE_INVALID _RPAGE_SW0 47 57 48 58 /* 49 59 * Top and bottom bits of RPN which can be used by hash ··· 578 568 579 569 static inline int pte_present(pte_t pte) 580 570 { 581 - return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 571 + /* 572 + * A pte is considerent present if _PAGE_PRESENT is set. 573 + * We also need to consider the pte present which is marked 574 + * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 575 + * if we find _PAGE_PRESENT cleared. 576 + */ 577 + return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)); 582 578 } 583 579 584 580 #ifdef CONFIG_PPC_MEM_KEYS
+3 -6
arch/powerpc/include/asm/nohash/pgtable.h
··· 51 51 #define pte_access_permitted pte_access_permitted 52 52 static inline bool pte_access_permitted(pte_t pte, bool write) 53 53 { 54 - unsigned long pteval = pte_val(pte); 55 54 /* 56 55 * A read-only access is controlled by _PAGE_USER bit. 57 56 * We have _PAGE_READ set for WRITE and EXECUTE 58 57 */ 59 - unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_USER; 58 + if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 59 + return false; 60 60 61 - if (write) 62 - need_pte_bits |= _PAGE_WRITE; 63 - 64 - if ((pteval & need_pte_bits) != need_pte_bits) 61 + if (write && !pte_write(pte)) 65 62 return false; 66 63 67 64 return true;
+1
arch/powerpc/include/asm/opal.h
··· 308 308 extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 309 309 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 310 310 extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len); 311 + extern int opal_flush_chars(uint32_t vtermno, bool wait); 311 312 extern int opal_flush_console(uint32_t vtermno); 312 313 313 314 extern void hvc_opal_init_early(void);
+5
arch/powerpc/include/asm/topology.h
··· 92 92 extern int prrn_is_enabled(void); 93 93 extern int find_and_online_cpu_nid(int cpu); 94 94 extern int timed_topology_update(int nsecs); 95 + extern void __init shared_proc_topology_init(void); 95 96 #else 96 97 static inline int start_topology_update(void) 97 98 { ··· 114 113 { 115 114 return 0; 116 115 } 116 + 117 + #ifdef CONFIG_SMP 118 + static inline void shared_proc_topology_init(void) {} 119 + #endif 117 120 #endif /* CONFIG_NUMA && CONFIG_PPC_SPLPAR */ 118 121 119 122 #include <asm-generic/topology.h>
+1 -7
arch/powerpc/kernel/fadump.c
··· 34 34 #include <linux/crash_dump.h> 35 35 #include <linux/kobject.h> 36 36 #include <linux/sysfs.h> 37 + #include <linux/slab.h> 37 38 38 39 #include <asm/debugfs.h> 39 40 #include <asm/page.h> ··· 1019 1018 1020 1019 pr_debug("Setup crash memory ranges.\n"); 1021 1020 crash_mem_ranges = 0; 1022 - 1023 - /* allocate memory for crash memory ranges for the first time */ 1024 - if (!max_crash_mem_ranges) { 1025 - ret = allocate_crash_memory_ranges(); 1026 - if (ret) 1027 - return ret; 1028 - } 1029 1021 1030 1022 /* 1031 1023 * add the first memory chunk (RMA_START through boot_memory_size) as
+14 -2
arch/powerpc/kernel/idle_power4.S
··· 32 32 cmpwi 0,r4,0 33 33 beqlr 34 34 35 + /* This sequence is similar to prep_irq_for_idle() */ 36 + 35 37 /* Hard disable interrupts */ 36 38 mfmsr r7 37 39 rldicl r0,r7,48,1 ··· 43 41 /* Check if something happened while soft-disabled */ 44 42 lbz r0,PACAIRQHAPPENED(r13) 45 43 cmpwi cr0,r0,0 46 - bnelr 44 + bne- 2f 47 45 48 - /* Soft-enable interrupts */ 46 + /* 47 + * Soft-enable interrupts. This will make power4_fixup_nap return 48 + * to our caller with interrupts enabled (soft and hard). The caller 49 + * can cope with either interrupts disabled or enabled upon return. 50 + */ 49 51 #ifdef CONFIG_TRACE_IRQFLAGS 52 + /* Tell the tracer interrupts are on, because idle responds to them. */ 50 53 mflr r0 51 54 std r0,16(r1) 52 55 stdu r1,-128(r1) ··· 80 73 isync 81 74 b 1b 82 75 76 + 2: /* Return if an interrupt had happened while soft disabled */ 77 + /* Set the HARD_DIS flag because interrupts are now hard disabled */ 78 + ori r0,r0,PACA_IRQ_HARD_DIS 79 + stb r0,PACAIRQHAPPENED(r13) 80 + blr
+5
arch/powerpc/kernel/smp.c
··· 1160 1160 if (smp_ops && smp_ops->bringup_done) 1161 1161 smp_ops->bringup_done(); 1162 1162 1163 + /* 1164 + * On a shared LPAR, associativity needs to be requested. 1165 + * Hence, get numa topology before dumping cpu topology 1166 + */ 1167 + shared_proc_topology_init(); 1163 1168 dump_numa_cpu_topology(); 1164 1169 1165 1170 /*
+7 -8
arch/powerpc/kernel/traps.c
··· 315 315 info->si_addr = (void __user *)regs->nip; 316 316 } 317 317 318 - static bool show_unhandled_signals_ratelimited(void) 319 - { 320 - static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 321 - DEFAULT_RATELIMIT_BURST); 322 - return show_unhandled_signals && __ratelimit(&rs); 323 - } 324 - 325 318 static void show_signal_msg(int signr, struct pt_regs *regs, int code, 326 319 unsigned long addr) 327 320 { 328 - if (!show_unhandled_signals_ratelimited()) 321 + static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 322 + DEFAULT_RATELIMIT_BURST); 323 + 324 + if (!show_unhandled_signals) 329 325 return; 330 326 331 327 if (!unhandled_signal(current, signr)) 328 + return; 329 + 330 + if (!__ratelimit(&rs)) 332 331 return; 333 332 334 333 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
+1
arch/powerpc/kvm/book3s_hv.c
··· 46 46 #include <linux/compiler.h> 47 47 #include <linux/of.h> 48 48 49 + #include <asm/ftrace.h> 49 50 #include <asm/reg.h> 50 51 #include <asm/ppc-opcode.h> 51 52 #include <asm/asm-prototypes.h>
+10 -7
arch/powerpc/mm/mmu_context_iommu.c
··· 129 129 long i, j, ret = 0, locked_entries = 0; 130 130 unsigned int pageshift; 131 131 unsigned long flags; 132 + unsigned long cur_ua; 132 133 struct page *page = NULL; 133 134 134 135 mutex_lock(&mem_list_mutex); ··· 178 177 } 179 178 180 179 for (i = 0; i < entries; ++i) { 181 - if (1 != get_user_pages_fast(ua + (i << PAGE_SHIFT), 180 + cur_ua = ua + (i << PAGE_SHIFT); 181 + if (1 != get_user_pages_fast(cur_ua, 182 182 1/* pages */, 1/* iswrite */, &page)) { 183 183 ret = -EFAULT; 184 184 for (j = 0; j < i; ++j) ··· 198 196 if (is_migrate_cma_page(page)) { 199 197 if (mm_iommu_move_page_from_cma(page)) 200 198 goto populate; 201 - if (1 != get_user_pages_fast(ua + (i << PAGE_SHIFT), 199 + if (1 != get_user_pages_fast(cur_ua, 202 200 1/* pages */, 1/* iswrite */, 203 201 &page)) { 204 202 ret = -EFAULT; ··· 212 210 } 213 211 populate: 214 212 pageshift = PAGE_SHIFT; 215 - if (PageCompound(page)) { 213 + if (mem->pageshift > PAGE_SHIFT && PageCompound(page)) { 216 214 pte_t *pte; 217 215 struct page *head = compound_head(page); 218 216 unsigned int compshift = compound_order(head); 217 + unsigned int pteshift; 219 218 220 219 local_irq_save(flags); /* disables as well */ 221 - pte = find_linux_pte(mm->pgd, ua, NULL, &pageshift); 222 - local_irq_restore(flags); 220 + pte = find_linux_pte(mm->pgd, cur_ua, NULL, &pteshift); 223 221 224 222 /* Double check it is still the same pinned page */ 225 223 if (pte && pte_page(*pte) == head && 226 - pageshift == compshift) 227 - pageshift = max_t(unsigned int, pageshift, 224 + pteshift == compshift + PAGE_SHIFT) 225 + pageshift = max_t(unsigned int, pteshift, 228 226 PAGE_SHIFT); 227 + local_irq_restore(flags); 229 228 } 230 229 mem->pageshift = min(mem->pageshift, pageshift); 231 230 mem->hpas[i] = page_to_pfn(page) << PAGE_SHIFT;
+10 -10
arch/powerpc/mm/numa.c
··· 1078 1078 static void reset_topology_timer(void); 1079 1079 static int topology_timer_secs = 1; 1080 1080 static int topology_inited; 1081 - static int topology_update_needed; 1082 1081 1083 1082 /* 1084 1083 * Change polling interval for associativity changes. ··· 1305 1306 struct device *dev; 1306 1307 int weight, new_nid, i = 0; 1307 1308 1308 - if (!prrn_enabled && !vphn_enabled) { 1309 - if (!topology_inited) 1310 - topology_update_needed = 1; 1309 + if (!prrn_enabled && !vphn_enabled && topology_inited) 1311 1310 return 0; 1312 - } 1313 1311 1314 1312 weight = cpumask_weight(&cpu_associativity_changes_mask); 1315 1313 if (!weight) ··· 1419 1423 1420 1424 out: 1421 1425 kfree(updates); 1422 - topology_update_needed = 0; 1423 1426 return changed; 1424 1427 } 1425 1428 ··· 1546 1551 return prrn_enabled; 1547 1552 } 1548 1553 1554 + void __init shared_proc_topology_init(void) 1555 + { 1556 + if (lppaca_shared_proc(get_lppaca())) { 1557 + bitmap_fill(cpumask_bits(&cpu_associativity_changes_mask), 1558 + nr_cpumask_bits); 1559 + numa_update_cpu_topology(false); 1560 + } 1561 + } 1562 + 1549 1563 static int topology_read(struct seq_file *file, void *v) 1550 1564 { 1551 1565 if (vphn_enabled || prrn_enabled) ··· 1612 1608 return -ENOMEM; 1613 1609 1614 1610 topology_inited = 1; 1615 - if (topology_update_needed) 1616 - bitmap_fill(cpumask_bits(&cpu_associativity_changes_mask), 1617 - nr_cpumask_bits); 1618 - 1619 1611 return 0; 1620 1612 } 1621 1613 device_initcall(topology_update_init);
+5 -3
arch/powerpc/mm/pgtable-radix.c
··· 1045 1045 struct mm_struct *mm = vma->vm_mm; 1046 1046 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | 1047 1047 _PAGE_RW | _PAGE_EXEC); 1048 + 1049 + unsigned long change = pte_val(entry) ^ pte_val(*ptep); 1048 1050 /* 1049 1051 * To avoid NMMU hang while relaxing access, we need mark 1050 1052 * the pte invalid in between. 1051 1053 */ 1052 - if (atomic_read(&mm->context.copros) > 0) { 1054 + if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) { 1053 1055 unsigned long old_pte, new_pte; 1054 1056 1055 - old_pte = __radix_pte_update(ptep, ~0, 0); 1057 + old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID); 1056 1058 /* 1057 1059 * new value of pte 1058 1060 */ 1059 1061 new_pte = old_pte | set; 1060 1062 radix__flush_tlb_page_psize(mm, address, psize); 1061 - __radix_pte_update(ptep, 0, new_pte); 1063 + __radix_pte_update(ptep, _PAGE_INVALID, new_pte); 1062 1064 } else { 1063 1065 __radix_pte_update(ptep, 0, set); 1064 1066 /*
+1 -1
arch/powerpc/mm/slb.c
··· 70 70 71 71 static inline void slb_shadow_clear(enum slb_index index) 72 72 { 73 - WRITE_ONCE(get_slb_shadow()->save_area[index].esid, 0); 73 + WRITE_ONCE(get_slb_shadow()->save_area[index].esid, cpu_to_be64(index)); 74 74 } 75 75 76 76 static inline void create_shadowed_slbe(unsigned long ea, int ssize,
+54 -33
arch/powerpc/platforms/powernv/opal.c
··· 370 370 olen = cpu_to_be64(total_len); 371 371 rc = opal_console_write(vtermno, &olen, data); 372 372 if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 373 - if (rc == OPAL_BUSY_EVENT) { 374 - mdelay(OPAL_BUSY_DELAY_MS); 373 + if (rc == OPAL_BUSY_EVENT) 375 374 opal_poll_events(NULL); 376 - } else if (rc == OPAL_BUSY_EVENT) { 377 - mdelay(OPAL_BUSY_DELAY_MS); 378 - } 379 375 written = -EAGAIN; 380 376 goto out; 381 377 } ··· 397 401 if (atomic) 398 402 spin_unlock_irqrestore(&opal_write_lock, flags); 399 403 400 - /* In the -EAGAIN case, callers loop, so we have to flush the console 401 - * here in case they have interrupts off (and we don't want to wait 402 - * for async flushing if we can make immediate progress here). If 403 - * necessary the API could be made entirely non-flushing if the 404 - * callers had a ->flush API to use. 405 - */ 406 - if (written == -EAGAIN) 407 - opal_flush_console(vtermno); 408 - 409 404 return written; 410 405 } 411 406 ··· 416 429 return __opal_put_chars(vtermno, data, total_len, true); 417 430 } 418 431 419 - int opal_flush_console(uint32_t vtermno) 432 + static s64 __opal_flush_console(uint32_t vtermno) 420 433 { 421 434 s64 rc; 422 435 423 436 if (!opal_check_token(OPAL_CONSOLE_FLUSH)) { 424 437 __be64 evt; 425 438 426 - WARN_ONCE(1, "opal: OPAL_CONSOLE_FLUSH missing.\n"); 427 439 /* 428 440 * If OPAL_CONSOLE_FLUSH is not implemented in the firmware, 429 441 * the console can still be flushed by calling the polling 430 442 * function while it has OPAL_EVENT_CONSOLE_OUTPUT events. 431 443 */ 432 - do { 433 - opal_poll_events(&evt); 434 - } while (be64_to_cpu(evt) & OPAL_EVENT_CONSOLE_OUTPUT); 444 + WARN_ONCE(1, "opal: OPAL_CONSOLE_FLUSH missing.\n"); 435 445 436 - return OPAL_SUCCESS; 446 + opal_poll_events(&evt); 447 + if (!(be64_to_cpu(evt) & OPAL_EVENT_CONSOLE_OUTPUT)) 448 + return OPAL_SUCCESS; 449 + return OPAL_BUSY; 450 + 451 + } else { 452 + rc = opal_console_flush(vtermno); 453 + if (rc == OPAL_BUSY_EVENT) { 454 + opal_poll_events(NULL); 455 + rc = OPAL_BUSY; 456 + } 457 + return rc; 437 458 } 438 459 439 - do { 440 - rc = OPAL_BUSY; 441 - while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { 442 - rc = opal_console_flush(vtermno); 443 - if (rc == OPAL_BUSY_EVENT) { 444 - mdelay(OPAL_BUSY_DELAY_MS); 445 - opal_poll_events(NULL); 446 - } else if (rc == OPAL_BUSY) { 447 - mdelay(OPAL_BUSY_DELAY_MS); 448 - } 449 - } 450 - } while (rc == OPAL_PARTIAL); /* More to flush */ 460 + } 451 461 452 - return opal_error_code(rc); 462 + /* 463 + * opal_flush_console spins until the console is flushed 464 + */ 465 + int opal_flush_console(uint32_t vtermno) 466 + { 467 + for (;;) { 468 + s64 rc = __opal_flush_console(vtermno); 469 + 470 + if (rc == OPAL_BUSY || rc == OPAL_PARTIAL) { 471 + mdelay(1); 472 + continue; 473 + } 474 + 475 + return opal_error_code(rc); 476 + } 477 + } 478 + 479 + /* 480 + * opal_flush_chars is an hvc interface that sleeps until the console is 481 + * flushed if wait, otherwise it will return -EBUSY if the console has data, 482 + * -EAGAIN if it has data and some of it was flushed. 483 + */ 484 + int opal_flush_chars(uint32_t vtermno, bool wait) 485 + { 486 + for (;;) { 487 + s64 rc = __opal_flush_console(vtermno); 488 + 489 + if (rc == OPAL_BUSY || rc == OPAL_PARTIAL) { 490 + if (wait) { 491 + msleep(OPAL_BUSY_DELAY_MS); 492 + continue; 493 + } 494 + if (rc == OPAL_PARTIAL) 495 + return -EAGAIN; 496 + } 497 + 498 + return opal_error_code(rc); 499 + } 453 500 } 454 501 455 502 static int opal_recover_mce(struct pt_regs *regs,
+37
arch/powerpc/platforms/powernv/pci-ioda.c
··· 3228 3228 #endif /* CONFIG_DEBUG_FS */ 3229 3229 } 3230 3230 3231 + static void pnv_pci_enable_bridge(struct pci_bus *bus) 3232 + { 3233 + struct pci_dev *dev = bus->self; 3234 + struct pci_bus *child; 3235 + 3236 + /* Empty bus ? bail */ 3237 + if (list_empty(&bus->devices)) 3238 + return; 3239 + 3240 + /* 3241 + * If there's a bridge associated with that bus enable it. This works 3242 + * around races in the generic code if the enabling is done during 3243 + * parallel probing. This can be removed once those races have been 3244 + * fixed. 3245 + */ 3246 + if (dev) { 3247 + int rc = pci_enable_device(dev); 3248 + if (rc) 3249 + pci_err(dev, "Error enabling bridge (%d)\n", rc); 3250 + pci_set_master(dev); 3251 + } 3252 + 3253 + /* Perform the same to child busses */ 3254 + list_for_each_entry(child, &bus->children, node) 3255 + pnv_pci_enable_bridge(child); 3256 + } 3257 + 3258 + static void pnv_pci_enable_bridges(void) 3259 + { 3260 + struct pci_controller *hose; 3261 + 3262 + list_for_each_entry(hose, &hose_list, list_node) 3263 + pnv_pci_enable_bridge(hose->bus); 3264 + } 3265 + 3231 3266 static void pnv_pci_ioda_fixup(void) 3232 3267 { 3233 3268 pnv_pci_ioda_setup_PEs(); 3234 3269 pnv_pci_ioda_setup_iommu_api(); 3235 3270 pnv_pci_ioda_create_dbgfs(); 3271 + 3272 + pnv_pci_enable_bridges(); 3236 3273 3237 3274 #ifdef CONFIG_EEH 3238 3275 pnv_eeh_post_init();
+2
drivers/tty/hvc/hvc_opal.c
··· 52 52 static const struct hv_ops hvc_opal_raw_ops = { 53 53 .get_chars = opal_get_chars, 54 54 .put_chars = opal_put_chars, 55 + .flush = opal_flush_chars, 55 56 .notifier_add = notifier_add_irq, 56 57 .notifier_del = notifier_del_irq, 57 58 .notifier_hangup = notifier_hangup_irq, ··· 142 141 static const struct hv_ops hvc_opal_hvsi_ops = { 143 142 .get_chars = hvc_opal_hvsi_get_chars, 144 143 .put_chars = hvc_opal_hvsi_put_chars, 144 + .flush = opal_flush_chars, 145 145 .notifier_add = hvc_opal_hvsi_open, 146 146 .notifier_del = hvc_opal_hvsi_close, 147 147 .notifier_hangup = hvc_opal_hvsi_hangup,