Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'rtw-next-2026-04-02' of https://github.com/pkshih/rtw into wireless-next
Ping-Ke Shih says:
==================
rtw-next patches for -next
Improve MLO and some random fixes. Notable changes are:
* drop usb device reference across drivers
rtw89:
* add RTL8922DE but not enabled yet, because BT coexistence is still
cooking.
* add USB RX aggregation to improve performance.
* add USB TX flow control by tracking in-flight URBs.
==================
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+5192
-415
-4
drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c
-4
drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c
···
1475
1475
usb_set_intfdata(intf, dev);
1476
1476
priv->udev = udev;
1477
1477
1478
-
usb_get_dev(udev);
1479
-
1480
1478
skb_queue_head_init(&priv->rx_queue);
1481
1479
1482
1480
BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
···
1661
1663
err_free_dmabuf:
1662
1664
kfree(priv->io_dmabuf);
1663
1665
usb_set_intfdata(intf, NULL);
1664
-
usb_put_dev(udev);
1665
1666
err_free_dev:
1666
1667
ieee80211_free_hw(dev);
1667
1668
return err;
···
1682
1685
1683
1686
priv = dev->priv;
1684
1687
usb_reset_device(priv->udev);
1685
-
usb_put_dev(interface_to_usbdev(intf));
1686
1688
kfree(priv->io_dmabuf);
1687
1689
ieee80211_free_hw(dev);
1688
1690
}
+12
-28
drivers/net/wireless/realtek/rtl8xxxu/core.c
+12
-28
drivers/net/wireless/realtek/rtl8xxxu/core.c
···
4697
4697
{.bitrate = 540, .hw_value = 0x0b,},
4698
4698
};
4699
4699
4700
-
static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss)
4701
-
{
4702
-
if (rate <= DESC_RATE_54M)
4703
-
return;
4704
-
4705
-
if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {
4706
-
if (rate < DESC_RATE_MCS8)
4707
-
*nss = 1;
4708
-
else
4709
-
*nss = 2;
4710
-
*mcs = rate - DESC_RATE_MCS0;
4711
-
}
4712
-
}
4713
-
4714
4700
static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4715
4701
{
4716
4702
struct ieee80211_hw *hw = priv->hw;
···
4806
4820
void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt,
4807
4821
u8 rate, u8 sgi, u8 bw)
4808
4822
{
4809
-
u8 mcs, nss;
4810
-
4811
4823
rarpt->txrate.flags = 0;
4812
4824
4813
4825
if (rate <= DESC_RATE_54M) {
4814
4826
rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate;
4815
-
} else {
4816
-
rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss);
4827
+
} else if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {
4817
4828
rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS;
4829
+
if (rate < DESC_RATE_MCS8)
4830
+
rarpt->txrate.nss = 1;
4831
+
else
4832
+
rarpt->txrate.nss = 2;
4818
4833
4819
-
rarpt->txrate.mcs = mcs;
4820
-
rarpt->txrate.nss = nss;
4834
+
rarpt->txrate.mcs = rate - DESC_RATE_MCS0;
4821
4835
4822
4836
if (sgi)
4823
4837
rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
4824
4838
4825
4839
rarpt->txrate.bw = bw;
4840
+
} else {
4841
+
return;
4826
4842
}
4827
4843
4828
4844
rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);
···
7686
7698
int ret;
7687
7699
int untested = 1;
7688
7700
7689
-
udev = usb_get_dev(interface_to_usbdev(interface));
7701
+
udev = interface_to_usbdev(interface);
7690
7702
7691
7703
switch (id->idVendor) {
7692
7704
case USB_VENDOR_ID_REALTEK:
7693
7705
switch(id->idProduct) {
7706
+
case 0x0179:
7694
7707
case 0x1724:
7695
7708
case 0x8176:
7696
7709
case 0x8178:
···
7745
7756
}
7746
7757
7747
7758
hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7748
-
if (!hw) {
7749
-
ret = -ENOMEM;
7750
-
goto err_put_dev;
7751
-
}
7759
+
if (!hw)
7760
+
return -ENOMEM;
7752
7761
7753
7762
priv = hw->priv;
7754
7763
priv->hw = hw;
···
7888
7901
mutex_destroy(&priv->h2c_mutex);
7889
7902
7890
7903
ieee80211_free_hw(hw);
7891
-
err_put_dev:
7892
-
usb_put_dev(udev);
7893
7904
7894
7905
return ret;
7895
7906
}
···
7920
7935
"Device still attached, trying to reset\n");
7921
7936
usb_reset_device(priv->udev);
7922
7937
}
7923
-
usb_put_dev(priv->udev);
7924
7938
ieee80211_free_hw(hw);
7925
7939
}
7926
7940
+1
drivers/net/wireless/realtek/rtlwifi/pci.c
+1
drivers/net/wireless/realtek/rtlwifi/pci.c
+6
-6
drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c
+6
-6
drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c
···
212
212
struct rtl_priv *rtlpriv = rtl_priv(hw);
213
213
u8 boxcontent[4], boxextcontent[2];
214
214
u16 box_reg = 0, box_extreg = 0;
215
-
u8 wait_writeh2c_limmit = 100;
215
+
u8 wait_writeh2c_limit = 100;
216
216
bool bwrite_success = false;
217
-
u8 wait_h2c_limmit = 100;
217
+
u8 wait_h2c_limit = 100;
218
218
u32 h2c_waitcounter = 0;
219
219
bool isfw_read = false;
220
220
unsigned long flag;
···
261
261
}
262
262
263
263
while (!bwrite_success) {
264
-
wait_writeh2c_limmit--;
265
-
if (wait_writeh2c_limmit == 0) {
264
+
wait_writeh2c_limit--;
265
+
if (wait_writeh2c_limit == 0) {
266
266
pr_err("Write H2C fail because no trigger for FW INT!\n");
267
267
break;
268
268
}
···
278
278
279
279
isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
280
280
while (!isfw_read) {
281
-
wait_h2c_limmit--;
282
-
if (wait_h2c_limmit == 0) {
281
+
wait_h2c_limit--;
282
+
if (wait_h2c_limit == 0) {
283
283
rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
284
284
"Waiting too long for FW read clear HMEBox(%d)!\n",
285
285
boxnum);
-4
drivers/net/wireless/realtek/rtlwifi/usb.c
-4
drivers/net/wireless/realtek/rtlwifi/usb.c
···
986
986
init_completion(&rtlpriv->firmware_loading_complete);
987
987
SET_IEEE80211_DEV(hw, &intf->dev);
988
988
udev = interface_to_usbdev(intf);
989
-
usb_get_dev(udev);
990
989
usb_priv = rtl_usbpriv(hw);
991
990
memset(usb_priv, 0, sizeof(*usb_priv));
992
991
usb_priv->dev.intf = intf;
···
1037
1038
rtl_deinit_core(hw);
1038
1039
error_out2:
1039
1040
_rtl_usb_io_handler_release(hw);
1040
-
usb_put_dev(udev);
1041
1041
kfree(rtlpriv->usb_data);
1042
1042
ieee80211_free_hw(hw);
1043
1043
return -ENODEV;
···
1048
1050
struct ieee80211_hw *hw = usb_get_intfdata(intf);
1049
1051
struct rtl_priv *rtlpriv = rtl_priv(hw);
1050
1052
struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1051
-
struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1052
1053
1053
1054
if (unlikely(!rtlpriv))
1054
1055
return;
···
1069
1072
kfree(rtlpriv->usb_data);
1070
1073
rtlpriv->cfg->ops->deinit_sw_vars(hw);
1071
1074
_rtl_usb_io_handler_release(hw);
1072
-
usb_put_dev(rtlusb->udev);
1073
1075
usb_set_intfdata(intf, NULL);
1074
1076
ieee80211_free_hw(hw);
1075
1077
}
+32
-15
drivers/net/wireless/realtek/rtw88/coex.c
+32
-15
drivers/net/wireless/realtek/rtw88/coex.c
···
485
485
"[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
486
486
coex_stat->hi_pri_rx, coex_stat->hi_pri_tx,
487
487
coex_stat->lo_pri_rx, coex_stat->lo_pri_tx);
488
+
489
+
if (coex_stat->wl_under_lps || coex_stat->wl_under_ips ||
490
+
(coex_stat->hi_pri_rx > 60000 && coex_stat->hi_pri_tx == 60000 &&
491
+
coex_stat->lo_pri_rx > 60000 && coex_stat->lo_pri_tx == 60000))
492
+
coex_stat->bt_ctr_ok = false;
493
+
else
494
+
coex_stat->bt_ctr_ok = true;
488
495
}
489
496
490
497
static void rtw_coex_monitor_bt_enable(struct rtw_dev *rtwdev)
···
1966
1959
struct rtw_coex *coex = &rtwdev->coex;
1967
1960
struct rtw_coex_stat *coex_stat = &coex->stat;
1968
1961
struct rtw_efuse *efuse = &rtwdev->efuse;
1962
+
bool is_bt_ctr_hi = false, is_toggle_table = false;
1969
1963
u8 table_case, tdma_case;
1970
1964
u32 slot_type = 0;
1971
-
bool bt_multi_link_remain = false, is_toggle_table = false;
1972
1965
1973
1966
rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], %s()\n", __func__);
1974
1967
rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
1975
1968
rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1969
+
1970
+
if (coex_stat->bt_ctr_ok &&
1971
+
coex_stat->lo_pri_rx + coex_stat->lo_pri_tx > 360)
1972
+
is_bt_ctr_hi = true;
1976
1973
1977
1974
if (efuse->share_ant) {
1978
1975
/* Shared-Ant */
···
1991
1980
}
1992
1981
} else {
1993
1982
/* Legacy HID */
1994
-
if (coex_stat->bt_profile_num == 1 &&
1995
-
(coex_stat->bt_multi_link ||
1996
-
(coex_stat->lo_pri_rx +
1997
-
coex_stat->lo_pri_tx > 360) ||
1998
-
coex_stat->bt_slave ||
1999
-
bt_multi_link_remain)) {
2000
-
slot_type = TDMA_4SLOT;
2001
-
table_case = 12;
2002
-
tdma_case = 20;
2003
-
} else if (coex_stat->bt_a2dp_active) {
1983
+
if (coex_stat->bt_a2dp_active) {
2004
1984
table_case = 9;
2005
1985
tdma_case = 18;
1986
+
} else if (coex_stat->bt_profile_num == 1 &&
1987
+
(coex_stat->bt_multi_link &&
1988
+
(is_bt_ctr_hi || coex_stat->bt_slave ||
1989
+
coex_stat->bt_multi_link_remain))) {
1990
+
if (coex_stat->wl_gl_busy &&
1991
+
(coex_stat->wl_rx_rate <= 3 ||
1992
+
coex_stat->wl_rts_rx_rate <= 3))
1993
+
table_case = 13;
1994
+
else
1995
+
table_case = 12;
1996
+
1997
+
tdma_case = 26;
2006
1998
} else if (coex_stat->bt_418_hid_exist &&
2007
1999
coex_stat->wl_gl_busy) {
2008
2000
is_toggle_table = true;
2009
2001
slot_type = TDMA_4SLOT;
2010
-
table_case = 9;
2011
-
tdma_case = 24;
2002
+
table_case = 32;
2003
+
tdma_case = 27;
2012
2004
} else if (coex_stat->bt_ble_hid_exist &&
2013
2005
coex_stat->wl_gl_busy) {
2014
-
table_case = 32;
2015
-
tdma_case = 9;
2006
+
table_case = 36;
2007
+
tdma_case = 0;
2016
2008
} else {
2017
2009
table_case = 9;
2018
2010
tdma_case = 9;
···
3108
3094
3109
3095
for (i = 0; i < COEX_BTINFO_LENGTH; i++)
3110
3096
coex_stat->bt_info_c2h[rsp_source][i] = buf[i];
3097
+
3098
+
if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
3099
+
coex_stat->bt_info_c2h[rsp_source][5] = 0;
3111
3100
3112
3101
/* get the same info from bt, skip it */
3113
3102
if (coex_stat->bt_info_c2h[rsp_source][1] == coex_stat->bt_info_lb2 &&
+6
drivers/net/wireless/realtek/rtw88/main.c
+6
drivers/net/wireless/realtek/rtw88/main.c
···
1805
1805
{
1806
1806
struct rtw_fw_state *fw = context;
1807
1807
struct rtw_dev *rtwdev = fw->rtwdev;
1808
+
struct wiphy *wiphy = rtwdev->hw->wiphy;
1808
1809
1809
1810
if (!firmware || !firmware->data) {
1810
1811
rtw_err(rtwdev, "failed to request firmware\n");
···
1820
1819
rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n",
1821
1820
fw->type == RTW_WOWLAN_FW ? "WOW " : "",
1822
1821
fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1822
+
1823
+
if (fw->type == RTW_NORMAL_FW)
1824
+
snprintf(wiphy->fw_version, sizeof(wiphy->fw_version),
1825
+
"%u.%u.%u",
1826
+
fw->version, fw->sub_version, fw->sub_index);
1823
1827
}
1824
1828
1825
1829
static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
+6
drivers/net/wireless/realtek/rtw88/main.h
+6
drivers/net/wireless/realtek/rtw88/main.h
···
432
432
RTW_WOW_FLAG_MAX,
433
433
};
434
434
435
+
enum rtw_quirk_dis_caps {
436
+
QUIRK_DIS_CAP_PCI_ASPM,
437
+
QUIRK_DIS_CAP_LPS_DEEP,
438
+
};
439
+
435
440
/* the power index is represented by differences, which cck-1s & ht40-1s are
436
441
* the base values, so for 1s's differences, there are only ht20 & ofdm
437
442
*/
···
1480
1475
bool bt_game_hid_exist;
1481
1476
bool bt_hid_handle_cnt;
1482
1477
bool bt_mailbox_reply;
1478
+
bool bt_ctr_ok;
1483
1479
1484
1480
bool wl_under_lps;
1485
1481
bool wl_under_ips;
+33
-1
drivers/net/wireless/realtek/rtw88/pci.c
+33
-1
drivers/net/wireless/realtek/rtw88/pci.c
···
2
2
/* Copyright(c) 2018-2019 Realtek Corporation
3
3
*/
4
4
5
+
#include <linux/dmi.h>
5
6
#include <linux/module.h>
6
7
#include <linux/pci.h>
7
8
#include "main.h"
···
1745
1744
};
1746
1745
EXPORT_SYMBOL(rtw_pci_err_handler);
1747
1746
1747
+
static int rtw_pci_disable_caps(const struct dmi_system_id *dmi)
1748
+
{
1749
+
uintptr_t dis_caps = (uintptr_t)dmi->driver_data;
1750
+
1751
+
if (dis_caps & BIT(QUIRK_DIS_CAP_PCI_ASPM))
1752
+
rtw_pci_disable_aspm = true;
1753
+
1754
+
if (dis_caps & BIT(QUIRK_DIS_CAP_LPS_DEEP))
1755
+
rtw_disable_lps_deep_mode = true;
1756
+
1757
+
return 1;
1758
+
}
1759
+
1760
+
static const struct dmi_system_id rtw_pci_quirks[] = {
1761
+
{
1762
+
.callback = rtw_pci_disable_caps,
1763
+
.ident = "HP Notebook - P3S95EA#ACB",
1764
+
.matches = {
1765
+
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1766
+
DMI_MATCH(DMI_PRODUCT_NAME, "HP Notebook"),
1767
+
DMI_MATCH(DMI_PRODUCT_SKU, "P3S95EA#ACB"),
1768
+
},
1769
+
.driver_data = (void *)(BIT(QUIRK_DIS_CAP_PCI_ASPM) |
1770
+
BIT(QUIRK_DIS_CAP_LPS_DEEP)),
1771
+
},
1772
+
{}
1773
+
};
1774
+
1748
1775
int rtw_pci_probe(struct pci_dev *pdev,
1749
1776
const struct pci_device_id *id)
1750
1777
{
···
1799
1770
1800
1771
rtwpci = (struct rtw_pci *)rtwdev->priv;
1801
1772
atomic_set(&rtwpci->link_usage, 1);
1773
+
1774
+
dmi_check_system(rtw_pci_quirks);
1802
1775
1803
1776
ret = rtw_core_init(rtwdev);
1804
1777
if (ret)
···
1835
1804
}
1836
1805
1837
1806
/* Disable PCIe ASPM L1 while doing NAPI poll for 8821CE */
1838
-
if (rtwdev->chip->id == RTW_CHIP_TYPE_8821C && bridge->vendor == PCI_VENDOR_ID_INTEL)
1807
+
if (rtwdev->chip->id == RTW_CHIP_TYPE_8821C &&
1808
+
bridge && bridge->vendor == PCI_VENDOR_ID_INTEL)
1839
1809
rtwpci->rx_no_aspm = true;
1840
1810
1841
1811
rtw_pci_phy_cfg(rtwdev);
+5
drivers/net/wireless/realtek/rtw88/rtw8703b.c
+5
drivers/net/wireless/realtek/rtw88/rtw8703b.c
···
1794
1794
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1795
1795
{0xffffffff, 0x5aaa5aaa},
1796
1796
{0x56555555, 0x5a5a5aaa},
1797
+
{0xdaffdaff, 0xdaffdaff},
1798
+
{0xddffddff, 0xddffddff},
1799
+
{0xe5555555, 0xe5555555}, /* case-35 */
1800
+
{0xea5a5a5a, 0xea5a5a5a},
1801
+
{0xea6a6a6a, 0xea6a6a6a},
1797
1802
};
1798
1803
1799
1804
/* Shared-Antenna TDMA */
+5
drivers/net/wireless/realtek/rtw88/rtw8723d.c
+5
drivers/net/wireless/realtek/rtw88/rtw8723d.c
···
1459
1459
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1460
1460
{0xffffffff, 0x5aaa5aaa},
1461
1461
{0x56555555, 0x5a5a5aaa},
1462
+
{0xdaffdaff, 0xdaffdaff},
1463
+
{0xddffddff, 0xddffddff},
1464
+
{0xe5555555, 0xe5555555}, /* case-35 */
1465
+
{0xea5a5a5a, 0xea5a5a5a},
1466
+
{0xea6a6a6a, 0xea6a6a6a},
1462
1467
};
1463
1468
1464
1469
/* Non-Shared-Antenna Coex Table */
+6
-1
drivers/net/wireless/realtek/rtw88/rtw8821a.c
+6
-1
drivers/net/wireless/realtek/rtw88/rtw8821a.c
···
998
998
{0x66556655, 0x66556655},
999
999
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1000
1000
{0xffffffff, 0x5aaa5aaa},
1001
-
{0x56555555, 0x5a5a5aaa}
1001
+
{0x56555555, 0x5a5a5aaa},
1002
+
{0xdaffdaff, 0xdaffdaff},
1003
+
{0xddffddff, 0xddffddff},
1004
+
{0xe5555555, 0xe5555555}, /* case-35 */
1005
+
{0xea5a5a5a, 0xea5a5a5a},
1006
+
{0xea6a6a6a, 0xea6a6a6a},
1002
1007
};
1003
1008
1004
1009
/* Non-Shared-Antenna Coex Table */
+6
-1
drivers/net/wireless/realtek/rtw88/rtw8821c.c
+6
-1
drivers/net/wireless/realtek/rtw88/rtw8821c.c
···
1727
1727
{0x66556655, 0x66556655},
1728
1728
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1729
1729
{0xffffffff, 0x5aaa5aaa},
1730
-
{0x56555555, 0x5a5a5aaa}
1730
+
{0x56555555, 0x5a5a5aaa},
1731
+
{0xdaffdaff, 0xdaffdaff},
1732
+
{0xddffddff, 0xddffddff},
1733
+
{0xe5555555, 0xe5555555}, /* case-35 */
1734
+
{0xea5a5a5a, 0xea5a5a5a},
1735
+
{0xea6a6a6a, 0xea6a6a6a},
1731
1736
};
1732
1737
1733
1738
/* Non-Shared-Antenna Coex Table */
+5
drivers/net/wireless/realtek/rtw88/rtw8822b.c
+5
drivers/net/wireless/realtek/rtw88/rtw8822b.c
···
2217
2217
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2218
2218
{0xffffffff, 0x5aaa5aaa},
2219
2219
{0x56555555, 0x5a5a5aaa},
2220
+
{0xdaffdaff, 0xdaffdaff},
2221
+
{0xddffddff, 0xddffddff},
2222
+
{0xe5555555, 0xe5555555}, /* case-35 */
2223
+
{0xea5a5a5a, 0xea5a5a5a},
2224
+
{0xea6a6a6a, 0xea6a6a6a},
2220
2225
};
2221
2226
2222
2227
/* Non-Shared-Antenna Coex Table */
+4
-1
drivers/net/wireless/realtek/rtw88/rtw8822c.c
+4
-1
drivers/net/wireless/realtek/rtw88/rtw8822c.c
···
5035
5035
{0x56555555, 0x5a5a5aaa},
5036
5036
{0xdaffdaff, 0xdaffdaff},
5037
5037
{0xddffddff, 0xddffddff},
5038
+
{0xe5555555, 0xe5555555}, /* case-35 */
5039
+
{0xea5a5a5a, 0xea5a5a5a},
5040
+
{0xea6a6a6a, 0xea6a6a6a},
5038
5041
};
5039
5042
5040
5043
/* Non-Shared-Antenna Coex Table */
···
5404
5401
.max_sched_scan_ssids = 4,
5405
5402
#endif
5406
5403
.max_scan_ie_len = (RTW_PROBE_PG_CNT - 1) * TX_PAGE_SIZE,
5407
-
.coex_para_ver = 0x22020720,
5404
+
.coex_para_ver = 0x26020420,
5408
5405
.bt_desired_ver = 0x20,
5409
5406
.scbd_support = true,
5410
5407
.new_scbd10_def = true,
+8
drivers/net/wireless/realtek/rtw88/rx.c
+8
drivers/net/wireless/realtek/rtw88/rx.c
···
295
295
296
296
pkt_stat->tsf_low = le32_get_bits(rx_desc->w5, RTW_RX_DESC_W5_TSFL);
297
297
298
+
if (unlikely(pkt_stat->rate >= DESC_RATE_MAX)) {
299
+
rtw_dbg(rtwdev, RTW_DBG_UNEXP,
300
+
"unexpected RX rate=0x%x\n", pkt_stat->rate);
301
+
302
+
pkt_stat->rate = DESC_RATE1M;
303
+
pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
304
+
}
305
+
298
306
/* drv_info_sz is in unit of 8-bytes */
299
307
pkt_stat->drv_info_sz *= 8;
300
308
+1
-1
drivers/net/wireless/realtek/rtw88/tx.c
+1
-1
drivers/net/wireless/realtek/rtw88/tx.c
···
421
421
pkt_info->mac_id = rtwvif->mac_id;
422
422
}
423
423
424
-
if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
424
+
if (ieee80211_is_mgmt(fc) || ieee80211_is_any_nullfunc(fc))
425
425
rtw_tx_mgmt_pkt_info_update(rtwdev, pkt_info, sta, skb);
426
426
else if (ieee80211_is_data(fc))
427
427
rtw_tx_data_pkt_info_update(rtwdev, pkt_info, sta, skb);
+1
-2
drivers/net/wireless/realtek/rtw88/usb.c
+1
-2
drivers/net/wireless/realtek/rtw88/usb.c
···
1041
1041
struct usb_interface *intf)
1042
1042
{
1043
1043
struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
1044
-
struct usb_device *udev = usb_get_dev(interface_to_usbdev(intf));
1044
+
struct usb_device *udev = interface_to_usbdev(intf);
1045
1045
int ret;
1046
1046
1047
1047
rtwusb->udev = udev;
···
1067
1067
{
1068
1068
struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
1069
1069
1070
-
usb_put_dev(rtwusb->udev);
1071
1070
kfree(rtwusb->usb_data);
1072
1071
usb_set_intfdata(intf, NULL);
1073
1072
}
+41
-31
drivers/net/wireless/realtek/rtw89/chan.c
+41
-31
drivers/net/wireless/realtek/rtw89/chan.c
···
276
276
}
277
277
278
278
hal->roc_chandef = *chandef;
279
-
hal->roc_link_index = rtw89_vif_link_inst_get_index(rtwvif_link);
280
279
} else {
281
280
cur = atomic_cmpxchg(&hal->roc_chanctx_idx, idx,
282
281
RTW89_CHANCTX_IDLE);
···
381
382
rtw89_swap_chanctx(rtwdev, rtwvif_link->chanctx_idx, cur->chanctx_idx);
382
383
}
383
384
385
+
static u8 rtw89_entity_role_get_index(struct rtw89_dev *rtwdev)
386
+
{
387
+
enum rtw89_entity_mode mode;
388
+
389
+
mode = rtw89_get_entity_mode(rtwdev);
390
+
switch (mode) {
391
+
default:
392
+
WARN(1, "Invalid ent mode: %d\n", mode);
393
+
fallthrough;
394
+
case RTW89_ENTITY_MODE_SCC_OR_SMLD:
395
+
case RTW89_ENTITY_MODE_MCC:
396
+
return 0;
397
+
case RTW89_ENTITY_MODE_MCC_PREPARE:
398
+
return 1;
399
+
}
400
+
}
401
+
384
402
const struct rtw89_chan *__rtw89_mgnt_chan_get(struct rtw89_dev *rtwdev,
385
403
const char *caller_message,
386
404
u8 link_index, bool nullchk)
···
405
389
struct rtw89_hal *hal = &rtwdev->hal;
406
390
struct rtw89_entity_mgnt *mgnt = &hal->entity_mgnt;
407
391
enum rtw89_chanctx_idx chanctx_idx;
408
-
enum rtw89_chanctx_idx roc_idx;
409
-
enum rtw89_entity_mode mode;
410
392
u8 role_index;
411
393
412
394
lockdep_assert_wiphy(rtwdev->hw->wiphy);
···
415
401
goto dflt;
416
402
}
417
403
418
-
mode = rtw89_get_entity_mode(rtwdev);
419
-
switch (mode) {
420
-
case RTW89_ENTITY_MODE_SCC_OR_SMLD:
421
-
case RTW89_ENTITY_MODE_MCC:
422
-
role_index = 0;
423
-
break;
424
-
case RTW89_ENTITY_MODE_MCC_PREPARE:
425
-
role_index = 1;
426
-
break;
427
-
default:
428
-
WARN(1, "Invalid ent mode: %d\n", mode);
429
-
goto dflt;
430
-
}
404
+
role_index = rtw89_entity_role_get_index(rtwdev);
431
405
432
406
chanctx_idx = mgnt->chanctx_tbl[role_index][link_index];
433
407
if (chanctx_idx == RTW89_CHANCTX_IDLE)
434
408
goto dflt;
435
-
436
-
roc_idx = atomic_read(&hal->roc_chanctx_idx);
437
-
if (roc_idx != RTW89_CHANCTX_IDLE) {
438
-
/* ROC is ongoing (given ROC runs on @hal->roc_link_index).
439
-
* If @link_index is the same, get the ongoing ROC chanctx.
440
-
*/
441
-
if (link_index == hal->roc_link_index)
442
-
chanctx_idx = roc_idx;
443
-
}
444
409
445
410
return rtw89_chan_get(rtwdev, chanctx_idx);
446
411
···
483
490
}
484
491
}
485
492
486
-
static
487
-
void rtw89_entity_recalc_mlo_dbcc_mode(struct rtw89_dev *rtwdev, u8 active_hws)
493
+
static void rtw89_entity_recalc_mlo_dbcc_mode(struct rtw89_dev *rtwdev)
488
494
{
495
+
struct rtw89_entity_mgnt *mgnt = &rtwdev->hal.entity_mgnt;
489
496
enum rtw89_mlo_dbcc_mode mode;
497
+
struct rtw89_vif *role;
498
+
u8 active_hws = 0;
499
+
u8 ridx;
500
+
501
+
ridx = rtw89_entity_role_get_index(rtwdev);
502
+
role = mgnt->active_roles[ridx];
503
+
if (role) {
504
+
struct rtw89_vif_link *link;
505
+
int i;
506
+
507
+
for (i = 0; i < role->links_inst_valid_num; i++) {
508
+
link = rtw89_vif_get_link_inst(role, i);
509
+
if (!link || !link->chanctx_assigned)
510
+
continue;
511
+
512
+
active_hws |= BIT(i);
513
+
}
514
+
}
490
515
491
516
mode = rtw89_entity_sel_mlo_dbcc_mode(rtwdev, active_hws);
492
517
rtwdev->mlo_dbcc_mode = mode;
···
518
507
struct rtw89_entity_mgnt *mgnt = &hal->entity_mgnt;
519
508
struct rtw89_vif_link *link;
520
509
struct rtw89_vif *role;
521
-
u8 active_hws = 0;
522
510
u8 pos = 0;
523
511
int i, j;
524
512
···
566
556
continue;
567
557
568
558
mgnt->chanctx_tbl[pos][i] = link->chanctx_idx;
569
-
active_hws |= BIT(i);
570
559
}
571
560
572
561
mgnt->active_roles[pos++] = role;
573
562
}
574
-
575
-
rtw89_entity_recalc_mlo_dbcc_mode(rtwdev, active_hws);
576
563
}
577
564
578
565
enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev)
···
639
632
return rtw89_get_entity_mode(rtwdev);
640
633
641
634
rtw89_set_entity_mode(rtwdev, mode);
635
+
636
+
rtw89_entity_recalc_mlo_dbcc_mode(rtwdev);
637
+
642
638
return mode;
643
639
}
644
640
+149
-6
drivers/net/wireless/realtek/rtw89/core.c
+149
-6
drivers/net/wireless/realtek/rtw89/core.c
···
463
463
chan = rtw89_mgnt_chan_get(rtwdev, 0);
464
464
__rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0);
465
465
466
-
if (!rtwdev->support_mlo)
466
+
if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
467
467
return;
468
468
469
469
chan = rtw89_mgnt_chan_get(rtwdev, 1);
···
558
558
chan = rtw89_mgnt_chan_get(rtwdev, 0);
559
559
__rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0);
560
560
561
-
if (!rtwdev->support_mlo)
561
+
if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
562
562
return 0;
563
563
564
564
chan = rtw89_mgnt_chan_get(rtwdev, 1);
···
3203
3203
u8 *variable;
3204
3204
int chan;
3205
3205
3206
-
if (!rtwdev->chip->rx_freq_frome_ie)
3206
+
if (!rtwdev->chip->rx_freq_from_ie)
3207
3207
return;
3208
3208
3209
3209
if (!rtwdev->scanning)
···
3270
3270
3271
3271
out:
3272
3272
rcu_read_unlock();
3273
+
}
3274
+
3275
+
static void __rtw89_core_tid_rx_stats_reset(struct rtw89_tid_stats *tid_stats)
3276
+
{
3277
+
tid_stats->last_pn = -1LL;
3278
+
tid_stats->last_sn = IEEE80211_SN_MASK;
3279
+
}
3280
+
3281
+
void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3282
+
struct ieee80211_ampdu_params *params, bool enable)
3283
+
{
3284
+
struct rtw89_tid_stats *tid_stats;
3285
+
u16 tid = params->tid;
3286
+
3287
+
tid_stats = &rtwsta->tid_rx_stats[tid];
3288
+
3289
+
if (enable) {
3290
+
__rtw89_core_tid_rx_stats_reset(tid_stats);
3291
+
tid_stats->started = true;
3292
+
} else {
3293
+
tid_stats->started = false;
3294
+
}
3295
+
}
3296
+
3297
+
void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev)
3298
+
{
3299
+
struct rtw89_tid_stats *tid_stats;
3300
+
struct ieee80211_sta *sta;
3301
+
struct rtw89_sta *rtwsta;
3302
+
u16 tid;
3303
+
3304
+
for_each_station(sta, rtwdev->hw) {
3305
+
rtwsta = sta_to_rtwsta(sta);
3306
+
3307
+
for (tid = 0; tid < IEEE80211_NUM_TIDS; tid++) {
3308
+
tid_stats = &rtwsta->tid_rx_stats[tid];
3309
+
3310
+
if (!tid_stats->started)
3311
+
continue;
3312
+
3313
+
__rtw89_core_tid_rx_stats_reset(tid_stats);
3314
+
}
3315
+
}
3316
+
}
3317
+
3318
+
static bool rtw89_core_skb_pn_valid(struct rtw89_dev *rtwdev,
3319
+
struct rtw89_rx_desc_info *desc_info,
3320
+
struct sk_buff *skb)
3321
+
{
3322
+
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3323
+
const struct rtw89_chip_info *chip = rtwdev->chip;
3324
+
struct rtw89_sta_link *rtwsta_link;
3325
+
struct rtw89_tid_stats *tid_stats;
3326
+
struct rtw89_sta *rtwsta;
3327
+
u8 tid, *ccmp_hdr_ptr;
3328
+
s64 pn, last_pn;
3329
+
u16 mpdu_sn;
3330
+
int hdrlen;
3331
+
3332
+
if (chip->chip_gen != RTW89_CHIP_AX)
3333
+
return true;
3334
+
3335
+
if (!ieee80211_is_data_qos(hdr->frame_control))
3336
+
return true;
3337
+
3338
+
if (!desc_info->hw_dec || !desc_info->addr1_match)
3339
+
return true;
3340
+
3341
+
guard(rcu)();
3342
+
3343
+
rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, desc_info->mac_id);
3344
+
if (!rtwsta_link)
3345
+
return true;
3346
+
3347
+
rtwsta = rtwsta_link->rtwsta;
3348
+
tid = ieee80211_get_tid(hdr);
3349
+
tid_stats = &rtwsta->tid_rx_stats[tid];
3350
+
3351
+
if (!tid_stats->started)
3352
+
return true;
3353
+
3354
+
switch (desc_info->sec_type) {
3355
+
case RTW89_SEC_KEY_TYPE_CCMP128:
3356
+
case RTW89_SEC_KEY_TYPE_CCMP256:
3357
+
case RTW89_SEC_KEY_TYPE_GCMP128:
3358
+
case RTW89_SEC_KEY_TYPE_GCMP256:
3359
+
mpdu_sn = ieee80211_get_sn(hdr);
3360
+
hdrlen = ieee80211_hdrlen(hdr->frame_control);
3361
+
ccmp_hdr_ptr = skb->data + hdrlen;
3362
+
ccmp_hdr2pn(&pn, ccmp_hdr_ptr);
3363
+
last_pn = tid_stats->last_pn;
3364
+
3365
+
if (pn > last_pn) {
3366
+
if (ieee80211_sn_less(mpdu_sn, tid_stats->last_sn)) {
3367
+
dev_kfree_skb_any(skb);
3368
+
3369
+
return false;
3370
+
}
3371
+
3372
+
tid_stats->last_sn = mpdu_sn;
3373
+
tid_stats->last_pn = pn;
3374
+
}
3375
+
break;
3376
+
default:
3377
+
break;
3378
+
}
3379
+
3380
+
return true;
3273
3381
}
3274
3382
3275
3383
static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
···
3529
3421
desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
3530
3422
desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
3531
3423
desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
3424
+
desc_info->sec_type = le32_get_bits(rxd_l->dword7, AX_RXD_SEC_TYPE_MASK);
3532
3425
}
3533
3426
EXPORT_SYMBOL(rtw89_core_query_rxdesc);
3534
3427
···
3559
3450
desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
3560
3451
desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
3561
3452
3453
+
desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK);
3562
3454
desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
3563
3455
desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
3564
3456
desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
···
3633
3523
desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_V1);
3634
3524
desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
3635
3525
3526
+
desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK);
3636
3527
desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
3637
3528
desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
3638
3529
desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
···
3913
3802
memset(rx_status, 0, sizeof(*rx_status));
3914
3803
rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status);
3915
3804
rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info);
3805
+
3806
+
if (!rtw89_core_skb_pn_valid(rtwdev, desc_info, skb))
3807
+
return;
3808
+
3916
3809
if (desc_info->long_rxdesc &&
3917
3810
BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
3918
3811
skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
···
4826
4711
4827
4712
if (rtwdev->lps_enabled && !rtwdev->btc.lps)
4828
4713
rtw89_enter_lps_track(rtwdev);
4714
+
}
4715
+
4716
+
void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new)
4717
+
{
4718
+
struct rtw89_hal *hal = &rtwdev->hal;
4719
+
u32 old = hal->disabled_dm_bitmap;
4720
+
4721
+
if (new == old)
4722
+
return;
4723
+
4724
+
hal->disabled_dm_bitmap = new;
4725
+
4726
+
rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new);
4727
+
}
4728
+
4729
+
void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type)
4730
+
{
4731
+
struct rtw89_hal *hal = &rtwdev->hal;
4732
+
u32 cur = hal->disabled_dm_bitmap;
4733
+
4734
+
rtw89_core_dm_disable_cfg(rtwdev, cur | BIT(type));
4735
+
}
4736
+
4737
+
void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type)
4738
+
{
4739
+
struct rtw89_hal *hal = &rtwdev->hal;
4740
+
u32 cur = hal->disabled_dm_bitmap;
4741
+
4742
+
rtw89_core_dm_disable_cfg(rtwdev, cur & ~BIT(type));
4829
4743
}
4830
4744
4831
4745
u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
···
6262
6118
return -ENOMEM;
6263
6119
spin_lock_init(&rtwdev->ba_lock);
6264
6120
spin_lock_init(&rtwdev->rpwm_lock);
6265
-
mutex_init(&rtwdev->rf_mutex);
6266
6121
rtwdev->total_sta_assoc = 0;
6267
6122
6268
6123
rtw89_init_wait(&rtwdev->mcc.wait);
···
6320
6177
__rtw89_fw_free_all_early_h2c(rtwdev);
6321
6178
6322
6179
destroy_workqueue(rtwdev->txq_wq);
6323
-
mutex_destroy(&rtwdev->rf_mutex);
6324
6180
}
6325
6181
EXPORT_SYMBOL(rtw89_core_deinit);
6326
6182
···
6895
6753
bool support_mlo;
6896
6754
bool no_chanctx;
6897
6755
6898
-
firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
6756
+
firmware = rtw89_early_fw_feature_recognize(device, chip, variant,
6757
+
&early_fw, &fw_format);
6899
6758
6900
6759
ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
6901
6760
if (!ops)
+91
-14
drivers/net/wireless/realtek/rtw89/core.h
+91
-14
drivers/net/wireless/realtek/rtw89/core.h
···
873
873
RTW89_PHY_NUM,
874
874
};
875
875
876
+
enum rtw89_fbtc_bt_index {
877
+
BTC_BT_1ST = 0x0,
878
+
BTC_BT_2ND = 0x1,
879
+
BTC_BT_EXT = 0x2,
880
+
BTC_ALL_BT = 0x2,
881
+
BTC_ALL_BT_EZL = 0x3 /* BT0+BT1+Ext-ZB(or Thread, or LTE) */
882
+
};
883
+
876
884
#define __RTW89_MLD_MAX_LINK_NUM 2
877
885
#define RTW89_MLD_NON_STA_LINK_NUM 1
878
886
···
1134
1126
bool addr_cam_valid;
1135
1127
u8 addr_cam_id;
1136
1128
u8 sec_cam_id;
1129
+
u8 sec_type;
1137
1130
u8 mac_id;
1138
1131
u16 offset;
1139
1132
u16 rxd_len;
···
2203
2194
u32 scan_info_update: 1;
2204
2195
u32 lna_constrain: 3;
2205
2196
u32 rsvd: 17;
2197
+
};
2198
+
2199
+
struct rtw89_btc_rf_trx_para_v9 {
2200
+
u32 wl_tx_power[RTW89_PHY_NUM]; /* absolute Tx power (dBm), 1's complement -5->0x85 */
2201
+
u32 wl_rx_gain[RTW89_PHY_NUM]; /* rx gain table index (TBD.) */
2202
+
u32 bt_tx_power[BTC_ALL_BT]; /* decrease Tx power (dB) */
2203
+
u32 bt_rx_gain[BTC_ALL_BT]; /* LNA constrain level */
2204
+
u32 zb_tx_power[BTC_ALL_BT]; /* 15.4 devrease Tx power (dB) */
2205
+
u32 zb_rx_gain[BTC_ALL_BT]; /* 15.4 constrain level */
2206
2206
};
2207
2207
2208
2208
struct rtw89_btc_cx {
···
3579
3561
u8 rfe_type;
3580
3562
char country_code[2];
3581
3563
u8 adc_td;
3564
+
u8 bt_setting_2;
3565
+
u8 bt_setting_3;
3582
3566
};
3583
3567
3584
3568
struct rtw89_phy_rate_pattern {
···
4172
4152
u32 set;
4173
4153
};
4174
4154
4155
+
#define RTW89_MODULE_FWNAME_PLACEHOLDER_0 0,
4156
+
#define __RTW89_GEN_MODULE_FWNAME_FMT(placeholder_or_ignored, strfmt) \
4157
+
__take_second_arg(placeholder_or_ignored, strfmt)
4158
+
#define RTW89_GEN_MODULE_FWNAME_FMT(maxfmt) \
4159
+
__RTW89_GEN_MODULE_FWNAME_FMT(RTW89_MODULE_FWNAME_PLACEHOLDER_ ## maxfmt, \
4160
+
"-" __stringify(maxfmt))
4161
+
#define RTW89_GEN_MODULE_FWNAME(basename, maxformat) \
4162
+
basename RTW89_GEN_MODULE_FWNAME_FMT(maxformat) ".bin"
4163
+
4164
+
struct rtw89_fw_def {
4165
+
const char *fw_basename;
4166
+
u8 fw_format_max;
4167
+
u16 fw_b_aid;
4168
+
};
4169
+
4175
4170
struct rtw89_phy_table {
4176
4171
const struct rtw89_reg2_def *regs;
4177
4172
u32 n_regs;
···
4529
4494
const struct rtw89_chip_ops *ops;
4530
4495
const struct rtw89_mac_gen_def *mac_def;
4531
4496
const struct rtw89_phy_gen_def *phy_def;
4532
-
const char *fw_basename;
4533
-
u8 fw_format_max;
4497
+
struct rtw89_fw_def fw_def;
4534
4498
bool try_ce_fw;
4535
4499
u8 bbmcu_nr;
4536
4500
u32 needed_fw_elms;
···
4563
4529
bool support_noise;
4564
4530
bool ul_tb_waveform_ctrl;
4565
4531
bool ul_tb_pwr_diff;
4566
-
bool rx_freq_frome_ie;
4532
+
bool rx_freq_from_ie;
4567
4533
bool hw_sec_hdr;
4568
4534
bool hw_mgmt_tx_encrypt;
4569
4535
bool hw_tkip_crypto;
···
4626
4592
const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4627
4593
u8 rf_para_dlink_num;
4628
4594
const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4595
+
const struct rtw89_btc_rf_trx_para_v9 *rf_para_ulink_v9;
4596
+
const struct rtw89_btc_rf_trx_para_v9 *rf_para_dlink_v9;
4597
+
u8 rf_para_ulink_num_v9;
4598
+
u8 rf_para_dlink_num_v9;
4629
4599
u8 ps_mode_supported;
4630
4600
u8 low_power_hci_modes;
4631
4601
···
4671
4633
struct rtw89_chip_variant {
4672
4634
bool no_mcs_12_13: 1;
4673
4635
u32 fw_min_ver_code;
4636
+
const struct rtw89_fw_def *fw_def_override;
4674
4637
};
4675
4638
4676
4639
union rtw89_bus_info {
···
4763
4724
RTW89_FW_NORMAL = 1,
4764
4725
RTW89_FW_WOWLAN = 3,
4765
4726
RTW89_FW_NORMAL_CE = 5,
4727
+
RTW89_FW_NORMAL_B = 14,
4728
+
RTW89_FW_WOWLAN_B = 15,
4766
4729
RTW89_FW_BBMCU0 = 64,
4767
4730
RTW89_FW_BBMCU1 = 65,
4768
4731
RTW89_FW_LOGFMT = 255,
···
4820
4779
RTW89_FW_FEATURE_SER_L1_BY_EVENT,
4821
4780
RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C,
4822
4781
RTW89_FW_FEATURE_LPS_ML_INFO_V1,
4782
+
RTW89_FW_FEATURE_SER_POST_RECOVER_DMAC,
4823
4783
4824
4784
NUM_OF_RTW89_FW_FEATURES,
4825
4785
};
···
5194
5152
bool no_eht;
5195
5153
5196
5154
atomic_t roc_chanctx_idx;
5197
-
u8 roc_link_index;
5198
5155
5199
5156
DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
5200
5157
DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX);
···
5616
5575
struct rtw89_power_trim_info {
5617
5576
bool pg_thermal_trim;
5618
5577
bool pg_pa_bias_trim;
5578
+
bool pg_vco_trim;
5619
5579
u8 thermal_trim[RF_PATH_MAX];
5620
5580
u8 pa_bias_trim[RF_PATH_MAX];
5621
5581
u8 pad_bias_trim[RF_PATH_MAX];
5582
+
u8 vco_trim[RF_PATH_MAX];
5622
5583
};
5623
5584
5624
5585
enum rtw89_regd_func {
···
5779
5736
RTW89_NUM_OF_SER_FLAGS
5780
5737
};
5781
5738
5739
+
struct rtw89_ser_count {
5740
+
unsigned int l1;
5741
+
unsigned int l2;
5742
+
};
5743
+
5782
5744
struct rtw89_ser {
5783
5745
u8 state;
5784
5746
u8 alarm_event;
5785
5747
bool prehandle_l1;
5748
+
5749
+
struct rtw89_ser_count sw_cnt;
5786
5750
5787
5751
struct work_struct ser_hdl_work;
5788
5752
struct delayed_work ser_alarm_work;
···
5951
5901
bool offset_valid;
5952
5902
bool comp_valid;
5953
5903
s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5904
+
s8 offset2[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5954
5905
s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */
5955
5906
s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */
5907
+
s8 ref_gain_base[RTW89_PHY_NUM]; /* S(8, 2) */
5908
+
s8 cck_rpl_base[RTW89_PHY_NUM]; /* S(8, 0) */
5956
5909
s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5957
5910
};
5958
5911
···
6182
6129
u32 tbtt_diff_th;
6183
6130
};
6184
6131
6132
+
struct rtw89_tid_stats {
6133
+
s64 last_pn;
6134
+
u16 last_sn;
6135
+
bool started;
6136
+
};
6137
+
6185
6138
struct rtw89_dev {
6186
6139
struct ieee80211_hw *hw;
6187
6140
struct device *dev;
···
6217
6158
refcount_t refcount_ap_info;
6218
6159
6219
6160
struct list_head rtwvifs_list;
6220
-
/* used to protect rf read write */
6221
-
struct mutex rf_mutex;
6222
6161
struct workqueue_struct *txq_wq;
6223
6162
struct work_struct txq_work;
6224
6163
struct delayed_work txq_reinvoke_work;
···
6394
6337
struct sk_buff_head roc_queue;
6395
6338
6396
6339
struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
6340
+
struct rtw89_tid_stats tid_rx_stats[IEEE80211_NUM_TIDS];
6397
6341
DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
6398
6342
6399
6343
DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
···
6842
6784
rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6843
6785
u32 addr, u32 mask)
6844
6786
{
6845
-
u32 val;
6787
+
lockdep_assert_wiphy(rtwdev->hw->wiphy);
6846
6788
6847
-
mutex_lock(&rtwdev->rf_mutex);
6848
-
val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
6849
-
mutex_unlock(&rtwdev->rf_mutex);
6850
-
6851
-
return val;
6789
+
return rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
6852
6790
}
6853
6791
6854
6792
static inline void
6855
6793
rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6856
6794
u32 addr, u32 mask, u32 data)
6857
6795
{
6858
-
mutex_lock(&rtwdev->rf_mutex);
6796
+
lockdep_assert_wiphy(rtwdev->hw->wiphy);
6797
+
6859
6798
rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
6860
-
mutex_unlock(&rtwdev->rf_mutex);
6861
6799
}
6862
6800
6863
6801
static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr)
···
7433
7379
chip->ops->calc_rx_gain_normal(rtwdev, chan, path, phy_idx, calc);
7434
7380
}
7435
7381
7382
+
static inline const struct rtw89_fw_def *
7383
+
__rtw89_chip_get_fw_def(const struct rtw89_chip_info *chip,
7384
+
const struct rtw89_chip_variant *variant)
7385
+
{
7386
+
if (variant && variant->fw_def_override)
7387
+
return variant->fw_def_override;
7388
+
7389
+
return &chip->fw_def;
7390
+
}
7391
+
7392
+
static inline
7393
+
const struct rtw89_fw_def *rtw89_chip_get_fw_def(struct rtw89_dev *rtwdev)
7394
+
{
7395
+
return __rtw89_chip_get_fw_def(rtwdev->chip, rtwdev->variant);
7396
+
}
7397
+
7436
7398
static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
7437
7399
const struct rtw89_txpwr_table *tbl)
7438
7400
{
···
7611
7541
7612
7542
switch (type) {
7613
7543
case RTW89_FW_WOWLAN:
7544
+
case RTW89_FW_WOWLAN_B:
7614
7545
return &fw_info->wowlan;
7615
7546
case RTW89_FW_LOGFMT:
7616
7547
return &fw_info->log.suit;
···
7805
7734
void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
7806
7735
struct ieee80211_sta *sta,
7807
7736
struct cfg80211_tid_config *tid_config);
7737
+
void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
7738
+
struct ieee80211_ampdu_params *params, bool enable);
7739
+
void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev);
7808
7740
void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force);
7809
7741
void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
7810
7742
int rtw89_core_init(struct rtw89_dev *rtwdev);
···
7894
7820
void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
7895
7821
int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7896
7822
unsigned int link_id);
7823
+
void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new);
7824
+
void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type);
7825
+
void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type);
7897
7826
7898
7827
#endif
+17
-36
drivers/net/wireless/realtek/rtw89/debug.c
+17
-36
drivers/net/wireless/realtek/rtw89/debug.c
···
1129
1129
pages = len / mem_page_size + 1;
1130
1130
start_page = start_addr / mem_page_size;
1131
1131
residue = start_addr % mem_page_size;
1132
-
base_addr = mac->mem_base_addrs[sel];
1132
+
base_addr = rtw89_mac_mem_base_addrs(rtwdev, sel);
1133
1133
base_addr += start_page * mem_page_size;
1134
1134
1135
1135
for (pp = 0; pp < pages; pp++) {
···
3552
3552
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
3553
3553
return -EBUSY;
3554
3554
3555
+
rtw89_leave_ps_mode(rtwdev);
3556
+
3555
3557
rtw89_write32_set(rtwdev, R_BE_FW_TRIGGER_IDCT_ISR,
3556
3558
B_BE_DMAC_FW_TRIG_IDCT | B_BE_DMAC_FW_ERR_IDCT_IMR);
3557
3559
···
3655
3653
{
3656
3654
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
3657
3655
return -EBUSY;
3656
+
3657
+
rtw89_leave_ps_mode(rtwdev);
3658
3658
3659
3659
rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR,
3660
3660
B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR);
···
3785
3781
struct rtw89_debugfs_priv *debugfs_priv,
3786
3782
char *buf, size_t bufsz)
3787
3783
{
3784
+
const struct rtw89_ser_count *sw_cnt = &rtwdev->ser.sw_cnt;
3788
3785
const struct rtw89_chip_info *chip = rtwdev->chip;
3789
3786
struct rtw89_dbg_ser_counters cnt = {};
3790
3787
char *p = buf, *end = buf + bufsz;
···
3803
3798
return -EOPNOTSUPP;
3804
3799
}
3805
3800
3801
+
p += scnprintf(p, end - p, "SER L1 SW Count: %u\n", sw_cnt->l1);
3802
+
p += scnprintf(p, end - p, "SER L2 SW Count: %u\n", sw_cnt->l2);
3803
+
3804
+
/* Some chipsets won't record SER simulation in HW cnt. */
3805
+
p += scnprintf(p, end - p, "---\n");
3806
3806
p += scnprintf(p, end - p, "SER L0 Count: %d\n", cnt.l0);
3807
3807
p += scnprintf(p, end - p, "SER L1 Count: %d\n", cnt.l1);
3808
3808
p += scnprintf(p, end - p, "SER L0 promote event: %d\n", cnt.l0_to_l1);
···
4337
4327
return p - buf;
4338
4328
}
4339
4329
4340
-
static void rtw89_debug_disable_dm_cfg_bmap(struct rtw89_dev *rtwdev, u32 new)
4341
-
{
4342
-
struct rtw89_hal *hal = &rtwdev->hal;
4343
-
u32 old = hal->disabled_dm_bitmap;
4344
-
4345
-
if (new == old)
4346
-
return;
4347
-
4348
-
hal->disabled_dm_bitmap = new;
4349
-
4350
-
rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new);
4351
-
}
4352
-
4353
-
static void rtw89_debug_disable_dm_set_flag(struct rtw89_dev *rtwdev, u8 flag)
4354
-
{
4355
-
struct rtw89_hal *hal = &rtwdev->hal;
4356
-
u32 cur = hal->disabled_dm_bitmap;
4357
-
4358
-
rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur | BIT(flag));
4359
-
}
4360
-
4361
-
static void rtw89_debug_disable_dm_clr_flag(struct rtw89_dev *rtwdev, u8 flag)
4362
-
{
4363
-
struct rtw89_hal *hal = &rtwdev->hal;
4364
-
u32 cur = hal->disabled_dm_bitmap;
4365
-
4366
-
rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur & ~BIT(flag));
4367
-
}
4368
-
4369
4330
#define DM_INFO(type) {RTW89_DM_ ## type, #type}
4370
4331
4371
4332
static const struct rtw89_disabled_dm_info {
···
4387
4406
if (ret)
4388
4407
return -EINVAL;
4389
4408
4390
-
rtw89_debug_disable_dm_cfg_bmap(rtwdev, conf);
4409
+
rtw89_core_dm_disable_cfg(rtwdev, conf);
4391
4410
4392
4411
return count;
4393
4412
}
···
4450
4469
if (num != 2)
4451
4470
return -EINVAL;
4452
4471
4453
-
rtw89_debug_disable_dm_set_flag(rtwdev, RTW89_DM_MLO);
4472
+
rtw89_core_dm_disable_set(rtwdev, RTW89_DM_MLO);
4454
4473
4455
4474
rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode);
4456
4475
···
4460
4479
break;
4461
4480
default:
4462
4481
rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n");
4463
-
rtw89_debug_disable_dm_clr_flag(rtwdev, RTW89_DM_MLO);
4482
+
rtw89_core_dm_disable_clr(rtwdev, RTW89_DM_MLO);
4464
4483
4465
4484
return -EOPNOTSUPP;
4466
4485
}
···
4863
4882
static const struct rtw89_debugfs rtw89_debugfs_templ = {
4864
4883
.read_reg = rtw89_debug_priv_select_and_get(read_reg),
4865
4884
.write_reg = rtw89_debug_priv_set(write_reg),
4866
-
.read_rf = rtw89_debug_priv_select_and_get(read_rf),
4867
-
.write_rf = rtw89_debug_priv_set(write_rf),
4868
-
.rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K),
4885
+
.read_rf = rtw89_debug_priv_select_and_get(read_rf, RLOCK),
4886
+
.write_rf = rtw89_debug_priv_set(write_rf, WLOCK),
4887
+
.rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K, RLOCK),
4869
4888
.txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK),
4870
4889
.mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K),
4871
4890
.mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK),
+21
-2
drivers/net/wireless/realtek/rtw89/efuse.c
+21
-2
drivers/net/wireless/realtek/rtw89/efuse.c
···
185
185
return 0;
186
186
}
187
187
188
-
static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,
189
-
u32 dump_addr, u32 dump_size, bool dav)
188
+
static int __rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,
189
+
u32 dump_addr, u32 dump_size, bool dav)
190
190
{
191
191
int ret;
192
192
···
206
206
}
207
207
208
208
return 0;
209
+
}
210
+
211
+
static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,
212
+
u32 dump_addr, u32 dump_size, bool dav)
213
+
{
214
+
int retry;
215
+
int ret;
216
+
217
+
for (retry = 0; retry < 5; retry++) {
218
+
ret = __rtw89_dump_physical_efuse_map(rtwdev, map, dump_addr,
219
+
dump_size, dav);
220
+
if (!ret)
221
+
return 0;
222
+
223
+
rtw89_warn(rtwdev, "efuse dump (dav=%d) failed, retrying (%d)\n",
224
+
dav, retry);
225
+
}
226
+
227
+
return ret;
209
228
}
210
229
211
230
#define invalid_efuse_header(hdr1, hdr2) \
+144
-17
drivers/net/wireless/realtek/rtw89/fw.c
+144
-17
drivers/net/wireless/realtek/rtw89/fw.c
···
730
730
{
731
731
const struct rtw89_fw_hdr *v0 = (const struct rtw89_fw_hdr *)fw_suit->data;
732
732
const struct rtw89_fw_hdr_v1 *v1 = (const struct rtw89_fw_hdr_v1 *)fw_suit->data;
733
+
struct wiphy *wiphy = rtwdev->hw->wiphy;
733
734
734
735
if (type == RTW89_FW_LOGFMT)
735
736
return 0;
···
755
754
"Firmware version %u.%u.%u.%u (%08x), cmd version %u, type %u\n",
756
755
fw_suit->major_ver, fw_suit->minor_ver, fw_suit->sub_ver,
757
756
fw_suit->sub_idex, fw_suit->commitid, fw_suit->cmd_ver, type);
757
+
758
+
if (type == RTW89_FW_NORMAL || type == RTW89_FW_NORMAL_CE ||
759
+
type == RTW89_FW_NORMAL_B)
760
+
snprintf(wiphy->fw_version, sizeof(wiphy->fw_version),
761
+
"%u.%u.%u.%u",
762
+
fw_suit->major_ver, fw_suit->minor_ver,
763
+
fw_suit->sub_ver, fw_suit->sub_idex);
758
764
759
765
return 0;
760
766
}
···
931
923
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, RFK_PRE_NOTIFY_MCC_V1),
932
924
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 84, 0, ADDR_CAM_V0),
933
925
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 97, 0, SIM_SER_L0L1_BY_HALT_H2C),
926
+
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 100, 0, SER_POST_RECOVER_DMAC),
934
927
};
935
928
936
929
static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,
···
974
965
const struct firmware *
975
966
rtw89_early_fw_feature_recognize(struct device *device,
976
967
const struct rtw89_chip_info *chip,
968
+
const struct rtw89_chip_variant *variant,
977
969
struct rtw89_fw_info *early_fw,
978
970
int *used_fw_format)
979
971
{
972
+
const struct rtw89_fw_def *fw_def = __rtw89_chip_get_fw_def(chip, variant);
980
973
const struct firmware *firmware;
981
974
char fw_name[64];
982
975
int fw_format;
983
976
u32 ver_code;
984
977
int ret;
985
978
986
-
for (fw_format = chip->fw_format_max; fw_format >= 0; fw_format--) {
979
+
for (fw_format = fw_def->fw_format_max; fw_format >= 0; fw_format--) {
987
980
rtw89_fw_get_filename(fw_name, sizeof(fw_name),
988
-
chip->fw_basename, fw_format);
981
+
fw_def->fw_basename, fw_format);
989
982
990
983
ret = request_firmware(&firmware, fw_name, device);
991
984
if (!ret) {
···
1036
1025
1037
1026
int rtw89_fw_recognize(struct rtw89_dev *rtwdev)
1038
1027
{
1028
+
const struct rtw89_fw_def *fw_def = rtw89_chip_get_fw_def(rtwdev);
1039
1029
const struct rtw89_chip_info *chip = rtwdev->chip;
1030
+
const struct rtw89_hal *hal = &rtwdev->hal;
1031
+
enum rtw89_fw_type normal_fw_type = RTW89_FW_NORMAL;
1032
+
enum rtw89_fw_type wowlan_fw_type = RTW89_FW_WOWLAN;
1040
1033
int ret;
1034
+
1035
+
if (fw_def->fw_b_aid && fw_def->fw_b_aid == hal->aid) {
1036
+
normal_fw_type = RTW89_FW_NORMAL_B;
1037
+
wowlan_fw_type = RTW89_FW_WOWLAN_B;
1038
+
}
1041
1039
1042
1040
if (chip->try_ce_fw) {
1043
1041
ret = __rtw89_fw_recognize(rtwdev, RTW89_FW_NORMAL_CE, true);
···
1054
1034
goto normal_done;
1055
1035
}
1056
1036
1057
-
ret = __rtw89_fw_recognize(rtwdev, RTW89_FW_NORMAL, false);
1037
+
ret = __rtw89_fw_recognize(rtwdev, normal_fw_type, false);
1058
1038
if (ret)
1059
1039
return ret;
1060
1040
···
1064
1044
return ret;
1065
1045
1066
1046
/* It still works if wowlan firmware isn't existing. */
1067
-
__rtw89_fw_recognize(rtwdev, RTW89_FW_WOWLAN, false);
1047
+
__rtw89_fw_recognize(rtwdev, wowlan_fw_type, false);
1068
1048
1069
1049
/* It still works if log format file isn't existing. */
1070
1050
__rtw89_fw_recognize(rtwdev, RTW89_FW_LOGFMT, true);
···
1082
1062
const union rtw89_fw_element_arg arg)
1083
1063
{
1084
1064
struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1065
+
const struct rtw89_chip_info *chip = rtwdev->chip;
1085
1066
struct rtw89_hal *hal = &rtwdev->hal;
1086
1067
struct rtw89_phy_table *tbl, **pp;
1087
1068
struct rtw89_reg2_def *regs;
···
1139
1118
1140
1119
if (radio) {
1141
1120
tbl->rf_path = arg.rf_path;
1142
-
tbl->config = rtw89_phy_config_rf_reg_v1;
1121
+
tbl->config = chip->chip_id == RTL8852A ?
1122
+
rtw89_phy_config_rf_reg :
1123
+
rtw89_phy_config_rf_reg_v1;
1143
1124
}
1144
1125
1145
1126
*pp = tbl;
···
1161
1138
const struct __rtw89_fw_txpwr_element *txpwr_elm = &elm->u.txpwr;
1162
1139
const unsigned long offset = arg.offset;
1163
1140
struct rtw89_efuse *efuse = &rtwdev->efuse;
1141
+
struct rtw89_hal *hal = &rtwdev->hal;
1142
+
u16 aid = le16_to_cpu(elm->aid);
1164
1143
struct rtw89_txpwr_conf *conf;
1144
+
1145
+
if (aid && aid != hal->aid)
1146
+
return 1;
1165
1147
1166
1148
if (!rtwdev->rfe_data) {
1167
1149
rtwdev->rfe_data = kzalloc_obj(*rtwdev->rfe_data);
···
2052
2024
{
2053
2025
struct rtw89_dev *rtwdev =
2054
2026
container_of(work, struct rtw89_dev, load_firmware_work);
2055
-
const struct rtw89_chip_info *chip = rtwdev->chip;
2027
+
const struct rtw89_fw_def *fw_def = rtw89_chip_get_fw_def(rtwdev);
2056
2028
char fw_name[64];
2057
2029
2058
2030
rtw89_fw_get_filename(fw_name, sizeof(fw_name),
2059
-
chip->fw_basename, rtwdev->fw.fw_format);
2031
+
fw_def->fw_basename, rtwdev->fw.fw_format);
2060
2032
2061
2033
rtw89_load_firmware_req(rtwdev, &rtwdev->fw.req, fw_name, false);
2062
2034
}
···
6885
6857
return 0;
6886
6858
}
6887
6859
6860
+
int rtw89_fw_h2c_trx_protect(struct rtw89_dev *rtwdev,
6861
+
enum rtw89_phy_idx phy_idx, bool enable)
6862
+
{
6863
+
struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
6864
+
const struct rtw89_chip_info *chip = rtwdev->chip;
6865
+
struct rtw89_h2c_trx_protect *h2c;
6866
+
u32 len = sizeof(*h2c);
6867
+
struct sk_buff *skb;
6868
+
int ret;
6869
+
6870
+
if (chip->chip_gen != RTW89_CHIP_BE)
6871
+
return 0;
6872
+
6873
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
6874
+
if (!skb) {
6875
+
rtw89_err(rtwdev, "failed to alloc skb for h2c trx protect\n");
6876
+
return -ENOMEM;
6877
+
}
6878
+
6879
+
skb_put(skb, len);
6880
+
h2c = (struct rtw89_h2c_trx_protect *)skb->data;
6881
+
6882
+
h2c->c0 = le32_encode_bits(BIT(phy_idx), RTW89_H2C_TRX_PROTECT_C0_BAND_BITMAP) |
6883
+
le32_encode_bits(0, RTW89_H2C_TRX_PROTECT_C0_OP_MODE);
6884
+
h2c->c1 = le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_C1_RX_IN) |
6885
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_C1_PPDU_STS) |
6886
+
le32_encode_bits(1, RTW89_H2C_TRX_PROTECT_C1_MSK_RX_IN) |
6887
+
le32_encode_bits(1, RTW89_H2C_TRX_PROTECT_C1_MSK_PPDU_STS);
6888
+
h2c->w0 = le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BE0) |
6889
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BK0) |
6890
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_VI0) |
6891
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_VO0) |
6892
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BE1) |
6893
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BK1) |
6894
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_VI1) |
6895
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_VO1) |
6896
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_MG0) |
6897
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_MG1) |
6898
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_MG2) |
6899
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_HI) |
6900
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BCN) |
6901
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_UL) |
6902
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT0) |
6903
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT1) |
6904
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT2) |
6905
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT3) |
6906
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ0) |
6907
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ1);
6908
+
h2c->m0 = cpu_to_le32(RTW89_H2C_TRX_PROTECT_W0_TXEN_BE0 |
6909
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_BK0 |
6910
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_VI0 |
6911
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_VO0 |
6912
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_BE1 |
6913
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_BK1 |
6914
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_VI1 |
6915
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_VO1 |
6916
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_MG0 |
6917
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_MG1 |
6918
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_MG2 |
6919
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_HI |
6920
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_BCN |
6921
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_UL |
6922
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT0 |
6923
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT1 |
6924
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT2 |
6925
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT3 |
6926
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ0 |
6927
+
RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ1);
6928
+
h2c->w1 = le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W1_CHINFO_EN) |
6929
+
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W1_DFS_EN);
6930
+
h2c->m1 = cpu_to_le32(RTW89_H2C_TRX_PROTECT_W1_CHINFO_EN |
6931
+
RTW89_H2C_TRX_PROTECT_W1_DFS_EN);
6932
+
6933
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
6934
+
H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
6935
+
H2C_FUNC_TRX_PROTECT, 0, 1, len);
6936
+
6937
+
ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait,
6938
+
RTW89_FW_OFLD_WAIT_COND_TRX_PROTECT);
6939
+
if (ret) {
6940
+
rtw89_debug(rtwdev, RTW89_DBG_FW, "failed to trx protect\n");
6941
+
return ret;
6942
+
}
6943
+
6944
+
return 0;
6945
+
}
6946
+
6888
6947
int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
6889
6948
struct rtw89_fw_h2c_rf_reg_info *info,
6890
6949
u16 len, u8 page)
···
7385
7270
h2c = (struct rtw89_fw_h2c_rfk_pre_info_mcc *)skb->data;
7386
7271
7387
7272
h2c->aid = cpu_to_le32(hal->aid);
7273
+
h2c->acv = hal->acv;
7388
7274
7389
7275
done:
7390
7276
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
···
9718
9602
return ret;
9719
9603
}
9720
9604
9721
-
#define H2C_WAKEUP_CTRL_LEN 4
9722
9605
int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
9723
9606
struct rtw89_vif_link *rtwvif_link,
9724
9607
bool enable)
9725
9608
{
9609
+
struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
9726
9610
struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
9611
+
struct rtw89_h2c_wow_wakeup_ctrl *h2c;
9727
9612
struct sk_buff *skb;
9613
+
u32 len = sizeof(*h2c);
9728
9614
u8 macid = rtwvif_link->mac_id;
9729
9615
int ret;
9730
9616
9731
-
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WAKEUP_CTRL_LEN);
9617
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
9732
9618
if (!skb) {
9733
9619
rtw89_err(rtwdev, "failed to alloc skb for wakeup ctrl\n");
9734
9620
return -ENOMEM;
9735
9621
}
9736
9622
9737
-
skb_put(skb, H2C_WAKEUP_CTRL_LEN);
9623
+
skb_put(skb, len);
9624
+
h2c = (struct rtw89_h2c_wow_wakeup_ctrl *)skb->data;
9738
9625
9739
9626
if (rtw_wow->pattern_cnt)
9740
-
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(skb->data, enable);
9741
-
if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags))
9742
-
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(skb->data, enable);
9743
-
if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags))
9744
-
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(skb->data, enable);
9627
+
h2c->w0 |= le32_encode_bits(enable,
9628
+
RTW89_H2C_WOW_WAKEUP_CTRL_W0_PATTERN_MATCH_ENABLE);
9629
+
if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags)) {
9630
+
h2c->w0 |= le32_encode_bits(enable,
9631
+
RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_ENABLE);
9632
+
if (ieee80211_vif_is_mld(vif))
9633
+
h2c->w0 |= le32_encode_bits(enable,
9634
+
RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_MLD_ENABLE);
9635
+
}
9745
9636
9746
-
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(skb->data, macid);
9637
+
if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags))
9638
+
h2c->w0 |= le32_encode_bits(enable,
9639
+
RTW89_H2C_WOW_WAKEUP_CTRL_W0_DEAUTH_ENABLE);
9640
+
9641
+
h2c->w0 |= le32_encode_bits(macid, RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAC_ID);
9747
9642
9748
9643
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
9749
9644
H2C_CAT_MAC,
9750
9645
H2C_CL_MAC_WOW,
9751
9646
H2C_FUNC_WAKEUP_CTRL, 0, 1,
9752
-
H2C_WAKEUP_CTRL_LEN);
9647
+
len);
9753
9648
9754
9649
ret = rtw89_h2c_tx(rtwdev, skb, false);
9755
9650
if (ret) {
+84
-50
drivers/net/wireless/realtek/rtw89/fw.h
+84
-50
drivers/net/wireless/realtek/rtw89/fw.h
···
2219
2219
#define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
2220
2220
#define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
2221
2221
2222
-
static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
2223
-
{
2224
-
le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2225
-
}
2222
+
struct rtw89_h2c_wow_wakeup_ctrl {
2223
+
__le32 w0;
2224
+
} __packed;
2226
2225
2227
-
static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
2228
-
{
2229
-
le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2230
-
}
2231
-
2232
-
static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
2233
-
{
2234
-
le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2235
-
}
2236
-
2237
-
static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
2238
-
{
2239
-
le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2240
-
}
2241
-
2242
-
static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2243
-
{
2244
-
le32p_replace_bits((__le32 *)h2c, val, BIT(4));
2245
-
}
2246
-
2247
-
static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2248
-
{
2249
-
le32p_replace_bits((__le32 *)h2c, val, BIT(5));
2250
-
}
2251
-
2252
-
static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2253
-
{
2254
-
le32p_replace_bits((__le32 *)h2c, val, BIT(6));
2255
-
}
2256
-
2257
-
static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2258
-
{
2259
-
le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2260
-
}
2261
-
2262
-
static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2263
-
{
2264
-
le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2265
-
}
2226
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_PATTERN_MATCH_ENABLE BIT(0)
2227
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_ENABLE BIT(1)
2228
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_HW_UNICAST_ENABLE BIT(2)
2229
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_FW_UNICAST_ENABLE BIT(3)
2230
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_DEAUTH_ENABLE BIT(4)
2231
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_REKEYP_ENABLE BIT(5)
2232
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_EAP_ENABLE BIT(6)
2233
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_ALL_DATA_ENABLE BIT(7)
2234
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_MLD_ENABLE BIT(8)
2235
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAC_ID_EXT GENMASK(23, 16)
2236
+
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAC_ID GENMASK(31, 24)
2266
2237
2267
2238
struct rtw89_h2c_wow_cam_update {
2268
2239
__le32 w0;
···
3076
3105
#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
3077
3106
#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
3078
3107
#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
3108
+
3109
+
struct rtw89_h2c_trx_protect {
3110
+
__le32 c0;
3111
+
__le32 c1;
3112
+
__le32 w0;
3113
+
__le32 m0;
3114
+
__le32 w1;
3115
+
__le32 m1;
3116
+
} __packed;
3117
+
3118
+
#define RTW89_H2C_TRX_PROTECT_C0_BAND_BITMAP GENMASK(2, 0)
3119
+
#define RTW89_H2C_TRX_PROTECT_C0_OP_MODE GENMASK(4, 3)
3120
+
#define RTW89_H2C_TRX_PROTECT_C1_RX_IN BIT(0)
3121
+
#define RTW89_H2C_TRX_PROTECT_C1_PPDU_STS BIT(4)
3122
+
#define RTW89_H2C_TRX_PROTECT_C1_MSK_RX_IN BIT(16)
3123
+
#define RTW89_H2C_TRX_PROTECT_C1_MSK_PPDU_STS BIT(20)
3124
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BE0 BIT(0)
3125
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BK0 BIT(1)
3126
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_VI0 BIT(2)
3127
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_VO0 BIT(3)
3128
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BE1 BIT(4)
3129
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BK1 BIT(5)
3130
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_VI1 BIT(6)
3131
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_VO1 BIT(7)
3132
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_MG0 BIT(8)
3133
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_MG1 BIT(9)
3134
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_MG2 BIT(10)
3135
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_HI BIT(11)
3136
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BCN BIT(12)
3137
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_UL BIT(13)
3138
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT0 BIT(14)
3139
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT1 BIT(15)
3140
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT2 BIT(16)
3141
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT3 BIT(17)
3142
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ0 BIT(18)
3143
+
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ1 BIT(19)
3144
+
#define RTW89_H2C_TRX_PROTECT_W1_CHINFO_EN BIT(0)
3145
+
#define RTW89_H2C_TRX_PROTECT_W1_DFS_EN BIT(1)
3079
3146
3080
3147
struct rtw89_h2c_fwips {
3081
3148
__le32 w0;
···
4298
4289
BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4299
4290
BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
4300
4291
4301
-
#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
4302
-
BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4303
-
BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4304
-
BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4305
-
BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4306
-
BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4307
-
BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
4292
+
#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_BASE \
4293
+
(BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4294
+
BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4295
+
BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4296
+
BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4297
+
BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4298
+
BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
4299
+
4300
+
#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS \
4301
+
(RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_BASE | \
4302
+
BIT(RTW89_FW_ELEMENT_ID_BBMCU0))
4303
+
4304
+
#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_V1 \
4305
+
(RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_BASE | \
4306
+
BIT(RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ) | \
4307
+
BIT(RTW89_FW_ELEMENT_ID_TX_COMP))
4308
4308
4309
4309
struct __rtw89_fw_txpwr_element {
4310
4310
u8 rsvd0;
···
4616
4598
H2C_FUNC_OFLD_TP = 0x20,
4617
4599
H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4618
4600
H2C_FUNC_SCANOFLD_BE = 0x2c,
4601
+
H2C_FUNC_TRX_PROTECT = 0x34,
4619
4602
4620
4603
NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4621
4604
};
···
4627
4608
#define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4628
4609
RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4629
4610
H2C_FUNC_PACKET_OFLD)
4611
+
#define RTW89_FW_OFLD_WAIT_COND_TRX_PROTECT RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_TRX_PROTECT)
4630
4612
4631
4613
#define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4632
4614
···
4861
4841
struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 base;
4862
4842
u8 rsvd[2];
4863
4843
__le32 aid;
4844
+
u8 acv;
4845
+
u8 rsvd2[3];
4864
4846
} __packed;
4865
4847
4866
4848
struct rtw89_h2c_rf_tssi {
···
5193
5171
const struct firmware *
5194
5172
rtw89_early_fw_feature_recognize(struct device *device,
5195
5173
const struct rtw89_chip_info *chip,
5174
+
const struct rtw89_chip_variant *variant,
5196
5175
struct rtw89_fw_info *early_fw,
5197
5176
int *used_fw_format);
5198
5177
int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
···
5316
5293
struct rtw89_scan_option *opt,
5317
5294
struct rtw89_vif_link *vif,
5318
5295
bool wowlan);
5296
+
int rtw89_fw_h2c_trx_protect(struct rtw89_dev *rtwdev,
5297
+
enum rtw89_phy_idx phy_idx, bool enable);
5319
5298
int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
5320
5299
struct rtw89_fw_h2c_rf_reg_info *info,
5321
5300
u16 len, u8 page);
···
5491
5466
5492
5467
if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
5493
5468
rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
5469
+
}
5470
+
5471
+
static inline void rtw89_fw_h2c_init_trx_protect(struct rtw89_dev *rtwdev)
5472
+
{
5473
+
u8 active_bands = rtw89_get_active_phy_bitmap(rtwdev);
5474
+
int i;
5475
+
5476
+
for (i = 0; i < RTW89_PHY_NUM; i++)
5477
+
rtw89_fw_h2c_trx_protect(rtwdev, i, active_bands & BIT(i));
5494
5478
}
5495
5479
5496
5480
static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
+48
-21
drivers/net/wireless/realtek/rtw89/mac.c
+48
-21
drivers/net/wireless/realtek/rtw89/mac.c
···
43
43
u32 val, enum rtw89_mac_mem_sel sel)
44
44
{
45
45
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
46
-
u32 addr = mac->mem_base_addrs[sel] + offset;
46
+
u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset;
47
47
48
48
rtw89_write32(rtwdev, mac->filter_model_addr, addr);
49
49
rtw89_write32(rtwdev, mac->indir_access_addr, val);
···
53
53
enum rtw89_mac_mem_sel sel)
54
54
{
55
55
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
56
-
u32 addr = mac->mem_base_addrs[sel] + offset;
56
+
u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset;
57
57
58
58
rtw89_write32(rtwdev, mac->filter_model_addr, addr);
59
59
return rtw89_read32(rtwdev, mac->indir_access_addr);
···
814
814
u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
815
815
{
816
816
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
817
+
const struct rtw89_chip_info *chip = rtwdev->chip;
817
818
u32 err, err_scnr;
818
819
int ret;
819
820
···
826
825
}
827
826
828
827
err = rtw89_read32(rtwdev, R_AX_HALT_C2H);
829
-
rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
828
+
829
+
if (!RTW89_CHK_FW_FEATURE(SER_POST_RECOVER_DMAC, &rtwdev->fw))
830
+
rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
830
831
831
832
err_scnr = RTW89_ERROR_SCENARIO(err);
832
833
if (err_scnr == RTW89_WCPU_CPU_EXCEPTION)
···
839
836
err = MAC_AX_ERR_RXI300;
840
837
841
838
if (rtw89_mac_suppress_log(rtwdev, err))
842
-
return err;
839
+
goto bottom;
843
840
844
841
rtw89_fw_st_dbg_dump(rtwdev);
845
842
mac->dump_err_status(rtwdev, err);
843
+
844
+
bottom:
845
+
if (chip->chip_gen != RTW89_CHIP_AX)
846
+
rtw89_write32(rtwdev, R_AX_HALT_C2H, 0);
847
+
848
+
if (RTW89_CHK_FW_FEATURE(SER_POST_RECOVER_DMAC, &rtwdev->fw))
849
+
rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
846
850
847
851
return err;
848
852
}
···
1739
1729
/* 8852C PCIE SCC */
1740
1730
.wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
1741
1731
.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
1742
-
/* 8852B USB2.0/USB3.0 SCC */
1743
-
.wde_size25 = {RTW89_WDE_PG_64, 162, 94,},
1732
+
/* 8852B USB2.0/USB3.0 SCC turbo */
1733
+
.wde_size30 = {RTW89_WDE_PG_64, 220, 36,},
1744
1734
/* 8852C USB2.0 */
1745
1735
.wde_size31 = {RTW89_WDE_PG_64, 384, 0,},
1746
1736
/* PCIE */
···
1764
1754
.ple_size19 = {RTW89_PLE_PG_128, 1904, 16,},
1765
1755
.ple_size20_v1 = {RTW89_PLE_PG_128, 2554, 182, 40960,},
1766
1756
.ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,},
1767
-
/* 8852B USB2.0 SCC */
1768
-
.ple_size32 = {RTW89_PLE_PG_128, 620, 20,},
1769
-
/* 8852B USB3.0 SCC */
1770
-
.ple_size33 = {RTW89_PLE_PG_128, 632, 8,},
1757
+
/* 8851B USB2.0 SCC turbo */
1758
+
.ple_size27 = {RTW89_PLE_PG_128, 1396, 12,},
1759
+
/* 8852B USB3.0 SCC turbo */
1760
+
.ple_size31 = {RTW89_PLE_PG_128, 1392, 16,},
1771
1761
/* 8852C USB2.0 */
1772
1762
.ple_size34 = {RTW89_PLE_PG_128, 3374, 18,},
1773
1763
/* PCIE 64 */
···
1790
1780
.wde_qt18 = {3228, 60, 0, 40,},
1791
1781
.wde_qt19_v1 = {613, 6, 0, 20,},
1792
1782
.wde_qt23 = {958, 48, 0, 16,},
1793
-
/* 8852B USB2.0/USB3.0 SCC */
1794
-
.wde_qt25 = {152, 2, 0, 8,},
1783
+
/* 8852B USB2.0/USB3.0 SCC turbo */
1784
+
.wde_qt30 = {210, 2, 0, 8,},
1795
1785
/* 8852C USB2.0 */
1796
1786
.wde_qt31 = {338, 6, 0, 40,},
1797
1787
.ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,},
···
1809
1799
/* 8852A USB SCC */
1810
1800
.ple_qt25 = {1536, 0, 16, 48, 13, 13, 360, 0, 32, 40, 8, 0,},
1811
1801
.ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,},
1802
+
/* 8852B USB3.0 SCC turbo */
1803
+
.ple_qt27 = {1040, 0, 16, 48, 13, 13, 178, 0, 32, 14, 8, 0,},
1804
+
.ple_qt28 = {1040, 0, 32, 48, 43, 13, 208, 0, 62, 14, 24, 0,},
1812
1805
/* USB 52C USB3.0 */
1813
1806
.ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
1814
1807
.ple_qt42_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,},
···
1830
1817
/* PCIE 64 */
1831
1818
.ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
1832
1819
.ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,},
1833
-
/* USB2.0 52B SCC */
1834
-
.ple_qt72 = {130, 0, 16, 48, 4, 13, 322, 0, 32, 14, 8, 0, 0,},
1835
-
/* USB2.0 52B 92K */
1836
-
.ple_qt73 = {130, 0, 32, 48, 37, 13, 355, 0, 65, 14, 24, 0, 0,},
1837
-
/* USB3.0 52B 92K */
1838
-
.ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,},
1839
-
.ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,},
1820
+
/* 8851B USB2.0 SCC turbo */
1821
+
.ple_qt61 = {858, 0, 16, 48, 4, 13, 370, 0, 32, 14, 8, 0, 0,},
1822
+
.ple_qt62 = {858, 0, 32, 48, 37, 13, 403, 0, 65, 14, 24, 0, 0,},
1840
1823
/* USB2.0 52C */
1841
1824
.ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,},
1842
1825
/* USB2.0 52C */
···
2013
2004
{
2014
2005
u32 size = rtwdev->chip->fifo_size;
2015
2006
2016
-
if (mode == RTW89_QTA_SCC)
2007
+
if (mode == RTW89_QTA_SCC && rtwdev->hci.type != RTW89_HCI_TYPE_USB)
2017
2008
size -= rtwdev->chip->dle_scc_rsvd_size;
2018
2009
2019
2010
return size;
···
5421
5412
cond = RTW89_SCANOFLD_BE_WAIT_COND_START;
5422
5413
h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN;
5423
5414
break;
5415
+
case H2C_FUNC_TRX_PROTECT:
5416
+
cond = RTW89_FW_OFLD_WAIT_COND_TRX_PROTECT;
5417
+
break;
5424
5418
}
5425
5419
5426
5420
data.err = !!h2c_return;
···
7183
7171
return ret;
7184
7172
}
7185
7173
7186
-
int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
7174
+
static int _rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
7187
7175
{
7188
7176
struct rtw89_mac_h2c_info h2c_info = {};
7189
7177
struct rtw89_mac_c2h_info c2h_info = {};
···
7202
7190
7203
7191
if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK)
7204
7192
ret = -EINVAL;
7193
+
7194
+
return ret;
7195
+
}
7196
+
7197
+
int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
7198
+
{
7199
+
int i, ret;
7200
+
7201
+
for (i = 0; i < CPU_IO_RX_RETRY_CNT; i++) {
7202
+
ret = _rtw89_mac_cpu_io_rx(rtwdev, wow_enable);
7203
+
if (!ret)
7204
+
return 0;
7205
+
}
7205
7206
7206
7207
return ret;
7207
7208
}
···
7332
7307
},
7333
7308
.wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,},
7334
7309
.agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, .mask = B_AX_AMPDU_MAX_TIME_MASK,},
7310
+
.ra_agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT,
7311
+
.mask = B_AX_RA_TRY_RATE_AGG_LMT_MASK,},
7335
7312
.txcnt_limit = {.addr = R_AX_TXCNT, .mask = B_AX_L_TXCNT_LMT_MASK,},
7336
7313
7337
7314
.check_mac_en = rtw89_mac_check_mac_en_ax,
+24
-10
drivers/net/wireless/realtek/rtw89/mac.h
+24
-10
drivers/net/wireless/realtek/rtw89/mac.h
···
17
17
#define BSSID_CAM_ENT_SIZE 0x08
18
18
#define HFC_PAGE_UNIT 64
19
19
#define RPWM_TRY_CNT 3
20
+
#define CPU_IO_RX_RETRY_CNT 3
20
21
21
22
enum rtw89_mac_hwmod_sel {
22
23
RTW89_DMAC_SEL = 0,
···
334
333
#define NAT25_CAM_BASE_ADDR_BE 0x18820000
335
334
#define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
336
335
#define SEC_CAM_BASE_ADDR_BE 0x18824000
336
+
#define SEC_CAM_BASE_ADDR_BE_8922D 0x1882C000
337
337
#define WOW_CAM_BASE_ADDR_BE 0x18828000
338
338
#define MLD_TBL_BASE_ADDR_BE 0x18829000
339
339
#define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
···
940
938
const struct rtw89_dle_size wde_size18_v1;
941
939
const struct rtw89_dle_size wde_size19;
942
940
const struct rtw89_dle_size wde_size23;
943
-
const struct rtw89_dle_size wde_size25;
941
+
const struct rtw89_dle_size wde_size30;
944
942
const struct rtw89_dle_size wde_size31;
945
943
const struct rtw89_dle_size ple_size0;
946
944
const struct rtw89_dle_size ple_size1;
···
955
953
const struct rtw89_dle_size ple_size19;
956
954
const struct rtw89_dle_size ple_size20_v1;
957
955
const struct rtw89_dle_size ple_size22_v1;
958
-
const struct rtw89_dle_size ple_size32;
959
-
const struct rtw89_dle_size ple_size33;
956
+
const struct rtw89_dle_size ple_size27;
957
+
const struct rtw89_dle_size ple_size31;
960
958
const struct rtw89_dle_size ple_size34;
961
959
const struct rtw89_wde_quota wde_qt0;
962
960
const struct rtw89_wde_quota wde_qt1;
···
970
968
const struct rtw89_wde_quota wde_qt18;
971
969
const struct rtw89_wde_quota wde_qt19_v1;
972
970
const struct rtw89_wde_quota wde_qt23;
973
-
const struct rtw89_wde_quota wde_qt25;
971
+
const struct rtw89_wde_quota wde_qt30;
974
972
const struct rtw89_wde_quota wde_qt31;
975
973
const struct rtw89_ple_quota ple_qt0;
976
974
const struct rtw89_ple_quota ple_qt1;
···
982
980
const struct rtw89_ple_quota ple_qt18;
983
981
const struct rtw89_ple_quota ple_qt25;
984
982
const struct rtw89_ple_quota ple_qt26;
983
+
const struct rtw89_ple_quota ple_qt27;
984
+
const struct rtw89_ple_quota ple_qt28;
985
985
const struct rtw89_ple_quota ple_qt42;
986
986
const struct rtw89_ple_quota ple_qt42_v2;
987
987
const struct rtw89_ple_quota ple_qt43;
···
995
991
const struct rtw89_ple_quota ple_qt57;
996
992
const struct rtw89_ple_quota ple_qt58;
997
993
const struct rtw89_ple_quota ple_qt59;
998
-
const struct rtw89_ple_quota ple_qt72;
999
-
const struct rtw89_ple_quota ple_qt73;
1000
-
const struct rtw89_ple_quota ple_qt74;
1001
-
const struct rtw89_ple_quota ple_qt75;
994
+
const struct rtw89_ple_quota ple_qt61;
995
+
const struct rtw89_ple_quota ple_qt62;
1002
996
const struct rtw89_ple_quota ple_qt78;
1003
997
const struct rtw89_ple_quota ple_qt79;
1004
998
const struct rtw89_ple_quota ple_qt_52a_wow;
···
1039
1037
struct rtw89_reg_def narrow_bw_ru_dis;
1040
1038
struct rtw89_reg_def wow_ctrl;
1041
1039
struct rtw89_reg_def agg_limit;
1040
+
struct rtw89_reg_def ra_agg_limit;
1042
1041
struct rtw89_reg_def txcnt_limit;
1043
1042
1044
1043
int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band,
···
1131
1128
1132
1129
extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
1133
1130
extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
1131
+
1132
+
static inline
1133
+
u32 rtw89_mac_mem_base_addrs(struct rtw89_dev *rtwdev, u8 sel)
1134
+
{
1135
+
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1136
+
1137
+
if (rtwdev->chip->chip_id == RTL8922D &&
1138
+
sel == RTW89_MAC_MEM_SECURITY_CAM)
1139
+
return SEC_CAM_BASE_ADDR_BE_8922D;
1140
+
1141
+
return mac->mem_base_addrs[sel];
1142
+
}
1134
1143
1135
1144
static inline
1136
1145
u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
···
1828
1813
if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE)
1829
1814
return false;
1830
1815
1831
-
if (rtwdev->chip->chip_id == RTL8922D && rtwdev->hal.cid == RTL8922D_CID7090)
1832
-
return true;
1816
+
/* The RTL8922DE will re-enable pre-load function after verification. */
1833
1817
1834
1818
return false;
1835
1819
}
+11
drivers/net/wireless/realtek/rtw89/mac80211.c
+11
drivers/net/wireless/realtek/rtw89/mac80211.c
···
528
528
if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
529
529
rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE);
530
530
531
+
rtw89_fw_h2c_init_trx_protect(rtwdev);
532
+
531
533
return 0;
532
534
533
535
unset_link:
···
964
962
rtw89_err(rtwdev, "failed to add key to sec cam\n");
965
963
return ret;
966
964
}
965
+
rtw89_core_tid_rx_stats_reset(rtwdev);
967
966
break;
968
967
case DISABLE_KEY:
969
968
flush_work(&rtwdev->txq_work);
···
1006
1003
clear_bit(tid, rtwsta->ampdu_map);
1007
1004
rtw89_chip_h2c_ampdu_cmac_tbl(rtwdev, rtwvif, rtwsta);
1008
1005
ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1006
+
rtw89_leave_ps_mode(rtwdev);
1007
+
rtw89_phy_ra_recalc_agg_limit(rtwdev);
1009
1008
break;
1010
1009
case IEEE80211_AMPDU_TX_OPERATIONAL:
1011
1010
set_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags);
···
1016
1011
set_bit(tid, rtwsta->ampdu_map);
1017
1012
rtw89_leave_ps_mode(rtwdev);
1018
1013
rtw89_chip_h2c_ampdu_cmac_tbl(rtwdev, rtwvif, rtwsta);
1014
+
rtw89_phy_ra_recalc_agg_limit(rtwdev);
1019
1015
break;
1020
1016
case IEEE80211_AMPDU_RX_START:
1017
+
rtw89_core_tid_rx_stats_ctrl(rtwdev, rtwsta, params, true);
1021
1018
rtw89_chip_h2c_ba_cam(rtwdev, rtwsta, true, params);
1022
1019
break;
1023
1020
case IEEE80211_AMPDU_RX_STOP:
1021
+
rtw89_core_tid_rx_stats_ctrl(rtwdev, rtwsta, params, false);
1024
1022
rtw89_chip_h2c_ba_cam(rtwdev, rtwsta, false, params);
1025
1023
break;
1026
1024
default:
···
1592
1584
if (unlikely(!rtwvif_link))
1593
1585
continue;
1594
1586
1587
+
rtw89_fw_h2c_trx_protect(rtwdev, rtwvif_link->phy_idx, false);
1588
+
1595
1589
__rtw89_ops_remove_iface_link(rtwdev, rtwvif_link);
1596
1590
1597
1591
rtw89_vif_unset_link(rtwvif, link_id);
···
1619
1609
__func__, link_id);
1620
1610
return ret;
1621
1611
}
1612
+
rtw89_fw_h2c_trx_protect(rtwdev, rtwvif_link->phy_idx, true);
1622
1613
}
1623
1614
1624
1615
return 0;
+2
drivers/net/wireless/realtek/rtw89/mac_be.c
+2
drivers/net/wireless/realtek/rtw89/mac_be.c
···
3193
3193
},
3194
3194
.wow_ctrl = {.addr = R_BE_WOW_CTRL, .mask = B_BE_WOW_WOWEN,},
3195
3195
.agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT, .mask = B_BE_AMPDU_MAX_TIME_MASK,},
3196
+
.ra_agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT,
3197
+
.mask = B_BE_RA_TRY_RATE_AGG_LMT_MASK,},
3196
3198
.txcnt_limit = {.addr = R_BE_TXCNT, .mask = B_BE_L_TXCNT_LMT_MASK,},
3197
3199
3198
3200
.check_mac_en = rtw89_mac_check_mac_en_be,
+7
drivers/net/wireless/realtek/rtw89/pci.h
+7
drivers/net/wireless/realtek/rtw89/pci.h
···
55
55
#define B_AX_CALIB_EN BIT(13)
56
56
#define B_AX_DIV GENMASK(15, 14)
57
57
#define RAC_SET_PPR_V1 0x31
58
+
#define RAC_ANA40 0x40
59
+
#define PHY_ERR_IMR_DIS (BIT(9) | BIT(0))
58
60
#define RAC_ANA41 0x41
59
61
#define PHY_ERR_FLAG_EN BIT(6)
60
62
···
1018
1016
#define B_BE_PL1_IGNORE_HOT_RST BIT(30)
1019
1017
#define B_BE_PL1_TIMER_UNIT_MASK GENMASK(19, 17)
1020
1018
#define PCIE_SER_TIMER_UNIT 0x2
1019
+
#define PCIE_SER_WOW_TIMER_UNIT 0x4
1021
1020
#define B_BE_PL1_TIMER_CLEAR BIT(0)
1022
1021
1023
1022
#define R_BE_REG_PL1_MASK 0x34B0
···
1031
1028
#define B_BE_SER_PMU_IMR BIT(0)
1032
1029
1033
1030
#define R_BE_REG_PL1_ISR 0x34B4
1031
+
#define B_PCIE_SER_ALL_ISR 0x7F
1034
1032
1035
1033
#define R_BE_RX_APPEND_MODE 0x8920
1036
1034
#define B_BE_APPEND_OFFSET_MASK GENMASK(23, 16)
···
1105
1101
B_BE_CH6_BUSY | B_BE_CH7_BUSY | B_BE_CH8_BUSY | \
1106
1102
B_BE_CH9_BUSY | B_BE_CH10_BUSY | B_BE_CH11_BUSY | \
1107
1103
B_BE_CH12_BUSY | B_BE_CH13_BUSY | B_BE_CH14_BUSY)
1104
+
#define DMA_BUSY1_CHECK_BE_V1 (B_BE_CH0_BUSY | B_BE_CH2_BUSY | B_BE_CH4_BUSY | \
1105
+
B_BE_CH6_BUSY | B_BE_CH8_BUSY | B_BE_CH10_BUSY | \
1106
+
B_BE_CH12_BUSY)
1108
1107
1109
1108
#define R_BE_HAXI_EXP_CTRL_V1 0xB020
1110
1109
#define B_BE_R_NO_SEC_ACCESS BIT(31)
+93
-11
drivers/net/wireless/realtek/rtw89/pci_be.c
+93
-11
drivers/net/wireless/realtek/rtw89/pci_be.c
···
351
351
return;
352
352
353
353
rtw89_write32(rtwdev, R_BE_PL1_DBG_INFO, 0x0);
354
-
rtw89_write32_set(rtwdev, R_BE_FWS1IMR, B_BE_PCIE_SER_TIMEOUT_INDIC_EN);
355
-
rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
356
-
rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK, 1);
357
354
358
-
val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
359
-
val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR |
360
-
B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK;
361
-
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
355
+
switch (hal->cv) {
356
+
case CHIP_CAV:
357
+
case CHIP_CBV:
358
+
rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
359
+
rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL,
360
+
B_BE_PL1_TIMER_UNIT_MASK, PCIE_SER_TIMER_UNIT);
361
+
362
+
val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
363
+
val32 &= ~(B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR |
364
+
B_BE_SER_PM_MASTER_IMR | B_BE_SER_LTSSM_IMR |
365
+
B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK);
366
+
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
367
+
break;
368
+
case CHIP_CCV:
369
+
default:
370
+
rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
371
+
372
+
ret = read_poll_timeout_atomic(rtw89_read32, val32, !val32,
373
+
1, 1000, false, rtwdev, R_BE_REG_PL1_ISR);
374
+
if (ret)
375
+
rtw89_warn(rtwdev, "[ERR] PCIE SER clear poll fail\n");
376
+
377
+
rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL,
378
+
B_BE_PL1_TIMER_UNIT_MASK, PCIE_SER_TIMER_UNIT);
379
+
rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
380
+
381
+
val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
382
+
val32 |= (B_BE_SER_PMU_IMR | B_BE_SER_PM_MASTER_IMR |
383
+
B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK |
384
+
B_BE_SER_PCLKREQ_ACK_MASK);
385
+
val32 &= ~B_BE_SER_L1SUB_IMR;
386
+
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
387
+
break;
388
+
}
362
389
363
390
return;
364
391
365
392
be2_chips:
366
393
rtw89_write32_clr(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
367
394
rtw89_write32_set(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
395
+
396
+
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
397
+
RAC_ANA40 * RAC_MULT, PHY_ERR_IMR_DIS);
398
+
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
399
+
RAC_ANA40 * RAC_MULT, PHY_ERR_IMR_DIS);
368
400
369
401
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
370
402
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
···
410
378
val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
411
379
val32 &= ~B_BE_PL1_SER_PL1_EN;
412
380
rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
381
+
rtw89_write32(rtwdev, R_BE_REG_PL1_ISR, B_PCIE_SER_ALL_ISR);
413
382
414
383
ret = read_poll_timeout_atomic(rtw89_read32, val32, !val32,
415
384
1, 1000, false, rtwdev, R_BE_REG_PL1_ISR);
···
418
385
rtw89_warn(rtwdev, "[ERR] PCIE SER clear poll fail\n");
419
386
420
387
val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
421
-
val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR |
388
+
val32 |= B_BE_SER_PMU_IMR | B_BE_SER_PM_MASTER_IMR |
422
389
B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK |
423
390
B_BE_SER_LTSSM_UNSTABLE_MASK;
391
+
val32 &= ~B_BE_SER_L1SUB_IMR;
424
392
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
425
393
426
394
rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK,
···
755
721
{
756
722
struct ieee80211_hw *hw = dev_get_drvdata(dev);
757
723
struct rtw89_dev *rtwdev = hw->priv;
724
+
u32 val32;
758
725
759
726
rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
760
727
rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST);
761
728
rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
762
729
rtw89_write32_set(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST);
763
-
rtw89_write32_clr(rtwdev, R_BE_REG_PL1_MASK, B_BE_SER_PM_MASTER_IMR);
730
+
731
+
val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
732
+
if (val32 & B_BE_PL1_SER_PL1_EN) {
733
+
val32 = u32_replace_bits(val32, PCIE_SER_WOW_TIMER_UNIT,
734
+
B_BE_PL1_TIMER_UNIT_MASK);
735
+
rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
736
+
737
+
if (rtwdev->chip->chip_id == RTL8922A)
738
+
rtw89_write32_clr(rtwdev, R_BE_REG_PL1_MASK,
739
+
B_BE_SER_PM_MASTER_IMR);
740
+
}
741
+
764
742
return 0;
765
743
}
766
744
···
781
735
struct ieee80211_hw *hw = dev_get_drvdata(dev);
782
736
struct rtw89_dev *rtwdev = hw->priv;
783
737
u32 polling;
738
+
u32 val32;
739
+
u16 val16;
784
740
int ret;
785
741
786
742
rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
787
743
rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST);
788
744
rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
789
745
rtw89_write32_clr(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST);
746
+
747
+
val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
748
+
if (!(val32 & B_BE_PL1_SER_PL1_EN))
749
+
goto clear_phy_isr;
750
+
790
751
rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
752
+
if (rtwdev->chip->chip_id == RTL8922D)
753
+
rtw89_write32(rtwdev, R_BE_REG_PL1_ISR, B_PCIE_SER_ALL_ISR);
791
754
792
755
ret = read_poll_timeout_atomic(rtw89_read32, polling, !polling, 1, 1000,
793
756
false, rtwdev, R_BE_REG_PL1_ISR);
794
757
if (ret)
795
758
rtw89_warn(rtwdev, "[ERR] PCIE SER clear polling fail\n");
796
759
797
-
rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
798
-
rtw89_write32_set(rtwdev, R_BE_REG_PL1_MASK, B_BE_SER_PM_MASTER_IMR);
760
+
if (rtwdev->chip->chip_id == RTL8922A)
761
+
rtw89_write32_set(rtwdev, R_BE_REG_PL1_MASK,
762
+
B_BE_SER_PM_MASTER_IMR | B_BE_SER_PCLKREQ_ACK_MASK);
763
+
764
+
val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
765
+
val32 = u32_replace_bits(val32, PCIE_SER_TIMER_UNIT, B_BE_PL1_TIMER_UNIT_MASK);
766
+
val32 |= B_BE_PL1_SER_PL1_EN;
767
+
rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
768
+
769
+
clear_phy_isr:
770
+
if (rtwdev->chip->chip_id == RTL8922D) {
771
+
val16 = rtw89_read16(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
772
+
RAC_ANA41 * RAC_MULT);
773
+
if (val16 & PHY_ERR_FLAG_EN) {
774
+
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
775
+
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
776
+
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
777
+
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
778
+
}
779
+
780
+
val16 = rtw89_read16(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
781
+
RAC_ANA41 * RAC_MULT);
782
+
if (val16 & PHY_ERR_FLAG_EN) {
783
+
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
784
+
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
785
+
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
786
+
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
787
+
}
788
+
}
799
789
800
790
rtw89_pci_basic_cfg(rtwdev, true);
801
791
+55
-16
drivers/net/wireless/realtek/rtw89/phy.c
+55
-16
drivers/net/wireless/realtek/rtw89/phy.c
···
775
775
rtw89_fw_h2c_ra(rtwdev, ra, csi);
776
776
}
777
777
778
+
void rtw89_phy_ra_recalc_agg_limit(struct rtw89_dev *rtwdev)
779
+
{
780
+
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
781
+
const struct rtw89_reg_def *ra_limit = &mac->ra_agg_limit;
782
+
struct ieee80211_sta *sta;
783
+
struct rtw89_sta *rtwsta;
784
+
u16 agg_num = U16_MAX;
785
+
u8 tid;
786
+
787
+
for_each_station(sta, rtwdev->hw) {
788
+
rtwsta = sta_to_rtwsta(sta);
789
+
790
+
for_each_set_bit(tid, rtwsta->ampdu_map, IEEE80211_NUM_TIDS)
791
+
agg_num = min(agg_num, rtwsta->ampdu_params[tid].agg_num);
792
+
}
793
+
794
+
if (agg_num == U16_MAX)
795
+
agg_num = 0x3F;
796
+
else
797
+
agg_num = clamp(agg_num, 1, 256) - 1;
798
+
799
+
rtw89_write32_idx(rtwdev, ra_limit->addr, ra_limit->mask, agg_num, RTW89_MAC_0);
800
+
if (!rtwdev->dbcc_en)
801
+
return;
802
+
rtw89_write32_idx(rtwdev, ra_limit->addr, ra_limit->mask, agg_num, RTW89_MAC_1);
803
+
}
804
+
778
805
u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
779
806
const struct rtw89_chan *chan,
780
807
enum rtw89_bandwidth dbw)
···
1686
1659
(struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1687
1660
}
1688
1661
1689
-
static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1690
-
const struct rtw89_reg2_def *reg,
1691
-
enum rtw89_rf_path rf_path,
1692
-
void *extra_data)
1662
+
void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1663
+
const struct rtw89_reg2_def *reg,
1664
+
enum rtw89_rf_path rf_path,
1665
+
void *extra_data)
1693
1666
{
1694
1667
if (reg->addr == 0xfe) {
1695
1668
mdelay(50);
···
1808
1781
}
1809
1782
1810
1783
static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1811
-
const struct rtw89_phy_table *table,
1784
+
const struct rtw89_phy_table *table, bool by_acv,
1812
1785
void (*config)(struct rtw89_dev *rtwdev,
1813
1786
const struct rtw89_reg2_def *reg,
1814
1787
enum rtw89_rf_path rf_path,
···
1817
1790
{
1818
1791
const struct rtw89_reg2_def *reg;
1819
1792
enum rtw89_rf_path rf_path = table->rf_path;
1793
+
u8 cv = by_acv ? rtwdev->hal.acv : rtwdev->hal.cv;
1820
1794
u8 rfe = rtwdev->efuse.rfe_type;
1821
-
u8 cv = rtwdev->hal.cv;
1822
1795
u32 i;
1823
1796
u32 headline_size = 0, headline_idx = 0;
1824
1797
u32 target = 0, cfg_target;
···
1885
1858
const struct rtw89_phy_table *bb_gain_table;
1886
1859
1887
1860
bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
1888
-
rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1861
+
rtw89_phy_init_reg(rtwdev, bb_table, false, rtw89_phy_config_bb_reg, NULL);
1889
1862
if (rtwdev->dbcc_en)
1890
-
rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg,
1863
+
rtw89_phy_init_reg(rtwdev, bb_table, false, rtw89_phy_config_bb_reg,
1891
1864
(void *)RTW89_PHY_1);
1892
1865
1893
1866
rtw89_chip_init_txpwr_unit(rtwdev);
1894
1867
1895
1868
bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
1896
1869
if (bb_gain_table)
1897
-
rtw89_phy_init_reg(rtwdev, bb_gain_table,
1870
+
rtw89_phy_init_reg(rtwdev, bb_gain_table, false,
1898
1871
chip->phy_def->config_bb_gain, NULL);
1899
1872
1900
1873
rtw89_phy_bb_reset(rtwdev);
···
2000
1973
const struct rtw89_chip_info *chip = rtwdev->chip;
2001
1974
const struct rtw89_phy_table *rf_table;
2002
1975
struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
1976
+
bool by_acv = chip->chip_id == RTL8922D;
2003
1977
u8 path;
2004
1978
2005
1979
rf_reg_info = kzalloc_obj(*rf_reg_info);
···
2016
1988
else
2017
1989
config = rf_table->config ? rf_table->config :
2018
1990
rtw89_phy_config_rf_reg;
2019
-
rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1991
+
rtw89_phy_init_reg(rtwdev, rf_table, by_acv, config, (void *)rf_reg_info);
2020
1992
if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
2021
1993
rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
2022
1994
rf_reg_info->rf_path);
···
2057
2029
rtw89_phy_preinit_rf_nctl(rtwdev);
2058
2030
2059
2031
nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table;
2060
-
rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
2032
+
rtw89_phy_init_reg(rtwdev, nctl_table, false, rtw89_phy_config_bb_reg, NULL);
2061
2033
2062
2034
if (chip->nctl_post_table)
2063
2035
rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
···
3214
3186
3215
3187
static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
3216
3188
struct ieee80211_link_sta *link_sta,
3217
-
struct rtw89_phy_iter_ra_data *ra_data)
3189
+
struct rtw89_phy_iter_ra_data *ra_data,
3190
+
bool *changed)
3218
3191
{
3219
3192
struct rtw89_dev *rtwdev = ra_data->rtwdev;
3220
3193
const struct rtw89_c2h_ra_rpt *c2h =
···
3224
3195
const struct rtw89_chip_info *chip = rtwdev->chip;
3225
3196
bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
3226
3197
u8 mode, rate, bw, giltf, mac_id;
3227
-
u16 legacy_bitrate;
3198
+
u16 legacy_bitrate, amsdu_len;
3228
3199
bool valid;
3229
3200
u8 mcs = 0;
3230
3201
u8 t;
···
3321
3292
u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
3322
3293
u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
3323
3294
ra_report->might_fallback_legacy = mcs <= 2;
3324
-
link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
3295
+
3296
+
amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
3297
+
if (link_sta->agg.max_rc_amsdu_len != amsdu_len) {
3298
+
link_sta->agg.max_rc_amsdu_len = amsdu_len;
3299
+
*changed = true;
3300
+
}
3301
+
3325
3302
rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1;
3326
3303
}
3327
3304
···
3338
3303
struct rtw89_sta_link *rtwsta_link;
3339
3304
struct ieee80211_link_sta *link_sta;
3340
3305
unsigned int link_id;
3306
+
bool changed = false;
3341
3307
3342
3308
rcu_read_lock();
3343
3309
3344
3310
rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
3345
3311
link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
3346
-
__rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data);
3312
+
__rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data, &changed);
3347
3313
}
3314
+
3315
+
if (changed)
3316
+
ieee80211_sta_recalc_aggregates(sta);
3348
3317
3349
3318
rcu_read_unlock();
3350
3319
}
···
4899
4860
{
4900
4861
struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4901
4862
const struct rtw89_chip_info *chip = rtwdev->chip;
4902
-
u8 sc_xi_val, sc_xo_val;
4863
+
u8 sc_xi_val = 0, sc_xo_val = 0;
4903
4864
4904
4865
if (!force && cfo->crystal_cap == crystal_cap)
4905
4866
return;
+5
drivers/net/wireless/realtek/rtw89/phy.h
+5
drivers/net/wireless/realtek/rtw89/phy.h
···
852
852
void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
853
853
void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev);
854
854
void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio);
855
+
void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
856
+
const struct rtw89_reg2_def *reg,
857
+
enum rtw89_rf_path rf_path,
858
+
void *extra_data);
855
859
void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
856
860
const struct rtw89_reg2_def *reg,
857
861
enum rtw89_rf_path rf_path,
···
1006
1002
void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
1007
1003
struct rtw89_sta_link *rtwsta_link,
1008
1004
u32 changed);
1005
+
void rtw89_phy_ra_recalc_agg_limit(struct rtw89_dev *rtwdev);
1009
1006
void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
1010
1007
struct ieee80211_vif *vif,
1011
1008
const struct cfg80211_bitrate_mask *mask);
+1
-1
drivers/net/wireless/realtek/rtw89/phy_be.c
+1
-1
drivers/net/wireless/realtek/rtw89/phy_be.c
···
199
199
(phy_page >= 0x240 && phy_page <= 0x24f) ||
200
200
(phy_page >= 0x260 && phy_page <= 0x26f) ||
201
201
(phy_page >= 0x2C0 && phy_page <= 0x2C9) ||
202
-
(phy_page >= 0x2E4 && phy_page <= 0x2E8) ||
202
+
(phy_page >= 0x2E0 && phy_page <= 0x2E8) ||
203
203
phy_page == 0x2EE)
204
204
ofst = 0x1000;
205
205
else
+2
drivers/net/wireless/realtek/rtw89/ps.c
+2
drivers/net/wireless/realtek/rtw89/ps.c
+283
-2
drivers/net/wireless/realtek/rtw89/reg.h
+283
-2
drivers/net/wireless/realtek/rtw89/reg.h
···
4291
4291
#define B_BE_VERIFY_ENV_MASK GENMASK(9, 8)
4292
4292
#define B_BE_HW_ID_MASK GENMASK(7, 0)
4293
4293
4294
+
#define R_BE_SCOREBOARD_0 0x0110
4295
+
#define B_BE_SB0_TOGGLE BIT(31)
4296
+
#define B_BE_SB0_WL_DATA_LINE_MASK GENMASK(30, 0)
4297
+
4298
+
#define R_BE_SCOREBOARD_0_BT_DATA 0x0114
4299
+
#define B_BE_SB0_BT_DATA_LINE_MASK GENMASK(30, 0)
4300
+
4301
+
#define R_BE_SCOREBOARD_1 0x0118
4302
+
#define B_BE_SB1_TOGGLE BIT(31)
4303
+
#define B_BE_SB1_WL_DATA_LINE_MASK GENMASK(30, 0)
4304
+
4305
+
#define R_BE_SCOREBOARD_1_BT_DATA 0x011C
4306
+
#define B_BE_SB1_BT_DATA_LINE_MASK GENMASK(30, 0)
4307
+
4294
4308
#define R_BE_HALT_H2C_CTRL 0x0160
4295
4309
#define B_BE_HALT_H2C_TRIGGER BIT(0)
4296
4310
···
4417
4403
#define B_BE_FS_GPIO17_INT_EN BIT(1)
4418
4404
#define B_BE_FS_GPIO16_INT_EN BIT(0)
4419
4405
4406
+
#define R_BE_FWS1ISR 0x019C
4407
+
#define B_BE_FS_WL_HW_RADIO_OFF_INT BIT(28)
4408
+
#define B_BE_SWRD_BOD_INT BIT(27)
4409
+
#define B_BE_HCIDBG_INT BIT(25)
4410
+
#define B_BE_FS_RPWM_INT_V1 BIT(24)
4411
+
#define B_BE_PCIE_HOTRST BIT(22)
4412
+
#define B_BE_PCIE_SER_TIMEOUT_INDIC BIT(21)
4413
+
#define B_BE_PCIE_RXI300_SLVTOUT_INDIC BIT(20)
4414
+
#define B_BE_AON_PCIE_FLR_INT BIT(19)
4415
+
#define B_BE_PCIE_ERR_INDIC BIT(18)
4416
+
#define B_BE_SDIO_ERR_INDIC BIT(17)
4417
+
#define B_BE_USB_ERR_INDIC BIT(16)
4418
+
#define B_BE_FS_GPIO27_INT BIT(11)
4419
+
#define B_BE_FS_GPIO26_INT BIT(10)
4420
+
#define B_BE_FS_GPIO25_INT BIT(9)
4421
+
#define B_BE_FS_GPIO24_INT BIT(8)
4422
+
#define B_BE_FS_GPIO23_INT BIT(7)
4423
+
#define B_BE_FS_GPIO22_INT BIT(6)
4424
+
#define B_BE_FS_GPIO21_INT BIT(5)
4425
+
#define B_BE_FS_GPIO20_INT BIT(4)
4426
+
#define B_BE_FS_GPIO19_INT BIT(3)
4427
+
#define B_BE_FS_GPIO18_INT BIT(2)
4428
+
#define B_BE_FS_GPIO17_INT BIT(1)
4429
+
#define B_BE_FS_GPIO16_INT BIT(0)
4430
+
4420
4431
#define R_BE_HIMR0 0x01A0
4421
4432
#define B_BE_WDT_DATACPU_TIMEOUT_INT_EN BIT(25)
4422
4433
#define B_BE_HALT_D2H_INT_EN BIT(24)
···
4541
4502
4542
4503
#define R_BE_UDM2 0x01F8
4543
4504
#define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0)
4505
+
4506
+
#define R_BE_SPS_DIG_ON_CTRL1 0x0204
4507
+
#define B_BE_SN_N_L_MASK GENMASK(31, 28)
4508
+
#define B_BE_SP_N_L_MASK GENMASK(27, 24)
4509
+
#define B_BE_SN_P_L_MASK GENMASK(23, 20)
4510
+
#define B_BE_SP_P_L_MASK GENMASK(19, 16)
4511
+
#define B_BE_VO_DISCHG_PWM_H BIT(15)
4512
+
#define B_BE_REG_MODE_PREDRIVER BIT(14)
4513
+
#define B_BE_VREFOCP_MASK GENMASK(13, 10)
4514
+
#define B_BE_POWOCP_L1 BIT(9)
4515
+
#define B_BE_PWM_FORCE BIT(8)
4516
+
#define B_BE_PFM_PD_RST BIT(7)
4517
+
#define B_BE_VC_PFM_RSTB BIT(6)
4518
+
#define B_BE_PFM_IN_SEL BIT(5)
4519
+
#define B_BE_VC_RSTB BIT(4)
4520
+
#define B_BE_FPWMDELAY BIT(3)
4521
+
#define B_BE_ENFPWMDELAY_H BIT(2)
4522
+
#define B_BE_REG_MOS_HALF_L BIT(1)
4523
+
#define B_BE_CURRENT_SENSE_MOS BIT(0)
4524
+
4525
+
#define R_BE_SPS_ANA_ON_CTRL1 0x0224
4526
+
#define B_BE_SN_N_L_ANA_MASK GENMASK(31, 28)
4527
+
#define B_BE_SP_N_L_ANA_MASK GENMASK(27, 24)
4528
+
#define B_BE_SN_P_L_ANA_MASK GENMASK(23, 20)
4529
+
#define B_BE_SP_P_L_ANA_MASK GENMASK(19, 16)
4530
+
#define B_BE_VO_DISCHG_PWM_H_ANA BIT(15)
4531
+
#define B_BE_REG_MODE_PREDRIVER_ANA BIT(14)
4532
+
#define B_BE_VREFOCP_ANA_MASK GENMASK(13, 10)
4533
+
#define B_BE_POWOCP_L1_ANA BIT(9)
4534
+
#define B_BE_PWM_FORCE_ANA BIT(8)
4535
+
#define B_BE_PFM_PD_RST_ANA BIT(7)
4536
+
#define B_BE_VC_PFM_RSTB_ANA BIT(6)
4537
+
#define B_BE_PFM_IN_SEL_ANA BIT(5)
4538
+
#define B_BE_VC_RSTB_ANA BIT(4)
4539
+
#define B_BE_FPWMDELAY_ANA BIT(3)
4540
+
#define B_BE_ENFPWMDELAY_H_ANA BIT(2)
4541
+
#define B_BE_REG_MOS_HALF_L_ANA BIT(1)
4542
+
#define B_BE_CURRENT_SENSE_MOS_ANA BIT(0)
4544
4543
4545
4544
#define R_BE_AFE_ON_CTRL0 0x0240
4546
4545
#define B_BE_REG_LPF_R3_3_0_MASK GENMASK(31, 29)
···
6815
6738
#define R_BE_MUEDCA_EN 0x10370
6816
6739
#define R_BE_MUEDCA_EN_C1 0x14370
6817
6740
#define B_BE_SIFS_TIMEOUT_TB_T2_MASK GENMASK(30, 24)
6741
+
#define B_BE_SIFS_MACTXEN_TB_T1_DOT05US_MASK GENMASK(23, 16)
6818
6742
#define B_BE_SIFS_MACTXEN_TB_T1_MASK GENMASK(22, 16)
6819
6743
#define B_BE_MUEDCA_WMM_SEL BIT(8)
6820
6744
#define B_BE_SET_MUEDCATIMER_TF_MASK GENMASK(5, 4)
···
8398
8320
#define B_BE_PWR_BT_VAL GENMASK(8, 0)
8399
8321
#define B_BE_PWR_FORCE_COEX_ON GENMASK(29, 27)
8400
8322
8323
+
#define R_PWR_BOOST_BE4 0x11A64
8324
+
#define B_PWR_BOOST_BE4 BIT(8)
8325
+
8401
8326
#define R_BE_PWR_TH 0x11A78
8402
8327
#define R_BE_PWR_RSSI_TARGET_LMT 0x11A84
8403
8328
···
8459
8378
#define RR_MOD_M_RXBB GENMASK(9, 5)
8460
8379
#define RR_MOD_LO_SEL BIT(1)
8461
8380
#define RR_MODOPT 0x01
8381
+
#define RR_MODOPT_V1 0x10001
8382
+
#define RR_SW_SEL BIT(19)
8462
8383
#define RR_TXG_SEL GENMASK(19, 17)
8463
8384
#define RR_MODOPT_M_TXPWR GENMASK(5, 0)
8464
8385
#define RR_WLSEL 0x02
···
8537
8454
#define RR_LUTWD0_LB GENMASK(5, 0)
8538
8455
#define RR_TM 0x42
8539
8456
#define RR_TM_TRI BIT(19)
8457
+
#define RR_TM_TRM GENMASK(17, 11)
8540
8458
#define RR_TM_VAL_V1 GENMASK(7, 0)
8541
8459
#define RR_TM_VAL GENMASK(6, 1)
8542
8460
#define RR_TM2 0x43
···
8670
8586
#define RR_LDO 0xb1
8671
8587
#define RR_LDO_SEL GENMASK(8, 6)
8672
8588
#define RR_VCO 0xb2
8589
+
#define RR_VCO_VAL GENMASK(18, 14)
8673
8590
#define RR_VCO_SEL GENMASK(9, 8)
8674
8591
#define RR_VCI 0xb3
8675
8592
#define RR_VCI_ON BIT(7)
···
8794
8709
#define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12)
8795
8710
#define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
8796
8711
#define R_MAC_PIN_SEL 0x0734
8712
+
#define R_MAC_PIN_SEL_BE4 0x20734
8797
8713
#define B_CH_IDX_SEG0 GENMASK(23, 16)
8798
8714
#define R_PLCP_HISTOGRAM 0x0738
8799
8715
#define R_PLCP_HISTOGRAM_BE_V1 0x20738
···
8823
8737
#define R_PHY_STS_BITMAP_EHT 0x0788
8824
8738
#define R_PHY_STS_BITMAP_EHT_BE4 0x20788
8825
8739
#define R_EDCCA_RPTREG_SEL_BE 0x078C
8740
+
#define R_EDCCA_RPTREG_SEL_BE4 0x2078C
8826
8741
#define B_EDCCA_RPTREG_SEL_BE_MSK GENMASK(22, 20)
8827
8742
#define R_PMAC_GNT 0x0980
8828
8743
#define B_PMAC_GNT_TXEN BIT(0)
···
8937
8850
#define R_UDP_COEEF 0x0CBC
8938
8851
#define B_UDP_COEEF BIT(19)
8939
8852
#define R_TX_COLLISION_T2R_ST_BE 0x0CC8
8853
+
#define R_TX_COLLISION_T2R_ST_BE4 0x20CC8
8940
8854
#define B_TX_COLLISION_T2R_ST_BE_M GENMASK(13, 8)
8941
8855
#define R_RXHT_MCS_LIMIT 0x0D18
8942
8856
#define B_RXHT_MCS_LIMIT GENMASK(9, 8)
···
9166
9078
#define R_P1_EN_SOUND_WO_NDP 0x2D7C
9167
9079
#define B_P1_EN_SOUND_WO_NDP BIT(1)
9168
9080
#define R_EDCCA_RPT_A_BE 0x2E38
9081
+
#define R_EDCCA_RPT_A_BE4 0x2EE30
9082
+
#define R_EDCCA_RPT_A_BE4_C1 0x2FE30
9169
9083
#define R_EDCCA_RPT_B_BE 0x2E3C
9084
+
#define R_EDCCA_RPT_B_BE4 0x2EE34
9085
+
#define R_EDCCA_RPT_B_BE4_C1 0x2FE34
9170
9086
#define R_EDCCA_RPT_P1_A_BE 0x2E40
9171
9087
#define R_EDCCA_RPT_P1_B_BE 0x2E44
9172
9088
#define R_S1_HW_SI_DIS 0x3200
···
9354
9262
#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24
9355
9263
#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8
9356
9264
#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V3 0x41C8
9265
+
#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_BE4 0x241C8
9357
9266
#define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
9358
9267
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4
9359
9268
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28
9360
9269
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC
9361
9270
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V3 0x41CC
9271
+
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_BE4 0x241CC
9362
9272
#define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
9363
9273
#define R_PATH0_RXB_INIT_V1 0x46A8
9364
9274
#define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
···
9407
9313
#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8
9408
9314
#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8
9409
9315
#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V3 0x45C8
9316
+
#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_BE4 0x245C8
9410
9317
#define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
9411
9318
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778
9412
9319
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC
9413
9320
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC
9414
9321
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V3 0x45CC
9322
+
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_BE4 0x245CC
9415
9323
#define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
9416
9324
#define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778
9417
9325
#define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
···
9434
9338
#define R_SEG0R_PD 0x481C
9435
9339
#define R_SEG0R_PD_V1 0x4860
9436
9340
#define R_SEG0R_PD_V2 0x6A74
9341
+
#define R_SEG0R_PD_BE4 0x26210
9437
9342
#define R_SEG0R_EDCCA_LVL 0x4840
9438
9343
#define R_SEG0R_EDCCA_LVL_V1 0x4884
9439
9344
#define B_EDCCA_LVL_MSK3 GENMASK(31, 24)
···
9573
9476
#define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
9574
9477
#define R_BMODE_PDTH_V1 0x4B64
9575
9478
#define R_BMODE_PDTH_V2 0x6708
9479
+
#define R_BMODE_PDTH_BE4 0x26040
9576
9480
#define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
9577
9481
#define R_BMODE_PDTH_EN_V1 0x4B74
9578
9482
#define R_BMODE_PDTH_EN_V2 0x6718
9483
+
#define R_BMODE_PDTH_EN_BE4 0x26050
9579
9484
#define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30)
9580
9485
#define R_BSS_CLR_VLD_V2 0x4EBC
9581
9486
#define B_BSS_CLR_VLD0_V2 BIT(2)
···
9752
9653
#define R_CCK_FC0INV 0x675c
9753
9654
#define B_CCK_FC0INV GENMASK(18, 0)
9754
9655
#define R_SEG0R_EDCCA_LVL_BE 0x69EC
9656
+
#define R_SEG0R_EDCCA_LVL_BE4 0x2623C
9755
9657
#define R_SEG0R_PPDU_LVL_BE 0x69F0
9658
+
#define R_SEG0R_PPDU_LVL_BE4 0x26240
9756
9659
#define R_SEGSND 0x6A14
9757
9660
#define B_SEGSND_EN BIT(31)
9758
9661
#define R_DBCC 0x6B48
···
10249
10148
#define B_TSSI_CONT_EN BIT(3)
10250
10149
#define R_P0_TXPWRB_BE 0xE61C
10251
10150
#define R_P1_TXPWRB_BE 0xE71C
10151
+
#define R_P0_TXPWRB_BE4 0x2251C
10152
+
#define R_P1_TXPWRB_BE4 0x2261C
10252
10153
#define B_TXPWRB_MAX_BE GENMASK(20, 12)
10253
10154
#define R_TSSI_MAP_OFST_P0 0xE620
10254
10155
#define R_TSSI_MAP_OFST_P1 0xE720
···
10269
10166
#define R_TSSI_K_P1 0xE7A0
10270
10167
#define B_TSSI_K_OFDM_P1 GENMASK(29, 20)
10271
10168
10169
+
#define R_BBWRAP_ELMSR_BE4 0x11974
10170
+
#define B_BBWRAP_ELMSR_EN_BE4 GENMASK(29, 28)
10272
10171
#define R_COMP_CIM3K_BE4 0x11998
10273
10172
#define B_COMP_CIM3K_OW_BE4 BIT(1)
10274
10173
#define B_COMP_CIM3K_TH_BE4 BIT(2)
···
10475
10370
#define R_BANDEDGE_DBWY_BE4 0x11AD0
10476
10371
#define B_BANDEDGE_DBW160_BE4 BIT(0)
10477
10372
10373
+
#define R_SYS_DBCC_BE4 0x20000
10374
+
#define B_SYS_DBCC_BE4 BIT(0)
10375
+
#define B_SYS_DBCC_24G_BAND_SEL_BE4 BIT(1)
10376
+
#define R_EMLSR_SWITCH_BE4 0x20044
10377
+
#define B_EMLSR_SWITCH_BE4 GENMASK(27, 12)
10378
+
#define B_EMLSR_BB_CLK_BE4 GENMASK(31, 30)
10478
10379
#define R_CHINFO_SEG_BE4 0x200B4
10479
10380
#define B_CHINFO_SEG_LEN_BE4 GENMASK(12, 10)
10480
-
#define R_STS_HDR2_PARSING_BE4 0x2070C
10481
-
#define B_STS_HDR2_PARSING_BE4 BIT(10)
10381
+
#define R_SEL_GNT_BT_RX_BE4 0x2010C
10382
+
#define B_SEL_GNT_BT_RX_PATH0_BE4 GENMASK(3, 0)
10383
+
#define B_SEL_GNT_BT_RX_PATH1_BE4 GENMASK(11, 8)
10482
10384
#define R_SW_SI_WDATA_BE4 0x20370
10483
10385
#define B_SW_SI_DATA_PATH_BE4 GENMASK(31, 28)
10484
10386
#define B_SW_SI_DATA_ADR_BE4 GENMASK(27, 20)
10485
10387
#define B_SW_SI_DATA_DAT_BE4 GENMASK(19, 0)
10486
10388
#define R_SW_SI_READ_ADDR_BE4 0x20378
10487
10389
#define B_SW_SI_READ_ADDR_BE4 GENMASK(10, 0)
10390
+
#define R_RXBW67_BE4 0x2040C
10391
+
#define B_RXBW6_BE4 GENMASK(22, 20)
10392
+
#define B_RXBW7_BE4 GENMASK(25, 23)
10393
+
#define R_RXBW_BE4 0x20410
10394
+
#define B_RXBW_BE4 GENMASK(29, 27)
10395
+
#define R_TXERRCT_EN_BE4 0x20518
10396
+
#define B_TXERRCT_EN_BE4 BIT(13)
10397
+
#define R_TXERRCT1_EN_BE4 0x2051C
10398
+
#define B_TXERRCT1_EN_BE4 BIT(31)
10399
+
#define R_ENABLE_CCK0_BE4 0x20700
10400
+
#define B_ENABLE_CCK0_BE4 BIT(5)
10401
+
#define R_RSTB_ASYNC_BE4 0x20704
10402
+
#define B_RSTB_ASYNC_BE4 BIT(1)
10403
+
#define R_STS_HDR2_PARSING_BE4 0x2070C
10404
+
#define B_STS_HDR2_PARSING_BE4 BIT(10)
10405
+
#define R_EDCCA_RPT_SEL_BE4 0x20780
10406
+
#define R_EDCCA_RPT_SEL_BE4_C1 0x21780
10407
+
#define B_EDCCA_RPT_SEL_BE4_MSK 0xE0000
10408
+
#define R_SEL_GNT_BT_RXPHY_BE4 0x2079C
10409
+
#define B_SEL_GNT_BT_RXPHY_BE4 GENMASK(11, 8)
10410
+
#define R_IMR_TX_ERROR_BE4 0x20920
10411
+
#define B_IMR_TX_ERROR_BE4 BIT(30)
10412
+
#define R_TXINFO_PATH_BE4 0x209A4
10413
+
#define B_TXINFO_PATH_EN_BE4 BIT(17)
10414
+
#define B_TXINFO_PATH_MA_BE4 BIT(18)
10415
+
#define B_TXINFO_PATH_MB_BE4 BIT(19)
10416
+
#define R_SHAPER_COEFF_BE4 0x20CBC
10417
+
#define B_SHAPER_COEFF_BE4 BIT(19)
10488
10418
#define R_IFS_T1_AVG_BE4 0x20EDC
10489
10419
#define B_IFS_T1_AVG_BE4 GENMASK(15, 0)
10490
10420
#define B_IFS_T2_AVG_BE4 GENMASK(31, 16)
···
10542
10402
#define B_IFS_T3_HIS_BE4 GENMASK(15, 0)
10543
10403
#define B_IFS_T4_HIS_BE4 GENMASK(31, 16)
10544
10404
10405
+
#define R_TX_ERROR_SEL_BE4 0x21254
10406
+
#define B_TX_ERROR_PSDU_BE4 BIT(11)
10407
+
#define B_TX_ERROR_NSYM_BE4 BIT(10)
10408
+
#define B_TX_ERROR_LSIG_BE4 BIT(9)
10409
+
#define B_TX_ERROR_TXINFO_BE4 BIT(8)
10410
+
10411
+
#define R_TXPWR_RSTB0_BE4 0x2250C
10412
+
#define B_TXPWR_RSTB0_BE4 BIT(16)
10413
+
#define R_TSSI_EN_P0_BE4 0x22510
10414
+
#define B_TSSI_EN_P0_BE4 GENMASK(3, 0)
10415
+
#define R_TXAGC_REF_DBM_PATH0_TBL0_BE4 0x22528
10416
+
#define B_TXAGC_OFDM_REF_DBM_PATH0_TBL0_BE4 GENMASK(8, 0)
10417
+
#define B_TXAGC_CCK_REF_DBM_PATH0_TBL0_BE4 GENMASK(17, 9)
10418
+
#define R_USED_TSSI_TRK_ON_P0_BE4 0x22534
10419
+
#define B_USED_TSSI_TRK_ON_P0_BE4 BIT(22)
10420
+
#define R_TSSI_K_OFDM_PATH0_TBL0_BE4 0x225A0
10421
+
#define B_TSSI_K_OFDM_PATH0_TBL0_BE4 GENMASK(29, 20)
10422
+
#define R_TSSI_DCK_MOV_AVG_LEN_P0_BE4 0x225CC
10423
+
#define B_TSSI_DCK_MOV_AVG_LEN_P0_BE4 GENMASK(8, 6)
10424
+
#define R_TXPWR_RSTB1_BE4 0x2260C
10425
+
#define B_TXPWR_RSTB1_BE4 BIT(16)
10426
+
10427
+
#define R_TXAGC_REF_DBM_PATH0_TBL1_BE4 0x23528
10428
+
#define B_TXAGC_OFDM_REF_DBM_PATH0_TBL1_BE4 GENMASK(8, 0)
10429
+
#define B_TXAGC_CCK_REF_DBM_PATH0_TBL1_BE4 GENMASK(17, 9)
10430
+
#define R_TSSI_K_OFDM_PATH0_TBL1_BE4 0x235A0
10431
+
#define B_TSSI_K_OFDM_PATH0_TBL1_BE4 GENMASK(29, 20)
10432
+
10433
+
#define R_OFDM_OFST_P0_BE4 0x240C8
10434
+
#define B_OFDM_OFST_P0_BE4 GENMASK(31, 24)
10435
+
#define R_PATH0_RXIDX_INIT_BE4 0x24108
10436
+
#define B_PATH0_RXIDX_INIT_BE4 GENMASK(29, 25)
10437
+
#define R_PATH0_LNA_INIT_BE4 0x24158
10438
+
#define B_PATH0_LNA_INIT_IDX_BE4 GENMASK(14, 12)
10439
+
#define R_BAND_SEL0_BE4 0x24160
10440
+
#define B_BAND_SEL0_BE4 BIT(26)
10441
+
#define R_PATH0_TIA_INIT_BE4 0x24168
10442
+
#define B_PATH0_TIA_INIT_IDX_BE4 BIT(18)
10443
+
#define R_OFDM_RPL_BIAS_P0_BE4 0x2420C
10444
+
#define B_OFDM_RPL_BIAS_P0_BE4 GENMASK(11, 2)
10445
+
#define R_OFDM_OFST_P1_BE4 0x244C8
10446
+
#define B_OFDM_OFST_P1_BE4 GENMASK(31, 24)
10447
+
#define R_PATH1_RXIDX_INIT_BE4 0x24508
10448
+
#define B_PATH1_RXIDX_INIT_BE4 GENMASK(29, 25)
10449
+
#define R_PATH1_LNA_INIT_BE4 0x24558
10450
+
#define B_PATH1_LNA_INIT_IDX_BE4 GENMASK(14, 12)
10451
+
#define R_BAND_SEL1_BE4 0x24560
10452
+
#define B_BAND_SEL1_BE4 BIT(26)
10453
+
#define R_PATH1_TIA_INIT_BE4 0x24568
10454
+
#define B_PATH1_TIA_INIT_IDX_BE4 BIT(18)
10455
+
#define R_OFDM_RPL_BIAS_P1_BE4 0x2460C
10456
+
#define B_OFDM_RPL_BIAS_P1_BE4 GENMASK(11, 2)
10545
10457
#define R_TX_CFR_MANUAL_EN_BE4 0x2483C
10546
10458
#define B_TX_CFR_MANUAL_EN_BE4_M BIT(30)
10459
+
#define R_PCOEFF0_BE4 0x24880
10460
+
#define B_PCOEFF01_BE4 GENMASK(23, 0)
10461
+
#define R_PCOEFF2_BE4 0x24884
10462
+
#define B_PCOEFF23_BE4 GENMASK(23, 0)
10463
+
#define R_PCOEFF4_BE4 0x24888
10464
+
#define B_PCOEFF45_BE4 GENMASK(23, 0)
10465
+
#define R_PCOEFF6_BE4 0x2488C
10466
+
#define B_PCOEFF67_BE4 GENMASK(23, 0)
10467
+
#define R_PCOEFF8_BE4 0x24890
10468
+
#define B_PCOEFF89_BE4 GENMASK(23, 0)
10469
+
#define R_PCOEFF10_BE4 0x24894
10470
+
#define B_PCOEFF10_BE4 GENMASK(23, 0)
10471
+
#define R_PCOEFF12_BE4 0x24898
10472
+
#define B_PCOEFF12_BE4 GENMASK(23, 0)
10473
+
#define R_PCOEFF14_BE4 0x2489C
10474
+
#define B_PCOEFF14_BE4 GENMASK(23, 0)
10475
+
#define R_BW_BE4 0x24EE4
10476
+
#define B_BW_BE4 GENMASK(6, 4)
10477
+
#define B_PRISB_BE4 GENMASK(3, 0)
10478
+
#define R_FC0_BE4 0x24EE8
10479
+
#define B_FC0_BE4 GENMASK(12, 0)
10480
+
#define R_ANT_RX_1RCCA_BE4 0x24EEC
10481
+
#define B_ANT_RX_1RCCA_BE4 GENMASK(17, 14)
10482
+
#define R_ANT_RX_BE4 0x24EF0
10483
+
#define B_ANT_RX_BE4 GENMASK(3, 0)
10484
+
#define R_FC0_INV_BE4 0x24EF4
10485
+
#define B_FC0_INV_BE4 GENMASK(15, 0)
10547
10486
10487
+
#define R_CCK_RPL_OFST_BE4 0x26084
10488
+
#define B_CCK_RPL_OFST_BE4 GENMASK(7, 0)
10489
+
#define R_BK_FC0_INV_BE4 0x2608C
10490
+
#define B_BK_FC0_INV_BE4 GENMASK(18, 0)
10491
+
#define R_CCK_FC0_INV_BE4 0x26090
10492
+
#define B_CCK_FC0_INV_BE4 GENMASK(18, 0)
10493
+
#define R_GAIN_BIAS_BE4 0x260A0
10494
+
#define B_GAIN_BIAS_BW20_BE4 GENMASK(11, 6)
10495
+
#define B_GAIN_BIAS_BW40_BE4 GENMASK(17, 12)
10496
+
#define R_AWGN_DET_BE4 0x2668C
10497
+
#define B_AWGN_DET_BE4 GENMASK(17, 9)
10498
+
#define R_CSI_WGT_BE4 0x26770
10499
+
#define B_CSI_WGT_EN_BE4 BIT(0)
10500
+
#define B_CSI_WGT_IDX_BE4 GENMASK(31, 20)
10548
10501
#define R_CHINFO_OPT_BE4 0x267C8
10549
10502
#define B_CHINFO_OPT_BE4 GENMASK(14, 13)
10550
10503
#define R_CHINFO_NX_BE4 0x267D0
10551
10504
#define B_CHINFO_NX_BE4 GENMASK(16, 6)
10552
10505
#define R_CHINFO_ALG_BE4 0x267C8
10553
10506
#define B_CHINFO_ALG_BE4 GENMASK(31, 30)
10507
+
#define R_RX_AWGN02_BE4 0x2680C
10508
+
#define B_RX_AWGN11_BE4 GENMASK(23, 18)
10509
+
#define R_RX_AWGN00_BE4 0x26814
10510
+
#define B_RX_AWGN04_BE4 GENMASK(5, 0)
10511
+
#define B_RX_AWGN07_BE4 GENMASK(23, 18)
10512
+
#define R_RX_AWGN01_BE4 0x26818
10513
+
#define B_RX_AWGN09_BE4 GENMASK(5, 0)
10514
+
#define R_RXCH_BCC0_BE4 0x26824
10515
+
#define B_RXCH_MCS4_BE4 GENMASK(29, 24)
10516
+
#define R_RXCH_BCC1_BE4 0x26828
10517
+
#define B_RXCH_MCS5_BE4 GENMASK(5, 0)
10518
+
#define B_RXCH_MCS6_BE4 GENMASK(11, 6)
10519
+
#define B_RXCH_MCS7_BE4 GENMASK(17, 12)
10520
+
#define B_RXCH_MCS8_BE4 GENMASK(23, 18)
10521
+
#define B_RXCH_MCS9_BE4 GENMASK(29, 24)
10522
+
#define R_RX_LDPC02_BE4 0x26834
10523
+
#define B_RX_LDPC10_BE4 GENMASK(17, 12)
10524
+
#define B_RX_LDPC11_BE4 GENMASK(23, 18)
10525
+
#define R_RX_LDPC00_BE4 0x2683C
10526
+
#define B_RX_LDPC04_BE4 GENMASK(5, 0)
10527
+
#define B_RX_LDPC05_BE4 GENMASK(11, 6)
10528
+
#define B_RX_LDPC06_BE4 GENMASK(17, 12)
10529
+
#define B_RX_LDPC07_BE4 GENMASK(23, 18)
10530
+
#define B_RX_LDPC08_BE4 GENMASK(29, 24)
10531
+
#define R_RX_LDPC01_BE4 0x26840
10532
+
#define B_RX_LDPC09_BE4 GENMASK(5, 0)
10533
+
#define R_BSS_CLR_MAP_BE4 0x26914
10534
+
#define R_BSS_CLR_VLD_BE4 0x26920
10535
+
#define B_BSS_CLR_VLD_BE4 BIT(2)
10554
10536
10555
10537
#define R_SW_SI_DATA_BE4 0x2CF4C
10556
10538
#define B_SW_SI_READ_DATA_BE4 GENMASK(19, 0)
10557
10539
#define B_SW_SI_W_BUSY_BE4 BIT(24)
10558
10540
#define B_SW_SI_R_BUSY_BE4 BIT(25)
10559
10541
#define B_SW_SI_READ_DATA_DONE_BE4 BIT(26)
10542
+
10543
+
#define R_RX_PATH0_TBL0_BE4 0x2E028
10544
+
#define R_RX_PATH1_TBL0_BE4 0x2E128
10545
+
10546
+
#define R_KTBL0A_BE4 0x38104
10547
+
#define R_KTBL0B_BE4 0x38204
10548
+
#define B_KTBL0_IDX0 GENMASK(1, 0)
10549
+
#define B_KTBL0_IDX1 GENMASK(9, 8)
10550
+
#define B_KTBL0_RST BIT(31)
10551
+
#define R_KTBL1A_BE4 0x38154
10552
+
#define R_KTBL1B_BE4 0x38254
10553
+
#define B_KTBL1_TBL0 BIT(3)
10554
+
#define B_KTBL1_TBL1 BIT(5)
10555
+
10556
+
#define R_TC_EN_BE4 0x3c200
10557
+
#define B_TC_EN_BE4 BIT(0)
10558
+
#define B_TC_TRIG_BE4 BIT(1)
10559
+
#define R_TC_VAL_BE4 0x3c208
10560
+
#define B_TC_VAL_BE4 GENMASK(7, 0)
10560
10561
10561
10562
/* WiFi CPU local domain */
10562
10563
#define R_AX_WDT_CTRL 0x0040
+28
-21
drivers/net/wireless/realtek/rtw89/rtw8851b.c
+28
-21
drivers/net/wireless/realtek/rtw89/rtw8851b.c
···
15
15
#include "txrx.h"
16
16
#include "util.h"
17
17
18
-
#define RTW8851B_FW_FORMAT_MAX 0
18
+
#define RTW8851B_FW_FORMAT_MAX 1
19
19
#define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw"
20
20
#define RTW8851B_MODULE_FIRMWARE \
21
-
RTW8851B_FW_BASENAME ".bin"
21
+
RTW89_GEN_MODULE_FWNAME(RTW8851B_FW_BASENAME, RTW8851B_FW_FORMAT_MAX)
22
22
23
23
static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = {
24
24
{5, 343, grp_0}, /* ACH 0 */
···
52
52
};
53
53
54
54
static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_usb[] = {
55
-
{18, 152, grp_0}, /* ACH 0 */
56
-
{18, 152, grp_0}, /* ACH 1 */
57
-
{18, 152, grp_0}, /* ACH 2 */
58
-
{18, 152, grp_0}, /* ACH 3 */
55
+
{18, 210, grp_0}, /* ACH 0 */
56
+
{18, 210, grp_0}, /* ACH 1 */
57
+
{18, 210, grp_0}, /* ACH 2 */
58
+
{18, 210, grp_0}, /* ACH 3 */
59
59
{0, 0, grp_0}, /* ACH 4 */
60
60
{0, 0, grp_0}, /* ACH 5 */
61
61
{0, 0, grp_0}, /* ACH 6 */
62
62
{0, 0, grp_0}, /* ACH 7 */
63
-
{18, 152, grp_0}, /* B0MGQ */
64
-
{18, 152, grp_0}, /* B0HIQ */
63
+
{18, 210, grp_0}, /* B0MGQ */
64
+
{18, 210, grp_0}, /* B0HIQ */
65
65
{0, 0, grp_0}, /* B1MGQ */
66
66
{0, 0, grp_0}, /* B1HIQ */
67
67
{0, 0, 0} /* FWCMDQ */
68
68
};
69
69
70
70
static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_usb = {
71
-
152, /* Group 0 */
71
+
210, /* Group 0 */
72
72
0, /* Group 1 */
73
-
152, /* Public Max */
73
+
210, /* Public Max */
74
74
0 /* WP threshold */
75
75
};
76
76
···
111
111
};
112
112
113
113
static const struct rtw89_dle_mem rtw8851b_dle_mem_usb2[] = {
114
-
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
115
-
&rtw89_mac_size.ple_size32, &rtw89_mac_size.wde_qt25,
116
-
&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt72,
117
-
&rtw89_mac_size.ple_qt73},
114
+
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
115
+
&rtw89_mac_size.ple_size27, &rtw89_mac_size.wde_qt30,
116
+
&rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt61,
117
+
&rtw89_mac_size.ple_qt62},
118
118
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
119
119
&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
120
120
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
···
124
124
};
125
125
126
126
static const struct rtw89_dle_mem rtw8851b_dle_mem_usb3[] = {
127
-
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
128
-
&rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25,
129
-
&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74,
130
-
&rtw89_mac_size.ple_qt75},
127
+
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
128
+
&rtw89_mac_size.ple_size31, &rtw89_mac_size.wde_qt30,
129
+
&rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt27,
130
+
&rtw89_mac_size.ple_qt28},
131
131
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
132
132
&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
133
133
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
···
2580
2580
.ops = &rtw8851b_chip_ops,
2581
2581
.mac_def = &rtw89_mac_gen_ax,
2582
2582
.phy_def = &rtw89_phy_gen_ax,
2583
-
.fw_basename = RTW8851B_FW_BASENAME,
2584
-
.fw_format_max = RTW8851B_FW_FORMAT_MAX,
2583
+
.fw_def = {
2584
+
.fw_basename = RTW8851B_FW_BASENAME,
2585
+
.fw_format_max = RTW8851B_FW_FORMAT_MAX,
2586
+
.fw_b_aid = 0,
2587
+
},
2585
2588
.try_ce_fw = true,
2586
2589
.bbmcu_nr = 0,
2587
2590
.needed_fw_elms = 0,
···
2641
2638
.support_noise = false,
2642
2639
.ul_tb_waveform_ctrl = true,
2643
2640
.ul_tb_pwr_diff = false,
2644
-
.rx_freq_frome_ie = true,
2641
+
.rx_freq_from_ie = true,
2645
2642
.hw_sec_hdr = false,
2646
2643
.hw_mgmt_tx_encrypt = false,
2647
2644
.hw_tkip_crypto = false,
···
2681
2678
.rf_para_ulink = rtw89_btc_8851b_rf_ul,
2682
2679
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_dl),
2683
2680
.rf_para_dlink = rtw89_btc_8851b_rf_dl,
2681
+
.rf_para_ulink_v9 = NULL,
2682
+
.rf_para_dlink_v9 = NULL,
2683
+
.rf_para_ulink_num_v9 = 0,
2684
+
.rf_para_dlink_num_v9 = 0,
2684
2685
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2685
2686
BIT(RTW89_PS_MODE_CLK_GATED),
2686
2687
.low_power_hci_modes = 0,
+1
drivers/net/wireless/realtek/rtw89/rtw8851bu.c
+1
drivers/net/wireless/realtek/rtw89/rtw8851bu.c
+63
-5
drivers/net/wireless/realtek/rtw89/rtw8852a.c
+63
-5
drivers/net/wireless/realtek/rtw89/rtw8852a.c
···
12
12
#include "rtw8852a_table.h"
13
13
#include "txrx.h"
14
14
15
-
#define RTW8852A_FW_FORMAT_MAX 0
15
+
#define RTW8852A_FW_FORMAT_MAX 1
16
16
#define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw"
17
17
#define RTW8852A_MODULE_FIRMWARE \
18
-
RTW8852A_FW_BASENAME ".bin"
18
+
RTW89_GEN_MODULE_FWNAME(RTW8852A_FW_BASENAME, RTW8852A_FW_FORMAT_MAX)
19
19
20
20
static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
21
21
{128, 1896, grp_0}, /* ACH 0 */
···
2179
2179
rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2180
2180
}
2181
2181
2182
+
#define DECLARE_DIG_TABLE(name) \
2183
+
static const struct rtw89_phy_dig_gain_cfg name##_table = { \
2184
+
.table = name, \
2185
+
.size = ARRAY_SIZE(name) \
2186
+
}
2187
+
2188
+
static const struct rtw89_reg_def rtw89_8852a_lna_gain_g[] = {
2189
+
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_G_MSK},
2190
+
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G1_G_MSK},
2191
+
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_G_MSK},
2192
+
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_G_MSK},
2193
+
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_G_MSK},
2194
+
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_G_MSK},
2195
+
{R_PATH0_LNA_ERR5, B_PATH0_LNA_ERR_G6_G_MSK},
2196
+
};
2197
+
2198
+
DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_g);
2199
+
2200
+
static const struct rtw89_reg_def rtw89_8852a_tia_gain_g[] = {
2201
+
{R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_G_MSK},
2202
+
{R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_G_MSK},
2203
+
};
2204
+
2205
+
DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_g);
2206
+
2207
+
static const struct rtw89_reg_def rtw89_8852a_lna_gain_a[] = {
2208
+
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_A_MSK},
2209
+
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G1_A_MSK},
2210
+
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_A_MSK},
2211
+
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_A_MSK},
2212
+
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_A_MSK},
2213
+
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_A_MSK},
2214
+
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G6_A_MSK},
2215
+
};
2216
+
2217
+
DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_a);
2218
+
2219
+
static const struct rtw89_reg_def rtw89_8852a_tia_gain_a[] = {
2220
+
{R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_A_MSK},
2221
+
{R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_A_MSK},
2222
+
};
2223
+
2224
+
DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_a);
2225
+
2226
+
static const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table = {
2227
+
.cfg_lna_g = &rtw89_8852a_lna_gain_g_table,
2228
+
.cfg_tia_g = &rtw89_8852a_tia_gain_g_table,
2229
+
.cfg_lna_a = &rtw89_8852a_lna_gain_a_table,
2230
+
.cfg_tia_a = &rtw89_8852a_tia_gain_a_table
2231
+
};
2232
+
2182
2233
#ifdef CONFIG_PM
2183
2234
static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
2184
2235
.flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
···
2316
2265
.ops = &rtw8852a_chip_ops,
2317
2266
.mac_def = &rtw89_mac_gen_ax,
2318
2267
.phy_def = &rtw89_phy_gen_ax,
2319
-
.fw_basename = RTW8852A_FW_BASENAME,
2320
-
.fw_format_max = RTW8852A_FW_FORMAT_MAX,
2268
+
.fw_def = {
2269
+
.fw_basename = RTW8852A_FW_BASENAME,
2270
+
.fw_format_max = RTW8852A_FW_FORMAT_MAX,
2271
+
.fw_b_aid = 0,
2272
+
},
2321
2273
.try_ce_fw = false,
2322
2274
.bbmcu_nr = 0,
2323
2275
.needed_fw_elms = 0,
···
2378
2324
.support_noise = true,
2379
2325
.ul_tb_waveform_ctrl = false,
2380
2326
.ul_tb_pwr_diff = false,
2381
-
.rx_freq_frome_ie = true,
2327
+
.rx_freq_from_ie = true,
2382
2328
.hw_sec_hdr = false,
2383
2329
.hw_mgmt_tx_encrypt = false,
2384
2330
.hw_tkip_crypto = false,
···
2418
2364
.rf_para_ulink = rtw89_btc_8852a_rf_ul,
2419
2365
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl),
2420
2366
.rf_para_dlink = rtw89_btc_8852a_rf_dl,
2367
+
.rf_para_ulink_v9 = NULL,
2368
+
.rf_para_dlink_v9 = NULL,
2369
+
.rf_para_ulink_num_v9 = 0,
2370
+
.rf_para_dlink_num_v9 = 0,
2421
2371
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2422
2372
BIT(RTW89_PS_MODE_CLK_GATED) |
2423
2373
BIT(RTW89_PS_MODE_PWR_GATED),
-51
drivers/net/wireless/realtek/rtw89/rtw8852a_table.c
-51
drivers/net/wireless/realtek/rtw89/rtw8852a_table.c
···
50952
50952
[2][1][RTW89_UK][46] = 32,
50953
50953
};
50954
50954
50955
-
#define DECLARE_DIG_TABLE(name) \
50956
-
static const struct rtw89_phy_dig_gain_cfg name##_table = { \
50957
-
.table = name, \
50958
-
.size = ARRAY_SIZE(name) \
50959
-
}
50960
-
50961
-
static const struct rtw89_reg_def rtw89_8852a_lna_gain_g[] = {
50962
-
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_G_MSK},
50963
-
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G1_G_MSK},
50964
-
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_G_MSK},
50965
-
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_G_MSK},
50966
-
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_G_MSK},
50967
-
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_G_MSK},
50968
-
{R_PATH0_LNA_ERR5, B_PATH0_LNA_ERR_G6_G_MSK},
50969
-
};
50970
-
50971
-
DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_g);
50972
-
50973
-
static const struct rtw89_reg_def rtw89_8852a_tia_gain_g[] = {
50974
-
{R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_G_MSK},
50975
-
{R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_G_MSK},
50976
-
};
50977
-
50978
-
DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_g);
50979
-
50980
-
static const struct rtw89_reg_def rtw89_8852a_lna_gain_a[] = {
50981
-
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_A_MSK},
50982
-
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G1_A_MSK},
50983
-
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_A_MSK},
50984
-
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_A_MSK},
50985
-
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_A_MSK},
50986
-
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_A_MSK},
50987
-
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G6_A_MSK},
50988
-
};
50989
-
50990
-
DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_a);
50991
-
50992
-
static const struct rtw89_reg_def rtw89_8852a_tia_gain_a[] = {
50993
-
{R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_A_MSK},
50994
-
{R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_A_MSK},
50995
-
};
50996
-
50997
-
DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_a);
50998
-
50999
50955
const struct rtw89_phy_table rtw89_8852a_phy_bb_table = {
51000
50956
.regs = rtw89_8852a_phy_bb_regs,
51001
50957
.n_regs = ARRAY_SIZE(rtw89_8852a_phy_bb_regs),
···
50996
51040
.delta_swingidx_2g_cck_b_p = _txpwr_track_delta_swingidx_2g_cck_b_p,
50997
51041
.delta_swingidx_2g_cck_a_n = _txpwr_track_delta_swingidx_2g_cck_a_n,
50998
51042
.delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p,
50999
-
};
51000
-
51001
-
const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table = {
51002
-
.cfg_lna_g = &rtw89_8852a_lna_gain_g_table,
51003
-
.cfg_tia_g = &rtw89_8852a_tia_gain_g_table,
51004
-
.cfg_lna_a = &rtw89_8852a_lna_gain_a_table,
51005
-
.cfg_tia_a = &rtw89_8852a_tia_gain_a_table
51006
51043
};
51007
51044
51008
51045
const struct rtw89_rfe_parms rtw89_8852a_dflt_parms = {
-1
drivers/net/wireless/realtek/rtw89/rtw8852a_table.h
-1
drivers/net/wireless/realtek/rtw89/rtw8852a_table.h
···
11
11
extern const struct rtw89_phy_table rtw89_8852a_phy_radioa_table;
12
12
extern const struct rtw89_phy_table rtw89_8852a_phy_radiob_table;
13
13
extern const struct rtw89_phy_table rtw89_8852a_phy_nctl_table;
14
-
extern const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table;
15
14
extern const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg;
16
15
extern const struct rtw89_rfe_parms rtw89_8852a_dflt_parms;
17
16
+1
drivers/net/wireless/realtek/rtw89/rtw8852au.c
+1
drivers/net/wireless/realtek/rtw89/rtw8852au.c
+24
-17
drivers/net/wireless/realtek/rtw89/rtw8852b.c
+24
-17
drivers/net/wireless/realtek/rtw89/rtw8852b.c
···
13
13
#include "rtw8852b_table.h"
14
14
#include "txrx.h"
15
15
16
-
#define RTW8852B_FW_FORMAT_MAX 1
16
+
#define RTW8852B_FW_FORMAT_MAX 2
17
17
#define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw"
18
18
#define RTW8852B_MODULE_FIRMWARE \
19
-
RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin"
19
+
RTW89_GEN_MODULE_FWNAME(RTW8852B_FW_BASENAME, RTW8852B_FW_FORMAT_MAX)
20
20
21
21
static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = {
22
22
{5, 341, grp_0}, /* ACH 0 */
···
50
50
};
51
51
52
52
static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_usb[] = {
53
-
{18, 152, grp_0}, /* ACH 0 */
54
-
{18, 152, grp_0}, /* ACH 1 */
55
-
{18, 152, grp_0}, /* ACH 2 */
56
-
{18, 152, grp_0}, /* ACH 3 */
53
+
{18, 210, grp_0}, /* ACH 0 */
54
+
{18, 210, grp_0}, /* ACH 1 */
55
+
{18, 210, grp_0}, /* ACH 2 */
56
+
{18, 210, grp_0}, /* ACH 3 */
57
57
{0, 0, grp_0}, /* ACH 4 */
58
58
{0, 0, grp_0}, /* ACH 5 */
59
59
{0, 0, grp_0}, /* ACH 6 */
60
60
{0, 0, grp_0}, /* ACH 7 */
61
-
{18, 152, grp_0}, /* B0MGQ */
62
-
{18, 152, grp_0}, /* B0HIQ */
61
+
{18, 210, grp_0}, /* B0MGQ */
62
+
{18, 210, grp_0}, /* B0HIQ */
63
63
{0, 0, grp_0}, /* B1MGQ */
64
64
{0, 0, grp_0}, /* B1HIQ */
65
65
{0, 0, 0} /* FWCMDQ */
66
66
};
67
67
68
68
static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_usb = {
69
-
152, /* Group 0 */
69
+
210, /* Group 0 */
70
70
0, /* Group 1 */
71
-
152, /* Public Max */
71
+
210, /* Public Max */
72
72
0 /* WP threshold */
73
73
};
74
74
···
109
109
};
110
110
111
111
static const struct rtw89_dle_mem rtw8852b_dle_mem_usb3[] = {
112
-
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
113
-
&rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25,
114
-
&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74,
115
-
&rtw89_mac_size.ple_qt75},
112
+
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
113
+
&rtw89_mac_size.ple_size31, &rtw89_mac_size.wde_qt30,
114
+
&rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt27,
115
+
&rtw89_mac_size.ple_qt28},
116
116
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
117
117
&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
118
118
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
···
911
911
.ops = &rtw8852b_chip_ops,
912
912
.mac_def = &rtw89_mac_gen_ax,
913
913
.phy_def = &rtw89_phy_gen_ax,
914
-
.fw_basename = RTW8852B_FW_BASENAME,
915
-
.fw_format_max = RTW8852B_FW_FORMAT_MAX,
914
+
.fw_def = {
915
+
.fw_basename = RTW8852B_FW_BASENAME,
916
+
.fw_format_max = RTW8852B_FW_FORMAT_MAX,
917
+
.fw_b_aid = 0,
918
+
},
916
919
.try_ce_fw = true,
917
920
.bbmcu_nr = 0,
918
921
.needed_fw_elms = 0,
···
974
971
.support_noise = false,
975
972
.ul_tb_waveform_ctrl = true,
976
973
.ul_tb_pwr_diff = false,
977
-
.rx_freq_frome_ie = true,
974
+
.rx_freq_from_ie = true,
978
975
.hw_sec_hdr = false,
979
976
.hw_mgmt_tx_encrypt = false,
980
977
.hw_tkip_crypto = false,
···
1014
1011
.rf_para_ulink = rtw89_btc_8852b_rf_ul,
1015
1012
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl),
1016
1013
.rf_para_dlink = rtw89_btc_8852b_rf_dl,
1014
+
.rf_para_ulink_v9 = NULL,
1015
+
.rf_para_dlink_v9 = NULL,
1016
+
.rf_para_ulink_num_v9 = 0,
1017
+
.rf_para_dlink_num_v9 = 0,
1017
1018
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
1018
1019
BIT(RTW89_PS_MODE_CLK_GATED) |
1019
1020
BIT(RTW89_PS_MODE_PWR_GATED),
+11
-4
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
+11
-4
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
···
14
14
#define RTW8852BT_FW_FORMAT_MAX 0
15
15
#define RTW8852BT_FW_BASENAME "rtw89/rtw8852bt_fw"
16
16
#define RTW8852BT_MODULE_FIRMWARE \
17
-
RTW8852BT_FW_BASENAME ".bin"
17
+
RTW89_GEN_MODULE_FWNAME(RTW8852BT_FW_BASENAME, RTW8852BT_FW_FORMAT_MAX)
18
18
19
19
static const struct rtw89_hfc_ch_cfg rtw8852bt_hfc_chcfg_pcie[] = {
20
20
{16, 742, grp_0}, /* ACH 0 */
···
757
757
.ops = &rtw8852bt_chip_ops,
758
758
.mac_def = &rtw89_mac_gen_ax,
759
759
.phy_def = &rtw89_phy_gen_ax,
760
-
.fw_basename = RTW8852BT_FW_BASENAME,
761
-
.fw_format_max = RTW8852BT_FW_FORMAT_MAX,
760
+
.fw_def = {
761
+
.fw_basename = RTW8852BT_FW_BASENAME,
762
+
.fw_format_max = RTW8852BT_FW_FORMAT_MAX,
763
+
.fw_b_aid = 0,
764
+
},
762
765
.try_ce_fw = true,
763
766
.bbmcu_nr = 0,
764
767
.needed_fw_elms = RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ,
···
813
810
.support_sar_by_ant = true,
814
811
.ul_tb_waveform_ctrl = true,
815
812
.ul_tb_pwr_diff = false,
816
-
.rx_freq_frome_ie = true,
813
+
.rx_freq_from_ie = true,
817
814
.hw_sec_hdr = false,
818
815
.hw_mgmt_tx_encrypt = false,
819
816
.hw_tkip_crypto = true,
···
853
850
.rf_para_ulink = rtw89_btc_8852bt_rf_ul,
854
851
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852bt_rf_dl),
855
852
.rf_para_dlink = rtw89_btc_8852bt_rf_dl,
853
+
.rf_para_ulink_v9 = NULL,
854
+
.rf_para_dlink_v9 = NULL,
855
+
.rf_para_ulink_num_v9 = 0,
856
+
.rf_para_dlink_num_v9 = 0,
856
857
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
857
858
BIT(RTW89_PS_MODE_CLK_GATED) |
858
859
BIT(RTW89_PS_MODE_PWR_GATED),
+1
drivers/net/wireless/realtek/rtw89/rtw8852bu.c
+1
drivers/net/wireless/realtek/rtw89/rtw8852bu.c
+12
-5
drivers/net/wireless/realtek/rtw89/rtw8852c.c
+12
-5
drivers/net/wireless/realtek/rtw89/rtw8852c.c
···
18
18
#define RTW8852C_FW_FORMAT_MAX 2
19
19
#define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw"
20
20
#define RTW8852C_MODULE_FIRMWARE \
21
-
RTW8852C_FW_BASENAME "-" __stringify(RTW8852C_FW_FORMAT_MAX) ".bin"
21
+
RTW89_GEN_MODULE_FWNAME(RTW8852C_FW_BASENAME, RTW8852C_FW_FORMAT_MAX)
22
22
23
23
static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = {
24
24
{13, 1614, grp_0}, /* ACH 0 */
···
463
463
else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
464
464
rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_EDSWR);
465
465
466
-
rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
466
+
rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
467
467
rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
468
468
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
469
469
B_AX_REG_ZCDC_H_MASK, 0x3);
···
3106
3106
.ops = &rtw8852c_chip_ops,
3107
3107
.mac_def = &rtw89_mac_gen_ax,
3108
3108
.phy_def = &rtw89_phy_gen_ax,
3109
-
.fw_basename = RTW8852C_FW_BASENAME,
3110
-
.fw_format_max = RTW8852C_FW_FORMAT_MAX,
3109
+
.fw_def = {
3110
+
.fw_basename = RTW8852C_FW_BASENAME,
3111
+
.fw_format_max = RTW8852C_FW_FORMAT_MAX,
3112
+
.fw_b_aid = 0,
3113
+
},
3111
3114
.try_ce_fw = false,
3112
3115
.bbmcu_nr = 0,
3113
3116
.needed_fw_elms = 0,
···
3171
3168
.support_noise = false,
3172
3169
.ul_tb_waveform_ctrl = false,
3173
3170
.ul_tb_pwr_diff = true,
3174
-
.rx_freq_frome_ie = false,
3171
+
.rx_freq_from_ie = false,
3175
3172
.hw_sec_hdr = true,
3176
3173
.hw_mgmt_tx_encrypt = true,
3177
3174
.hw_tkip_crypto = true,
···
3211
3208
.rf_para_ulink = rtw89_btc_8852c_rf_ul,
3212
3209
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl),
3213
3210
.rf_para_dlink = rtw89_btc_8852c_rf_dl,
3211
+
.rf_para_ulink_v9 = NULL,
3212
+
.rf_para_dlink_v9 = NULL,
3213
+
.rf_para_ulink_num_v9 = 0,
3214
+
.rf_para_dlink_num_v9 = 0,
3214
3215
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
3215
3216
BIT(RTW89_PS_MODE_CLK_GATED) |
3216
3217
BIT(RTW89_PS_MODE_PWR_GATED),
+7
drivers/net/wireless/realtek/rtw89/rtw8852cu.c
+7
drivers/net/wireless/realtek/rtw89/rtw8852cu.c
···
15
15
.usb3_mac_npi_config_intf_0 = R_AX_USB3_MAC_NPI_CONFIG_INTF_0_V1,
16
16
.usb_endpoint_0 = R_AX_USB_ENDPOINT_0_V1,
17
17
.usb_endpoint_2 = R_AX_USB_ENDPOINT_2_V1,
18
+
.rx_agg_alignment = 8,
18
19
.bulkout_id = {
19
20
[RTW89_DMA_ACH0] = 3,
20
21
[RTW89_DMA_ACH2] = 5,
···
39
38
};
40
39
41
40
static const struct usb_device_id rtw_8852cu_id_table[] = {
41
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0411, 0x03a6, 0xff, 0xff, 0xff),
42
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
43
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4024, 0xff, 0xff, 0xff),
44
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
42
45
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xc832, 0xff, 0xff, 0xff),
43
46
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
44
47
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xc85a, 0xff, 0xff, 0xff),
···
58
53
{ USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0101, 0xff, 0xff, 0xff),
59
54
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
60
55
{ USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0102, 0xff, 0xff, 0xff),
56
+
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
57
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x37ad, 0x0103, 0xff, 0xff, 0xff),
61
58
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
62
59
{},
63
60
};
+13
-5
drivers/net/wireless/realtek/rtw89/rtw8922a.c
+13
-5
drivers/net/wireless/realtek/rtw89/rtw8922a.c
···
18
18
#define RTW8922A_FW_FORMAT_MAX 4
19
19
#define RTW8922A_FW_BASENAME "rtw89/rtw8922a_fw"
20
20
#define RTW8922A_MODULE_FIRMWARE \
21
-
RTW8922A_FW_BASENAME "-" __stringify(RTW8922A_FW_FORMAT_MAX) ".bin"
21
+
RTW89_GEN_MODULE_FWNAME(RTW8922A_FW_BASENAME, RTW8922A_FW_FORMAT_MAX)
22
22
23
23
#define HE_N_USER_MAX_8922A 4
24
24
···
492
492
return ret;
493
493
494
494
rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2);
495
-
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_XTAL_OFF_A_DIE);
495
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_XTAL_OFF_A_DIE);
496
496
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
497
497
rtw89_write32(rtwdev, R_BE_UDM1, 0);
498
498
···
2916
2916
.ops = &rtw8922a_chip_ops,
2917
2917
.mac_def = &rtw89_mac_gen_be,
2918
2918
.phy_def = &rtw89_phy_gen_be,
2919
-
.fw_basename = RTW8922A_FW_BASENAME,
2920
-
.fw_format_max = RTW8922A_FW_FORMAT_MAX,
2919
+
.fw_def = {
2920
+
.fw_basename = RTW8922A_FW_BASENAME,
2921
+
.fw_format_max = RTW8922A_FW_FORMAT_MAX,
2922
+
.fw_b_aid = 0,
2923
+
},
2921
2924
.try_ce_fw = false,
2922
2925
.bbmcu_nr = 1,
2923
2926
.needed_fw_elms = RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS,
···
2975
2972
.support_noise = false,
2976
2973
.ul_tb_waveform_ctrl = false,
2977
2974
.ul_tb_pwr_diff = false,
2978
-
.rx_freq_frome_ie = false,
2975
+
.rx_freq_from_ie = false,
2979
2976
.hw_sec_hdr = true,
2980
2977
.hw_mgmt_tx_encrypt = true,
2981
2978
.hw_tkip_crypto = true,
···
3015
3012
.rf_para_ulink = rtw89_btc_8922a_rf_ul,
3016
3013
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8922a_rf_dl),
3017
3014
.rf_para_dlink = rtw89_btc_8922a_rf_dl,
3015
+
.rf_para_ulink_v9 = NULL,
3016
+
.rf_para_dlink_v9 = NULL,
3017
+
.rf_para_ulink_num_v9 = 0,
3018
+
.rf_para_dlink_num_v9 = 0,
3018
3019
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
3019
3020
BIT(RTW89_PS_MODE_CLK_GATED) |
3020
3021
BIT(RTW89_PS_MODE_PWR_GATED),
···
3064
3057
const struct rtw89_chip_variant rtw8922ae_vs_variant = {
3065
3058
.no_mcs_12_13 = true,
3066
3059
.fw_min_ver_code = RTW89_FW_VER_CODE(0, 35, 54, 0),
3060
+
.fw_def_override = NULL,
3067
3061
};
3068
3062
EXPORT_SYMBOL(rtw8922ae_vs_variant);
3069
3063
+3093
drivers/net/wireless/realtek/rtw89/rtw8922d.c
+3093
drivers/net/wireless/realtek/rtw89/rtw8922d.c
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/* Copyright(c) 2026 Realtek Corporation
3
+
*/
4
+
5
+
#include "chan.h"
6
+
#include "coex.h"
7
+
#include "debug.h"
8
+
#include "efuse.h"
9
+
#include "mac.h"
10
+
#include "phy.h"
11
+
#include "reg.h"
12
+
#include "rtw8922d.h"
13
+
#include "rtw8922d_rfk.h"
14
+
#include "sar.h"
15
+
#include "util.h"
16
+
17
+
#define RTW8922D_FW_FORMAT_MAX 0
18
+
#define RTW8922D_FW_BASENAME "rtw89/rtw8922d_fw"
19
+
#define RTW8922D_MODULE_FIRMWARE \
20
+
RTW89_GEN_MODULE_FWNAME(RTW8922D_FW_BASENAME, RTW8922D_FW_FORMAT_MAX)
21
+
22
+
#define RTW8922DS_FW_FORMAT_MAX 0
23
+
#define RTW8922DS_FW_BASENAME "rtw89/rtw8922ds_fw"
24
+
#define RTW8922DS_MODULE_FIRMWARE \
25
+
RTW89_GEN_MODULE_FWNAME(RTW8922DS_FW_BASENAME, RTW8922DS_FW_FORMAT_MAX)
26
+
27
+
static const struct rtw89_hfc_ch_cfg rtw8922d_hfc_chcfg_pcie[] = {
28
+
{2, 603, 0}, /* ACH 0 */
29
+
{0, 601, 0}, /* ACH 1 */
30
+
{2, 603, 0}, /* ACH 2 */
31
+
{0, 601, 0}, /* ACH 3 */
32
+
{2, 603, 0}, /* ACH 4 */
33
+
{0, 601, 0}, /* ACH 5 */
34
+
{2, 603, 0}, /* ACH 6 */
35
+
{0, 601, 0}, /* ACH 7 */
36
+
{2, 603, 0}, /* B0MGQ */
37
+
{0, 601, 0}, /* B0HIQ */
38
+
{2, 603, 0}, /* B1MGQ */
39
+
{0, 601, 0}, /* B1HIQ */
40
+
{0, 0, 0}, /* FWCMDQ */
41
+
{0, 0, 0}, /* BMC */
42
+
{0, 0, 0}, /* H2D */
43
+
};
44
+
45
+
static const struct rtw89_hfc_pub_cfg rtw8922d_hfc_pubcfg_pcie = {
46
+
613, /* Group 0 */
47
+
0, /* Group 1 */
48
+
613, /* Public Max */
49
+
0, /* WP threshold */
50
+
};
51
+
52
+
static const struct rtw89_hfc_param_ini rtw8922d_hfc_param_ini_pcie[] = {
53
+
[RTW89_QTA_SCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
54
+
&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
55
+
[RTW89_QTA_DBCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
56
+
&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
57
+
[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
58
+
RTW89_HCIFC_POH},
59
+
[RTW89_QTA_INVALID] = {NULL},
60
+
};
61
+
62
+
static const struct rtw89_dle_mem rtw8922d_dle_mem_pcie[] = {
63
+
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size16_v1,
64
+
&rtw89_mac_size.ple_size20_v1, &rtw89_mac_size.wde_qt19_v1,
65
+
&rtw89_mac_size.wde_qt19_v1, &rtw89_mac_size.ple_qt42_v2,
66
+
&rtw89_mac_size.ple_qt43_v2, &rtw89_mac_size.ple_rsvd_qt9,
67
+
&rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
68
+
&rtw89_mac_size.dle_input18},
69
+
[RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size16_v1,
70
+
&rtw89_mac_size.ple_size20_v1, &rtw89_mac_size.wde_qt19_v1,
71
+
&rtw89_mac_size.wde_qt19_v1, &rtw89_mac_size.ple_qt42_v2,
72
+
&rtw89_mac_size.ple_qt43_v2, &rtw89_mac_size.ple_rsvd_qt9,
73
+
&rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
74
+
&rtw89_mac_size.dle_input18},
75
+
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18_v1,
76
+
&rtw89_mac_size.ple_size22_v1, &rtw89_mac_size.wde_qt3,
77
+
&rtw89_mac_size.wde_qt3, &rtw89_mac_size.ple_qt5_v2,
78
+
&rtw89_mac_size.ple_qt5_v2, &rtw89_mac_size.ple_rsvd_qt1,
79
+
&rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
80
+
&rtw89_mac_size.dle_input3},
81
+
[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
82
+
NULL},
83
+
};
84
+
85
+
static const u32 rtw8922d_h2c_regs[RTW89_H2CREG_MAX] = {
86
+
R_BE_H2CREG_DATA0, R_BE_H2CREG_DATA1, R_BE_H2CREG_DATA2,
87
+
R_BE_H2CREG_DATA3
88
+
};
89
+
90
+
static const u32 rtw8922d_c2h_regs[RTW89_H2CREG_MAX] = {
91
+
R_BE_C2HREG_DATA0, R_BE_C2HREG_DATA1, R_BE_C2HREG_DATA2,
92
+
R_BE_C2HREG_DATA3
93
+
};
94
+
95
+
static const u32 rtw8922d_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
96
+
R_BE_DBG_WOW, R_BE_DBG_WOW,
97
+
};
98
+
99
+
static const struct rtw89_page_regs rtw8922d_page_regs = {
100
+
.hci_fc_ctrl = R_BE_HCI_FC_CTRL,
101
+
.ch_page_ctrl = R_BE_CH_PAGE_CTRL,
102
+
.ach_page_ctrl = R_BE_CH0_PAGE_CTRL,
103
+
.ach_page_info = R_BE_CH0_PAGE_INFO,
104
+
.pub_page_info3 = R_BE_PUB_PAGE_INFO3,
105
+
.pub_page_ctrl1 = R_BE_PUB_PAGE_CTRL1,
106
+
.pub_page_ctrl2 = R_BE_PUB_PAGE_CTRL2,
107
+
.pub_page_info1 = R_BE_PUB_PAGE_INFO1,
108
+
.pub_page_info2 = R_BE_PUB_PAGE_INFO2,
109
+
.wp_page_ctrl1 = R_BE_WP_PAGE_CTRL1,
110
+
.wp_page_ctrl2 = R_BE_WP_PAGE_CTRL2,
111
+
.wp_page_info1 = R_BE_WP_PAGE_INFO1,
112
+
};
113
+
114
+
static const struct rtw89_reg_imr rtw8922d_imr_dmac_regs[] = {
115
+
{R_BE_HCI_BUF_IMR, B_BE_HCI_BUF_IMR_CLR, B_BE_HCI_BUF_IMR_SET},
116
+
{R_BE_DISP_HOST_IMR, B_BE_DISP_HOST_IMR_CLR_V1, B_BE_DISP_HOST_IMR_SET_V1},
117
+
{R_BE_DISP_CPU_IMR, B_BE_DISP_CPU_IMR_CLR_V1, B_BE_DISP_CPU_IMR_SET_V1},
118
+
{R_BE_DISP_OTHER_IMR, B_BE_DISP_OTHER_IMR_CLR_V1, B_BE_DISP_OTHER_IMR_SET_V1},
119
+
{R_BE_PKTIN_ERR_IMR, B_BE_PKTIN_ERR_IMR_CLR, B_BE_PKTIN_ERR_IMR_SET},
120
+
{R_BE_MLO_ERR_IDCT_IMR, B_BE_MLO_ERR_IDCT_IMR_CLR, B_BE_MLO_ERR_IDCT_IMR_SET},
121
+
{R_BE_MPDU_TX_ERR_IMR, B_BE_MPDU_TX_ERR_IMR_CLR, B_BE_MPDU_TX_ERR_IMR_SET},
122
+
{R_BE_MPDU_RX_ERR_IMR, B_BE_MPDU_RX_ERR_IMR_CLR, B_BE_MPDU_RX_ERR_IMR_SET},
123
+
{R_BE_SEC_ERROR_IMR, B_BE_SEC_ERROR_IMR_CLR, B_BE_SEC_ERROR_IMR_SET},
124
+
{R_BE_CPUIO_ERR_IMR, B_BE_CPUIO_ERR_IMR_CLR, B_BE_CPUIO_ERR_IMR_SET},
125
+
{R_BE_WDE_ERR_IMR, B_BE_WDE_ERR_IMR_CLR, B_BE_WDE_ERR_IMR_SET},
126
+
{R_BE_PLE_ERR_IMR, B_BE_PLE_ERR_IMR_CLR, B_BE_PLE_ERR_IMR_SET},
127
+
{R_BE_WDRLS_ERR_IMR, B_BE_WDRLS_ERR_IMR_CLR, B_BE_WDRLS_ERR_IMR_SET},
128
+
{R_BE_TXPKTCTL_B0_ERRFLAG_IMR, B_BE_TXPKTCTL_B0_ERRFLAG_IMR_CLR,
129
+
B_BE_TXPKTCTL_B0_ERRFLAG_IMR_SET},
130
+
{R_BE_TXPKTCTL_B1_ERRFLAG_IMR, B_BE_TXPKTCTL_B1_ERRFLAG_IMR_CLR,
131
+
B_BE_TXPKTCTL_B1_ERRFLAG_IMR_SET},
132
+
{R_BE_BBRPT_COM_ERR_IMR, B_BE_BBRPT_COM_ERR_IMR_CLR, B_BE_BBRPT_COM_ERR_IMR_SET},
133
+
{R_BE_BBRPT_CHINFO_ERR_IMR, B_BE_BBRPT_CHINFO_ERR_IMR_CLR,
134
+
B_BE_BBRPT_CHINFO_ERR_IMR_SET},
135
+
{R_BE_BBRPT_DFS_ERR_IMR, B_BE_BBRPT_DFS_ERR_IMR_CLR, B_BE_BBRPT_DFS_ERR_IMR_SET},
136
+
{R_BE_LA_ERRFLAG_IMR, B_BE_LA_ERRFLAG_IMR_CLR, B_BE_LA_ERRFLAG_IMR_SET},
137
+
{R_BE_CH_INFO_DBGFLAG_IMR, B_BE_CH_INFO_DBGFLAG_IMR_CLR, B_BE_CH_INFO_DBGFLAG_IMR_SET},
138
+
{R_BE_PLRLS_ERR_IMR_V1, B_BE_PLRLS_ERR_IMR_V1_CLR, B_BE_PLRLS_ERR_IMR_V1_SET},
139
+
{R_BE_HAXI_IDCT_MSK, B_BE_HAXI_IDCT_MSK_CLR, B_BE_HAXI_IDCT_MSK_SET},
140
+
};
141
+
142
+
static const struct rtw89_imr_table rtw8922d_imr_dmac_table = {
143
+
.regs = rtw8922d_imr_dmac_regs,
144
+
.n_regs = ARRAY_SIZE(rtw8922d_imr_dmac_regs),
145
+
};
146
+
147
+
static const struct rtw89_reg_imr rtw8922d_imr_cmac_regs[] = {
148
+
{R_BE_RESP_IMR, B_BE_RESP_IMR_CLR_V1, B_BE_RESP_IMR_SET_V1},
149
+
{R_BE_RESP_IMR1, B_BE_RESP_IMR1_CLR, B_BE_RESP_IMR1_SET},
150
+
{R_BE_RX_ERROR_FLAG_IMR, B_BE_RX_ERROR_FLAG_IMR_CLR_V1, B_BE_RX_ERROR_FLAG_IMR_SET_V1},
151
+
{R_BE_TX_ERROR_FLAG_IMR, B_BE_TX_ERROR_FLAG_IMR_CLR, B_BE_TX_ERROR_FLAG_IMR_SET},
152
+
{R_BE_RX_ERROR_FLAG_IMR_1, B_BE_TX_ERROR_FLAG_IMR_1_CLR, B_BE_TX_ERROR_FLAG_IMR_1_SET},
153
+
{R_BE_PTCL_IMR1, B_BE_PTCL_IMR1_CLR, B_BE_PTCL_IMR1_SET},
154
+
{R_BE_PTCL_IMR0, B_BE_PTCL_IMR0_CLR, B_BE_PTCL_IMR0_SET},
155
+
{R_BE_PTCL_IMR_2, B_BE_PTCL_IMR_2_CLR, B_BE_PTCL_IMR_2_SET},
156
+
{R_BE_SCHEDULE_ERR_IMR, B_BE_SCHEDULE_ERR_IMR_CLR, B_BE_SCHEDULE_ERR_IMR_SET},
157
+
{R_BE_C0_TXPWR_IMR, B_BE_C0_TXPWR_IMR_CLR, B_BE_C0_TXPWR_IMR_SET},
158
+
{R_BE_TRXPTCL_ERROR_INDICA_MASK, B_BE_TRXPTCL_ERROR_INDICA_MASK_CLR,
159
+
B_BE_TRXPTCL_ERROR_INDICA_MASK_SET},
160
+
{R_BE_RX_ERR_IMR, B_BE_RX_ERR_IMR_CLR, B_BE_RX_ERR_IMR_SET},
161
+
{R_BE_PHYINFO_ERR_IMR_V1, B_BE_PHYINFO_ERR_IMR_V1_CLR, B_BE_PHYINFO_ERR_IMR_V1_SET},
162
+
};
163
+
164
+
static const struct rtw89_imr_table rtw8922d_imr_cmac_table = {
165
+
.regs = rtw8922d_imr_cmac_regs,
166
+
.n_regs = ARRAY_SIZE(rtw8922d_imr_cmac_regs),
167
+
};
168
+
169
+
static const struct rtw89_rrsr_cfgs rtw8922d_rrsr_cfgs = {
170
+
.ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
171
+
.rsc = {R_BE_PTCL_RRSR1, B_BE_RSC_MASK, 2},
172
+
};
173
+
174
+
static const struct rtw89_rfkill_regs rtw8922d_rfkill_regs = {
175
+
.pinmux = {R_BE_GPIO8_15_FUNC_SEL,
176
+
B_BE_PINMUX_GPIO9_FUNC_SEL_MASK,
177
+
0xf},
178
+
.mode = {R_BE_GPIO_EXT_CTRL + 2,
179
+
(B_BE_GPIO_MOD_9 | B_BE_GPIO_IO_SEL_9) >> 16,
180
+
0x0},
181
+
};
182
+
183
+
static const struct rtw89_dig_regs rtw8922d_dig_regs = {
184
+
.seg0_pd_reg = R_SEG0R_PD_BE4,
185
+
.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
186
+
.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
187
+
.bmode_pd_reg = R_BMODE_PDTH_EN_BE4,
188
+
.bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
189
+
.bmode_pd_lower_bound_reg = R_BMODE_PDTH_BE4,
190
+
.bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
191
+
.p0_lna_init = {R_PATH0_LNA_INIT_BE4, B_PATH0_LNA_INIT_IDX_BE4},
192
+
.p1_lna_init = {R_PATH1_LNA_INIT_BE4, B_PATH1_LNA_INIT_IDX_BE4},
193
+
.p0_tia_init = {R_PATH0_TIA_INIT_BE4, B_PATH0_TIA_INIT_IDX_BE4},
194
+
.p1_tia_init = {R_PATH1_TIA_INIT_BE4, B_PATH1_TIA_INIT_IDX_BE4},
195
+
.p0_rxb_init = {R_PATH0_RXIDX_INIT_BE4, B_PATH0_RXIDX_INIT_BE4},
196
+
.p1_rxb_init = {R_PATH1_RXIDX_INIT_BE4, B_PATH1_RXIDX_INIT_BE4},
197
+
.p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_BE4,
198
+
B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
199
+
.p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_BE4,
200
+
B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
201
+
.p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_BE4,
202
+
B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
203
+
.p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_BE4,
204
+
B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
205
+
};
206
+
207
+
static const struct rtw89_edcca_regs rtw8922d_edcca_regs = {
208
+
.edcca_level = R_SEG0R_EDCCA_LVL_BE4,
209
+
.edcca_mask = B_EDCCA_LVL_MSK0,
210
+
.edcca_p_mask = B_EDCCA_LVL_MSK1,
211
+
.ppdu_level = R_SEG0R_PPDU_LVL_BE4,
212
+
.ppdu_mask = B_EDCCA_LVL_MSK1,
213
+
.p = {{
214
+
.rpt_a = R_EDCCA_RPT_A_BE4,
215
+
.rpt_b = R_EDCCA_RPT_B_BE4,
216
+
.rpt_sel = R_EDCCA_RPT_SEL_BE4,
217
+
.rpt_sel_mask = B_EDCCA_RPT_SEL_BE4_MSK,
218
+
}, {
219
+
.rpt_a = R_EDCCA_RPT_A_BE4_C1,
220
+
.rpt_b = R_EDCCA_RPT_A_BE4_C1,
221
+
.rpt_sel = R_EDCCA_RPT_SEL_BE4_C1,
222
+
.rpt_sel_mask = B_EDCCA_RPT_SEL_BE4_MSK,
223
+
}},
224
+
.rpt_sel_be = R_EDCCA_RPTREG_SEL_BE4,
225
+
.rpt_sel_be_mask = B_EDCCA_RPTREG_SEL_BE_MSK,
226
+
.tx_collision_t2r_st = R_TX_COLLISION_T2R_ST_BE4,
227
+
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_BE_M,
228
+
};
229
+
230
+
static const struct rtw89_efuse_block_cfg rtw8922d_efuse_blocks[] = {
231
+
[RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
232
+
[RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
233
+
[RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO] = {.offset = 0x20000, .size = 0x4800},
234
+
[RTW89_EFUSE_BLOCK_HCI_DIG_USB] = {.offset = 0x30000, .size = 0x890},
235
+
[RTW89_EFUSE_BLOCK_HCI_PHY_PCIE] = {.offset = 0x40000, .size = 0x400},
236
+
[RTW89_EFUSE_BLOCK_HCI_PHY_USB3] = {.offset = 0x50000, .size = 0x80},
237
+
[RTW89_EFUSE_BLOCK_HCI_PHY_USB2] = {.offset = 0x60000, .size = 0x50},
238
+
[RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
239
+
};
240
+
241
+
static void rtw8922d_sel_bt_rx_path(struct rtw89_dev *rtwdev, u8 val,
242
+
enum rtw89_rf_path rx_path)
243
+
{
244
+
if (rx_path == RF_PATH_A)
245
+
rtw89_phy_write32_mask(rtwdev, R_SEL_GNT_BT_RX_BE4,
246
+
B_SEL_GNT_BT_RX_PATH0_BE4, val);
247
+
else if (rx_path == RF_PATH_B)
248
+
rtw89_phy_write32_mask(rtwdev, R_SEL_GNT_BT_RX_BE4,
249
+
B_SEL_GNT_BT_RX_PATH1_BE4, val);
250
+
else
251
+
rtw89_warn(rtwdev, "[%s] Not support path = %d\n", __func__, rx_path);
252
+
}
253
+
254
+
static void rtw8922d_sel_bt_rx_phy(struct rtw89_dev *rtwdev, u8 val,
255
+
enum rtw89_phy_idx phy_idx)
256
+
{
257
+
rtw89_phy_write32_idx(rtwdev, R_SEL_GNT_BT_RXPHY_BE4,
258
+
B_SEL_GNT_BT_RXPHY_BE4, val, phy_idx);
259
+
}
260
+
261
+
static void rtw8922d_set_gbt_bt_rx_sel(struct rtw89_dev *rtwdev, bool en,
262
+
enum rtw89_phy_idx phy_idx)
263
+
{
264
+
rtw8922d_sel_bt_rx_path(rtwdev, 0x3, RF_PATH_A);
265
+
rtw8922d_sel_bt_rx_phy(rtwdev, 0x0, RTW89_PHY_0);
266
+
rtw8922d_sel_bt_rx_path(rtwdev, 0x3, RF_PATH_B);
267
+
rtw8922d_sel_bt_rx_phy(rtwdev, 0x0, RTW89_PHY_1);
268
+
}
269
+
270
+
static int rtw8922d_pwr_on_func(struct rtw89_dev *rtwdev)
271
+
{
272
+
struct rtw89_hal *hal = &rtwdev->hal;
273
+
u32 val32;
274
+
int ret;
275
+
276
+
if (hal->cid != RTL8922D_CID7025)
277
+
goto begin;
278
+
279
+
switch (hal->cv) {
280
+
case CHIP_CAV:
281
+
case CHIP_CBV:
282
+
rtw89_write32_set(rtwdev, R_BE_SPS_DIG_ON_CTRL1, B_BE_PWM_FORCE);
283
+
rtw89_write32_set(rtwdev, R_BE_SPS_ANA_ON_CTRL1, B_BE_PWM_FORCE_ANA);
284
+
break;
285
+
default:
286
+
break;
287
+
}
288
+
289
+
begin:
290
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_AFSM_WLSUS_EN |
291
+
B_BE_AFSM_PCIE_SUS_EN);
292
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_DIS_WLBT_PDNSUSEN_SOPC);
293
+
rtw89_write32_set(rtwdev, R_BE_WLLPS_CTRL, B_BE_DIS_WLBT_LPSEN_LOPC);
294
+
if (hal->cid != RTL8922D_CID7090)
295
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APDM_HPDN);
296
+
rtw89_write32_clr(rtwdev, R_BE_FWS1ISR, B_BE_FS_WL_HW_RADIO_OFF_INT);
297
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
298
+
299
+
ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_RDY_SYSPWR,
300
+
1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
301
+
if (ret)
302
+
return ret;
303
+
304
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
305
+
rtw89_write32_set(rtwdev, R_BE_WLRESUME_CTRL, B_BE_LPSROP_CMAC0 |
306
+
B_BE_LPSROP_CMAC1);
307
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFN_ONMAC);
308
+
309
+
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_APFN_ONMAC),
310
+
1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
311
+
if (ret)
312
+
return ret;
313
+
314
+
rtw89_write8_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_PLATFORM_EN);
315
+
rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
316
+
317
+
ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_HAXIDMA_IO_ST,
318
+
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
319
+
if (ret)
320
+
return ret;
321
+
322
+
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
323
+
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
324
+
if (ret)
325
+
return ret;
326
+
327
+
rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
328
+
329
+
ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_HCI_WLAN_IO_ST,
330
+
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
331
+
if (ret)
332
+
return ret;
333
+
334
+
rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN);
335
+
336
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_NORMAL_WRITE, 0x10, 0x10);
337
+
if (ret)
338
+
return ret;
339
+
340
+
rtw89_write32_set(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC1_1P3);
341
+
342
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
343
+
if (ret)
344
+
return ret;
345
+
346
+
rtw89_write32_set(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC0_1P3);
347
+
348
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
349
+
if (ret)
350
+
return ret;
351
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
352
+
if (ret)
353
+
return ret;
354
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
355
+
if (ret)
356
+
return ret;
357
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x10);
358
+
if (ret)
359
+
return ret;
360
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xEB, 0xFF);
361
+
if (ret)
362
+
return ret;
363
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xEB, 0xFF);
364
+
if (ret)
365
+
return ret;
366
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
367
+
if (ret)
368
+
return ret;
369
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
370
+
if (ret)
371
+
return ret;
372
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x80);
373
+
if (ret)
374
+
return ret;
375
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, 0x70);
376
+
if (ret)
377
+
return ret;
378
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, 0x02);
379
+
if (ret)
380
+
return ret;
381
+
382
+
rtw89_write32_set(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
383
+
rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_ISO_EB2CORE);
384
+
rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_B);
385
+
386
+
mdelay(1);
387
+
388
+
rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_S);
389
+
rtw89_write32_clr(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
390
+
391
+
rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
392
+
B_BE_MAC_FUNC_EN | B_BE_DMAC_FUNC_EN |
393
+
B_BE_MPDU_PROC_EN | B_BE_WD_RLS_EN |
394
+
B_BE_DLE_WDE_EN | B_BE_TXPKT_CTRL_EN |
395
+
B_BE_STA_SCH_EN | B_BE_DLE_PLE_EN |
396
+
B_BE_PKT_BUF_EN | B_BE_DMAC_TBL_EN |
397
+
B_BE_PKT_IN_EN | B_BE_DLE_CPUIO_EN |
398
+
B_BE_DISPATCHER_EN | B_BE_BBRPT_EN |
399
+
B_BE_MAC_SEC_EN | B_BE_H_AXIDMA_EN |
400
+
B_BE_DMAC_MLO_EN | B_BE_PLRLS_EN |
401
+
B_BE_P_AXIDMA_EN | B_BE_DLE_DATACPUIO_EN |
402
+
B_BE_LTR_CTL_EN);
403
+
404
+
set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
405
+
406
+
rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_FUNC_EN,
407
+
B_BE_CMAC_SHARE_EN | B_BE_RESPBA_EN |
408
+
B_BE_ADDRSRCH_EN | B_BE_BTCOEX_EN);
409
+
410
+
rtw89_write32_set(rtwdev, R_BE_CMAC_FUNC_EN,
411
+
B_BE_CMAC_EN | B_BE_CMAC_TXEN |
412
+
B_BE_CMAC_RXEN | B_BE_SIGB_EN |
413
+
B_BE_PHYINTF_EN | B_BE_CMAC_DMA_EN |
414
+
B_BE_PTCLTOP_EN | B_BE_SCHEDULER_EN |
415
+
B_BE_TMAC_EN | B_BE_RMAC_EN |
416
+
B_BE_TXTIME_EN | B_BE_RESP_PKTCTL_EN);
417
+
418
+
set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
419
+
420
+
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
421
+
B_BE_FEN_BB_IP_RSTN | B_BE_FEN_BBPLAT_RSTB);
422
+
423
+
return 0;
424
+
}
425
+
426
+
static int rtw8922d_pwr_off_func(struct rtw89_dev *rtwdev)
427
+
{
428
+
u32 val32;
429
+
int ret;
430
+
431
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
432
+
if (ret)
433
+
return ret;
434
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x08);
435
+
if (ret)
436
+
return ret;
437
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x04);
438
+
if (ret)
439
+
return ret;
440
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, 0x01);
441
+
if (ret)
442
+
return ret;
443
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, 0x01);
444
+
if (ret)
445
+
return ret;
446
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
447
+
if (ret)
448
+
return ret;
449
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x02);
450
+
if (ret)
451
+
return ret;
452
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x01);
453
+
if (ret)
454
+
return ret;
455
+
456
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
457
+
rtw89_write8_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_FEN_BB_IP_RSTN |
458
+
B_BE_FEN_BBPLAT_RSTB);
459
+
rtw89_write32_clr(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL,
460
+
B_BE_SYM_PADPDN_WL_RFC0_1P3);
461
+
462
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x20);
463
+
if (ret)
464
+
return ret;
465
+
466
+
rtw89_write32_clr(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL,
467
+
B_BE_SYM_PADPDN_WL_RFC1_1P3);
468
+
469
+
ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x40);
470
+
if (ret)
471
+
return ret;
472
+
473
+
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
474
+
475
+
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_IO_ST),
476
+
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
477
+
if (ret)
478
+
return ret;
479
+
ret = read_poll_timeout(rtw89_read32, val32,
480
+
!(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
481
+
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
482
+
if (ret)
483
+
return ret;
484
+
485
+
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
486
+
487
+
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HCI_WLAN_IO_ST),
488
+
1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
489
+
if (ret)
490
+
return ret;
491
+
492
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
493
+
494
+
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_APFM_OFFMAC),
495
+
1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
496
+
if (ret)
497
+
return ret;
498
+
499
+
rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x00015002);
500
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_XTAL_OFF_A_DIE);
501
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
502
+
rtw89_write32(rtwdev, R_BE_UDM1, 0);
503
+
504
+
return 0;
505
+
}
506
+
507
+
static void rtw8922d_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
508
+
struct rtw8922d_efuse *map)
509
+
{
510
+
const struct rtw8922d_tssi_offset_6g * const ofst_6g[] = {
511
+
&map->path_a_tssi_6g,
512
+
&map->path_b_tssi_6g,
513
+
};
514
+
const struct rtw8922d_tssi_offset * const ofst[] = {
515
+
&map->path_a_tssi,
516
+
&map->path_b_tssi,
517
+
};
518
+
struct rtw89_tssi_info *tssi = &rtwdev->tssi;
519
+
u8 i, j;
520
+
521
+
tssi->thermal[RF_PATH_A] = map->path_a_therm;
522
+
tssi->thermal[RF_PATH_B] = map->path_b_therm;
523
+
524
+
for (i = 0; i < RF_PATH_NUM_8922D; i++) {
525
+
memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, TSSI_CCK_CH_GROUP_NUM);
526
+
527
+
for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
528
+
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
529
+
"[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
530
+
i, j, tssi->tssi_cck[i][j]);
531
+
532
+
memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
533
+
TSSI_MCS_2G_CH_GROUP_NUM);
534
+
memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
535
+
ofst[i]->bw40_1s_tssi_5g, TSSI_MCS_5G_CH_GROUP_NUM);
536
+
memcpy(tssi->tssi_6g_mcs[i], ofst_6g[i]->bw40_1s_tssi_6g,
537
+
TSSI_MCS_6G_CH_GROUP_NUM);
538
+
539
+
for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
540
+
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
541
+
"[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
542
+
i, j, tssi->tssi_mcs[i][j]);
543
+
544
+
for (j = 0; j < TSSI_MCS_6G_CH_GROUP_NUM; j++)
545
+
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
546
+
"[TSSI][EFUSE] path=%d mcs_6g[%d]=0x%x\n",
547
+
i, j, tssi->tssi_6g_mcs[i][j]);
548
+
}
549
+
}
550
+
551
+
static void
552
+
__rtw8922d_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
553
+
s8 offset[RTW89_GAIN_OFFSET_NR],
554
+
const s8 *offset_default,
555
+
const struct rtw8922d_rx_gain *rx_gain,
556
+
const struct rtw8922d_rx_gain_6g *rx_gain_6g)
557
+
{
558
+
int i;
559
+
u8 t;
560
+
561
+
offset[RTW89_GAIN_OFFSET_2G_CCK] = rx_gain->_2g_cck;
562
+
offset[RTW89_GAIN_OFFSET_2G_OFDM] = rx_gain->_2g_ofdm;
563
+
offset[RTW89_GAIN_OFFSET_5G_LOW] = rx_gain->_5g_low;
564
+
offset[RTW89_GAIN_OFFSET_5G_MID] = rx_gain->_5g_mid;
565
+
offset[RTW89_GAIN_OFFSET_5G_HIGH] = rx_gain->_5g_high;
566
+
offset[RTW89_GAIN_OFFSET_6G_L0] = rx_gain_6g->_6g_l0;
567
+
offset[RTW89_GAIN_OFFSET_6G_L1] = rx_gain_6g->_6g_l1;
568
+
offset[RTW89_GAIN_OFFSET_6G_M0] = rx_gain_6g->_6g_m0;
569
+
offset[RTW89_GAIN_OFFSET_6G_M1] = rx_gain_6g->_6g_m1;
570
+
offset[RTW89_GAIN_OFFSET_6G_H0] = rx_gain_6g->_6g_h0;
571
+
offset[RTW89_GAIN_OFFSET_6G_H1] = rx_gain_6g->_6g_h1;
572
+
offset[RTW89_GAIN_OFFSET_6G_UH0] = rx_gain_6g->_6g_uh0;
573
+
offset[RTW89_GAIN_OFFSET_6G_UH1] = rx_gain_6g->_6g_uh1;
574
+
575
+
for (i = 0; i < RTW89_GAIN_OFFSET_NR; i++) {
576
+
t = offset[i];
577
+
if (t == 0xff) {
578
+
if (offset_default) {
579
+
offset[i] = offset_default[i];
580
+
continue;
581
+
}
582
+
t = 0;
583
+
}
584
+
585
+
/* transform: sign-bit + U(7,2) to S(8,2) */
586
+
if (t & 0x80)
587
+
offset[i] = (t ^ 0x7f) + 1;
588
+
else
589
+
offset[i] = t;
590
+
}
591
+
}
592
+
593
+
static void rtw8922d_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
594
+
struct rtw8922d_efuse *map)
595
+
{
596
+
struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
597
+
598
+
__rtw8922d_efuse_parsing_gain_offset(rtwdev, gain->offset[RF_PATH_A],
599
+
NULL,
600
+
&map->rx_gain_a, &map->rx_gain_6g_a);
601
+
__rtw8922d_efuse_parsing_gain_offset(rtwdev, gain->offset[RF_PATH_B],
602
+
NULL,
603
+
&map->rx_gain_b, &map->rx_gain_6g_b);
604
+
605
+
__rtw8922d_efuse_parsing_gain_offset(rtwdev, gain->offset2[RF_PATH_A],
606
+
gain->offset[RF_PATH_A],
607
+
&map->rx_gain_a_2, &map->rx_gain_6g_a_2);
608
+
__rtw8922d_efuse_parsing_gain_offset(rtwdev, gain->offset2[RF_PATH_B],
609
+
gain->offset[RF_PATH_B],
610
+
&map->rx_gain_b_2, &map->rx_gain_6g_b_2);
611
+
612
+
gain->offset_valid = true;
613
+
}
614
+
615
+
static int rtw8922d_read_efuse_pci_sdio(struct rtw89_dev *rtwdev, u8 *log_map)
616
+
{
617
+
struct rtw89_efuse *efuse = &rtwdev->efuse;
618
+
619
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
620
+
ether_addr_copy(efuse->addr, log_map + 0x4104);
621
+
else
622
+
ether_addr_copy(efuse->addr, log_map + 0x001A);
623
+
624
+
return 0;
625
+
}
626
+
627
+
static int rtw8922d_read_efuse_usb(struct rtw89_dev *rtwdev, u8 *log_map)
628
+
{
629
+
struct rtw89_efuse *efuse = &rtwdev->efuse;
630
+
631
+
ether_addr_copy(efuse->addr, log_map + 0x0078);
632
+
633
+
return 0;
634
+
}
635
+
636
+
static int rtw8922d_read_efuse_rf(struct rtw89_dev *rtwdev, u8 *log_map)
637
+
{
638
+
struct rtw8922d_efuse *map = (struct rtw8922d_efuse *)log_map;
639
+
struct rtw89_efuse *efuse = &rtwdev->efuse;
640
+
641
+
efuse->rfe_type = map->rfe_type;
642
+
efuse->xtal_cap = map->xtal_k;
643
+
efuse->country_code[0] = map->country_code[0];
644
+
efuse->country_code[1] = map->country_code[1];
645
+
efuse->bt_setting_2 = map->bt_setting_2;
646
+
efuse->bt_setting_3 = map->bt_setting_3;
647
+
rtw8922d_efuse_parsing_tssi(rtwdev, map);
648
+
rtw8922d_efuse_parsing_gain_offset(rtwdev, map);
649
+
650
+
return 0;
651
+
}
652
+
653
+
static int rtw8922d_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
654
+
enum rtw89_efuse_block block)
655
+
{
656
+
switch (block) {
657
+
case RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO:
658
+
return rtw8922d_read_efuse_pci_sdio(rtwdev, log_map);
659
+
case RTW89_EFUSE_BLOCK_HCI_DIG_USB:
660
+
return rtw8922d_read_efuse_usb(rtwdev, log_map);
661
+
case RTW89_EFUSE_BLOCK_RF:
662
+
return rtw8922d_read_efuse_rf(rtwdev, log_map);
663
+
default:
664
+
return 0;
665
+
}
666
+
}
667
+
668
+
static void rtw8922d_phycap_parsing_vco_trim(struct rtw89_dev *rtwdev,
669
+
u8 *phycap_map)
670
+
{
671
+
static const u32 vco_trim_addr[RF_PATH_NUM_8922D] = {0x175E, 0x175F};
672
+
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
673
+
u32 addr = rtwdev->chip->phycap_addr;
674
+
const u32 vco_check_addr = 0x1700;
675
+
u8 val;
676
+
677
+
val = phycap_map[vco_check_addr - addr];
678
+
if (val & BIT(1))
679
+
return;
680
+
681
+
info->pg_vco_trim = true;
682
+
683
+
info->vco_trim[0] = u8_get_bits(phycap_map[vco_trim_addr[0] - addr], GENMASK(4, 0));
684
+
info->vco_trim[1] = u8_get_bits(phycap_map[vco_trim_addr[1] - addr], GENMASK(4, 0));
685
+
}
686
+
687
+
static void rtw8922d_vco_trim(struct rtw89_dev *rtwdev)
688
+
{
689
+
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
690
+
691
+
if (!info->pg_vco_trim)
692
+
return;
693
+
694
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_VCO, RR_VCO_VAL, info->vco_trim[0]);
695
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_VCO, RR_VCO_VAL, info->vco_trim[1]);
696
+
}
697
+
698
+
#define THM_TRIM_POSITIVE_MASK BIT(6)
699
+
#define THM_TRIM_MAGNITUDE_MASK GENMASK(5, 0)
700
+
#define THM_TRIM_MAX (15)
701
+
#define THM_TRIM_MIN (-15)
702
+
703
+
static void rtw8922d_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
704
+
u8 *phycap_map)
705
+
{
706
+
static const u32 thm_trim_addr[RF_PATH_NUM_8922D] = {0x1706, 0x1732};
707
+
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
708
+
u32 addr = rtwdev->chip->phycap_addr;
709
+
bool pg = true;
710
+
u8 pg_th;
711
+
s8 val;
712
+
u8 i;
713
+
714
+
for (i = 0; i < RF_PATH_NUM_8922D; i++) {
715
+
pg_th = phycap_map[thm_trim_addr[i] - addr];
716
+
if (pg_th == 0xff) {
717
+
memset(info->thermal_trim, 0, sizeof(info->thermal_trim));
718
+
pg = false;
719
+
goto out;
720
+
}
721
+
722
+
val = u8_get_bits(pg_th, THM_TRIM_MAGNITUDE_MASK);
723
+
724
+
if (!(pg_th & THM_TRIM_POSITIVE_MASK))
725
+
val *= -1;
726
+
727
+
if (val <= THM_TRIM_MIN || val >= THM_TRIM_MAX) {
728
+
val = 0;
729
+
info->thermal_trim[i] = 0;
730
+
} else {
731
+
info->thermal_trim[i] = pg_th;
732
+
}
733
+
734
+
rtw89_debug(rtwdev, RTW89_DBG_RFK,
735
+
"[THERMAL][TRIM] path=%d thermal_trim=0x%x (%d)\n",
736
+
i, pg_th, val);
737
+
}
738
+
739
+
out:
740
+
info->pg_thermal_trim = pg;
741
+
}
742
+
743
+
static void rtw8922d_thermal_trim(struct rtw89_dev *rtwdev)
744
+
{
745
+
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
746
+
u8 thermal;
747
+
int i;
748
+
749
+
for (i = 0; i < RF_PATH_NUM_8922D; i++) {
750
+
thermal = info->pg_thermal_trim ? info->thermal_trim[i] : 0;
751
+
rtw89_write_rf(rtwdev, i, RR_TM, RR_TM_TRM, thermal & 0x7f);
752
+
}
753
+
}
754
+
755
+
static void rtw8922d_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
756
+
u8 *phycap_map)
757
+
{
758
+
static const u32 pabias_trim_addr[RF_PATH_NUM_8922D] = {0x1707, 0x1733};
759
+
static const u32 check_pa_pad_trim_addr = 0x1700;
760
+
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
761
+
u32 addr = rtwdev->chip->phycap_addr;
762
+
bool pg = true;
763
+
u8 val;
764
+
u8 i;
765
+
766
+
val = phycap_map[check_pa_pad_trim_addr - addr];
767
+
if (val == 0xff) {
768
+
pg = false;
769
+
goto out;
770
+
}
771
+
772
+
for (i = 0; i < RF_PATH_NUM_8922D; i++) {
773
+
info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
774
+
775
+
rtw89_debug(rtwdev, RTW89_DBG_RFK,
776
+
"[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
777
+
i, info->pa_bias_trim[i]);
778
+
}
779
+
780
+
out:
781
+
info->pg_pa_bias_trim = pg;
782
+
}
783
+
784
+
static void rtw8922d_pa_bias_trim(struct rtw89_dev *rtwdev)
785
+
{
786
+
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
787
+
u8 pabias_2g, pabias_5g;
788
+
u8 i;
789
+
790
+
if (!info->pg_pa_bias_trim) {
791
+
rtw89_debug(rtwdev, RTW89_DBG_RFK,
792
+
"[PA_BIAS][TRIM] no PG, do nothing\n");
793
+
794
+
return;
795
+
}
796
+
797
+
for (i = 0; i < RF_PATH_NUM_8922D; i++) {
798
+
pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
799
+
pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
800
+
801
+
rtw89_debug(rtwdev, RTW89_DBG_RFK,
802
+
"[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
803
+
i, pabias_2g, pabias_5g);
804
+
805
+
rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG_V1, pabias_2g);
806
+
rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA_V1, pabias_5g);
807
+
}
808
+
}
809
+
810
+
static void rtw8922d_phycap_parsing_pad_bias_trim(struct rtw89_dev *rtwdev,
811
+
u8 *phycap_map)
812
+
{
813
+
static const u32 pad_bias_trim_addr[RF_PATH_NUM_8922D] = {0x1708, 0x1734};
814
+
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
815
+
u32 addr = rtwdev->chip->phycap_addr;
816
+
u8 i;
817
+
818
+
if (!info->pg_pa_bias_trim)
819
+
return;
820
+
821
+
for (i = 0; i < RF_PATH_NUM_8922D; i++) {
822
+
info->pad_bias_trim[i] = phycap_map[pad_bias_trim_addr[i] - addr];
823
+
824
+
rtw89_debug(rtwdev, RTW89_DBG_RFK,
825
+
"[PAD_BIAS][TRIM] path=%d pad_bias_trim=0x%x\n",
826
+
i, info->pad_bias_trim[i]);
827
+
}
828
+
}
829
+
830
+
static void rtw8922d_pad_bias_trim(struct rtw89_dev *rtwdev)
831
+
{
832
+
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
833
+
u8 pad_bias_2g, pad_bias_5g;
834
+
u8 i;
835
+
836
+
if (!info->pg_pa_bias_trim) {
837
+
rtw89_debug(rtwdev, RTW89_DBG_RFK,
838
+
"[PAD_BIAS][TRIM] no PG, do nothing\n");
839
+
return;
840
+
}
841
+
842
+
for (i = 0; i < RF_PATH_NUM_8922D; i++) {
843
+
pad_bias_2g = u8_get_bits(info->pad_bias_trim[i], GENMASK(3, 0));
844
+
pad_bias_5g = u8_get_bits(info->pad_bias_trim[i], GENMASK(7, 4));
845
+
846
+
rtw89_debug(rtwdev, RTW89_DBG_RFK,
847
+
"[PAD_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
848
+
i, pad_bias_2g, pad_bias_5g);
849
+
850
+
rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASD_TXG_V1, pad_bias_2g);
851
+
rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASD_TXA_V1, pad_bias_5g);
852
+
}
853
+
}
854
+
855
+
static int rtw8922d_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
856
+
{
857
+
rtw8922d_phycap_parsing_vco_trim(rtwdev, phycap_map);
858
+
rtw8922d_phycap_parsing_thermal_trim(rtwdev, phycap_map);
859
+
rtw8922d_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
860
+
rtw8922d_phycap_parsing_pad_bias_trim(rtwdev, phycap_map);
861
+
862
+
return 0;
863
+
}
864
+
865
+
static void rtw8922d_power_trim(struct rtw89_dev *rtwdev)
866
+
{
867
+
rtw8922d_vco_trim(rtwdev);
868
+
rtw8922d_thermal_trim(rtwdev);
869
+
rtw8922d_pa_bias_trim(rtwdev);
870
+
rtw8922d_pad_bias_trim(rtwdev);
871
+
}
872
+
873
+
static void rtw8922d_set_channel_mac(struct rtw89_dev *rtwdev,
874
+
const struct rtw89_chan *chan,
875
+
u8 mac_idx)
876
+
{
877
+
u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_BE_TX_SUB_BAND_VALUE, mac_idx);
878
+
u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_BE_TXRATE_CHK, mac_idx);
879
+
u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_RFMOD, mac_idx);
880
+
u8 txsb20 = 0, txsb40 = 0, txsb80 = 0;
881
+
u8 rf_mod_val, chk_rate_mask, sifs;
882
+
u32 txsb;
883
+
u32 reg;
884
+
885
+
switch (chan->band_width) {
886
+
case RTW89_CHANNEL_WIDTH_160:
887
+
txsb80 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_80);
888
+
fallthrough;
889
+
case RTW89_CHANNEL_WIDTH_80:
890
+
txsb40 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
891
+
fallthrough;
892
+
case RTW89_CHANNEL_WIDTH_40:
893
+
txsb20 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
894
+
break;
895
+
default:
896
+
break;
897
+
}
898
+
899
+
switch (chan->band_width) {
900
+
case RTW89_CHANNEL_WIDTH_160:
901
+
rf_mod_val = BE_WMAC_RFMOD_160M;
902
+
txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK) |
903
+
u32_encode_bits(txsb40, B_BE_TXSB_40M_MASK) |
904
+
u32_encode_bits(txsb80, B_BE_TXSB_80M_MASK);
905
+
break;
906
+
case RTW89_CHANNEL_WIDTH_80:
907
+
rf_mod_val = BE_WMAC_RFMOD_80M;
908
+
txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK) |
909
+
u32_encode_bits(txsb40, B_BE_TXSB_40M_MASK);
910
+
break;
911
+
case RTW89_CHANNEL_WIDTH_40:
912
+
rf_mod_val = BE_WMAC_RFMOD_40M;
913
+
txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK);
914
+
break;
915
+
case RTW89_CHANNEL_WIDTH_20:
916
+
default:
917
+
rf_mod_val = BE_WMAC_RFMOD_20M;
918
+
txsb = 0;
919
+
break;
920
+
}
921
+
922
+
if (txsb20 <= BE_PRI20_BITMAP_MAX)
923
+
txsb |= u32_encode_bits(BIT(txsb20), B_BE_PRI20_BITMAP_MASK);
924
+
925
+
rtw89_write8_mask(rtwdev, rf_mod, B_BE_WMAC_RFMOD_MASK, rf_mod_val);
926
+
rtw89_write32(rtwdev, sub_carr, txsb);
927
+
928
+
switch (chan->band_type) {
929
+
case RTW89_BAND_2G:
930
+
chk_rate_mask = B_BE_BAND_MODE;
931
+
break;
932
+
case RTW89_BAND_5G:
933
+
case RTW89_BAND_6G:
934
+
chk_rate_mask = B_BE_CHECK_CCK_EN | B_BE_RTS_LIMIT_IN_OFDM6;
935
+
break;
936
+
default:
937
+
rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type);
938
+
return;
939
+
}
940
+
941
+
rtw89_write8_clr(rtwdev, chk_rate, B_BE_BAND_MODE | B_BE_CHECK_CCK_EN |
942
+
B_BE_RTS_LIMIT_IN_OFDM6);
943
+
rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask);
944
+
945
+
switch (chan->band_width) {
946
+
case RTW89_CHANNEL_WIDTH_160:
947
+
sifs = 0x8C;
948
+
break;
949
+
case RTW89_CHANNEL_WIDTH_80:
950
+
sifs = 0x8A;
951
+
break;
952
+
case RTW89_CHANNEL_WIDTH_40:
953
+
sifs = 0x84;
954
+
break;
955
+
case RTW89_CHANNEL_WIDTH_20:
956
+
default:
957
+
sifs = 0x82;
958
+
}
959
+
960
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MUEDCA_EN, mac_idx);
961
+
rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_DOT05US_MASK, sifs);
962
+
}
963
+
964
+
static const u32 rtw8922d_sco_barker_threshold[14] = {
965
+
0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
966
+
0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
967
+
};
968
+
969
+
static const u32 rtw8922d_sco_cck_threshold[14] = {
970
+
0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
971
+
0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
972
+
};
973
+
974
+
static int rtw8922d_ctrl_sco_cck(struct rtw89_dev *rtwdev,
975
+
u8 primary_ch, enum rtw89_bandwidth bw,
976
+
enum rtw89_phy_idx phy_idx)
977
+
{
978
+
u8 ch_element;
979
+
980
+
if (primary_ch >= 14)
981
+
return -EINVAL;
982
+
983
+
ch_element = primary_ch - 1;
984
+
985
+
rtw89_phy_write32_idx(rtwdev, R_BK_FC0_INV_BE4, B_BK_FC0_INV_BE4,
986
+
rtw8922d_sco_barker_threshold[ch_element],
987
+
phy_idx);
988
+
rtw89_phy_write32_idx(rtwdev, R_CCK_FC0_INV_BE4, B_CCK_FC0_INV_BE4,
989
+
rtw8922d_sco_cck_threshold[ch_element],
990
+
phy_idx);
991
+
992
+
return 0;
993
+
}
994
+
995
+
static void rtw8922d_ctrl_ch_core(struct rtw89_dev *rtwdev,
996
+
const struct rtw89_chan *chan,
997
+
enum rtw89_phy_idx phy_idx)
998
+
{
999
+
u16 central_freq = chan->freq;
1000
+
u16 sco;
1001
+
1002
+
if (chan->band_type == RTW89_BAND_2G) {
1003
+
rtw89_phy_write32_idx(rtwdev, R_BAND_SEL0_BE4, B_BAND_SEL0_BE4,
1004
+
1, phy_idx);
1005
+
rtw89_phy_write32_idx(rtwdev, R_BAND_SEL1_BE4, B_BAND_SEL1_BE4,
1006
+
1, phy_idx);
1007
+
rtw89_phy_write32_idx(rtwdev, R_ENABLE_CCK0_BE4, B_ENABLE_CCK0_BE4,
1008
+
1, phy_idx);
1009
+
} else {
1010
+
rtw89_phy_write32_idx(rtwdev, R_BAND_SEL0_BE4, B_BAND_SEL0_BE4,
1011
+
0, phy_idx);
1012
+
rtw89_phy_write32_idx(rtwdev, R_BAND_SEL1_BE4, B_BAND_SEL1_BE4,
1013
+
0, phy_idx);
1014
+
rtw89_phy_write32_idx(rtwdev, R_ENABLE_CCK0_BE4, B_ENABLE_CCK0_BE4,
1015
+
0, phy_idx);
1016
+
}
1017
+
1018
+
rtw89_phy_write32_idx(rtwdev, R_FC0_BE4, B_FC0_BE4, central_freq, phy_idx);
1019
+
1020
+
sco = phy_div((BIT(0) << 27) + (central_freq / 2), central_freq);
1021
+
rtw89_phy_write32_idx(rtwdev, R_FC0_INV_BE4, B_FC0_INV_BE4, sco, phy_idx);
1022
+
}
1023
+
1024
+
struct rtw8922d_bb_gain {
1025
+
u32 gain_g[BB_PATH_NUM_8922D];
1026
+
u32 gain_a[BB_PATH_NUM_8922D];
1027
+
u32 gain_g_mask;
1028
+
u32 gain_a_mask;
1029
+
};
1030
+
1031
+
static const struct rtw89_reg_def rpl_comp_bw160[RTW89_BW20_SC_160M] = {
1032
+
{ .addr = 0x241E8, .mask = 0xFF00},
1033
+
{ .addr = 0x241E8, .mask = 0xFF0000},
1034
+
{ .addr = 0x241E8, .mask = 0xFF000000},
1035
+
{ .addr = 0x241EC, .mask = 0xFF},
1036
+
{ .addr = 0x241EC, .mask = 0xFF00},
1037
+
{ .addr = 0x241EC, .mask = 0xFF0000},
1038
+
{ .addr = 0x241EC, .mask = 0xFF000000},
1039
+
{ .addr = 0x241F0, .mask = 0xFF}
1040
+
};
1041
+
1042
+
static const struct rtw89_reg_def rpl_comp_bw80[RTW89_BW20_SC_80M] = {
1043
+
{ .addr = 0x241F4, .mask = 0xFF},
1044
+
{ .addr = 0x241F4, .mask = 0xFF00},
1045
+
{ .addr = 0x241F4, .mask = 0xFF0000},
1046
+
{ .addr = 0x241F4, .mask = 0xFF000000}
1047
+
};
1048
+
1049
+
static const struct rtw89_reg_def rpl_comp_bw40[RTW89_BW20_SC_40M] = {
1050
+
{ .addr = 0x241F0, .mask = 0xFF0000},
1051
+
{ .addr = 0x241F0, .mask = 0xFF000000}
1052
+
};
1053
+
1054
+
static const struct rtw89_reg_def rpl_comp_bw20[RTW89_BW20_SC_20M] = {
1055
+
{ .addr = 0x241F0, .mask = 0xFF00}
1056
+
};
1057
+
1058
+
static const struct rtw8922d_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
1059
+
{ .gain_g = {0x2409C, 0x2449C}, .gain_a = {0x2406C, 0x2446C},
1060
+
.gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1061
+
{ .gain_g = {0x2409C, 0x2449C}, .gain_a = {0x2406C, 0x2446C},
1062
+
.gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
1063
+
{ .gain_g = {0x240A0, 0x244A0}, .gain_a = {0x24070, 0x24470},
1064
+
.gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1065
+
{ .gain_g = {0x240A0, 0x244A0}, .gain_a = {0x24070, 0x24470},
1066
+
.gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
1067
+
{ .gain_g = {0x240A4, 0x244A4}, .gain_a = {0x24074, 0x24474},
1068
+
.gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1069
+
{ .gain_g = {0x240A4, 0x244A4}, .gain_a = {0x24074, 0x24474},
1070
+
.gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
1071
+
{ .gain_g = {0x240A8, 0x244A8}, .gain_a = {0x24078, 0x24478},
1072
+
.gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
1073
+
};
1074
+
1075
+
static const struct rtw8922d_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
1076
+
{ .gain_g = {0x24054, 0x24454}, .gain_a = {0x24054, 0x24454},
1077
+
.gain_g_mask = 0x7FC0000, .gain_a_mask = 0x1FF},
1078
+
{ .gain_g = {0x24058, 0x24458}, .gain_a = {0x24054, 0x24454},
1079
+
.gain_g_mask = 0x1FF, .gain_a_mask = 0x3FE00 },
1080
+
};
1081
+
1082
+
static const struct rtw8922d_bb_gain bb_op1db_lna[LNA_GAIN_NUM] = {
1083
+
{ .gain_g = {0x240AC, 0x244AC}, .gain_a = {0x24078, 0x24478},
1084
+
.gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
1085
+
{ .gain_g = {0x240AC, 0x244AC}, .gain_a = {0x2407C, 0x2447C},
1086
+
.gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
1087
+
{ .gain_g = {0x240AC, 0x244AC}, .gain_a = {0x2407C, 0x2447C},
1088
+
.gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
1089
+
{ .gain_g = {0x240B0, 0x244B0}, .gain_a = {0x2407C, 0x2447C},
1090
+
.gain_g_mask = 0xFF, .gain_a_mask = 0xFF0000},
1091
+
{ .gain_g = {0x240B0, 0x244B0}, .gain_a = {0x2407C, 0x2447C},
1092
+
.gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
1093
+
{ .gain_g = {0x240B0, 0x244B0}, .gain_a = {0x24080, 0x24480},
1094
+
.gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
1095
+
{ .gain_g = {0x240B0, 0x244B0}, .gain_a = {0x24080, 0x24480},
1096
+
.gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
1097
+
};
1098
+
1099
+
static const struct rtw8922d_bb_gain bb_op1db_tia_lna[TIA_LNA_OP1DB_NUM] = {
1100
+
{ .gain_g = {0x240B4, 0x244B4}, .gain_a = {0x24080, 0x24480},
1101
+
.gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1102
+
{ .gain_g = {0x240B4, 0x244B4}, .gain_a = {0x24084, 0x24484},
1103
+
.gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1104
+
{ .gain_g = {0x240B8, 0x244B8}, .gain_a = {0x24084, 0x24484},
1105
+
.gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1106
+
{ .gain_g = {0x240B8, 0x244B8}, .gain_a = {0x24084, 0x24484},
1107
+
.gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1108
+
{ .gain_g = {0x240B8, 0x244B8}, .gain_a = {0x24084, 0x24484},
1109
+
.gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1110
+
{ .gain_g = {0x240B8, 0x244B8}, .gain_a = {0x24088, 0x24488},
1111
+
.gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1112
+
{ .gain_g = {0x240BC, 0x244BC}, .gain_a = {0x24088, 0x24488},
1113
+
.gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1114
+
{ .gain_g = {0x240BC, 0x244BC}, .gain_a = {0x24088, 0x24488},
1115
+
.gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1116
+
};
1117
+
1118
+
static void rtw8922d_set_rpl_gain(struct rtw89_dev *rtwdev,
1119
+
const struct rtw89_chan *chan,
1120
+
enum rtw89_rf_path path,
1121
+
enum rtw89_phy_idx phy_idx)
1122
+
{
1123
+
const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1124
+
u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1125
+
u32 reg_path_ofst = 0;
1126
+
u32 mask;
1127
+
s32 val;
1128
+
u32 reg;
1129
+
int i;
1130
+
1131
+
if (path == RF_PATH_B)
1132
+
reg_path_ofst = 0x400;
1133
+
1134
+
for (i = 0; i < RTW89_BW20_SC_160M; i++) {
1135
+
reg = rpl_comp_bw160[i].addr | reg_path_ofst;
1136
+
mask = rpl_comp_bw160[i].mask;
1137
+
val = gain->rpl_ofst_160[gain_band][path][i];
1138
+
rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1139
+
}
1140
+
1141
+
for (i = 0; i < RTW89_BW20_SC_80M; i++) {
1142
+
reg = rpl_comp_bw80[i].addr | reg_path_ofst;
1143
+
mask = rpl_comp_bw80[i].mask;
1144
+
val = gain->rpl_ofst_80[gain_band][path][i];
1145
+
rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1146
+
}
1147
+
1148
+
for (i = 0; i < RTW89_BW20_SC_40M; i++) {
1149
+
reg = rpl_comp_bw40[i].addr | reg_path_ofst;
1150
+
mask = rpl_comp_bw40[i].mask;
1151
+
val = gain->rpl_ofst_40[gain_band][path][i];
1152
+
rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1153
+
}
1154
+
1155
+
for (i = 0; i < RTW89_BW20_SC_20M; i++) {
1156
+
reg = rpl_comp_bw20[i].addr | reg_path_ofst;
1157
+
mask = rpl_comp_bw20[i].mask;
1158
+
val = gain->rpl_ofst_20[gain_band][path][i];
1159
+
rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1160
+
}
1161
+
}
1162
+
1163
+
static void rtw8922d_set_lna_tia_gain(struct rtw89_dev *rtwdev,
1164
+
const struct rtw89_chan *chan,
1165
+
enum rtw89_rf_path path,
1166
+
enum rtw89_phy_idx phy_idx)
1167
+
{
1168
+
const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1169
+
u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1170
+
enum rtw89_phy_bb_bw_be bw_type;
1171
+
u32 mask;
1172
+
s32 val;
1173
+
u32 reg;
1174
+
int i;
1175
+
1176
+
bw_type = chan->band_width <= RTW89_CHANNEL_WIDTH_40 ?
1177
+
RTW89_BB_BW_20_40 : RTW89_BB_BW_80_160_320;
1178
+
1179
+
for (i = 0; i < LNA_GAIN_NUM; i++) {
1180
+
if (chan->band_type == RTW89_BAND_2G) {
1181
+
reg = bb_gain_lna[i].gain_g[path];
1182
+
mask = bb_gain_lna[i].gain_g_mask;
1183
+
} else {
1184
+
reg = bb_gain_lna[i].gain_a[path];
1185
+
mask = bb_gain_lna[i].gain_a_mask;
1186
+
}
1187
+
val = gain->lna_gain[gain_band][bw_type][path][i];
1188
+
rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1189
+
}
1190
+
1191
+
for (i = 0; i < TIA_GAIN_NUM; i++) {
1192
+
if (chan->band_type == RTW89_BAND_2G) {
1193
+
reg = bb_gain_tia[i].gain_g[path];
1194
+
mask = bb_gain_tia[i].gain_g_mask;
1195
+
} else {
1196
+
reg = bb_gain_tia[i].gain_a[path];
1197
+
mask = bb_gain_tia[i].gain_a_mask;
1198
+
}
1199
+
val = gain->tia_gain[gain_band][bw_type][path][i];
1200
+
rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1201
+
}
1202
+
}
1203
+
1204
+
static void rtw8922d_set_op1db(struct rtw89_dev *rtwdev,
1205
+
const struct rtw89_chan *chan,
1206
+
enum rtw89_rf_path path,
1207
+
enum rtw89_phy_idx phy_idx)
1208
+
{
1209
+
const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1210
+
u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1211
+
enum rtw89_phy_bb_bw_be bw_type;
1212
+
u32 mask;
1213
+
s32 val;
1214
+
u32 reg;
1215
+
int i;
1216
+
1217
+
bw_type = chan->band_width <= RTW89_CHANNEL_WIDTH_40 ?
1218
+
RTW89_BB_BW_20_40 : RTW89_BB_BW_80_160_320;
1219
+
1220
+
for (i = 0; i < LNA_GAIN_NUM; i++) {
1221
+
if (chan->band_type == RTW89_BAND_2G) {
1222
+
reg = bb_op1db_lna[i].gain_g[path];
1223
+
mask = bb_op1db_lna[i].gain_g_mask;
1224
+
} else {
1225
+
reg = bb_op1db_lna[i].gain_a[path];
1226
+
mask = bb_op1db_lna[i].gain_a_mask;
1227
+
}
1228
+
val = gain->lna_op1db[gain_band][bw_type][path][i];
1229
+
rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1230
+
}
1231
+
1232
+
for (i = 0; i < TIA_LNA_OP1DB_NUM; i++) {
1233
+
if (chan->band_type == RTW89_BAND_2G) {
1234
+
reg = bb_op1db_tia_lna[i].gain_g[path];
1235
+
mask = bb_op1db_tia_lna[i].gain_g_mask;
1236
+
} else {
1237
+
reg = bb_op1db_tia_lna[i].gain_a[path];
1238
+
mask = bb_op1db_tia_lna[i].gain_a_mask;
1239
+
}
1240
+
val = gain->tia_lna_op1db[gain_band][bw_type][path][i];
1241
+
rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1242
+
}
1243
+
}
1244
+
1245
+
static void rtw8922d_set_gain(struct rtw89_dev *rtwdev,
1246
+
const struct rtw89_chan *chan,
1247
+
enum rtw89_rf_path path,
1248
+
enum rtw89_phy_idx phy_idx)
1249
+
{
1250
+
rtw8922d_set_rpl_gain(rtwdev, chan, path, phy_idx);
1251
+
rtw8922d_set_lna_tia_gain(rtwdev, chan, path, phy_idx);
1252
+
rtw8922d_set_op1db(rtwdev, chan, path, phy_idx);
1253
+
}
1254
+
1255
+
static s8 rtw8922d_get_rx_gain_by_chan(struct rtw89_dev *rtwdev,
1256
+
const struct rtw89_chan *chan,
1257
+
enum rtw89_rf_path path, bool is_cck)
1258
+
{
1259
+
struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1260
+
enum rtw89_gain_offset band;
1261
+
u8 fc_ch = chan->channel;
1262
+
s8 normal_efuse = 0;
1263
+
1264
+
if (path > RF_PATH_B)
1265
+
return 0;
1266
+
1267
+
if (is_cck) {
1268
+
if (fc_ch >= 1 && fc_ch <= 7)
1269
+
return gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK];
1270
+
else if (fc_ch >= 8 && fc_ch <= 14)
1271
+
return gain->offset2[path][RTW89_GAIN_OFFSET_2G_CCK];
1272
+
1273
+
return 0;
1274
+
}
1275
+
1276
+
band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
1277
+
1278
+
if (band == RTW89_GAIN_OFFSET_2G_OFDM) {
1279
+
if (fc_ch >= 1 && fc_ch <= 7)
1280
+
normal_efuse = gain->offset[path][band];
1281
+
else if (fc_ch >= 8 && fc_ch <= 14)
1282
+
normal_efuse = gain->offset2[path][band];
1283
+
} else if (band == RTW89_GAIN_OFFSET_5G_LOW) {
1284
+
if (fc_ch == 50)
1285
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1286
+
else if (fc_ch >= 36 && fc_ch <= 48)
1287
+
normal_efuse = gain->offset[path][band];
1288
+
else if (fc_ch >= 52 && fc_ch <= 64)
1289
+
normal_efuse = gain->offset2[path][band];
1290
+
1291
+
} else if (band == RTW89_GAIN_OFFSET_5G_MID) {
1292
+
if (fc_ch == 122)
1293
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1294
+
else if (fc_ch >= 100 && fc_ch <= 120)
1295
+
normal_efuse = gain->offset[path][band];
1296
+
else if (fc_ch >= 124 && fc_ch <= 144)
1297
+
normal_efuse = gain->offset2[path][band];
1298
+
} else if (band == RTW89_GAIN_OFFSET_5G_HIGH) {
1299
+
if (fc_ch == 163)
1300
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1301
+
else if (fc_ch >= 149 && fc_ch <= 161)
1302
+
normal_efuse = gain->offset[path][band];
1303
+
else if (fc_ch >= 165 && fc_ch <= 177)
1304
+
normal_efuse = gain->offset2[path][band];
1305
+
} else if (band == RTW89_GAIN_OFFSET_6G_L0) {
1306
+
if (fc_ch == 15)
1307
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1308
+
else if (fc_ch >= 1 && fc_ch <= 13)
1309
+
normal_efuse = gain->offset[path][band];
1310
+
else if (fc_ch >= 17 && fc_ch <= 29)
1311
+
normal_efuse = gain->offset2[path][band];
1312
+
} else if (band == RTW89_GAIN_OFFSET_6G_L1) {
1313
+
if (fc_ch == 47)
1314
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1315
+
else if (fc_ch >= 33 && fc_ch <= 45)
1316
+
normal_efuse = gain->offset[path][band];
1317
+
else if (fc_ch >= 49 && fc_ch <= 61)
1318
+
normal_efuse = gain->offset2[path][band];
1319
+
} else if (band == RTW89_GAIN_OFFSET_6G_M0) {
1320
+
if (fc_ch == 79)
1321
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1322
+
else if (fc_ch >= 65 && fc_ch <= 77)
1323
+
normal_efuse = gain->offset[path][band];
1324
+
else if (fc_ch >= 81 && fc_ch <= 93)
1325
+
normal_efuse = gain->offset2[path][band];
1326
+
} else if (band == RTW89_GAIN_OFFSET_6G_M1) {
1327
+
if (fc_ch == 111)
1328
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1329
+
else if (fc_ch >= 97 && fc_ch <= 109)
1330
+
normal_efuse = gain->offset[path][band];
1331
+
else if (fc_ch >= 113 && fc_ch <= 125)
1332
+
normal_efuse = gain->offset2[path][band];
1333
+
} else if (band == RTW89_GAIN_OFFSET_6G_H0) {
1334
+
if (fc_ch == 143)
1335
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1336
+
else if (fc_ch >= 129 && fc_ch <= 141)
1337
+
normal_efuse = gain->offset[path][band];
1338
+
else if (fc_ch >= 145 && fc_ch <= 157)
1339
+
normal_efuse = gain->offset2[path][band];
1340
+
} else if (band == RTW89_GAIN_OFFSET_6G_H1) {
1341
+
if (fc_ch == 175)
1342
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1343
+
else if (fc_ch >= 161 && fc_ch <= 173)
1344
+
normal_efuse = gain->offset[path][band];
1345
+
else if (fc_ch >= 177 && fc_ch <= 189)
1346
+
normal_efuse = gain->offset2[path][band];
1347
+
} else if (band == RTW89_GAIN_OFFSET_6G_UH0) {
1348
+
if (fc_ch == 207)
1349
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1350
+
else if (fc_ch >= 193 && fc_ch <= 205)
1351
+
normal_efuse = gain->offset[path][band];
1352
+
else if (fc_ch >= 209 && fc_ch <= 221)
1353
+
normal_efuse = gain->offset2[path][band];
1354
+
} else if (band == RTW89_GAIN_OFFSET_6G_UH1) {
1355
+
if (fc_ch == 239)
1356
+
normal_efuse = (gain->offset[path][band] + gain->offset2[path][band]) >> 1;
1357
+
else if (fc_ch >= 225 && fc_ch <= 237)
1358
+
normal_efuse = gain->offset[path][band];
1359
+
else if (fc_ch >= 241 && fc_ch <= 253)
1360
+
normal_efuse = gain->offset2[path][band];
1361
+
} else {
1362
+
normal_efuse = gain->offset[path][band];
1363
+
}
1364
+
1365
+
return normal_efuse;
1366
+
}
1367
+
1368
+
static void rtw8922d_calc_rx_gain_normal_cck(struct rtw89_dev *rtwdev,
1369
+
const struct rtw89_chan *chan,
1370
+
enum rtw89_rf_path path,
1371
+
enum rtw89_phy_idx phy_idx,
1372
+
struct rtw89_phy_calc_efuse_gain *calc)
1373
+
{
1374
+
struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1375
+
s8 rx_gain_offset;
1376
+
1377
+
rx_gain_offset = -rtw8922d_get_rx_gain_by_chan(rtwdev, chan, path, true);
1378
+
1379
+
if (chan->band_width == RTW89_CHANNEL_WIDTH_40)
1380
+
rx_gain_offset += (3 << 2); /* compensate RPL loss of 3dB */
1381
+
1382
+
calc->cck_mean_gain_bias = (rx_gain_offset & 0x3) << 1;
1383
+
calc->cck_rpl_ofst = (rx_gain_offset >> 2) + gain->cck_rpl_base[phy_idx];
1384
+
}
1385
+
1386
+
static void rtw8922d_set_rx_gain_normal_cck(struct rtw89_dev *rtwdev,
1387
+
const struct rtw89_chan *chan,
1388
+
enum rtw89_rf_path path,
1389
+
enum rtw89_phy_idx phy_idx)
1390
+
{
1391
+
struct rtw89_phy_calc_efuse_gain calc = {};
1392
+
1393
+
rtw8922d_calc_rx_gain_normal_cck(rtwdev, chan, path, phy_idx, &calc);
1394
+
1395
+
rtw89_phy_write32_idx(rtwdev, R_GAIN_BIAS_BE4, B_GAIN_BIAS_BW20_BE4,
1396
+
calc.cck_mean_gain_bias, phy_idx);
1397
+
rtw89_phy_write32_idx(rtwdev, R_GAIN_BIAS_BE4, B_GAIN_BIAS_BW40_BE4,
1398
+
calc.cck_mean_gain_bias, phy_idx);
1399
+
rtw89_phy_write32_idx(rtwdev, R_CCK_RPL_OFST_BE4, B_CCK_RPL_OFST_BE4,
1400
+
calc.cck_rpl_ofst, phy_idx);
1401
+
}
1402
+
1403
+
static void rtw8922d_calc_rx_gain_normal_ofdm(struct rtw89_dev *rtwdev,
1404
+
const struct rtw89_chan *chan,
1405
+
enum rtw89_rf_path path,
1406
+
enum rtw89_phy_idx phy_idx,
1407
+
struct rtw89_phy_calc_efuse_gain *calc)
1408
+
{
1409
+
struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1410
+
s8 rx_gain_offset;
1411
+
1412
+
rx_gain_offset = rtw8922d_get_rx_gain_by_chan(rtwdev, chan, path, false);
1413
+
calc->rssi_ofst = (rx_gain_offset + gain->ref_gain_base[phy_idx]) & 0xff;
1414
+
}
1415
+
1416
+
static void rtw8922d_set_rx_gain_normal_ofdm(struct rtw89_dev *rtwdev,
1417
+
const struct rtw89_chan *chan,
1418
+
enum rtw89_rf_path path,
1419
+
enum rtw89_phy_idx phy_idx)
1420
+
{
1421
+
static const u32 rssi_ofst_addr[2] = {R_OFDM_OFST_P0_BE4, R_OFDM_OFST_P1_BE4};
1422
+
static const u32 rssi_ofst_addr_m[2] = {B_OFDM_OFST_P0_BE4, B_OFDM_OFST_P1_BE4};
1423
+
static const u32 rpl_bias_comp[2] = {R_OFDM_RPL_BIAS_P0_BE4, R_OFDM_RPL_BIAS_P1_BE4};
1424
+
static const u32 rpl_bias_comp_m[2] = {B_OFDM_RPL_BIAS_P0_BE4, B_OFDM_RPL_BIAS_P1_BE4};
1425
+
struct rtw89_phy_calc_efuse_gain calc = {};
1426
+
1427
+
rtw8922d_calc_rx_gain_normal_ofdm(rtwdev, chan, path, phy_idx, &calc);
1428
+
1429
+
rtw89_phy_write32_idx(rtwdev, rssi_ofst_addr[path], rssi_ofst_addr_m[path],
1430
+
calc.rssi_ofst, phy_idx);
1431
+
rtw89_phy_write32_idx(rtwdev, rpl_bias_comp[path], rpl_bias_comp_m[path], 0, phy_idx);
1432
+
}
1433
+
1434
+
static void rtw8922d_set_rx_gain_normal(struct rtw89_dev *rtwdev,
1435
+
const struct rtw89_chan *chan,
1436
+
enum rtw89_rf_path path,
1437
+
enum rtw89_phy_idx phy_idx)
1438
+
{
1439
+
struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1440
+
1441
+
if (!gain->offset_valid)
1442
+
return;
1443
+
1444
+
if (chan->band_type == RTW89_BAND_2G)
1445
+
rtw8922d_set_rx_gain_normal_cck(rtwdev, chan, path, phy_idx);
1446
+
1447
+
rtw8922d_set_rx_gain_normal_ofdm(rtwdev, chan, path, phy_idx);
1448
+
}
1449
+
1450
+
static void rtw8922d_calc_rx_gain_normal(struct rtw89_dev *rtwdev,
1451
+
const struct rtw89_chan *chan,
1452
+
enum rtw89_rf_path path,
1453
+
enum rtw89_phy_idx phy_idx,
1454
+
struct rtw89_phy_calc_efuse_gain *calc)
1455
+
{
1456
+
rtw8922d_calc_rx_gain_normal_ofdm(rtwdev, chan, path, phy_idx, calc);
1457
+
1458
+
if (chan->band_type != RTW89_BAND_2G)
1459
+
return;
1460
+
1461
+
rtw8922d_calc_rx_gain_normal_cck(rtwdev, chan, path, phy_idx, calc);
1462
+
}
1463
+
1464
+
static void rtw8922d_set_cck_parameters(struct rtw89_dev *rtwdev,
1465
+
const struct rtw89_chan *chan,
1466
+
enum rtw89_phy_idx phy_idx)
1467
+
{
1468
+
u8 regd = rtw89_regd_get(rtwdev, chan->band_type);
1469
+
u8 central_ch = chan->channel;
1470
+
1471
+
if (central_ch == 14) {
1472
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF0_BE4, B_PCOEFF01_BE4, 0x3b13ff, phy_idx);
1473
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF2_BE4, B_PCOEFF23_BE4, 0x1c42de, phy_idx);
1474
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF4_BE4, B_PCOEFF45_BE4, 0xfdb0ad, phy_idx);
1475
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF6_BE4, B_PCOEFF67_BE4, 0xf60f6e, phy_idx);
1476
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF8_BE4, B_PCOEFF89_BE4, 0xfd8f92, phy_idx);
1477
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF10_BE4, B_PCOEFF10_BE4, 0x2d011, phy_idx);
1478
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF12_BE4, B_PCOEFF12_BE4, 0x1c02c, phy_idx);
1479
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF14_BE4, B_PCOEFF14_BE4, 0xfff00a, phy_idx);
1480
+
1481
+
return;
1482
+
}
1483
+
1484
+
if (regd == RTW89_FCC) {
1485
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF0_BE4, B_PCOEFF01_BE4, 0x39A3BC, phy_idx);
1486
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF2_BE4, B_PCOEFF23_BE4, 0x2AA339, phy_idx);
1487
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF4_BE4, B_PCOEFF45_BE4, 0x15B202, phy_idx);
1488
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF6_BE4, B_PCOEFF67_BE4, 0x0550C7, phy_idx);
1489
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF8_BE4, B_PCOEFF89_BE4, 0xfe0009, phy_idx);
1490
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF10_BE4, B_PCOEFF10_BE4, 0xfd7fd3, phy_idx);
1491
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF12_BE4, B_PCOEFF12_BE4, 0xfeffe2, phy_idx);
1492
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF14_BE4, B_PCOEFF14_BE4, 0xffeff8, phy_idx);
1493
+
} else {
1494
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF0_BE4, B_PCOEFF01_BE4, 0x3d23ff, phy_idx);
1495
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF2_BE4, B_PCOEFF23_BE4, 0x29b354, phy_idx);
1496
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF4_BE4, B_PCOEFF45_BE4, 0xfc1c8, phy_idx);
1497
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF6_BE4, B_PCOEFF67_BE4, 0xfdb053, phy_idx);
1498
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF8_BE4, B_PCOEFF89_BE4, 0xf86f9a, phy_idx);
1499
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF10_BE4, B_PCOEFF10_BE4, 0xfaef92, phy_idx);
1500
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF12_BE4, B_PCOEFF12_BE4, 0xfe5fcc, phy_idx);
1501
+
rtw89_phy_write32_idx(rtwdev, R_PCOEFF14_BE4, B_PCOEFF14_BE4, 0xffdff5, phy_idx);
1502
+
}
1503
+
}
1504
+
1505
+
static void rtw8922d_ctrl_ch(struct rtw89_dev *rtwdev,
1506
+
const struct rtw89_chan *chan,
1507
+
enum rtw89_phy_idx phy_idx)
1508
+
{
1509
+
u16 central_freq = chan->freq;
1510
+
u8 band = chan->band_type;
1511
+
u8 chan_idx;
1512
+
1513
+
if (!central_freq) {
1514
+
rtw89_warn(rtwdev, "Invalid central_freq\n");
1515
+
return;
1516
+
}
1517
+
1518
+
rtw8922d_ctrl_ch_core(rtwdev, chan, phy_idx);
1519
+
1520
+
chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1521
+
rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL_BE4, B_CH_IDX_SEG0, chan_idx, phy_idx);
1522
+
1523
+
rtw8922d_set_gain(rtwdev, chan, RF_PATH_A, phy_idx);
1524
+
rtw8922d_set_gain(rtwdev, chan, RF_PATH_B, phy_idx);
1525
+
1526
+
rtw8922d_set_rx_gain_normal(rtwdev, chan, RF_PATH_A, phy_idx);
1527
+
rtw8922d_set_rx_gain_normal(rtwdev, chan, RF_PATH_B, phy_idx);
1528
+
1529
+
if (band == RTW89_BAND_2G)
1530
+
rtw8922d_set_cck_parameters(rtwdev, chan, phy_idx);
1531
+
}
1532
+
1533
+
static void rtw8922d_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_sb, u8 bw,
1534
+
enum rtw89_phy_idx phy_idx)
1535
+
{
1536
+
switch (bw) {
1537
+
default:
1538
+
case RTW89_CHANNEL_WIDTH_20:
1539
+
rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_BW_BE4, 0x0, phy_idx);
1540
+
rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_PRISB_BE4, 0x0, phy_idx);
1541
+
rtw89_phy_write32_idx(rtwdev, R_RXBW_BE4, B_RXBW_BE4, 0x2, phy_idx);
1542
+
rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW6_BE4, 0x2, phy_idx);
1543
+
rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW7_BE4, 0x2, phy_idx);
1544
+
break;
1545
+
case RTW89_CHANNEL_WIDTH_40:
1546
+
rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_BW_BE4, 0x1, phy_idx);
1547
+
rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_PRISB_BE4, pri_sb, phy_idx);
1548
+
rtw89_phy_write32_idx(rtwdev, R_RXBW_BE4, B_RXBW_BE4, 0x3, phy_idx);
1549
+
rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW6_BE4, 0x3, phy_idx);
1550
+
rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW7_BE4, 0x3, phy_idx);
1551
+
break;
1552
+
case RTW89_CHANNEL_WIDTH_80:
1553
+
rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_BW_BE4, 0x2, phy_idx);
1554
+
rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_PRISB_BE4, pri_sb, phy_idx);
1555
+
rtw89_phy_write32_idx(rtwdev, R_RXBW_BE4, B_RXBW_BE4, 0x4, phy_idx);
1556
+
rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW6_BE4, 0x4, phy_idx);
1557
+
rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW7_BE4, 0x4, phy_idx);
1558
+
break;
1559
+
case RTW89_CHANNEL_WIDTH_160:
1560
+
rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_BW_BE4, 0x3, phy_idx);
1561
+
rtw89_phy_write32_idx(rtwdev, R_BW_BE4, B_PRISB_BE4, pri_sb, phy_idx);
1562
+
rtw89_phy_write32_idx(rtwdev, R_RXBW_BE4, B_RXBW_BE4, 0x5, phy_idx);
1563
+
rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW6_BE4, 0x5, phy_idx);
1564
+
rtw89_phy_write32_idx(rtwdev, R_RXBW67_BE4, B_RXBW7_BE4, 0x5, phy_idx);
1565
+
break;
1566
+
}
1567
+
}
1568
+
1569
+
static const u16 spur_nbi_a[] = {6400};
1570
+
static const u16 spur_csi[] = {6400};
1571
+
1572
+
static u32 rtw8922d_spur_freq(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1573
+
bool nbi_or_csi, enum rtw89_rf_path path)
1574
+
{
1575
+
static const u16 cbw[RTW89_CHANNEL_WIDTH_ORDINARY_NUM] = {
1576
+
20, 40, 80, 160, 320,
1577
+
};
1578
+
u16 freq_lower, freq_upper, freq;
1579
+
const u16 *spur_freq;
1580
+
int spur_freq_nr, i;
1581
+
1582
+
if (rtwdev->hal.aid != RTL8922D_AID7060)
1583
+
return 0;
1584
+
1585
+
if (nbi_or_csi && path == RF_PATH_A) {
1586
+
spur_freq = spur_nbi_a;
1587
+
spur_freq_nr = ARRAY_SIZE(spur_nbi_a);
1588
+
} else if (!nbi_or_csi) {
1589
+
spur_freq = spur_csi;
1590
+
spur_freq_nr = ARRAY_SIZE(spur_csi);
1591
+
} else {
1592
+
return 0;
1593
+
}
1594
+
1595
+
if (chan->band_width >= RTW89_CHANNEL_WIDTH_ORDINARY_NUM)
1596
+
return 0;
1597
+
1598
+
freq_lower = chan->freq - cbw[chan->band_width] / 2;
1599
+
freq_upper = chan->freq + cbw[chan->band_width] / 2;
1600
+
1601
+
for (i = 0; i < spur_freq_nr; i++) {
1602
+
freq = spur_freq[i];
1603
+
1604
+
if (freq >= freq_lower && freq <= freq_upper)
1605
+
return freq;
1606
+
}
1607
+
1608
+
return 0;
1609
+
}
1610
+
1611
+
#define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1612
+
#define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1613
+
#define MAX_TONE_NUM 2048
1614
+
1615
+
static void rtw8922d_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1616
+
const struct rtw89_chan *chan,
1617
+
enum rtw89_phy_idx phy_idx)
1618
+
{
1619
+
s32 freq_diff, csi_idx, csi_tone_idx;
1620
+
u32 spur_freq;
1621
+
1622
+
spur_freq = rtw8922d_spur_freq(rtwdev, chan, false, RF_PATH_AB);
1623
+
if (spur_freq == 0) {
1624
+
rtw89_phy_write32_idx(rtwdev, R_CSI_WGT_BE4, B_CSI_WGT_EN_BE4,
1625
+
0, phy_idx);
1626
+
return;
1627
+
}
1628
+
1629
+
freq_diff = (spur_freq - chan->freq) * 1000000;
1630
+
csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1631
+
s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1632
+
1633
+
rtw89_phy_write32_idx(rtwdev, R_CSI_WGT_BE4, B_CSI_WGT_IDX_BE4,
1634
+
csi_tone_idx, phy_idx);
1635
+
rtw89_phy_write32_idx(rtwdev, R_CSI_WGT_BE4, B_CSI_WGT_EN_BE4, 1, phy_idx);
1636
+
}
1637
+
1638
+
static const struct rtw89_nbi_reg_def rtw8922d_nbi_reg_def[] = {
1639
+
[RF_PATH_A] = {
1640
+
.notch1_idx = {0x241A0, 0xFF},
1641
+
.notch1_frac_idx = {0x241A0, 0xC00},
1642
+
.notch1_en = {0x241A0, 0x1000},
1643
+
.notch2_idx = {0x241AC, 0xFF},
1644
+
.notch2_frac_idx = {0x241AC, 0xC00},
1645
+
.notch2_en = {0x241AC, 0x1000},
1646
+
},
1647
+
[RF_PATH_B] = {
1648
+
.notch1_idx = {0x245A0, 0xFF},
1649
+
.notch1_frac_idx = {0x245A0, 0xC00},
1650
+
.notch1_en = {0x245A0, 0x1000},
1651
+
.notch2_idx = {0x245AC, 0xFF},
1652
+
.notch2_frac_idx = {0x245AC, 0xC00},
1653
+
.notch2_en = {0x245AC, 0x1000},
1654
+
},
1655
+
};
1656
+
1657
+
static void rtw8922d_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1658
+
const struct rtw89_chan *chan,
1659
+
enum rtw89_rf_path path,
1660
+
enum rtw89_phy_idx phy_idx)
1661
+
{
1662
+
const struct rtw89_nbi_reg_def *nbi = &rtw8922d_nbi_reg_def[path];
1663
+
s32 nbi_frac_idx, nbi_frac_tone_idx;
1664
+
s32 nbi_idx, nbi_tone_idx;
1665
+
bool notch2_chk = false;
1666
+
u32 spur_freq, fc;
1667
+
s32 freq_diff;
1668
+
1669
+
spur_freq = rtw8922d_spur_freq(rtwdev, chan, true, path);
1670
+
if (spur_freq == 0) {
1671
+
rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1672
+
nbi->notch1_en.mask, 0, phy_idx);
1673
+
rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1674
+
nbi->notch2_en.mask, 0, phy_idx);
1675
+
return;
1676
+
}
1677
+
1678
+
fc = chan->freq;
1679
+
if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1680
+
fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1681
+
if ((fc > spur_freq &&
1682
+
chan->channel < chan->primary_channel) ||
1683
+
(fc < spur_freq &&
1684
+
chan->channel > chan->primary_channel))
1685
+
notch2_chk = true;
1686
+
}
1687
+
1688
+
freq_diff = (spur_freq - fc) * 1000000;
1689
+
nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
1690
+
&nbi_frac_idx);
1691
+
1692
+
if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1693
+
s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1694
+
} else {
1695
+
u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1696
+
128 : 256;
1697
+
1698
+
s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1699
+
}
1700
+
nbi_frac_tone_idx =
1701
+
s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125);
1702
+
1703
+
if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1704
+
rtw89_phy_write32_idx(rtwdev, nbi->notch2_idx.addr,
1705
+
nbi->notch2_idx.mask, nbi_tone_idx, phy_idx);
1706
+
rtw89_phy_write32_idx(rtwdev, nbi->notch2_frac_idx.addr,
1707
+
nbi->notch2_frac_idx.mask, nbi_frac_tone_idx,
1708
+
phy_idx);
1709
+
rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1710
+
nbi->notch2_en.mask, 0, phy_idx);
1711
+
rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1712
+
nbi->notch2_en.mask, 1, phy_idx);
1713
+
rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1714
+
nbi->notch1_en.mask, 0, phy_idx);
1715
+
} else {
1716
+
rtw89_phy_write32_idx(rtwdev, nbi->notch1_idx.addr,
1717
+
nbi->notch1_idx.mask, nbi_tone_idx, phy_idx);
1718
+
rtw89_phy_write32_idx(rtwdev, nbi->notch1_frac_idx.addr,
1719
+
nbi->notch1_frac_idx.mask, nbi_frac_tone_idx,
1720
+
phy_idx);
1721
+
rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1722
+
nbi->notch1_en.mask, 0, phy_idx);
1723
+
rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1724
+
nbi->notch1_en.mask, 1, phy_idx);
1725
+
rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1726
+
nbi->notch2_en.mask, 0, phy_idx);
1727
+
}
1728
+
}
1729
+
1730
+
static void rtw8922d_spur_elimination(struct rtw89_dev *rtwdev,
1731
+
const struct rtw89_chan *chan,
1732
+
enum rtw89_phy_idx phy_idx)
1733
+
{
1734
+
rtw8922d_set_csi_tone_idx(rtwdev, chan, phy_idx);
1735
+
rtw8922d_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A, phy_idx);
1736
+
rtw8922d_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B, phy_idx);
1737
+
}
1738
+
1739
+
static const u32 bbrst_mask[2] = {B_BE_FEN_BBPLAT_RSTB, B_BE_FEN_BB1PLAT_RSTB};
1740
+
static const u32 glbrst_mask[2] = {B_BE_FEN_BB_IP_RSTN, B_BE_FEN_BB1_IP_RSTN};
1741
+
static const u32 chip_top_bitmask[2] = {0xffff, 0xffff0000};
1742
+
1743
+
static void rtw8922d_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1744
+
{
1745
+
rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0);
1746
+
rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0);
1747
+
rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, chip_top_bitmask[phy_idx], 0x74F9);
1748
+
rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1);
1749
+
rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC_BE4, B_RSTB_ASYNC_BE4, 0, phy_idx);
1750
+
rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x1);
1751
+
}
1752
+
1753
+
static void rtw8922d_bb_postinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1754
+
{
1755
+
rtw89_phy_write32_idx_clr(rtwdev, R_SHAPER_COEFF_BE4, B_SHAPER_COEFF_BE4, phy_idx);
1756
+
rtw89_phy_write32_idx_set(rtwdev, R_SHAPER_COEFF_BE4, B_SHAPER_COEFF_BE4, phy_idx);
1757
+
}
1758
+
1759
+
static void rtw8922d_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1760
+
bool en, enum rtw89_phy_idx phy_idx)
1761
+
{
1762
+
if (en)
1763
+
rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC_BE4, B_RSTB_ASYNC_BE4, 1, phy_idx);
1764
+
else
1765
+
rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC_BE4, B_RSTB_ASYNC_BE4, 0, phy_idx);
1766
+
}
1767
+
1768
+
static int rtw8922d_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev,
1769
+
enum rtw89_rf_path tx_path,
1770
+
enum rtw89_phy_idx phy_idx)
1771
+
{
1772
+
struct rtw89_reg2_def path_com_cr[] = {
1773
+
{0x11A00, 0x21C86900},
1774
+
{0x11A04, 0x00E4E433},
1775
+
{0x11A08, 0x39390CC9},
1776
+
{0x11A10, 0x10CC0000},
1777
+
{0x11A14, 0x00240393},
1778
+
{0x11A18, 0x201C8600},
1779
+
{0x11B38, 0x39393FDB},
1780
+
{0x11B3C, 0x00E4E4FF},
1781
+
};
1782
+
int ret = 0;
1783
+
u32 reg;
1784
+
int i;
1785
+
1786
+
rtw89_phy_write32_idx(rtwdev, R_TXINFO_PATH_BE4, B_TXINFO_PATH_EN_BE4, 0x0, phy_idx);
1787
+
rtw89_phy_write32_idx(rtwdev, R_TXINFO_PATH_BE4, B_TXINFO_PATH_MA_BE4, 0x0, phy_idx);
1788
+
rtw89_phy_write32_idx(rtwdev, R_TXINFO_PATH_BE4, B_TXINFO_PATH_MB_BE4, 0x0, phy_idx);
1789
+
1790
+
if (phy_idx == RTW89_PHY_1 && !rtwdev->dbcc_en)
1791
+
return 0;
1792
+
1793
+
if (tx_path == RF_PATH_A) {
1794
+
path_com_cr[1].data = 0x40031;
1795
+
path_com_cr[2].data = 0x1000C48;
1796
+
path_com_cr[5].data = 0x200;
1797
+
path_com_cr[6].data = 0x1000C48;
1798
+
path_com_cr[7].data = 0x40031;
1799
+
} else if (tx_path == RF_PATH_B) {
1800
+
path_com_cr[1].data = 0x40032;
1801
+
path_com_cr[2].data = 0x1000C88;
1802
+
path_com_cr[5].data = 0x400;
1803
+
path_com_cr[6].data = 0x1000C88;
1804
+
path_com_cr[7].data = 0x40032;
1805
+
} else if (tx_path == RF_PATH_AB) {
1806
+
path_com_cr[1].data = 0x00E4E433;
1807
+
path_com_cr[2].data = 0x39390CC9;
1808
+
path_com_cr[5].data = 0x201C8600;
1809
+
path_com_cr[6].data = 0x1010CC9;
1810
+
path_com_cr[7].data = 0x40433;
1811
+
} else {
1812
+
ret = -EINVAL;
1813
+
}
1814
+
1815
+
for (i = 0; i < ARRAY_SIZE(path_com_cr); i++) {
1816
+
reg = rtw89_mac_reg_by_idx(rtwdev, path_com_cr[i].addr, phy_idx);
1817
+
rtw89_write32(rtwdev, reg, path_com_cr[i].data);
1818
+
}
1819
+
1820
+
return ret;
1821
+
}
1822
+
1823
+
static void rtw8922d_bb_reset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1824
+
{
1825
+
}
1826
+
1827
+
static void rtw8922d_tssi_reset(struct rtw89_dev *rtwdev,
1828
+
enum rtw89_rf_path path,
1829
+
enum rtw89_phy_idx phy_idx)
1830
+
{
1831
+
if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
1832
+
if (phy_idx == RTW89_PHY_0) {
1833
+
rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB0_BE4,
1834
+
B_TXPWR_RSTB0_BE4, 0x0);
1835
+
rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB0_BE4,
1836
+
B_TXPWR_RSTB0_BE4, 0x1);
1837
+
} else {
1838
+
rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB1_BE4,
1839
+
B_TXPWR_RSTB1_BE4, 0x0);
1840
+
rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB1_BE4,
1841
+
B_TXPWR_RSTB1_BE4, 0x1);
1842
+
}
1843
+
} else {
1844
+
rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB0_BE4, B_TXPWR_RSTB0_BE4, 0x0);
1845
+
rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB0_BE4, B_TXPWR_RSTB0_BE4, 0x1);
1846
+
rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB1_BE4, B_TXPWR_RSTB1_BE4, 0x0);
1847
+
rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB1_BE4, B_TXPWR_RSTB1_BE4, 0x1);
1848
+
}
1849
+
}
1850
+
1851
+
static int rtw8922d_ctrl_rx_path_tmac(struct rtw89_dev *rtwdev,
1852
+
enum rtw89_rf_path rx_path,
1853
+
enum rtw89_phy_idx phy_idx)
1854
+
{
1855
+
enum rtw89_rf_path_bit path;
1856
+
1857
+
if (rx_path == RF_PATH_A)
1858
+
path = RF_A;
1859
+
else if (rx_path == RF_PATH_B)
1860
+
path = RF_B;
1861
+
else
1862
+
path = RF_AB;
1863
+
1864
+
rtw89_phy_write32_idx(rtwdev, R_ANT_RX_BE4, B_ANT_RX_BE4, path, phy_idx);
1865
+
rtw89_phy_write32_idx(rtwdev, R_ANT_RX_1RCCA_BE4, B_ANT_RX_1RCCA_BE4,
1866
+
path, phy_idx);
1867
+
1868
+
if (rx_path == RF_PATH_AB) {
1869
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC0_BE4, B_RXCH_MCS4_BE4, 8, phy_idx);
1870
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS5_BE4, 4, phy_idx);
1871
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS6_BE4, 3, phy_idx);
1872
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS7_BE4, 7, phy_idx);
1873
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS8_BE4, 2, phy_idx);
1874
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS9_BE4, 2, phy_idx);
1875
+
rtw89_phy_write32_idx(rtwdev, R_RX_AWGN00_BE4, B_RX_AWGN04_BE4, 4, phy_idx);
1876
+
rtw89_phy_write32_idx(rtwdev, R_RX_AWGN00_BE4, B_RX_AWGN07_BE4, 2, phy_idx);
1877
+
rtw89_phy_write32_idx(rtwdev, R_RX_AWGN01_BE4, B_RX_AWGN09_BE4, 0, phy_idx);
1878
+
rtw89_phy_write32_idx(rtwdev, R_RX_AWGN02_BE4, B_RX_AWGN11_BE4, 1, phy_idx);
1879
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC04_BE4, 8, phy_idx);
1880
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC05_BE4, 5, phy_idx);
1881
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC06_BE4, 3, phy_idx);
1882
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC07_BE4, 5, phy_idx);
1883
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC08_BE4, 1, phy_idx);
1884
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC01_BE4, B_RX_LDPC09_BE4, 2, phy_idx);
1885
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC10_BE4, 4, phy_idx);
1886
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC11_BE4, 2, phy_idx);
1887
+
} else {
1888
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC0_BE4, B_RXCH_MCS4_BE4, 13, phy_idx);
1889
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS5_BE4, 15, phy_idx);
1890
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS6_BE4, 6, phy_idx);
1891
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS7_BE4, 15, phy_idx);
1892
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS8_BE4, 4, phy_idx);
1893
+
rtw89_phy_write32_idx(rtwdev, R_RXCH_BCC1_BE4, B_RXCH_MCS9_BE4, 15, phy_idx);
1894
+
rtw89_phy_write32_idx(rtwdev, R_RX_AWGN00_BE4, B_RX_AWGN04_BE4, 9, phy_idx);
1895
+
rtw89_phy_write32_idx(rtwdev, R_RX_AWGN00_BE4, B_RX_AWGN07_BE4, 3, phy_idx);
1896
+
rtw89_phy_write32_idx(rtwdev, R_RX_AWGN01_BE4, B_RX_AWGN09_BE4, 1, phy_idx);
1897
+
rtw89_phy_write32_idx(rtwdev, R_RX_AWGN02_BE4, B_RX_AWGN11_BE4, 0, phy_idx);
1898
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC04_BE4, 9, phy_idx);
1899
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC05_BE4, 8, phy_idx);
1900
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC06_BE4, 6, phy_idx);
1901
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC07_BE4, 16, phy_idx);
1902
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC00_BE4, B_RX_LDPC08_BE4, 4, phy_idx);
1903
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC01_BE4, B_RX_LDPC09_BE4, 9, phy_idx);
1904
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC10_BE4, 9, phy_idx);
1905
+
rtw89_phy_write32_idx(rtwdev, R_RX_LDPC02_BE4, B_RX_LDPC11_BE4, 7, phy_idx);
1906
+
}
1907
+
1908
+
return 0;
1909
+
}
1910
+
1911
+
static void rtw8922d_set_digital_pwr_comp(struct rtw89_dev *rtwdev,
1912
+
const struct rtw89_chan *chan, u8 nss,
1913
+
enum rtw89_rf_path path,
1914
+
enum rtw89_phy_idx phy_idx)
1915
+
{
1916
+
#define DIGITAL_PWR_COMP_REG_NUM 22
1917
+
static const u32 pw_comp_cr[2] = {R_RX_PATH0_TBL0_BE4, R_RX_PATH1_TBL0_BE4};
1918
+
const __le32 (*pwr_comp_val)[2][RTW89_TX_COMP_BAND_NR]
1919
+
[BB_PATH_NUM_8922D][DIGITAL_PWR_COMP_REG_NUM];
1920
+
struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1921
+
const struct rtw89_fw_element_hdr *txcomp_elm = elm_info->tx_comp;
1922
+
const __le32 *digital_pwr_comp;
1923
+
u32 addr, val;
1924
+
u32 i;
1925
+
1926
+
if (sizeof(*pwr_comp_val) != le32_to_cpu(txcomp_elm->size)) {
1927
+
rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
1928
+
"incorrect power comp size %d\n",
1929
+
le32_to_cpu(txcomp_elm->size));
1930
+
return;
1931
+
}
1932
+
1933
+
pwr_comp_val = (const void *)txcomp_elm->u.common.contents;
1934
+
digital_pwr_comp = (*pwr_comp_val)[nss][chan->tx_comp_band][path];
1935
+
addr = pw_comp_cr[path];
1936
+
1937
+
for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) {
1938
+
val = le32_to_cpu(digital_pwr_comp[i]);
1939
+
rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
1940
+
}
1941
+
}
1942
+
1943
+
static void rtw8922d_digital_pwr_comp(struct rtw89_dev *rtwdev,
1944
+
enum rtw89_phy_idx phy_idx)
1945
+
{
1946
+
const struct rtw89_chan *chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
1947
+
const struct rtw89_chan *chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
1948
+
1949
+
if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
1950
+
rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 0, RF_PATH_A, RTW89_PHY_0);
1951
+
rtw8922d_set_digital_pwr_comp(rtwdev, chan1, 0, RF_PATH_B, RTW89_PHY_1);
1952
+
} else {
1953
+
rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 1, RF_PATH_A, phy_idx);
1954
+
rtw8922d_set_digital_pwr_comp(rtwdev, chan0, 1, RF_PATH_B, phy_idx);
1955
+
}
1956
+
}
1957
+
1958
+
static int rtw8922d_ctrl_mlo(struct rtw89_dev *rtwdev, enum rtw89_mlo_dbcc_mode mode,
1959
+
bool pwr_comp)
1960
+
{
1961
+
const struct rtw89_chan *chan1;
1962
+
u32 reg0, reg1;
1963
+
u8 cck_phy_idx;
1964
+
1965
+
if (mode == MLO_2_PLUS_0_1RF) {
1966
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
1967
+
udelay(1);
1968
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
1969
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xAFFF);
1970
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEBAD);
1971
+
udelay(1);
1972
+
1973
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
1974
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEAAD);
1975
+
} else if (mode == MLO_0_PLUS_2_1RF) {
1976
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
1977
+
udelay(1);
1978
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
1979
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xAFFF);
1980
+
udelay(1);
1981
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEFFF);
1982
+
1983
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
1984
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEEFF);
1985
+
} else if ((mode == MLO_1_PLUS_1_1RF) || (mode == DBCC_LEGACY)) {
1986
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
1987
+
udelay(1);
1988
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
1989
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xAFFF);
1990
+
udelay(1);
1991
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
1992
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x3AAB);
1993
+
} else {
1994
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x6180);
1995
+
udelay(1);
1996
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
1997
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x180);
1998
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
1999
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0x0);
2000
+
}
2001
+
2002
+
if (pwr_comp)
2003
+
rtw8922d_digital_pwr_comp(rtwdev, RTW89_PHY_0);
2004
+
2005
+
reg0 = R_BBWRAP_ELMSR_BE4;
2006
+
reg1 = rtw89_mac_reg_by_idx(rtwdev, reg0, 1);
2007
+
2008
+
if (mode == MLO_2_PLUS_0_1RF) {
2009
+
rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4,
2010
+
B_SYS_DBCC_24G_BAND_SEL_BE4, RTW89_PHY_0);
2011
+
rtw89_write32_mask(rtwdev, reg0, B_BBWRAP_ELMSR_EN_BE4, 0);
2012
+
rtw89_write32_mask(rtwdev, reg1, B_BBWRAP_ELMSR_EN_BE4, 0);
2013
+
} else if (mode == MLO_0_PLUS_2_1RF) {
2014
+
rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4,
2015
+
B_SYS_DBCC_24G_BAND_SEL_BE4, RTW89_PHY_0);
2016
+
rtw89_write32_mask(rtwdev, reg0, B_BBWRAP_ELMSR_EN_BE4, 0);
2017
+
rtw89_write32_mask(rtwdev, reg1, B_BBWRAP_ELMSR_EN_BE4, 0);
2018
+
} else if ((mode == MLO_1_PLUS_1_1RF) || (mode == DBCC_LEGACY)) {
2019
+
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
2020
+
cck_phy_idx = chan1->band_type == RTW89_BAND_2G ?
2021
+
RTW89_PHY_1 : RTW89_PHY_0;
2022
+
2023
+
rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4,
2024
+
B_SYS_DBCC_24G_BAND_SEL_BE4, cck_phy_idx);
2025
+
rtw89_write32_mask(rtwdev, reg0, B_BBWRAP_ELMSR_EN_BE4, 0x3);
2026
+
rtw89_write32_mask(rtwdev, reg1, B_BBWRAP_ELMSR_EN_BE4, 0x3);
2027
+
} else {
2028
+
rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4,
2029
+
B_SYS_DBCC_24G_BAND_SEL_BE4, RTW89_PHY_0);
2030
+
rtw89_write32_mask(rtwdev, reg0, B_BBWRAP_ELMSR_EN_BE4, 0);
2031
+
rtw89_write32_mask(rtwdev, reg1, B_BBWRAP_ELMSR_EN_BE4, 0);
2032
+
}
2033
+
2034
+
udelay(1);
2035
+
2036
+
return 0;
2037
+
}
2038
+
2039
+
static void rtw8922d_bb_sethw(struct rtw89_dev *rtwdev)
2040
+
{
2041
+
struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
2042
+
struct rtw89_hal *hal = &rtwdev->hal;
2043
+
enum rtw89_phy_idx phy_idx;
2044
+
u32 reg;
2045
+
2046
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, RTW89_PHY_0);
2047
+
rtw89_write32_clr(rtwdev, reg, B_BE_PWR_CTRL_SEL);
2048
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, RTW89_PHY_1);
2049
+
rtw89_write32_clr(rtwdev, reg, B_BE_PWR_CTRL_SEL);
2050
+
2051
+
if (hal->cid == RTL8922D_CID7090) {
2052
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_PWR_BOOST_BE4, RTW89_PHY_0);
2053
+
rtw89_write32_set(rtwdev, reg, B_PWR_BOOST_BE4);
2054
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_PWR_BOOST_BE4, RTW89_PHY_1);
2055
+
rtw89_write32_set(rtwdev, reg, B_PWR_BOOST_BE4);
2056
+
}
2057
+
2058
+
rtw89_phy_write32_mask(rtwdev, R_TX_ERROR_SEL_BE4, B_TX_ERROR_PSDU_BE4, 0);
2059
+
rtw89_phy_write32_mask(rtwdev, R_TX_ERROR_SEL_BE4, B_TX_ERROR_NSYM_BE4, 1);
2060
+
rtw89_phy_write32_mask(rtwdev, R_TX_ERROR_SEL_BE4, B_TX_ERROR_LSIG_BE4, 1);
2061
+
rtw89_phy_write32_mask(rtwdev, R_TX_ERROR_SEL_BE4, B_TX_ERROR_TXINFO_BE4, 1);
2062
+
rtw89_phy_write32_mask(rtwdev, R_TXERRCT_EN_BE4, B_TXERRCT_EN_BE4, 0);
2063
+
rtw89_phy_write32_mask(rtwdev, R_TXERRCT1_EN_BE4, B_TXERRCT1_EN_BE4, 0);
2064
+
rtw89_phy_write32_idx(rtwdev, R_IMR_TX_ERROR_BE4, B_IMR_TX_ERROR_BE4, 1, RTW89_PHY_0);
2065
+
rtw89_phy_write32_idx(rtwdev, R_IMR_TX_ERROR_BE4, B_IMR_TX_ERROR_BE4, 1, RTW89_PHY_1);
2066
+
2067
+
rtw8922d_ctrl_mlo(rtwdev, rtwdev->mlo_dbcc_mode, false);
2068
+
2069
+
/* read these registers after loading BB parameters */
2070
+
for (phy_idx = RTW89_PHY_0; phy_idx < RTW89_PHY_NUM; phy_idx++) {
2071
+
gain->ref_gain_base[phy_idx] =
2072
+
rtw89_phy_read32_idx(rtwdev, R_OFDM_OFST_P0_BE4,
2073
+
B_OFDM_OFST_P0_BE4, phy_idx);
2074
+
gain->cck_rpl_base[phy_idx] =
2075
+
rtw89_phy_read32_idx(rtwdev, R_CCK_RPL_OFST_BE4,
2076
+
B_CCK_RPL_OFST_BE4, phy_idx);
2077
+
}
2078
+
}
2079
+
2080
+
static void rtw8922d_set_channel_bb(struct rtw89_dev *rtwdev,
2081
+
const struct rtw89_chan *chan,
2082
+
enum rtw89_phy_idx phy_idx)
2083
+
{
2084
+
struct rtw89_hal *hal = &rtwdev->hal;
2085
+
bool cck_en = chan->band_type == RTW89_BAND_2G;
2086
+
u8 pri_sb = chan->pri_sb_idx;
2087
+
u32 val;
2088
+
2089
+
rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, phy_idx);
2090
+
rtw8922d_ctrl_ch(rtwdev, chan, phy_idx);
2091
+
rtw8922d_ctrl_bw(rtwdev, pri_sb, chan->band_width, phy_idx);
2092
+
rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(rtwdev, chan, phy_idx);
2093
+
2094
+
if (cck_en)
2095
+
rtw8922d_ctrl_sco_cck(rtwdev, chan->primary_channel,
2096
+
chan->band_width, phy_idx);
2097
+
2098
+
rtw8922d_spur_elimination(rtwdev, chan, phy_idx);
2099
+
2100
+
if (hal->cid == RTL8922D_CID7025) {
2101
+
if (chan->band_width == RTW89_CHANNEL_WIDTH_160)
2102
+
val = 0x1f9;
2103
+
else if (chan->band_width == RTW89_CHANNEL_WIDTH_80)
2104
+
val = 0x1f5;
2105
+
else
2106
+
val = 0x1e2;
2107
+
2108
+
rtw89_phy_write32_idx(rtwdev, R_AWGN_DET_BE4, B_AWGN_DET_BE4, val, phy_idx);
2109
+
}
2110
+
2111
+
rtw8922d_tssi_reset(rtwdev, RF_PATH_AB, phy_idx);
2112
+
}
2113
+
2114
+
static void rtw8922d_pre_set_channel_bb(struct rtw89_dev *rtwdev,
2115
+
enum rtw89_phy_idx phy_idx)
2116
+
{
2117
+
if (!rtwdev->dbcc_en)
2118
+
return;
2119
+
2120
+
rtw89_phy_write32_mask(rtwdev, R_SYS_DBCC_BE4, B_SYS_DBCC_BE4, 0x0);
2121
+
2122
+
if (phy_idx == RTW89_PHY_0) {
2123
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
2124
+
fsleep(1);
2125
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
2126
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xAFFF);
2127
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEBAD);
2128
+
fsleep(1);
2129
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
2130
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEAAD);
2131
+
} else {
2132
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xBBBB);
2133
+
fsleep(1);
2134
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x3);
2135
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xAFFF);
2136
+
fsleep(1);
2137
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEFFF);
2138
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_BB_CLK_BE4, 0x0);
2139
+
rtw89_phy_write32_mask(rtwdev, R_EMLSR_SWITCH_BE4, B_EMLSR_SWITCH_BE4, 0xEEFF);
2140
+
}
2141
+
2142
+
fsleep(1);
2143
+
}
2144
+
2145
+
static void rtw8922d_post_set_channel_bb(struct rtw89_dev *rtwdev,
2146
+
enum rtw89_mlo_dbcc_mode mode,
2147
+
enum rtw89_phy_idx phy_idx)
2148
+
{
2149
+
if (!rtwdev->dbcc_en)
2150
+
return;
2151
+
2152
+
rtw8922d_ctrl_mlo(rtwdev, mode, true);
2153
+
}
2154
+
2155
+
static void rtw8922d_set_channel(struct rtw89_dev *rtwdev,
2156
+
const struct rtw89_chan *chan,
2157
+
enum rtw89_mac_idx mac_idx,
2158
+
enum rtw89_phy_idx phy_idx)
2159
+
{
2160
+
rtw8922d_set_channel_mac(rtwdev, chan, mac_idx);
2161
+
rtw8922d_set_channel_bb(rtwdev, chan, phy_idx);
2162
+
rtw8922d_set_channel_rf(rtwdev, chan, phy_idx);
2163
+
}
2164
+
2165
+
static void __rtw8922d_dack_reset(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2166
+
{
2167
+
rtw89_phy_write32_mask(rtwdev, 0x3c000 + (path << 8), BIT(17), 0x0);
2168
+
rtw89_phy_write32_mask(rtwdev, 0x3c000 + (path << 8), BIT(17), 0x1);
2169
+
}
2170
+
2171
+
static void rtw8922d_dack_reset(struct rtw89_dev *rtwdev)
2172
+
{
2173
+
__rtw8922d_dack_reset(rtwdev, RF_PATH_A);
2174
+
__rtw8922d_dack_reset(rtwdev, RF_PATH_B);
2175
+
}
2176
+
2177
+
static
2178
+
void rtw8922d_hal_reset(struct rtw89_dev *rtwdev,
2179
+
enum rtw89_phy_idx phy_idx, enum rtw89_mac_idx mac_idx,
2180
+
enum rtw89_band band, u32 *tx_en, bool enter)
2181
+
{
2182
+
if (enter) {
2183
+
rtw89_chip_stop_sch_tx(rtwdev, mac_idx, tx_en, RTW89_SCH_TX_SEL_ALL);
2184
+
rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
2185
+
rtw8922d_dack_reset(rtwdev);
2186
+
rtw8922d_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
2187
+
fsleep(40);
2188
+
rtw8922d_bb_reset_en(rtwdev, band, false, phy_idx);
2189
+
} else {
2190
+
rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
2191
+
rtw8922d_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
2192
+
rtw8922d_bb_reset_en(rtwdev, band, true, phy_idx);
2193
+
rtw89_chip_resume_sch_tx(rtwdev, mac_idx, *tx_en);
2194
+
}
2195
+
}
2196
+
2197
+
static void rtw8922d_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
2198
+
struct rtw89_channel_help_params *p,
2199
+
const struct rtw89_chan *chan,
2200
+
enum rtw89_mac_idx mac_idx,
2201
+
enum rtw89_phy_idx phy_idx)
2202
+
{
2203
+
if (enter) {
2204
+
rtw8922d_pre_set_channel_bb(rtwdev, phy_idx);
2205
+
rtw8922d_pre_set_channel_rf(rtwdev, phy_idx);
2206
+
}
2207
+
2208
+
rtw8922d_hal_reset(rtwdev, phy_idx, mac_idx, chan->band_type, &p->tx_en, enter);
2209
+
2210
+
if (!enter) {
2211
+
rtw8922d_post_set_channel_bb(rtwdev, rtwdev->mlo_dbcc_mode, phy_idx);
2212
+
rtw8922d_post_set_channel_rf(rtwdev, phy_idx);
2213
+
}
2214
+
}
2215
+
2216
+
static void rtw8922d_rfk_init(struct rtw89_dev *rtwdev)
2217
+
{
2218
+
struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
2219
+
struct rtw89_lck_info *lck = &rtwdev->lck;
2220
+
2221
+
rtwdev->is_tssi_mode[RF_PATH_A] = false;
2222
+
rtwdev->is_tssi_mode[RF_PATH_B] = false;
2223
+
memset(rfk_mcc, 0, sizeof(*rfk_mcc));
2224
+
memset(lck, 0, sizeof(*lck));
2225
+
}
2226
+
2227
+
static void __rtw8922d_rfk_init_late(struct rtw89_dev *rtwdev,
2228
+
enum rtw89_phy_idx phy_idx,
2229
+
const struct rtw89_chan *chan)
2230
+
{
2231
+
rtw8922d_rfk_mlo_ctrl(rtwdev);
2232
+
2233
+
rtw89_phy_rfk_pre_ntfy_and_wait(rtwdev, phy_idx, 5);
2234
+
if (!test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
2235
+
rtw89_phy_rfk_rxdck_and_wait(rtwdev, phy_idx, chan, false, 128);
2236
+
if (phy_idx == RTW89_PHY_0)
2237
+
rtw89_phy_rfk_dack_and_wait(rtwdev, phy_idx, chan, 58);
2238
+
}
2239
+
2240
+
static void rtw8922d_rfk_init_late(struct rtw89_dev *rtwdev)
2241
+
{
2242
+
const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2243
+
2244
+
__rtw8922d_rfk_init_late(rtwdev, RTW89_PHY_0, chan);
2245
+
if (rtwdev->dbcc_en)
2246
+
__rtw8922d_rfk_init_late(rtwdev, RTW89_PHY_1, chan);
2247
+
}
2248
+
2249
+
static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
2250
+
{
2251
+
u32 rf_mode;
2252
+
u8 path;
2253
+
int ret;
2254
+
2255
+
for (path = 0; path < RF_PATH_NUM_8922D; path++) {
2256
+
if (!(kpath & BIT(path)))
2257
+
continue;
2258
+
2259
+
ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2,
2260
+
2, 5000, false, rtwdev, path, 0x00,
2261
+
RR_MOD_MASK);
2262
+
rtw89_debug(rtwdev, RTW89_DBG_RFK,
2263
+
"[RFK] Wait S%d to Rx mode!! (ret = %d)\n",
2264
+
path, ret);
2265
+
}
2266
+
}
2267
+
2268
+
static void __rtw8922d_tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2269
+
{
2270
+
u8 path;
2271
+
2272
+
for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
2273
+
u32 addr_ofst = (phy_idx << 12) + (path << 8);
2274
+
2275
+
rtw89_phy_write32_mask(rtwdev, R_TSSI_DCK_MOV_AVG_LEN_P0_BE4 + addr_ofst,
2276
+
B_TSSI_DCK_MOV_AVG_LEN_P0_BE4, 0x4);
2277
+
rtw89_phy_write32_clr(rtwdev, R_USED_TSSI_TRK_ON_P0_BE4 + addr_ofst,
2278
+
B_USED_TSSI_TRK_ON_P0_BE4);
2279
+
rtw89_phy_write32_set(rtwdev, R_USED_TSSI_TRK_ON_P0_BE4 + addr_ofst,
2280
+
B_USED_TSSI_TRK_ON_P0_BE4);
2281
+
rtw89_phy_write32_clr(rtwdev, R_TSSI_EN_P0_BE4 + addr_ofst,
2282
+
B_TSSI_EN_P0_BE4);
2283
+
rtw89_phy_write32_mask(rtwdev, R_TSSI_EN_P0_BE4 + addr_ofst,
2284
+
B_TSSI_EN_P0_BE4, 0x3);
2285
+
}
2286
+
}
2287
+
2288
+
static void __rtw8922d_tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2289
+
{
2290
+
u8 path;
2291
+
2292
+
for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
2293
+
u32 addr_ofst = (phy_idx << 12) + (path << 8);
2294
+
2295
+
rtw89_phy_write32_clr(rtwdev, R_TSSI_DCK_MOV_AVG_LEN_P0_BE4 + addr_ofst,
2296
+
B_TSSI_DCK_MOV_AVG_LEN_P0_BE4);
2297
+
rtw89_phy_write32_clr(rtwdev, R_USED_TSSI_TRK_ON_P0_BE4 + addr_ofst,
2298
+
B_USED_TSSI_TRK_ON_P0_BE4);
2299
+
rtw89_phy_write32_clr(rtwdev, R_TSSI_EN_P0_BE4 + addr_ofst,
2300
+
B_TSSI_EN_P0_BE4);
2301
+
}
2302
+
}
2303
+
2304
+
static void rtw8922d_rfk_tssi(struct rtw89_dev *rtwdev,
2305
+
enum rtw89_phy_idx phy_idx,
2306
+
const struct rtw89_chan *chan,
2307
+
enum rtw89_tssi_mode tssi_mode,
2308
+
unsigned int ms)
2309
+
{
2310
+
int ret;
2311
+
2312
+
ret = rtw89_phy_rfk_tssi_and_wait(rtwdev, phy_idx, chan, tssi_mode, ms);
2313
+
if (ret) {
2314
+
rtwdev->is_tssi_mode[RF_PATH_A] = false;
2315
+
rtwdev->is_tssi_mode[RF_PATH_B] = false;
2316
+
} else {
2317
+
rtwdev->is_tssi_mode[RF_PATH_A] = true;
2318
+
rtwdev->is_tssi_mode[RF_PATH_B] = true;
2319
+
}
2320
+
}
2321
+
2322
+
static void rtw8922d_rfk_channel(struct rtw89_dev *rtwdev,
2323
+
struct rtw89_vif_link *rtwvif_link)
2324
+
{
2325
+
enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
2326
+
const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2327
+
enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
2328
+
u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB, chanctx_idx);
2329
+
u32 tx_en;
2330
+
2331
+
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_START);
2332
+
rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
2333
+
_wait_rx_mode(rtwdev, RF_AB);
2334
+
2335
+
rtw89_phy_rfk_pre_ntfy_and_wait(rtwdev, phy_idx, 5);
2336
+
rtw89_phy_rfk_txgapk_and_wait(rtwdev, phy_idx, chan, 54);
2337
+
rtw89_phy_rfk_txiqk_and_wait(rtwdev, phy_idx, chan, 45);
2338
+
rtw89_phy_rfk_iqk_and_wait(rtwdev, phy_idx, chan, 84);
2339
+
rtw8922d_rfk_tssi(rtwdev, phy_idx, chan, RTW89_TSSI_NORMAL, 20);
2340
+
rtw89_phy_rfk_cim3k_and_wait(rtwdev, phy_idx, chan, 44);
2341
+
rtw89_phy_rfk_dpk_and_wait(rtwdev, phy_idx, chan, 68);
2342
+
rtw89_phy_rfk_rxdck_and_wait(rtwdev, RTW89_PHY_0, chan, true, 32);
2343
+
2344
+
rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
2345
+
rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_STOP);
2346
+
}
2347
+
2348
+
static void rtw8922d_rfk_band_changed(struct rtw89_dev *rtwdev,
2349
+
enum rtw89_phy_idx phy_idx,
2350
+
const struct rtw89_chan *chan)
2351
+
{
2352
+
}
2353
+
2354
+
static void rtw8922d_rfk_scan(struct rtw89_dev *rtwdev,
2355
+
struct rtw89_vif_link *rtwvif_link,
2356
+
bool start)
2357
+
{
2358
+
if (start)
2359
+
__rtw8922d_tssi_disable(rtwdev, rtwvif_link->phy_idx);
2360
+
else
2361
+
__rtw8922d_tssi_enable(rtwdev, rtwvif_link->phy_idx);
2362
+
}
2363
+
2364
+
static void rtw8922d_rfk_track(struct rtw89_dev *rtwdev)
2365
+
{
2366
+
rtw8922d_lck_track(rtwdev);
2367
+
}
2368
+
2369
+
static const struct rtw89_reg_def rtw8922d_txpwr_ref[][3] = {
2370
+
{{ .addr = R_TXAGC_REF_DBM_PATH0_TBL0_BE4,
2371
+
.mask = B_TXAGC_OFDM_REF_DBM_PATH0_TBL0_BE4 },
2372
+
{ .addr = R_TXAGC_REF_DBM_PATH0_TBL0_BE4,
2373
+
.mask = B_TXAGC_CCK_REF_DBM_PATH0_TBL0_BE4 },
2374
+
{ .addr = R_TSSI_K_OFDM_PATH0_TBL0_BE4,
2375
+
.mask = B_TSSI_K_OFDM_PATH0_TBL0_BE4 }
2376
+
},
2377
+
{{ .addr = R_TXAGC_REF_DBM_PATH0_TBL1_BE4,
2378
+
.mask = B_TXAGC_OFDM_REF_DBM_PATH0_TBL1_BE4 },
2379
+
{ .addr = R_TXAGC_REF_DBM_PATH0_TBL1_BE4,
2380
+
.mask = B_TXAGC_CCK_REF_DBM_PATH0_TBL1_BE4 },
2381
+
{ .addr = R_TSSI_K_OFDM_PATH0_TBL1_BE4,
2382
+
.mask = B_TSSI_K_OFDM_PATH0_TBL1_BE4 }
2383
+
},
2384
+
};
2385
+
2386
+
static void rtw8922d_set_txpwr_diff(struct rtw89_dev *rtwdev,
2387
+
const struct rtw89_chan *chan,
2388
+
enum rtw89_phy_idx phy_idx)
2389
+
{
2390
+
s16 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan);
2391
+
const struct rtw89_chip_info *chip = rtwdev->chip;
2392
+
static const u32 path_ofst[] = {0x0, 0x100};
2393
+
const struct rtw89_reg_def *txpwr_ref;
2394
+
s16 tssi_k_ofst = abs(pwr_ofst);
2395
+
s16 ofst_dec[RF_PATH_NUM_8922D];
2396
+
s16 tssi_k[RF_PATH_NUM_8922D];
2397
+
s16 pwr_ref_ofst;
2398
+
s16 pwr_ref = 16;
2399
+
u8 i;
2400
+
2401
+
pwr_ref <<= chip->txpwr_factor_rf;
2402
+
pwr_ref_ofst = pwr_ref - rtw89_phy_txpwr_bb_to_rf(rtwdev, abs(pwr_ofst));
2403
+
2404
+
ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? pwr_ref : pwr_ref_ofst;
2405
+
ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ref_ofst : pwr_ref;
2406
+
tssi_k[RF_PATH_A] = pwr_ofst > 0 ? 0 : tssi_k_ofst;
2407
+
tssi_k[RF_PATH_B] = pwr_ofst > 0 ? tssi_k_ofst : 0;
2408
+
2409
+
for (i = 0; i < RF_PATH_NUM_8922D; i++) {
2410
+
txpwr_ref = rtw8922d_txpwr_ref[phy_idx];
2411
+
2412
+
rtw89_phy_write32_mask(rtwdev, txpwr_ref[0].addr + path_ofst[i],
2413
+
txpwr_ref[0].mask, ofst_dec[i]);
2414
+
rtw89_phy_write32_mask(rtwdev, txpwr_ref[1].addr + path_ofst[i],
2415
+
txpwr_ref[1].mask, ofst_dec[i]);
2416
+
rtw89_phy_write32_mask(rtwdev, txpwr_ref[2].addr + path_ofst[i],
2417
+
txpwr_ref[2].mask, tssi_k[i]);
2418
+
}
2419
+
}
2420
+
2421
+
static void rtw8922d_set_txpwr_ref(struct rtw89_dev *rtwdev,
2422
+
const struct rtw89_chan *chan,
2423
+
enum rtw89_phy_idx phy_idx)
2424
+
{
2425
+
s16 ref_ofdm = 0;
2426
+
s16 ref_cck = 0;
2427
+
2428
+
rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
2429
+
2430
+
rtw8922d_set_txpwr_diff(rtwdev, chan, phy_idx);
2431
+
2432
+
rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_BE_PWR_REF_CTRL,
2433
+
B_BE_PWR_REF_CTRL_OFDM, ref_ofdm);
2434
+
rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_BE_PWR_REF_CTRL,
2435
+
B_BE_PWR_REF_CTRL_CCK, ref_cck);
2436
+
}
2437
+
2438
+
static void rtw8922d_set_txpwr_sar_diff(struct rtw89_dev *rtwdev,
2439
+
const struct rtw89_chan *chan,
2440
+
enum rtw89_phy_idx phy_idx)
2441
+
{
2442
+
struct rtw89_sar_parm sar_parm = {
2443
+
.center_freq = chan->freq,
2444
+
.force_path = true,
2445
+
};
2446
+
s16 sar_rf;
2447
+
s8 sar_mac;
2448
+
2449
+
if (phy_idx != RTW89_PHY_0)
2450
+
return;
2451
+
2452
+
sar_parm.path = RF_PATH_A;
2453
+
sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2454
+
sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2455
+
rtw89_phy_write32_mask(rtwdev, R_P0_TXPWRB_BE4, B_TXPWRB_MAX_BE, sar_rf);
2456
+
2457
+
sar_parm.path = RF_PATH_B;
2458
+
sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2459
+
sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2460
+
rtw89_phy_write32_mask(rtwdev, R_P1_TXPWRB_BE4, B_TXPWRB_MAX_BE, sar_rf);
2461
+
}
2462
+
2463
+
static void rtw8922d_set_txpwr(struct rtw89_dev *rtwdev,
2464
+
const struct rtw89_chan *chan,
2465
+
enum rtw89_phy_idx phy_idx)
2466
+
{
2467
+
rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
2468
+
rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
2469
+
rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
2470
+
rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
2471
+
rtw8922d_set_txpwr_ref(rtwdev, chan, phy_idx);
2472
+
rtw8922d_set_txpwr_sar_diff(rtwdev, chan, phy_idx);
2473
+
}
2474
+
2475
+
static void rtw8922d_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
2476
+
enum rtw89_phy_idx phy_idx)
2477
+
{
2478
+
const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, phy_idx);
2479
+
2480
+
rtw8922d_set_txpwr_ref(rtwdev, chan, phy_idx);
2481
+
}
2482
+
2483
+
static void rtw8922d_ctrl_trx_path(struct rtw89_dev *rtwdev,
2484
+
enum rtw89_rf_path tx_path, u8 tx_nss,
2485
+
enum rtw89_rf_path rx_path, u8 rx_nss)
2486
+
{
2487
+
enum rtw89_phy_idx phy_idx;
2488
+
2489
+
for (phy_idx = RTW89_PHY_0; phy_idx <= RTW89_PHY_1; phy_idx++) {
2490
+
rtw8922d_ctrl_tx_path_tmac(rtwdev, tx_path, phy_idx);
2491
+
rtw8922d_ctrl_rx_path_tmac(rtwdev, rx_path, phy_idx);
2492
+
2493
+
rtw8922d_tssi_reset(rtwdev, rx_path, phy_idx);
2494
+
}
2495
+
}
2496
+
2497
+
static void rtw8922d_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
2498
+
enum rtw89_phy_idx phy_idx)
2499
+
{
2500
+
if (en) {
2501
+
rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x3, phy_idx);
2502
+
rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_A, B_RXBY_WBADC_A,
2503
+
0xf, phy_idx);
2504
+
rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_A, B_BT_RXBY_WBADC_A,
2505
+
0x0, phy_idx);
2506
+
rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x0, phy_idx);
2507
+
rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x80, phy_idx);
2508
+
rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x8080, phy_idx);
2509
+
rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x34, phy_idx);
2510
+
rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x34, phy_idx);
2511
+
rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x3, phy_idx);
2512
+
rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_B, B_RXBY_WBADC_B,
2513
+
0xf, phy_idx);
2514
+
rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_B, B_BT_RXBY_WBADC_B,
2515
+
0x0, phy_idx);
2516
+
rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x0, phy_idx);
2517
+
rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA1_B, 0x80, phy_idx);
2518
+
rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x34, phy_idx);
2519
+
rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x34, phy_idx);
2520
+
} else {
2521
+
rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x0, phy_idx);
2522
+
rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_A, B_RXBY_WBADC_A,
2523
+
0x0, phy_idx);
2524
+
rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_A, B_BT_RXBY_WBADC_A,
2525
+
0x1, phy_idx);
2526
+
rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x1, phy_idx);
2527
+
rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x1a, phy_idx);
2528
+
rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x2a2a, phy_idx);
2529
+
rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x7a6, phy_idx);
2530
+
rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x26, phy_idx);
2531
+
rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x0, phy_idx);
2532
+
rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_B, B_RXBY_WBADC_B,
2533
+
0x0, phy_idx);
2534
+
rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_B, B_BT_RXBY_WBADC_B,
2535
+
0x1, phy_idx);
2536
+
rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x1, phy_idx);
2537
+
rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA1_B, 0x2a, phy_idx);
2538
+
rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x7a6, phy_idx);
2539
+
rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x26, phy_idx);
2540
+
}
2541
+
}
2542
+
2543
+
static void rtw8922d_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2544
+
{
2545
+
const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2546
+
enum rtw89_band band = chan->band_type;
2547
+
struct rtw89_hal *hal = &rtwdev->hal;
2548
+
u8 ntx_path = RF_PATH_AB;
2549
+
u8 nrx_path = RF_PATH_AB;
2550
+
u32 tx_en0, tx_en1;
2551
+
u8 rx_nss = 2;
2552
+
2553
+
if (hal->antenna_tx == RF_A)
2554
+
ntx_path = RF_PATH_A;
2555
+
else if (hal->antenna_tx == RF_B)
2556
+
ntx_path = RF_PATH_B;
2557
+
2558
+
if (hal->antenna_rx == RF_A)
2559
+
nrx_path = RF_PATH_A;
2560
+
else if (hal->antenna_rx == RF_B)
2561
+
nrx_path = RF_PATH_B;
2562
+
2563
+
if (nrx_path != RF_PATH_AB)
2564
+
rx_nss = 1;
2565
+
2566
+
rtw8922d_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, true);
2567
+
if (rtwdev->dbcc_en)
2568
+
rtw8922d_hal_reset(rtwdev, RTW89_PHY_1, RTW89_MAC_1, band,
2569
+
&tx_en1, true);
2570
+
2571
+
rtw8922d_ctrl_trx_path(rtwdev, ntx_path, 2, nrx_path, rx_nss);
2572
+
2573
+
rtw8922d_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, false);
2574
+
if (rtwdev->dbcc_en)
2575
+
rtw8922d_hal_reset(rtwdev, RTW89_PHY_1, RTW89_MAC_1, band,
2576
+
&tx_en1, false);
2577
+
}
2578
+
2579
+
static u8 rtw8922d_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2580
+
{
2581
+
u8 val;
2582
+
2583
+
rtw89_phy_write32_mask(rtwdev, R_TC_EN_BE4, B_TC_EN_BE4, 0x1);
2584
+
rtw89_phy_write32_mask(rtwdev, R_TC_EN_BE4, B_TC_TRIG_BE4, 0x0);
2585
+
rtw89_phy_write32_mask(rtwdev, R_TC_EN_BE4, B_TC_TRIG_BE4, 0x1);
2586
+
2587
+
fsleep(100);
2588
+
2589
+
val = rtw89_phy_read32_mask(rtwdev, R_TC_VAL_BE4, B_TC_VAL_BE4);
2590
+
2591
+
return val;
2592
+
}
2593
+
2594
+
static u32 rtw8922d_chan_to_rf18_val(struct rtw89_dev *rtwdev,
2595
+
const struct rtw89_chan *chan)
2596
+
{
2597
+
u32 val = u32_encode_bits(chan->channel, RR_CFGCH_CH);
2598
+
2599
+
switch (chan->band_type) {
2600
+
case RTW89_BAND_2G:
2601
+
default:
2602
+
break;
2603
+
case RTW89_BAND_5G:
2604
+
val |= u32_encode_bits(CFGCH_BAND1_5G, RR_CFGCH_BAND1) |
2605
+
u32_encode_bits(CFGCH_BAND0_5G, RR_CFGCH_BAND0);
2606
+
break;
2607
+
case RTW89_BAND_6G:
2608
+
val |= u32_encode_bits(CFGCH_BAND1_6G, RR_CFGCH_BAND1) |
2609
+
u32_encode_bits(CFGCH_BAND0_6G, RR_CFGCH_BAND0);
2610
+
break;
2611
+
}
2612
+
2613
+
switch (chan->band_width) {
2614
+
case RTW89_CHANNEL_WIDTH_5:
2615
+
case RTW89_CHANNEL_WIDTH_10:
2616
+
case RTW89_CHANNEL_WIDTH_20:
2617
+
default:
2618
+
break;
2619
+
case RTW89_CHANNEL_WIDTH_40:
2620
+
val |= u32_encode_bits(CFGCH_BW_V2_40M, RR_CFGCH_BW_V2);
2621
+
break;
2622
+
case RTW89_CHANNEL_WIDTH_80:
2623
+
val |= u32_encode_bits(CFGCH_BW_V2_80M, RR_CFGCH_BW_V2);
2624
+
break;
2625
+
case RTW89_CHANNEL_WIDTH_160:
2626
+
val |= u32_encode_bits(CFGCH_BW_V2_160M, RR_CFGCH_BW_V2);
2627
+
break;
2628
+
case RTW89_CHANNEL_WIDTH_320:
2629
+
val |= u32_encode_bits(CFGCH_BW_V2_320M, RR_CFGCH_BW_V2);
2630
+
break;
2631
+
}
2632
+
2633
+
return val;
2634
+
}
2635
+
2636
+
static void rtw8922d_btc_set_rfe(struct rtw89_dev *rtwdev)
2637
+
{
2638
+
}
2639
+
2640
+
static void rtw8922d_btc_init_cfg(struct rtw89_dev *rtwdev)
2641
+
{
2642
+
/* offload to firmware */
2643
+
}
2644
+
2645
+
static void
2646
+
rtw8922d_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2647
+
{
2648
+
u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0));
2649
+
u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16));
2650
+
2651
+
switch (ctrl_all_time) {
2652
+
case 0xffff:
2653
+
rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2654
+
B_BE_FORCE_PWR_BY_RATE_EN, 0x0);
2655
+
rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2656
+
B_BE_FORCE_PWR_BY_RATE_VAL, 0x0);
2657
+
break;
2658
+
default:
2659
+
rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2660
+
B_BE_FORCE_PWR_BY_RATE_VAL, ctrl_all_time);
2661
+
rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2662
+
B_BE_FORCE_PWR_BY_RATE_EN, 0x1);
2663
+
break;
2664
+
}
2665
+
2666
+
switch (ctrl_gnt_bt) {
2667
+
case 0xffff:
2668
+
rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
2669
+
B_BE_PWR_BT_EN, 0x0);
2670
+
rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
2671
+
B_BE_PWR_BT_VAL, 0x0);
2672
+
break;
2673
+
default:
2674
+
rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
2675
+
B_BE_PWR_BT_VAL, ctrl_gnt_bt);
2676
+
rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
2677
+
B_BE_PWR_BT_EN, 0x1);
2678
+
break;
2679
+
}
2680
+
}
2681
+
2682
+
static
2683
+
s8 rtw8922d_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2684
+
{
2685
+
return clamp_t(s8, val, -100, 0) + 100;
2686
+
}
2687
+
2688
+
static const struct rtw89_btc_rf_trx_para_v9 rtw89_btc_8922d_rf_ul_v9[] = {
2689
+
/*
2690
+
* 0 -> original
2691
+
* 1 -> for BT-connected ACI issue && BTG co-rx
2692
+
* 2 ~ 4 ->reserved for shared-antenna
2693
+
* 5 ~ 8 ->for non-shared-antenna free-run
2694
+
*/
2695
+
{{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2696
+
{{15, 15}, {2, 2}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2697
+
{{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2698
+
{{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2699
+
{{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2700
+
{{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2701
+
{{ 6, 6}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2702
+
{{13, 13}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2703
+
{{13, 13}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2704
+
};
2705
+
2706
+
static const struct rtw89_btc_rf_trx_para_v9 rtw89_btc_8922d_rf_dl_v9[] = {
2707
+
/*
2708
+
* 0 -> original
2709
+
* 1 -> for BT-connected ACI issue && BTG co-rx
2710
+
* 2 ~ 4 ->reserved for shared-antenna
2711
+
* 5 ~ 8 ->for non-shared-antenna free-run
2712
+
*/
2713
+
{{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2714
+
{{15, 15}, {2, 2}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2715
+
{{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2716
+
{{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2717
+
{{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2718
+
{{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2719
+
{{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2720
+
{{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2721
+
{{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
2722
+
};
2723
+
2724
+
static const u8 rtw89_btc_8922d_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
2725
+
static const u8 rtw89_btc_8922d_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
2726
+
2727
+
static const struct rtw89_btc_fbtc_mreg rtw89_btc_8922d_mon_reg[] = {
2728
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe300),
2729
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe330),
2730
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe334),
2731
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe338),
2732
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe344),
2733
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe348),
2734
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe34c),
2735
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe350),
2736
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe354),
2737
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe35c),
2738
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe370),
2739
+
RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe380),
2740
+
};
2741
+
2742
+
static
2743
+
void rtw8922d_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2744
+
{
2745
+
/* Feature move to firmware */
2746
+
}
2747
+
2748
+
static
2749
+
void rtw8922d_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2750
+
{
2751
+
/* Feature move to firmware */
2752
+
}
2753
+
2754
+
static void rtw8922d_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2755
+
{
2756
+
/* Feature move to firmware */
2757
+
}
2758
+
2759
+
static void rtw8922d_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2760
+
struct rtw89_rx_phy_ppdu *phy_ppdu,
2761
+
struct ieee80211_rx_status *status)
2762
+
{
2763
+
u8 chan_idx = phy_ppdu->chan_idx;
2764
+
enum nl80211_band band;
2765
+
u8 ch;
2766
+
2767
+
if (chan_idx == 0)
2768
+
return;
2769
+
2770
+
rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band);
2771
+
status->freq = ieee80211_channel_to_frequency(ch, band);
2772
+
status->band = band;
2773
+
}
2774
+
2775
+
static void rtw8922d_query_ppdu(struct rtw89_dev *rtwdev,
2776
+
struct rtw89_rx_phy_ppdu *phy_ppdu,
2777
+
struct ieee80211_rx_status *status)
2778
+
{
2779
+
u8 path;
2780
+
u8 *rx_power = phy_ppdu->rssi;
2781
+
2782
+
if (!status->signal)
2783
+
status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A],
2784
+
rx_power[RF_PATH_B]));
2785
+
2786
+
for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2787
+
status->chains |= BIT(path);
2788
+
status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2789
+
}
2790
+
if (phy_ppdu->valid)
2791
+
rtw8922d_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2792
+
}
2793
+
2794
+
static void rtw8922d_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
2795
+
struct rtw89_rx_phy_ppdu *phy_ppdu)
2796
+
{
2797
+
/* Mapping to BW: 5, 10, 20, 40, 80, 160, 80_80 */
2798
+
static const u8 bw_compensate[] = {0, 0, 0, 6, 12, 18, 0};
2799
+
u8 *rssi = phy_ppdu->rssi;
2800
+
u8 compensate = 0;
2801
+
u8 i;
2802
+
2803
+
if (phy_ppdu->bw_idx < ARRAY_SIZE(bw_compensate))
2804
+
compensate = bw_compensate[phy_ppdu->bw_idx];
2805
+
2806
+
for (i = 0; i < RF_PATH_NUM_8922D; i++) {
2807
+
if (!(phy_ppdu->rx_path_en & BIT(i))) {
2808
+
rssi[i] = 0;
2809
+
phy_ppdu->rpl_path[i] = 0;
2810
+
phy_ppdu->rpl_fd[i] = 0;
2811
+
}
2812
+
2813
+
if (phy_ppdu->ie != RTW89_CCK_PKT && rssi[i])
2814
+
rssi[i] += compensate;
2815
+
2816
+
phy_ppdu->rpl_path[i] = rssi[i];
2817
+
}
2818
+
}
2819
+
2820
+
static void rtw8922d_phy_rpt_to_rssi(struct rtw89_dev *rtwdev,
2821
+
struct rtw89_rx_desc_info *desc_info,
2822
+
struct ieee80211_rx_status *rx_status)
2823
+
{
2824
+
if (desc_info->rssi <= 0x1 || (desc_info->rssi >> 2) > MAX_RSSI)
2825
+
return;
2826
+
2827
+
rx_status->signal = (desc_info->rssi >> 2) - MAX_RSSI;
2828
+
}
2829
+
2830
+
static int rtw8922d_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2831
+
{
2832
+
return 0;
2833
+
}
2834
+
2835
+
static int rtw8922d_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2836
+
{
2837
+
return 0;
2838
+
}
2839
+
2840
+
static const struct rtw89_chanctx_listener rtw8922d_chanctx_listener = {
2841
+
.callbacks[RTW89_CHANCTX_CALLBACK_TAS] = rtw89_tas_chanctx_cb,
2842
+
};
2843
+
2844
+
#ifdef CONFIG_PM
2845
+
static const struct wiphy_wowlan_support rtw_wowlan_stub_8922d = {
2846
+
.flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT |
2847
+
WIPHY_WOWLAN_NET_DETECT,
2848
+
.n_patterns = RTW89_MAX_PATTERN_NUM,
2849
+
.pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2850
+
.pattern_min_len = 1,
2851
+
.max_nd_match_sets = RTW89_SCANOFLD_MAX_SSID,
2852
+
};
2853
+
#endif
2854
+
2855
+
static const struct rtw89_chip_ops rtw8922d_chip_ops = {
2856
+
.enable_bb_rf = rtw8922d_mac_enable_bb_rf,
2857
+
.disable_bb_rf = rtw8922d_mac_disable_bb_rf,
2858
+
.bb_preinit = rtw8922d_bb_preinit,
2859
+
.bb_postinit = rtw8922d_bb_postinit,
2860
+
.bb_reset = rtw8922d_bb_reset,
2861
+
.bb_sethw = rtw8922d_bb_sethw,
2862
+
.read_rf = rtw89_phy_read_rf_v3,
2863
+
.write_rf = rtw89_phy_write_rf_v3,
2864
+
.set_channel = rtw8922d_set_channel,
2865
+
.set_channel_help = rtw8922d_set_channel_help,
2866
+
.read_efuse = rtw8922d_read_efuse,
2867
+
.read_phycap = rtw8922d_read_phycap,
2868
+
.fem_setup = NULL,
2869
+
.rfe_gpio = NULL,
2870
+
.rfk_hw_init = rtw8922d_rfk_hw_init,
2871
+
.rfk_init = rtw8922d_rfk_init,
2872
+
.rfk_init_late = rtw8922d_rfk_init_late,
2873
+
.rfk_channel = rtw8922d_rfk_channel,
2874
+
.rfk_band_changed = rtw8922d_rfk_band_changed,
2875
+
.rfk_scan = rtw8922d_rfk_scan,
2876
+
.rfk_track = rtw8922d_rfk_track,
2877
+
.power_trim = rtw8922d_power_trim,
2878
+
.set_txpwr = rtw8922d_set_txpwr,
2879
+
.set_txpwr_ctrl = rtw8922d_set_txpwr_ctrl,
2880
+
.init_txpwr_unit = NULL,
2881
+
.get_thermal = rtw8922d_get_thermal,
2882
+
.chan_to_rf18_val = rtw8922d_chan_to_rf18_val,
2883
+
.ctrl_btg_bt_rx = rtw8922d_set_gbt_bt_rx_sel,
2884
+
.query_ppdu = rtw8922d_query_ppdu,
2885
+
.convert_rpl_to_rssi = rtw8922d_convert_rpl_to_rssi,
2886
+
.phy_rpt_to_rssi = rtw8922d_phy_rpt_to_rssi,
2887
+
.ctrl_nbtg_bt_tx = rtw8922d_ctrl_nbtg_bt_tx,
2888
+
.cfg_txrx_path = rtw8922d_bb_cfg_txrx_path,
2889
+
.set_txpwr_ul_tb_offset = NULL,
2890
+
.digital_pwr_comp = rtw8922d_digital_pwr_comp,
2891
+
.calc_rx_gain_normal = rtw8922d_calc_rx_gain_normal,
2892
+
.pwr_on_func = rtw8922d_pwr_on_func,
2893
+
.pwr_off_func = rtw8922d_pwr_off_func,
2894
+
.query_rxdesc = rtw89_core_query_rxdesc_v3,
2895
+
.fill_txdesc = rtw89_core_fill_txdesc_v3,
2896
+
.fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v2,
2897
+
.get_ch_dma = {rtw89_core_get_ch_dma_v1,
2898
+
NULL,
2899
+
NULL,},
2900
+
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v2,
2901
+
.mac_cfg_gnt = rtw89_mac_cfg_gnt_v3,
2902
+
.stop_sch_tx = rtw89_mac_stop_sch_tx_v2,
2903
+
.resume_sch_tx = rtw89_mac_resume_sch_tx_v2,
2904
+
.h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v3,
2905
+
.h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl_be,
2906
+
.h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl_be,
2907
+
.h2c_ampdu_cmac_tbl = rtw89_fw_h2c_ampdu_cmac_tbl_be,
2908
+
.h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl_be,
2909
+
.h2c_punctured_cmac_tbl = rtw89_fw_h2c_punctured_cmac_tbl_be,
2910
+
.h2c_default_dmac_tbl = rtw89_fw_h2c_default_dmac_tbl_v3,
2911
+
.h2c_update_beacon = rtw89_fw_h2c_update_beacon_be,
2912
+
.h2c_ba_cam = rtw89_fw_h2c_ba_cam_v1,
2913
+
.h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update_v1,
2914
+
2915
+
.btc_set_rfe = rtw8922d_btc_set_rfe,
2916
+
.btc_init_cfg = rtw8922d_btc_init_cfg,
2917
+
.btc_set_wl_pri = NULL,
2918
+
.btc_set_wl_txpwr_ctrl = rtw8922d_btc_set_wl_txpwr_ctrl,
2919
+
.btc_get_bt_rssi = rtw8922d_btc_get_bt_rssi,
2920
+
.btc_update_bt_cnt = rtw8922d_btc_update_bt_cnt,
2921
+
.btc_wl_s1_standby = rtw8922d_btc_wl_s1_standby,
2922
+
.btc_set_wl_rx_gain = rtw8922d_btc_set_wl_rx_gain,
2923
+
.btc_set_policy = rtw89_btc_set_policy_v1,
2924
+
};
2925
+
2926
+
const struct rtw89_chip_info rtw8922d_chip_info = {
2927
+
.chip_id = RTL8922D,
2928
+
.chip_gen = RTW89_CHIP_BE,
2929
+
.ops = &rtw8922d_chip_ops,
2930
+
.mac_def = &rtw89_mac_gen_be,
2931
+
.phy_def = &rtw89_phy_gen_be_v1,
2932
+
.fw_def = {
2933
+
.fw_basename = RTW8922D_FW_BASENAME,
2934
+
.fw_format_max = RTW8922D_FW_FORMAT_MAX,
2935
+
.fw_b_aid = RTL8922D_AID7102,
2936
+
},
2937
+
.try_ce_fw = false,
2938
+
.bbmcu_nr = 0,
2939
+
.needed_fw_elms = RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_V1,
2940
+
.fw_blacklist = &rtw89_fw_blacklist_default,
2941
+
.fifo_size = 393216,
2942
+
.small_fifo_size = false,
2943
+
.dle_scc_rsvd_size = 0,
2944
+
.max_amsdu_limit = 11000,
2945
+
.max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991,
2946
+
.max_eht_mpdu_cap = IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
2947
+
.max_tx_agg_num = 128,
2948
+
.max_rx_agg_num = 256,
2949
+
.dis_2g_40m_ul_ofdma = false,
2950
+
.rsvd_ple_ofst = 0x5f800,
2951
+
.hfc_param_ini = {rtw8922d_hfc_param_ini_pcie, NULL, NULL},
2952
+
.dle_mem = {rtw8922d_dle_mem_pcie, NULL, NULL, NULL},
2953
+
.wde_qempty_acq_grpnum = 8,
2954
+
.wde_qempty_mgq_grpsel = 8,
2955
+
.rf_base_addr = {0x3e000, 0x3f000},
2956
+
.thermal_th = {0xac, 0xad},
2957
+
.pwr_on_seq = NULL,
2958
+
.pwr_off_seq = NULL,
2959
+
.bb_table = NULL,
2960
+
.bb_gain_table = NULL,
2961
+
.rf_table = {},
2962
+
.nctl_table = NULL,
2963
+
.nctl_post_table = &rtw8922d_nctl_post_defs_tbl,
2964
+
.dflt_parms = NULL, /* load parm from fw */
2965
+
.rfe_parms_conf = NULL, /* load parm from fw */
2966
+
.chanctx_listener = &rtw8922d_chanctx_listener,
2967
+
.txpwr_factor_bb = 3,
2968
+
.txpwr_factor_rf = 2,
2969
+
.txpwr_factor_mac = 1,
2970
+
.dig_table = NULL,
2971
+
.dig_regs = &rtw8922d_dig_regs,
2972
+
.tssi_dbw_table = NULL,
2973
+
.support_macid_num = 64,
2974
+
.support_link_num = 2,
2975
+
.support_chanctx_num = 2,
2976
+
.support_rnr = true,
2977
+
.support_bands = BIT(NL80211_BAND_2GHZ) |
2978
+
BIT(NL80211_BAND_5GHZ) |
2979
+
BIT(NL80211_BAND_6GHZ),
2980
+
.support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
2981
+
BIT(NL80211_CHAN_WIDTH_40) |
2982
+
BIT(NL80211_CHAN_WIDTH_80) |
2983
+
BIT(NL80211_CHAN_WIDTH_160),
2984
+
.support_unii4 = true,
2985
+
.support_ant_gain = false,
2986
+
.support_tas = false,
2987
+
.support_sar_by_ant = true,
2988
+
.support_noise = false,
2989
+
.ul_tb_waveform_ctrl = false,
2990
+
.ul_tb_pwr_diff = false,
2991
+
.rx_freq_frome_ie = false,
2992
+
.hw_sec_hdr = true,
2993
+
.hw_mgmt_tx_encrypt = true,
2994
+
.hw_tkip_crypto = true,
2995
+
.hw_mlo_bmc_crypto = true,
2996
+
.rf_path_num = 2,
2997
+
.tx_nss = 2,
2998
+
.rx_nss = 2,
2999
+
.acam_num = 128,
3000
+
.bcam_num = 16,
3001
+
.scam_num = 32,
3002
+
.bacam_num = 24,
3003
+
.bacam_dynamic_num = 8,
3004
+
.bacam_ver = RTW89_BACAM_V1,
3005
+
.addrcam_ver = 1,
3006
+
.ppdu_max_usr = 16,
3007
+
.sec_ctrl_efuse_size = 4,
3008
+
.physical_efuse_size = 0x1300,
3009
+
.logical_efuse_size = 0x70000,
3010
+
.limit_efuse_size = 0x40000,
3011
+
.dav_phy_efuse_size = 0,
3012
+
.dav_log_efuse_size = 0,
3013
+
.efuse_blocks = rtw8922d_efuse_blocks,
3014
+
.phycap_addr = 0x1700,
3015
+
.phycap_size = 0x60,
3016
+
.para_ver = 0x3ff,
3017
+
.wlcx_desired = 0x09150000,
3018
+
.scbd = 0x1,
3019
+
.mailbox = 0x1,
3020
+
3021
+
.afh_guard_ch = 6,
3022
+
.wl_rssi_thres = rtw89_btc_8922d_wl_rssi_thres,
3023
+
.bt_rssi_thres = rtw89_btc_8922d_bt_rssi_thres,
3024
+
.rssi_tol = 2,
3025
+
.mon_reg_num = ARRAY_SIZE(rtw89_btc_8922d_mon_reg),
3026
+
.mon_reg = rtw89_btc_8922d_mon_reg,
3027
+
.rf_para_ulink_v9 = rtw89_btc_8922d_rf_ul_v9,
3028
+
.rf_para_dlink_v9 = rtw89_btc_8922d_rf_dl_v9,
3029
+
.rf_para_ulink_num_v9 = ARRAY_SIZE(rtw89_btc_8922d_rf_ul_v9),
3030
+
.rf_para_dlink_num_v9 = ARRAY_SIZE(rtw89_btc_8922d_rf_dl_v9),
3031
+
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
3032
+
BIT(RTW89_PS_MODE_CLK_GATED) |
3033
+
BIT(RTW89_PS_MODE_PWR_GATED),
3034
+
.low_power_hci_modes = 0,
3035
+
.h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_G7,
3036
+
.hci_func_en_addr = R_BE_HCI_FUNC_EN,
3037
+
.h2c_desc_size = sizeof(struct rtw89_rxdesc_short_v3),
3038
+
.txwd_body_size = sizeof(struct rtw89_txwd_body_v2),
3039
+
.txwd_info_size = sizeof(struct rtw89_txwd_info_v2),
3040
+
.h2c_ctrl_reg = R_BE_H2CREG_CTRL,
3041
+
.h2c_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
3042
+
.h2c_regs = rtw8922d_h2c_regs,
3043
+
.c2h_ctrl_reg = R_BE_C2HREG_CTRL,
3044
+
.c2h_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
3045
+
.c2h_regs = rtw8922d_c2h_regs,
3046
+
.page_regs = &rtw8922d_page_regs,
3047
+
.wow_reason_reg = rtw8922d_wow_wakeup_regs,
3048
+
.cfo_src_fd = true,
3049
+
.cfo_hw_comp = true,
3050
+
.dcfo_comp = NULL,
3051
+
.dcfo_comp_sft = 0,
3052
+
.nhm_report = NULL,
3053
+
.nhm_th = NULL,
3054
+
.imr_info = NULL,
3055
+
.imr_dmac_table = &rtw8922d_imr_dmac_table,
3056
+
.imr_cmac_table = &rtw8922d_imr_cmac_table,
3057
+
.rrsr_cfgs = &rtw8922d_rrsr_cfgs,
3058
+
.bss_clr_vld = {R_BSS_CLR_VLD_BE4, B_BSS_CLR_VLD_BE4},
3059
+
.bss_clr_map_reg = R_BSS_CLR_MAP_BE4,
3060
+
.rfkill_init = &rtw8922d_rfkill_regs,
3061
+
.rfkill_get = {R_BE_GPIO_EXT_CTRL, B_BE_GPIO_IN_9},
3062
+
.btc_sb = {{{R_BE_SCOREBOARD_0, R_BE_SCOREBOARD_0_BT_DATA},
3063
+
{R_BE_SCOREBOARD_1, R_BE_SCOREBOARD_1_BT_DATA}}},
3064
+
.dma_ch_mask = BIT(RTW89_DMA_ACH1) | BIT(RTW89_DMA_ACH3) |
3065
+
BIT(RTW89_DMA_ACH5) | BIT(RTW89_DMA_ACH7) |
3066
+
BIT(RTW89_DMA_B0HI) | BIT(RTW89_DMA_B1HI),
3067
+
.edcca_regs = &rtw8922d_edcca_regs,
3068
+
#ifdef CONFIG_PM
3069
+
.wowlan_stub = &rtw_wowlan_stub_8922d,
3070
+
#endif
3071
+
.xtal_info = NULL,
3072
+
.default_quirks = BIT(RTW89_QUIRK_THERMAL_PROT_120C),
3073
+
};
3074
+
EXPORT_SYMBOL(rtw8922d_chip_info);
3075
+
3076
+
static const struct rtw89_fw_def rtw8922de_vs_fw_def = {
3077
+
.fw_basename = RTW8922DS_FW_BASENAME,
3078
+
.fw_format_max = RTW8922DS_FW_FORMAT_MAX,
3079
+
.fw_b_aid = RTL8922D_AID7060,
3080
+
};
3081
+
3082
+
const struct rtw89_chip_variant rtw8922de_vs_variant = {
3083
+
.no_mcs_12_13 = true,
3084
+
.fw_min_ver_code = RTW89_FW_VER_CODE(0, 0, 0, 0),
3085
+
.fw_def_override = &rtw8922de_vs_fw_def,
3086
+
};
3087
+
EXPORT_SYMBOL(rtw8922de_vs_variant);
3088
+
3089
+
MODULE_FIRMWARE(RTW8922D_MODULE_FIRMWARE);
3090
+
MODULE_FIRMWARE(RTW8922DS_MODULE_FIRMWARE);
3091
+
MODULE_AUTHOR("Realtek Corporation");
3092
+
MODULE_DESCRIPTION("Realtek 802.11be wireless 8922D driver");
3093
+
MODULE_LICENSE("Dual BSD/GPL");
+83
drivers/net/wireless/realtek/rtw89/rtw8922d.h
+83
drivers/net/wireless/realtek/rtw89/rtw8922d.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2
+
/* Copyright(c) 2026 Realtek Corporation
3
+
*/
4
+
5
+
#ifndef __RTW89_8922D_H__
6
+
#define __RTW89_8922D_H__
7
+
8
+
#include "core.h"
9
+
10
+
#define RF_PATH_NUM_8922D 2
11
+
#define BB_PATH_NUM_8922D 2
12
+
13
+
struct rtw8922d_tssi_offset {
14
+
u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
15
+
u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
16
+
u8 rsvd[7];
17
+
u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
18
+
u8 bw_diff_5g[10];
19
+
} __packed;
20
+
21
+
struct rtw8922d_tssi_offset_6g {
22
+
u8 bw40_1s_tssi_6g[TSSI_MCS_6G_CH_GROUP_NUM];
23
+
u8 rsvd[0xa];
24
+
} __packed;
25
+
26
+
struct rtw8922d_rx_gain {
27
+
u8 _2g_ofdm;
28
+
u8 _2g_cck;
29
+
u8 _5g_low;
30
+
u8 _5g_mid;
31
+
u8 _5g_high;
32
+
} __packed;
33
+
34
+
struct rtw8922d_rx_gain_6g {
35
+
u8 _6g_l0;
36
+
u8 _6g_l1;
37
+
u8 _6g_m0;
38
+
u8 _6g_m1;
39
+
u8 _6g_h0;
40
+
u8 _6g_h1;
41
+
u8 _6g_uh0;
42
+
u8 _6g_uh1;
43
+
} __packed;
44
+
45
+
struct rtw8922d_efuse {
46
+
u8 country_code[2];
47
+
u8 rsvd[0xe];
48
+
struct rtw8922d_tssi_offset path_a_tssi;
49
+
struct rtw8922d_tssi_offset path_b_tssi;
50
+
u8 rsvd1[0x54];
51
+
u8 channel_plan;
52
+
u8 xtal_k;
53
+
u8 rsvd2[0x7];
54
+
u8 board_info;
55
+
u8 rsvd3[0x8];
56
+
u8 rfe_type;
57
+
u8 rsvd4[2];
58
+
u8 bt_setting_2;
59
+
u8 bt_setting_3;
60
+
u8 rsvd4_2;
61
+
u8 path_a_therm;
62
+
u8 path_b_therm;
63
+
u8 rsvd5[0x2];
64
+
struct rtw8922d_rx_gain rx_gain_a;
65
+
struct rtw8922d_rx_gain rx_gain_b;
66
+
u8 rsvd6[0x18];
67
+
struct rtw8922d_rx_gain rx_gain_a_2;
68
+
struct rtw8922d_rx_gain rx_gain_b_2;
69
+
struct rtw8922d_tssi_offset_6g path_a_tssi_6g;
70
+
struct rtw8922d_tssi_offset_6g path_b_tssi_6g;
71
+
struct rtw8922d_tssi_offset_6g path_c_tssi_6g;
72
+
struct rtw8922d_tssi_offset_6g path_d_tssi_6g;
73
+
struct rtw8922d_rx_gain_6g rx_gain_6g_a;
74
+
struct rtw8922d_rx_gain_6g rx_gain_6g_b;
75
+
u8 rsvd7[0x5a];
76
+
struct rtw8922d_rx_gain_6g rx_gain_6g_a_2;
77
+
struct rtw8922d_rx_gain_6g rx_gain_6g_b_2;
78
+
} __packed;
79
+
80
+
extern const struct rtw89_chip_info rtw8922d_chip_info;
81
+
extern const struct rtw89_chip_variant rtw8922de_vs_variant;
82
+
83
+
#endif
+372
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.c
+372
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.c
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/* Copyright(c) 2026 Realtek Corporation
3
+
*/
4
+
5
+
#include "chan.h"
6
+
#include "debug.h"
7
+
#include "phy.h"
8
+
#include "reg.h"
9
+
#include "rtw8922d.h"
10
+
#include "rtw8922d_rfk.h"
11
+
12
+
static const struct rtw89_reg5_def rtw8922d_nctl_post_defs[] = {
13
+
RTW89_DECL_RFK_WM(0x20c7c, 0x00e00000, 0x1),
14
+
};
15
+
16
+
RTW89_DECLARE_RFK_TBL(rtw8922d_nctl_post_defs);
17
+
18
+
static void rtw8922d_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
19
+
enum rtw89_rf_path path, u8 phy_idx)
20
+
{
21
+
static const u32 tssi_trk_man[2] = {R_TSSI_EN_P0_BE4,
22
+
R_TSSI_EN_P0_BE4 + 0x100};
23
+
24
+
if (en)
25
+
rtw89_phy_write32_idx(rtwdev, tssi_trk_man[path],
26
+
B_TSSI_CONT_EN, 0, phy_idx);
27
+
else
28
+
rtw89_phy_write32_idx(rtwdev, tssi_trk_man[path],
29
+
B_TSSI_CONT_EN, 1, phy_idx);
30
+
}
31
+
32
+
void rtw8922d_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx)
33
+
{
34
+
if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
35
+
if (phy_idx == RTW89_PHY_0)
36
+
rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_A, phy_idx);
37
+
else
38
+
rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_B, phy_idx);
39
+
} else {
40
+
rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_A, phy_idx);
41
+
rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_B, phy_idx);
42
+
}
43
+
}
44
+
45
+
static
46
+
void rtw8922d_ctl_band_ch_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
47
+
const struct rtw89_chan *chan)
48
+
{
49
+
u8 synpath;
50
+
u32 rf18;
51
+
52
+
synpath = rtw89_phy_get_syn_sel(rtwdev, phy);
53
+
rf18 = rtw89_chip_chan_to_rf18_val(rtwdev, chan);
54
+
55
+
rtw89_write_rf(rtwdev, synpath, RR_RSV1, RFREG_MASK, 0x0);
56
+
rtw89_write_rf(rtwdev, synpath, RR_MOD, RFREG_MASK, 0x30000);
57
+
rtw89_write_rf(rtwdev, synpath, RR_CFGCH, RFREG_MASK, rf18);
58
+
fsleep(400);
59
+
rtw89_write_rf(rtwdev, synpath, RR_RSV1, RFREG_MASK, 0x1);
60
+
rtw89_write_rf(rtwdev, synpath, RR_CFGCH_V1, RFREG_MASK, rf18);
61
+
}
62
+
63
+
void rtw8922d_set_channel_rf(struct rtw89_dev *rtwdev,
64
+
const struct rtw89_chan *chan,
65
+
enum rtw89_phy_idx phy_idx)
66
+
{
67
+
rtw8922d_ctl_band_ch_bw(rtwdev, phy_idx, chan);
68
+
}
69
+
70
+
enum _rf_syn_pow {
71
+
RF_SYN_ON_OFF,
72
+
RF_SYN_OFF_ON,
73
+
RF_SYN_ALLON,
74
+
RF_SYN_ALLOFF,
75
+
};
76
+
77
+
static void rtw8922d_set_syn01(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn)
78
+
{
79
+
rtw89_debug(rtwdev, RTW89_DBG_RFK, "SYN config=%d\n", syn);
80
+
81
+
if (syn == RF_SYN_ALLON) {
82
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, BIT(1), 0x0);
83
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, BIT(1), 0x0);
84
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x0);
85
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x0);
86
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf);
87
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf);
88
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x1);
89
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x1);
90
+
} else if (syn == RF_SYN_ON_OFF) {
91
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, BIT(1), 0x0);
92
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x0);
93
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf);
94
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0);
95
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x1);
96
+
} else if (syn == RF_SYN_OFF_ON) {
97
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, BIT(1), 0x0);
98
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x0);
99
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0);
100
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf);
101
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x1);
102
+
} else if (syn == RF_SYN_ALLOFF) {
103
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0);
104
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0);
105
+
}
106
+
}
107
+
108
+
static void rtw8922d_chlk_ktbl_sel(struct rtw89_dev *rtwdev, u8 kpath, u8 idx)
109
+
{
110
+
bool mlo_linking = false;
111
+
112
+
if (idx > 2) {
113
+
rtw89_warn(rtwdev, "[DBCC][ERROR]indx is out of limit!! index(%d)", idx);
114
+
return;
115
+
}
116
+
117
+
if (mlo_linking) {
118
+
if (kpath & RF_A) {
119
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_SW_SEL, 0x0);
120
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_SW_SEL, 0x0);
121
+
}
122
+
123
+
if (kpath & RF_B) {
124
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_SW_SEL, 0x0);
125
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_SW_SEL, 0x0);
126
+
}
127
+
128
+
return;
129
+
}
130
+
131
+
if (kpath & RF_A) {
132
+
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_RST, 0x1);
133
+
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_IDX0, idx);
134
+
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_IDX1, idx);
135
+
136
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_TXG_SEL, 0x4 | idx);
137
+
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_TXG_SEL, 0x4 | idx);
138
+
139
+
rtw89_phy_write32_mask(rtwdev, R_KTBL1A_BE4, B_KTBL1_TBL0, idx & BIT(0));
140
+
rtw89_phy_write32_mask(rtwdev, R_KTBL1A_BE4, B_KTBL1_TBL1, (idx & BIT(1)) >> 1);
141
+
}
142
+
143
+
if (kpath & RF_B) {
144
+
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_RST, 0x1);
145
+
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_IDX0, idx);
146
+
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_IDX1, idx);
147
+
148
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_TXG_SEL, 0x4 | idx);
149
+
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_TXG_SEL, 0x4 | idx);
150
+
151
+
rtw89_phy_write32_mask(rtwdev, R_KTBL1B_BE4, B_KTBL1_TBL0, idx & BIT(0));
152
+
rtw89_phy_write32_mask(rtwdev, R_KTBL1B_BE4, B_KTBL1_TBL1, (idx & BIT(1)) >> 1);
153
+
}
154
+
}
155
+
156
+
static u8 rtw8922d_chlk_reload_sel_tbl(struct rtw89_dev *rtwdev,
157
+
const struct rtw89_chan *chan, u8 path)
158
+
{
159
+
struct rtw89_rfk_mcc_info_data *rfk_mcc = rtwdev->rfk_mcc.data;
160
+
struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V1] = {};
161
+
u8 tbl_sel;
162
+
163
+
for (tbl_sel = 0; tbl_sel < ARRAY_SIZE(desc); tbl_sel++) {
164
+
struct rtw89_rfk_chan_desc *p = &desc[tbl_sel];
165
+
166
+
p->ch = rfk_mcc->ch[tbl_sel];
167
+
168
+
p->has_band = true;
169
+
p->band = rfk_mcc->band[tbl_sel];
170
+
171
+
p->has_bw = true;
172
+
p->bw = rfk_mcc->bw[tbl_sel];
173
+
}
174
+
175
+
tbl_sel = rtw89_rfk_chan_lookup(rtwdev, desc, ARRAY_SIZE(desc), chan);
176
+
177
+
rfk_mcc->ch[tbl_sel] = chan->channel;
178
+
rfk_mcc->band[tbl_sel] = chan->band_type;
179
+
rfk_mcc->bw[tbl_sel] = chan->band_width;
180
+
rfk_mcc->rf18[tbl_sel] = rtw89_chip_chan_to_rf18_val(rtwdev, chan);
181
+
182
+
/* shared table array, but tbl_sel can be independent by path */
183
+
rfk_mcc[path].table_idx = tbl_sel;
184
+
185
+
return tbl_sel;
186
+
}
187
+
188
+
static void rtw8922d_chlk_reload(struct rtw89_dev *rtwdev)
189
+
{
190
+
const struct rtw89_chan *chan0, *chan1;
191
+
u8 s0_tbl, s1_tbl;
192
+
193
+
switch (rtwdev->mlo_dbcc_mode) {
194
+
default:
195
+
case MLO_2_PLUS_0_1RF:
196
+
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
197
+
chan1 = chan0;
198
+
break;
199
+
case MLO_0_PLUS_2_1RF:
200
+
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
201
+
chan0 = chan1;
202
+
break;
203
+
case MLO_1_PLUS_1_1RF:
204
+
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
205
+
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
206
+
break;
207
+
}
208
+
209
+
s0_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, chan0, 0);
210
+
s1_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, chan1, 1);
211
+
212
+
rtw8922d_chlk_ktbl_sel(rtwdev, RF_A, s0_tbl);
213
+
rtw8922d_chlk_ktbl_sel(rtwdev, RF_B, s1_tbl);
214
+
}
215
+
216
+
static enum _rf_syn_pow rtw8922d_get_syn_pow(struct rtw89_dev *rtwdev)
217
+
{
218
+
switch (rtwdev->mlo_dbcc_mode) {
219
+
case MLO_0_PLUS_2_1RF:
220
+
return RF_SYN_OFF_ON;
221
+
case MLO_0_PLUS_2_2RF:
222
+
case MLO_1_PLUS_1_2RF:
223
+
case MLO_2_PLUS_0_1RF:
224
+
case MLO_2_PLUS_0_2RF:
225
+
case MLO_2_PLUS_2_2RF:
226
+
case MLO_DBCC_NOT_SUPPORT:
227
+
default:
228
+
return RF_SYN_ON_OFF;
229
+
case MLO_1_PLUS_1_1RF:
230
+
case DBCC_LEGACY:
231
+
return RF_SYN_ALLON;
232
+
}
233
+
}
234
+
235
+
void rtw8922d_rfk_mlo_ctrl(struct rtw89_dev *rtwdev)
236
+
{
237
+
enum _rf_syn_pow syn_pow = rtw8922d_get_syn_pow(rtwdev);
238
+
239
+
if (!rtwdev->dbcc_en)
240
+
goto set_rfk_reload;
241
+
242
+
rtw8922d_set_syn01(rtwdev, syn_pow);
243
+
244
+
set_rfk_reload:
245
+
rtw8922d_chlk_reload(rtwdev);
246
+
}
247
+
248
+
static void rtw8922d_x4k_setting(struct rtw89_dev *rtwdev)
249
+
{
250
+
u32 val;
251
+
252
+
val = rtw89_read_rf(rtwdev, RF_PATH_A, 0xB9, 0xF000);
253
+
rtw89_write_rf(rtwdev, RF_PATH_A, 0xB9, 0xF000, val);
254
+
val = rtw89_read_rf(rtwdev, RF_PATH_B, 0xB9, 0xF000);
255
+
rtw89_write_rf(rtwdev, RF_PATH_B, 0xB9, 0xF000, val);
256
+
257
+
rtw89_write_rf(rtwdev, RF_PATH_A, 0xC2, BIT(19), 0x1);
258
+
rtw89_write_rf(rtwdev, RF_PATH_B, 0xC2, BIT(19), 0x1);
259
+
}
260
+
261
+
void rtw8922d_rfk_hw_init(struct rtw89_dev *rtwdev)
262
+
{
263
+
rtw8922d_x4k_setting(rtwdev);
264
+
}
265
+
266
+
void rtw8922d_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
267
+
{
268
+
bool mlo_1_1;
269
+
270
+
if (!rtwdev->dbcc_en)
271
+
return;
272
+
273
+
mlo_1_1 = rtw89_is_mlo_1_1(rtwdev);
274
+
if (mlo_1_1)
275
+
rtw8922d_set_syn01(rtwdev, RF_SYN_ALLON);
276
+
else if (phy_idx == RTW89_PHY_0)
277
+
rtw8922d_set_syn01(rtwdev, RF_SYN_ON_OFF);
278
+
else
279
+
rtw8922d_set_syn01(rtwdev, RF_SYN_OFF_ON);
280
+
281
+
fsleep(1000);
282
+
}
283
+
284
+
void rtw8922d_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
285
+
{
286
+
rtw8922d_rfk_mlo_ctrl(rtwdev);
287
+
}
288
+
289
+
static u8 _get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
290
+
{
291
+
rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
292
+
rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0);
293
+
rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
294
+
295
+
fsleep(200);
296
+
297
+
return rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL_V1);
298
+
}
299
+
300
+
static void _lck_keep_thermal(struct rtw89_dev *rtwdev)
301
+
{
302
+
struct rtw89_lck_info *lck = &rtwdev->lck;
303
+
int path;
304
+
305
+
for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
306
+
lck->thermal[path] = _get_thermal(rtwdev, path);
307
+
rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
308
+
"[LCK] path=%d thermal=0x%x", path, lck->thermal[path]);
309
+
}
310
+
}
311
+
312
+
static void _lck(struct rtw89_dev *rtwdev)
313
+
{
314
+
enum _rf_syn_pow syn_pow = rtw8922d_get_syn_pow(rtwdev);
315
+
u8 path_mask = 0;
316
+
u32 tmp18, tmp5;
317
+
int path;
318
+
319
+
rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "[LCK] DO LCK\n");
320
+
321
+
if (syn_pow == RF_SYN_ALLON)
322
+
path_mask = BIT(RF_PATH_A) | BIT(RF_PATH_B);
323
+
else if (syn_pow == RF_SYN_ON_OFF)
324
+
path_mask = BIT(RF_PATH_A);
325
+
else if (syn_pow == RF_SYN_OFF_ON)
326
+
path_mask = BIT(RF_PATH_B);
327
+
else
328
+
return;
329
+
330
+
for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
331
+
if (!(path_mask & BIT(path)))
332
+
continue;
333
+
334
+
tmp18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, MASKDWORD);
335
+
tmp5 = rtw89_read_rf(rtwdev, path, RR_RSV1, MASKDWORD);
336
+
337
+
rtw89_write_rf(rtwdev, path, RR_MOD, MASKDWORD, 0x10000);
338
+
rtw89_write_rf(rtwdev, path, RR_RSV1, MASKDWORD, 0x0);
339
+
rtw89_write_rf(rtwdev, path, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
340
+
rtw89_write_rf(rtwdev, path, RR_CFGCH, MASKDWORD, tmp18);
341
+
rtw89_write_rf(rtwdev, path, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
342
+
343
+
fsleep(400);
344
+
345
+
rtw89_write_rf(rtwdev, path, RR_RSV1, MASKDWORD, tmp5);
346
+
}
347
+
348
+
_lck_keep_thermal(rtwdev);
349
+
}
350
+
351
+
#define RTW8922D_LCK_TH 16
352
+
void rtw8922d_lck_track(struct rtw89_dev *rtwdev)
353
+
{
354
+
struct rtw89_lck_info *lck = &rtwdev->lck;
355
+
u8 cur_thermal;
356
+
int delta;
357
+
int path;
358
+
359
+
for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
360
+
cur_thermal = _get_thermal(rtwdev, path);
361
+
delta = abs((int)cur_thermal - lck->thermal[path]);
362
+
363
+
rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
364
+
"[LCK] path=%d current thermal=0x%x delta=0x%x\n",
365
+
path, cur_thermal, delta);
366
+
367
+
if (delta >= RTW8922D_LCK_TH) {
368
+
_lck(rtwdev);
369
+
return;
370
+
}
371
+
}
372
+
}
+22
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.h
+22
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2
+
/* Copyright(c) 2026 Realtek Corporation
3
+
*/
4
+
5
+
#ifndef __RTW89_8922D_RFK_H__
6
+
#define __RTW89_8922D_RFK_H__
7
+
8
+
#include "core.h"
9
+
10
+
extern const struct rtw89_rfk_tbl rtw8922d_nctl_post_defs_tbl;
11
+
12
+
void rtw8922d_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx);
13
+
void rtw8922d_set_channel_rf(struct rtw89_dev *rtwdev,
14
+
const struct rtw89_chan *chan,
15
+
enum rtw89_phy_idx phy_idx);
16
+
void rtw8922d_rfk_hw_init(struct rtw89_dev *rtwdev);
17
+
void rtw8922d_rfk_mlo_ctrl(struct rtw89_dev *rtwdev);
18
+
void rtw8922d_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
19
+
void rtw8922d_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
20
+
void rtw8922d_lck_track(struct rtw89_dev *rtwdev);
21
+
22
+
#endif
+119
drivers/net/wireless/realtek/rtw89/rtw8922de.c
+119
drivers/net/wireless/realtek/rtw89/rtw8922de.c
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/* Copyright(c) 2026 Realtek Corporation
3
+
*/
4
+
5
+
#include <linux/module.h>
6
+
#include <linux/pci.h>
7
+
8
+
#include "pci.h"
9
+
#include "reg.h"
10
+
#include "rtw8922d.h"
11
+
12
+
static const struct rtw89_pci_info rtw8922d_pci_info = {
13
+
.gen_def = &rtw89_pci_gen_be,
14
+
.isr_def = &rtw89_pci_isr_be_v1,
15
+
.txbd_trunc_mode = MAC_AX_BD_TRUNC,
16
+
.rxbd_trunc_mode = MAC_AX_BD_TRUNC,
17
+
.rxbd_mode = MAC_AX_RXBD_PKT,
18
+
.tag_mode = MAC_AX_TAG_MULTI,
19
+
.tx_burst = MAC_AX_TX_BURST_V1_256B,
20
+
.rx_burst = MAC_AX_RX_BURST_V1_128B,
21
+
.wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_256NS,
22
+
.wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_256NS,
23
+
.multi_tag_num = MAC_AX_TAG_NUM_8,
24
+
.lbc_en = MAC_AX_PCIE_ENABLE,
25
+
.lbc_tmr = MAC_AX_LBC_TMR_2MS,
26
+
.autok_en = MAC_AX_PCIE_DISABLE,
27
+
.io_rcy_en = MAC_AX_PCIE_ENABLE,
28
+
.io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_DEF,
29
+
.rx_ring_eq_is_full = true,
30
+
.check_rx_tag = true,
31
+
.no_rxbd_fs = true,
32
+
.group_bd_addr = true,
33
+
.rpp_fmt_size = sizeof(struct rtw89_pci_rpp_fmt_v1),
34
+
35
+
.init_cfg_reg = R_BE_HAXI_INIT_CFG1,
36
+
.txhci_en_bit = B_BE_TXDMA_EN,
37
+
.rxhci_en_bit = B_BE_RXDMA_EN,
38
+
.rxbd_mode_bit = B_BE_RXQ_RXBD_MODE_MASK,
39
+
.exp_ctrl_reg = R_BE_HAXI_EXP_CTRL_V1,
40
+
.max_tag_num_mask = B_BE_MAX_TAG_NUM_MASK,
41
+
.rxbd_rwptr_clr_reg = R_BE_RXBD_RWPTR_CLR1_V1,
42
+
.txbd_rwptr_clr2_reg = R_BE_TXBD_RWPTR_CLR1,
43
+
.dma_io_stop = {R_BE_HAXI_INIT_CFG1, B_BE_STOP_AXI_MST},
44
+
.dma_stop1 = {R_BE_HAXI_DMA_STOP1, B_BE_TX_STOP1_MASK_V1},
45
+
.dma_stop2 = {0},
46
+
.dma_busy1 = {R_BE_HAXI_DMA_BUSY1, DMA_BUSY1_CHECK_BE_V1},
47
+
.dma_busy2_reg = 0,
48
+
.dma_busy3_reg = R_BE_HAXI_DMA_BUSY1,
49
+
50
+
.rpwm_addr = R_BE_PCIE_HRPWM,
51
+
.cpwm_addr = R_BE_PCIE_CRPWM,
52
+
.mit_addr = R_BE_PCIE_MIT_CH_EN,
53
+
.wp_sel_addr = R_BE_WP_ADDR_H_SEL0_3_V1,
54
+
.tx_dma_ch_mask = BIT(RTW89_TXCH_ACH1) | BIT(RTW89_TXCH_ACH3) |
55
+
BIT(RTW89_TXCH_ACH5) | BIT(RTW89_TXCH_ACH7) |
56
+
BIT(RTW89_TXCH_CH9) | BIT(RTW89_TXCH_CH11),
57
+
.bd_idx_addr_low_power = NULL,
58
+
.dma_addr_set = &rtw89_pci_ch_dma_addr_set_be_v1,
59
+
.bd_ram_table = NULL,
60
+
61
+
.ltr_set = rtw89_pci_ltr_set_v2,
62
+
.fill_txaddr_info = rtw89_pci_fill_txaddr_info_v1,
63
+
.parse_rpp = rtw89_pci_parse_rpp_v1,
64
+
.config_intr_mask = rtw89_pci_config_intr_mask_v3,
65
+
.enable_intr = rtw89_pci_enable_intr_v3,
66
+
.disable_intr = rtw89_pci_disable_intr_v3,
67
+
.recognize_intrs = rtw89_pci_recognize_intrs_v3,
68
+
69
+
.ssid_quirks = NULL,
70
+
};
71
+
72
+
static const struct rtw89_driver_info rtw89_8922de_vs_info = {
73
+
.chip = &rtw8922d_chip_info,
74
+
.variant = &rtw8922de_vs_variant,
75
+
.quirks = NULL,
76
+
.bus = {
77
+
.pci = &rtw8922d_pci_info,
78
+
},
79
+
};
80
+
81
+
static const struct rtw89_driver_info rtw89_8922de_info = {
82
+
.chip = &rtw8922d_chip_info,
83
+
.variant = NULL,
84
+
.quirks = NULL,
85
+
.bus = {
86
+
.pci = &rtw8922d_pci_info,
87
+
},
88
+
};
89
+
90
+
static const struct pci_device_id rtw89_8922de_id_table[] = {
91
+
{
92
+
PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x892D),
93
+
.driver_data = (kernel_ulong_t)&rtw89_8922de_vs_info,
94
+
},
95
+
{
96
+
PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x882D),
97
+
.driver_data = (kernel_ulong_t)&rtw89_8922de_vs_info,
98
+
},
99
+
{
100
+
PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x895D),
101
+
.driver_data = (kernel_ulong_t)&rtw89_8922de_info,
102
+
},
103
+
{},
104
+
};
105
+
MODULE_DEVICE_TABLE(pci, rtw89_8922de_id_table);
106
+
107
+
static struct pci_driver rtw89_8922de_driver = {
108
+
.name = "rtw89_8922de",
109
+
.id_table = rtw89_8922de_id_table,
110
+
.probe = rtw89_pci_probe,
111
+
.remove = rtw89_pci_remove,
112
+
.driver.pm = &rtw89_pm_ops_be,
113
+
.err_handler = &rtw89_pci_err_handler,
114
+
};
115
+
module_pci_driver(rtw89_8922de_driver);
116
+
117
+
MODULE_AUTHOR("Realtek Corporation");
118
+
MODULE_DESCRIPTION("Realtek 802.11be wireless 8922DE/8922DE-VS driver");
119
+
MODULE_LICENSE("Dual BSD/GPL");
+3
-1
drivers/net/wireless/realtek/rtw89/ser.c
+3
-1
drivers/net/wireless/realtek/rtw89/ser.c
···
498
498
switch (evt) {
499
499
case SER_EV_STATE_IN:
500
500
wiphy_lock(wiphy);
501
+
ser->sw_cnt.l1++;
501
502
wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work);
502
503
wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work);
503
504
wiphy_unlock(wiphy);
···
589
588
590
589
start_page = start_addr / mem_page_size;
591
590
residue = start_addr % mem_page_size;
592
-
base_addr = mac->mem_base_addrs[sel];
591
+
base_addr = rtw89_mac_mem_base_addrs(rtwdev, sel);
593
592
base_addr += start_page * mem_page_size;
594
593
595
594
while (cnt < len) {
···
731
730
switch (evt) {
732
731
case SER_EV_STATE_IN:
733
732
wiphy_lock(rtwdev->hw->wiphy);
733
+
ser->sw_cnt.l2++;
734
734
ser_l2_reset_st_pre_hdl(ser);
735
735
wiphy_unlock(rtwdev->hw->wiphy);
736
736
+90
-17
drivers/net/wireless/realtek/rtw89/usb.c
+90
-17
drivers/net/wireless/realtek/rtw89/usb.c
···
161
161
rtw89_usb_ops_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev,
162
162
u8 txch)
163
163
{
164
+
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
165
+
int inflight;
166
+
164
167
if (txch == RTW89_TXCH_CH12)
165
168
return 1;
166
169
167
-
return 42; /* TODO some kind of calculation? */
170
+
inflight = atomic_read(&rtwusb->tx_inflight[txch]);
171
+
if (inflight >= RTW89_USB_MAX_TX_URBS_PER_CH)
172
+
return 0;
173
+
174
+
return RTW89_USB_MAX_TX_URBS_PER_CH - inflight;
168
175
}
169
176
170
177
static void rtw89_usb_write_port_complete(struct urb *urb)
171
178
{
172
179
struct rtw89_usb_tx_ctrl_block *txcb = urb->context;
173
180
struct rtw89_dev *rtwdev = txcb->rtwdev;
181
+
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
174
182
struct ieee80211_tx_info *info;
175
183
struct rtw89_txwd_body *txdesc;
176
184
struct sk_buff *skb;
···
236
228
set_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags);
237
229
break;
238
230
}
231
+
232
+
atomic_dec(&rtwusb->tx_inflight[txcb->txch]);
239
233
240
234
kfree(txcb);
241
235
}
···
316
306
317
307
skb_queue_tail(&txcb->tx_ack_queue, skb);
318
308
309
+
atomic_inc(&rtwusb->tx_inflight[txch]);
310
+
319
311
ret = rtw89_usb_write_port(rtwdev, txch, skb->data, skb->len,
320
312
txcb);
321
313
if (ret) {
314
+
atomic_dec(&rtwusb->tx_inflight[txch]);
315
+
322
316
if (ret != -ENODEV)
323
317
rtw89_err(rtwdev, "write port txch %d failed: %d\n",
324
318
txch, ret);
···
422
408
static void rtw89_usb_rx_handler(struct work_struct *work)
423
409
{
424
410
struct rtw89_usb *rtwusb = container_of(work, struct rtw89_usb, rx_work);
411
+
const struct rtw89_usb_info *info = rtwusb->info;
425
412
struct rtw89_dev *rtwdev = rtwusb->rtwdev;
426
413
struct rtw89_rx_desc_info desc_info;
414
+
s32 aligned_offset, remaining;
427
415
struct sk_buff *rx_skb;
428
416
struct sk_buff *skb;
429
417
u32 pkt_offset;
418
+
u8 *pkt_ptr;
430
419
int limit;
431
420
432
421
for (limit = 0; limit < 200; limit++) {
···
442
425
goto free_or_reuse;
443
426
}
444
427
445
-
memset(&desc_info, 0, sizeof(desc_info));
446
-
rtw89_chip_query_rxdesc(rtwdev, &desc_info, rx_skb->data, 0);
428
+
pkt_ptr = rx_skb->data;
429
+
remaining = rx_skb->len;
447
430
448
-
skb = rtw89_alloc_skb_for_rx(rtwdev, desc_info.pkt_size);
449
-
if (!skb) {
450
-
rtw89_debug(rtwdev, RTW89_DBG_HCI,
451
-
"failed to allocate RX skb of size %u\n",
452
-
desc_info.pkt_size);
453
-
goto free_or_reuse;
454
-
}
431
+
do {
432
+
memset(&desc_info, 0, sizeof(desc_info));
433
+
rtw89_chip_query_rxdesc(rtwdev, &desc_info, pkt_ptr, 0);
455
434
456
-
pkt_offset = desc_info.offset + desc_info.rxd_len;
435
+
pkt_offset = desc_info.offset + desc_info.rxd_len;
436
+
if (remaining < (pkt_offset + desc_info.pkt_size)) {
437
+
rtw89_debug(rtwdev, RTW89_DBG_HCI,
438
+
"Failed to get remaining RX pkt %u > %u\n",
439
+
pkt_offset + desc_info.pkt_size, remaining);
440
+
goto free_or_reuse;
441
+
}
457
442
458
-
skb_put_data(skb, rx_skb->data + pkt_offset,
459
-
desc_info.pkt_size);
443
+
skb = rtw89_alloc_skb_for_rx(rtwdev, desc_info.pkt_size);
444
+
if (!skb) {
445
+
rtw89_debug(rtwdev, RTW89_DBG_HCI,
446
+
"failed to allocate RX skb of size %u\n",
447
+
desc_info.pkt_size);
448
+
goto free_or_reuse;
449
+
}
460
450
461
-
rtw89_core_rx(rtwdev, &desc_info, skb);
451
+
skb_put_data(skb, pkt_ptr + pkt_offset, desc_info.pkt_size);
452
+
rtw89_core_rx(rtwdev, &desc_info, skb);
453
+
454
+
/* next frame */
455
+
pkt_offset += desc_info.pkt_size;
456
+
aligned_offset = ALIGN(pkt_offset, info->rx_agg_alignment);
457
+
pkt_ptr += aligned_offset;
458
+
remaining -= aligned_offset;
459
+
} while (remaining > 0);
462
460
463
461
free_or_reuse:
464
462
if (skb_queue_len(&rtwusb->rx_free_queue) >= RTW89_USB_RX_SKB_NUM)
···
698
666
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
699
667
int i;
700
668
701
-
for (i = 0; i < ARRAY_SIZE(rtwusb->tx_queue); i++)
669
+
for (i = 0; i < ARRAY_SIZE(rtwusb->tx_queue); i++) {
702
670
skb_queue_head_init(&rtwusb->tx_queue[i]);
671
+
atomic_set(&rtwusb->tx_inflight[i], 0);
672
+
}
703
673
}
704
674
705
675
static void rtw89_usb_deinit_tx(struct rtw89_dev *rtwdev)
···
779
745
return 0; /* Nothing to do. */
780
746
}
781
747
748
+
static void rtw89_usb_rx_agg_cfg_v1(struct rtw89_dev *rtwdev)
749
+
{
750
+
const u32 rxagg_0 = FIELD_PREP_CONST(B_AX_RXAGG_0_EN, 1) |
751
+
FIELD_PREP_CONST(B_AX_RXAGG_0_NUM_TH, 0) |
752
+
FIELD_PREP_CONST(B_AX_RXAGG_0_TIME_32US_TH, 32) |
753
+
FIELD_PREP_CONST(B_AX_RXAGG_0_BUF_SZ_4K, 5);
754
+
755
+
rtw89_write32(rtwdev, R_AX_RXAGG_0, rxagg_0);
756
+
}
757
+
758
+
static void rtw89_usb_rx_agg_cfg_v2(struct rtw89_dev *rtwdev)
759
+
{
760
+
const u32 rxagg_0 = FIELD_PREP_CONST(B_AX_RXAGG_0_EN, 1) |
761
+
FIELD_PREP_CONST(B_AX_RXAGG_0_NUM_TH, 255) |
762
+
FIELD_PREP_CONST(B_AX_RXAGG_0_TIME_32US_TH, 32) |
763
+
FIELD_PREP_CONST(B_AX_RXAGG_0_BUF_SZ_1K, 20);
764
+
765
+
rtw89_write32(rtwdev, R_AX_RXAGG_0_V1, rxagg_0);
766
+
rtw89_write32(rtwdev, R_AX_RXAGG_1_V1, 0x1F);
767
+
}
768
+
769
+
static void rtw89_usb_rx_agg_cfg(struct rtw89_dev *rtwdev)
770
+
{
771
+
switch (rtwdev->chip->chip_id) {
772
+
case RTL8851B:
773
+
case RTL8852A:
774
+
case RTL8852B:
775
+
rtw89_usb_rx_agg_cfg_v1(rtwdev);
776
+
break;
777
+
case RTL8852C:
778
+
rtw89_usb_rx_agg_cfg_v2(rtwdev);
779
+
break;
780
+
default:
781
+
rtw89_warn(rtwdev, "%s: USB RX agg not support\n", __func__);
782
+
return;
783
+
}
784
+
}
785
+
782
786
static int rtw89_usb_ops_mac_post_init(struct rtw89_dev *rtwdev)
783
787
{
784
788
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
···
844
772
B_AX_EP_IDX, ep);
845
773
rtw89_write8(rtwdev, info->usb_endpoint_2 + 1, NUMP);
846
774
}
775
+
776
+
rtw89_usb_rx_agg_cfg(rtwdev);
847
777
848
778
return 0;
849
779
}
···
1009
935
if (!rtwusb->vendor_req_buf)
1010
936
return -ENOMEM;
1011
937
1012
-
rtwusb->udev = usb_get_dev(interface_to_usbdev(intf));
938
+
rtwusb->udev = interface_to_usbdev(intf);
1013
939
1014
940
usb_set_intfdata(intf, rtwdev->hw);
1015
941
···
1023
949
{
1024
950
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
1025
951
1026
-
usb_put_dev(rtwusb->udev);
1027
952
kfree(rtwusb->vendor_req_buf);
1028
953
usb_set_intfdata(intf, NULL);
1029
954
}
+15
drivers/net/wireless/realtek/rtw89/usb.h
+15
drivers/net/wireless/realtek/rtw89/usb.h
···
20
20
#define RTW89_MAX_ENDPOINT_NUM 9
21
21
#define RTW89_MAX_BULKOUT_NUM 7
22
22
23
+
#define R_AX_RXAGG_0_V1 0x6000
24
+
#define B_AX_RXAGG_0_EN BIT(31)
25
+
#define B_AX_RXAGG_0_NUM_TH GENMASK(23, 16)
26
+
#define B_AX_RXAGG_0_TIME_32US_TH GENMASK(15, 8)
27
+
#define B_AX_RXAGG_0_BUF_SZ_1K GENMASK(7, 0)
28
+
29
+
#define R_AX_RXAGG_1_V1 0x6004
30
+
31
+
#define R_AX_RXAGG_0 0x8900
32
+
#define B_AX_RXAGG_0_BUF_SZ_4K GENMASK(7, 0)
33
+
34
+
#define RTW89_USB_MAX_TX_URBS_PER_CH 128
35
+
23
36
struct rtw89_usb_info {
24
37
u32 usb_host_request_2;
25
38
u32 usb_wlan0_1;
···
40
27
u32 usb3_mac_npi_config_intf_0;
41
28
u32 usb_endpoint_0;
42
29
u32 usb_endpoint_2;
30
+
u8 rx_agg_alignment;
43
31
u8 bulkout_id[RTW89_DMA_CH_NUM];
44
32
};
45
33
···
77
63
struct usb_anchor tx_submitted;
78
64
79
65
struct sk_buff_head tx_queue[RTW89_TXCH_NUM];
66
+
atomic_t tx_inflight[RTW89_TXCH_NUM];
80
67
};
81
68
82
69
static inline struct rtw89_usb *rtw89_usb_priv(struct rtw89_dev *rtwdev)
+17
drivers/net/wireless/realtek/rtw89/util.h
+17
drivers/net/wireless/realtek/rtw89/util.h
···
6
6
7
7
#include "core.h"
8
8
9
+
#define RTW89_KEY_PN_0 GENMASK_ULL(7, 0)
10
+
#define RTW89_KEY_PN_1 GENMASK_ULL(15, 8)
11
+
#define RTW89_KEY_PN_2 GENMASK_ULL(23, 16)
12
+
#define RTW89_KEY_PN_3 GENMASK_ULL(31, 24)
13
+
#define RTW89_KEY_PN_4 GENMASK_ULL(39, 32)
14
+
#define RTW89_KEY_PN_5 GENMASK_ULL(47, 40)
15
+
9
16
#define rtw89_iterate_vifs_bh(rtwdev, iterator, data) \
10
17
ieee80211_iterate_active_interfaces_atomic((rtwdev)->hw, \
11
18
IEEE80211_IFACE_ITER_NORMAL, iterator, data)
···
78
71
if (mask & BIT(i))
79
72
dst[i] = src[i];
80
73
}
74
+
}
75
+
76
+
static inline void ccmp_hdr2pn(s64 *pn, const u8 *hdr)
77
+
{
78
+
*pn = u64_encode_bits(hdr[0], RTW89_KEY_PN_0) |
79
+
u64_encode_bits(hdr[1], RTW89_KEY_PN_1) |
80
+
u64_encode_bits(hdr[4], RTW89_KEY_PN_2) |
81
+
u64_encode_bits(hdr[5], RTW89_KEY_PN_3) |
82
+
u64_encode_bits(hdr[6], RTW89_KEY_PN_4) |
83
+
u64_encode_bits(hdr[7], RTW89_KEY_PN_5);
81
84
}
82
85
83
86
s32 rtw89_linear_to_db_quarter(u64 val);
+2
drivers/net/wireless/realtek/rtw89/wow.c
+2
drivers/net/wireless/realtek/rtw89/wow.c
-7
drivers/net/wireless/realtek/rtw89/wow.h
-7
drivers/net/wireless/realtek/rtw89/wow.h
···
8
8
#define RTW89_KEY_TKIP_PN_IV16 GENMASK_ULL(15, 0)
9
9
#define RTW89_KEY_TKIP_PN_IV32 GENMASK_ULL(47, 16)
10
10
11
-
#define RTW89_KEY_PN_0 GENMASK_ULL(7, 0)
12
-
#define RTW89_KEY_PN_1 GENMASK_ULL(15, 8)
13
-
#define RTW89_KEY_PN_2 GENMASK_ULL(23, 16)
14
-
#define RTW89_KEY_PN_3 GENMASK_ULL(31, 24)
15
-
#define RTW89_KEY_PN_4 GENMASK_ULL(39, 32)
16
-
#define RTW89_KEY_PN_5 GENMASK_ULL(47, 40)
17
-
18
11
#define RTW89_IGTK_IPN_0 GENMASK_ULL(7, 0)
19
12
#define RTW89_IGTK_IPN_1 GENMASK_ULL(15, 8)
20
13
#define RTW89_IGTK_IPN_2 GENMASK_ULL(23, 16)