Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm_mpam: Add MPAM MSC register layout definitions
Memory Partitioning and Monitoring (MPAM) has memory mapped devices
(MSCs) with an identity/configuration page.
Add the definitions for these registers as offset within the page(s).
Link: https://developer.arm.com/documentation/ihi0099/aa/
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Ben Horgan <ben.horgan@arm.com>
Reviewed-by: Fenghua Yu <fenghuay@nvidia.com>
Reviewed-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Tested-by: Fenghua Yu <fenghuay@nvidia.com>
Tested-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Tested-by: Peter Newman <peternewman@google.com>
Tested-by: Carl Worth <carl@os.amperecomputing.com>
Tested-by: Gavin Shan <gshan@redhat.com>
Tested-by: Zeng Heng <zengheng4@huawei.com>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
authored by
James Morse
and committed by
Catalin Marinas
aa64b9e1
01fb4b82
+267
+267
drivers/resctrl/mpam_internal.h
+267
drivers/resctrl/mpam_internal.h
···
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int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level,
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cpumask_t *affinity);
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/*
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* MPAM MSCs have the following register layout. See:
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* Arm Memory System Resource Partitioning and Monitoring (MPAM) System
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* Component Specification.
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* https://developer.arm.com/documentation/ihi0099/aa/
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*/
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#define MPAM_ARCHITECTURE_V1 0x10
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/* Memory mapped control pages */
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/* ID Register offsets in the memory mapped page */
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#define MPAMF_IDR 0x0000 /* features id register */
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#define MPAMF_IIDR 0x0018 /* implementer id register */
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#define MPAMF_AIDR 0x0020 /* architectural id register */
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#define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */
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#define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */
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#define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */
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#define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */
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#define MPAMF_PRI_IDR 0x0048 /* priority partitioning */
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#define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */
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#define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */
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#define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */
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#define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */
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/* Configuration and Status Register offsets in the memory mapped page */
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#define MPAMCFG_PART_SEL 0x0100 /* partid to configure */
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#define MPAMCFG_CPBM 0x1000 /* cache-portion config */
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#define MPAMCFG_CMAX 0x0108 /* cache-capacity config */
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#define MPAMCFG_CMIN 0x0110 /* cache-capacity config */
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#define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */
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#define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */
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#define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */
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#define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */
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#define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */
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#define MPAMCFG_PRI 0x0400 /* priority partitioning config */
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#define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */
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#define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */
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#define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */
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#define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */
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#define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */
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#define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */
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#define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */
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#define MSMON_CSU 0x0840 /* current cache-usage */
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#define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */
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#define MSMON_MBWU 0x0860 /* current mem-bw usage value */
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#define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */
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#define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */
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#define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */
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#define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */
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#define MPAMF_ESR 0x00F8 /* error status register */
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#define MPAMF_ECR 0x00F0 /* error control register */
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/* MPAMF_IDR - MPAM features ID register */
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#define MPAMF_IDR_PARTID_MAX GENMASK(15, 0)
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#define MPAMF_IDR_PMG_MAX GENMASK(23, 16)
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#define MPAMF_IDR_HAS_CCAP_PART BIT(24)
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#define MPAMF_IDR_HAS_CPOR_PART BIT(25)
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#define MPAMF_IDR_HAS_MBW_PART BIT(26)
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#define MPAMF_IDR_HAS_PRI_PART BIT(27)
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#define MPAMF_IDR_EXT BIT(28)
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#define MPAMF_IDR_HAS_IMPL_IDR BIT(29)
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#define MPAMF_IDR_HAS_MSMON BIT(30)
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#define MPAMF_IDR_HAS_PARTID_NRW BIT(31)
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#define MPAMF_IDR_HAS_RIS BIT(32)
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#define MPAMF_IDR_HAS_EXTD_ESR BIT(38)
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#define MPAMF_IDR_HAS_ESR BIT(39)
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#define MPAMF_IDR_RIS_MAX GENMASK(59, 56)
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/* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */
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#define MPAMF_MSMON_IDR_MSMON_CSU BIT(16)
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#define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17)
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#define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31)
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/* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */
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#define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0)
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/* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */
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#define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0)
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#define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8)
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#define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28)
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#define MPAMF_CCAP_IDR_HAS_CMIN BIT(29)
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#define MPAMF_CCAP_IDR_NO_CMAX BIT(30)
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#define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31)
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/* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */
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#define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0)
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#define MPAMF_MBW_IDR_HAS_MIN BIT(10)
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#define MPAMF_MBW_IDR_HAS_MAX BIT(11)
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#define MPAMF_MBW_IDR_HAS_PBM BIT(12)
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#define MPAMF_MBW_IDR_HAS_PROP BIT(13)
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#define MPAMF_MBW_IDR_WINDWR BIT(14)
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#define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16)
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/* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */
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#define MPAMF_PRI_IDR_HAS_INTPRI BIT(0)
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#define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1)
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#define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4)
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#define MPAMF_PRI_IDR_HAS_DSPRI BIT(16)
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#define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17)
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#define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20)
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/* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */
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#define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0)
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#define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24)
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#define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25)
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#define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26)
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#define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27)
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#define MPAMF_CSUMON_IDR_HAS_XCL BIT(29)
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#define MPAMF_CSUMON_IDR_CSU_RO BIT(30)
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#define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31)
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/* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */
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#define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0)
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#define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28)
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#define MPAMF_MBWUMON_IDR_LWD BIT(29)
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#define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30)
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#define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31)
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/* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */
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#define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0)
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/* MPAMF_IIDR - MPAM implementation ID register */
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#define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0)
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#define MPAMF_IIDR_REVISION GENMASK(15, 12)
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#define MPAMF_IIDR_VARIANT GENMASK(19, 16)
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#define MPAMF_IIDR_PRODUCTID GENMASK(31, 20)
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/* MPAMF_AIDR - MPAM architecture ID register */
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#define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0)
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#define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4)
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/* MPAMCFG_PART_SEL - MPAM partition configuration selection register */
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#define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0)
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#define MPAMCFG_PART_SEL_INTERNAL BIT(16)
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#define MPAMCFG_PART_SEL_RIS GENMASK(27, 24)
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/* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */
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#define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0)
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/* MPAMCFG_CMAX - MPAM cache capacity configuration register */
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#define MPAMCFG_CMAX_SOFTLIM BIT(31)
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#define MPAMCFG_CMAX_CMAX GENMASK(15, 0)
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/* MPAMCFG_CMIN - MPAM cache capacity configuration register */
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#define MPAMCFG_CMIN_CMIN GENMASK(15, 0)
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/*
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* MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration
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* register
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*/
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#define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0)
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/*
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* MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration
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* register
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*/
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#define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0)
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#define MPAMCFG_MBW_MAX_HARDLIM BIT(31)
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/*
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* MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width
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* register
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*/
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#define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0)
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#define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8)
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/* MPAMCFG_PRI - MPAM priority partitioning configuration register */
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#define MPAMCFG_PRI_INTPRI GENMASK(15, 0)
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#define MPAMCFG_PRI_DSPRI GENMASK(31, 16)
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/*
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* MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning
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* configuration register
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*/
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#define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0)
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#define MPAMCFG_MBW_PROP_EN BIT(31)
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/*
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* MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register
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*/
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#define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0)
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#define MPAMCFG_INTPARTID_INTERNAL BIT(16)
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/* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */
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#define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0)
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#define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24)
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/* MPAMF_ESR - MPAM Error Status Register */
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#define MPAMF_ESR_PARTID_MON GENMASK(15, 0)
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#define MPAMF_ESR_PMG GENMASK(23, 16)
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#define MPAMF_ESR_ERRCODE GENMASK(27, 24)
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#define MPAMF_ESR_OVRWR BIT(31)
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#define MPAMF_ESR_RIS GENMASK(35, 32)
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/* MPAMF_ECR - MPAM Error Control Register */
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#define MPAMF_ECR_INTEN BIT(0)
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/* Error conditions in accessing memory mapped registers */
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#define MPAM_ERRCODE_NONE 0
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#define MPAM_ERRCODE_PARTID_SEL_RANGE 1
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#define MPAM_ERRCODE_REQ_PARTID_RANGE 2
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#define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3
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#define MPAM_ERRCODE_REQ_PMG_RANGE 4
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#define MPAM_ERRCODE_MONITOR_RANGE 5
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#define MPAM_ERRCODE_INTPARTID_RANGE 6
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#define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7
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#define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8
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#define MPAM_ERRCODE_RIS_NO_CONTROL 9
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#define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10
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#define MPAM_ERRCODE_RIS_NO_MONITOR 11
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/*
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* MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage
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* usage monitor control register
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* MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory
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* bandwidth usage monitor control register
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*/
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#define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0)
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#define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15)
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#define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16)
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#define MSMON_CFG_x_CTL_MATCH_PMG BIT(17)
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#define MSMON_CFG_MBWU_CTL_SCLEN BIT(19)
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#define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20)
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#define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24)
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#define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25)
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#define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26)
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#define MSMON_CFG_x_CTL_CAPT_RESET BIT(27)
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#define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28)
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#define MSMON_CFG_x_CTL_EN BIT(31)
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#define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42
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#define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43
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/*
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* MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage
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* usage monitor filter register
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* MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory
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* bandwidth usage monitor filter register
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*/
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#define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0)
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#define MSMON_CFG_x_FLT_PMG GENMASK(23, 16)
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#define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30)
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#define MSMON_CFG_CSU_FLT_XCL BIT(31)
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/*
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* MSMON_CSU - Memory system performance monitor cache storage usage monitor
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* register
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* MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage
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* capture register
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* MSMON_MBWU - Memory system performance monitor memory bandwidth usage
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* monitor register
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* MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage
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* capture register
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*/
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#define MSMON___VALUE GENMASK(30, 0)
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#define MSMON___NRDY BIT(31)
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#define MSMON___L_NRDY BIT(63)
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#define MSMON___L_VALUE GENMASK(43, 0)
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#define MSMON___LWD_VALUE GENMASK(62, 0)
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/*
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* MSMON_CAPT_EVNT - Memory system performance monitoring capture event
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* generation register
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*/
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#define MSMON_CAPT_EVNT_NOW BIT(0)
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#endif /* MPAM_INTERNAL_H */