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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: Add dpu_hw_cwb abstraction for CWB block
The CWB mux has its own registers and set of operations. Add dpu_hw_cwb
abstraction to allow driver to configure the CWB mux.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/629254/
Link: https://lore.kernel.org/r/20241216-concurrent-wb-v4-12-fe220297a7f0@quicinc.com
[DB: added #include <linux/bitfield.h>]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
authored by
Jessica Zhang
and committed by
Dmitry Baryshkov
aae87364
675c1edf
+150
-1
+1
drivers/gpu/drm/msm/Makefile
+1
drivers/gpu/drm/msm/Makefile
+75
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c
+75
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved
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*/
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#include <drm/drm_managed.h>
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#include "dpu_hw_cwb.h"
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#include <linux/bitfield.h>
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#define CWB_MUX 0x000
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#define CWB_MODE 0x004
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/* CWB mux block bit definitions */
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#define CWB_MUX_MASK GENMASK(3, 0)
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#define CWB_MODE_MASK GENMASK(2, 0)
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static void dpu_hw_cwb_config(struct dpu_hw_cwb *ctx,
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struct dpu_hw_cwb_setup_cfg *cwb_cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int cwb_mux_cfg = 0xF;
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enum dpu_pingpong pp;
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enum cwb_mode_input input;
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if (!cwb_cfg)
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return;
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input = cwb_cfg->input;
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pp = cwb_cfg->pp_idx;
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if (input >= INPUT_MODE_MAX)
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return;
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/*
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* The CWB_MUX register takes the pingpong index for the real-time
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* display
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*/
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if ((pp != PINGPONG_NONE) && (pp < PINGPONG_MAX))
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cwb_mux_cfg = FIELD_PREP(CWB_MUX_MASK, pp - PINGPONG_0);
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input = FIELD_PREP(CWB_MODE_MASK, input);
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DPU_REG_WRITE(c, CWB_MUX, cwb_mux_cfg);
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DPU_REG_WRITE(c, CWB_MODE, input);
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}
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/**
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* dpu_hw_cwb_init() - Initializes the writeback hw driver object with cwb.
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* @dev: Corresponding device for devres management
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* @cfg: wb_path catalog entry for which driver object is required
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* @addr: mapped register io address of MDP
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* Return: Error code or allocated dpu_hw_wb context
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*/
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struct dpu_hw_cwb *dpu_hw_cwb_init(struct drm_device *dev,
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const struct dpu_cwb_cfg *cfg,
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void __iomem *addr)
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{
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struct dpu_hw_cwb *c;
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if (!addr)
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return ERR_PTR(-EINVAL);
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c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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c->hw.blk_addr = addr + cfg->base;
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c->hw.log_mask = DPU_DBG_MASK_CWB;
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c->idx = cfg->id;
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c->ops.config_cwb = dpu_hw_cwb_config;
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return c;
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}
+70
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h
+70
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h
···
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved
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*/
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#ifndef _DPU_HW_CWB_H
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#define _DPU_HW_CWB_H
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#include "dpu_hw_util.h"
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struct dpu_hw_cwb;
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enum cwb_mode_input {
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INPUT_MODE_LM_OUT,
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INPUT_MODE_DSPP_OUT,
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INPUT_MODE_MAX
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};
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/**
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* struct dpu_hw_cwb_setup_cfg : Describes configuration for CWB mux
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* @pp_idx: Index of the real-time pinpong that the CWB mux will
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* feed the CWB mux
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* @input: Input tap point
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*/
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struct dpu_hw_cwb_setup_cfg {
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enum dpu_pingpong pp_idx;
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enum cwb_mode_input input;
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};
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/**
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*
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* struct dpu_hw_cwb_ops : Interface to the cwb hw driver functions
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* @config_cwb: configure CWB mux
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*/
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struct dpu_hw_cwb_ops {
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void (*config_cwb)(struct dpu_hw_cwb *ctx,
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struct dpu_hw_cwb_setup_cfg *cwb_cfg);
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};
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/**
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* struct dpu_hw_cwb : CWB mux driver object
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* @base: Hardware block base structure
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* @hw: Block hardware details
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* @idx: CWB index
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* @ops: handle to operations possible for this CWB
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*/
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struct dpu_hw_cwb {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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enum dpu_cwb idx;
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struct dpu_hw_cwb_ops ops;
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};
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/**
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* dpu_hw_cwb - convert base object dpu_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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static inline struct dpu_hw_cwb *to_dpu_hw_cwb(struct dpu_hw_blk *hw)
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{
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return container_of(hw, struct dpu_hw_cwb, base);
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}
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struct dpu_hw_cwb *dpu_hw_cwb_init(struct drm_device *dev,
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const struct dpu_cwb_cfg *cfg,
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void __iomem *addr);
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#endif /*_DPU_HW_CWB_H */
+4
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+4
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
···
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_HW_MDSS_H
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#define DPU_DBG_MASK_DSPP (1 << 10)
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#define DPU_DBG_MASK_DSC (1 << 11)
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#define DPU_DBG_MASK_CDM (1 << 12)
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#define DPU_DBG_MASK_CWB (1 << 13)
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/**
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* struct dpu_hw_tear_check - Struct contains parameters to configure